Wafer level packaging process for thin film inductor

Abstract

One aspect relates to a method of forming an integrated circuit (IC) package, including: forming a thin film inductor (TFI) over a first dummy carrier wafer; attaching an integrated circuit (IC) die to and over the TFI; attaching a second dummy carrier wafer to and over the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to the TFI and under the TFI; and removing the second dummy carrier wafer from the IC die. Another aspect relates to a method of forming an IC package, including: forming a first redistribution layer (RDL) over a through silicon via (TSV); forming a second RDL under the TSV; forming a thin film inductor (TFI) over the first RDL; and attaching at least one integrated circuit (IC) die to the second RDL or the TFI.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending non-provisional application serial number 18 / 172,975 filed on February 22, 2023 and provisional application serial number 63 / 400,971 filed on August 25, 2022, and these applications are assigned to the assignee of this application and are hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure relate generally to integrated circuit (IC) packaging, and particularly to a wafer level packaging (WLP) process for integrating an integrated circuit (IC) with a thin film inductor (TFI). Background Art

[0004] An integrated circuit (IC) may be electrically coupled to one or more inductors via metallized traces on a printed circuit board (PCB) to which the IC and the one or more inductors are mounted. In such an arrangement, the one or more inductors may occupy a considerable PCB footprint, which generally drives up the cost of a product incorporating such a PCB with the IC and the one or more inductors thereon. In addition, there may be a considerable electrical path length between the IC and the one or more inductors, which may adversely affect circuit performance. Summary of the invention

[0005] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is subsequently presented.

[0006] One aspect of the present disclosure relates to a method of forming an integrated circuit (IC) package. The method includes: forming a thin film inductor (TFI) on a first dummy carrier wafer; attaching an integrated circuit (IC) die to and above the TFI; attaching a second dummy carrier wafer to and above the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to and below the TFI; and removing the second dummy carrier wafer from the IC die.

[0007] Another aspect of the present disclosure relates to an integrated circuit (IC) package. The IC package includes: at least one thin film inductor (TFI); a set of integrated circuit (IC) dies, the set of integrated circuit (IC) dies coupled to the at least one TFI; and a set of solder bumps, the set of solder bumps coupled to the at least one TFI.

[0008] Another aspect of the present disclosure relates to a method of forming an integrated circuit (IC) package. The method includes: forming a first redistribution layer (RDL) above a through silicon via (TSV); forming a second RDL below the TSV; forming a thin film inductor (TFI) above the first RDL; and attaching at least one integrated circuit (IC) die to the second RDL or the TFI.

[0009] Another aspect of the present disclosure relates to an integrated circuit (IC) package. The IC package includes: a thin film inductor (TFI); an integrated circuit (IC) die, the integrated circuit (IC) die coupled to a first terminal of the TFI; a solder bump, the solder bump coupled to a second terminal of the TFI; and a through silicon via (TSV), through which the IC die or the solder bump is coupled to the first terminal or the second terminal of the TFI, respectively.

[0010] To achieve the foregoing and related purposes, one or more implementations include the features fully described below and specifically pointed out in the claims. The following description and the attached figures set forth in detail certain illustrative aspects of one or more implementations. However, these aspects are merely indicative of several of the various ways in which the principles of each implementation may be employed, and the specification implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A block diagram of an example power supply circuit according to one aspect of the present disclosure is illustrated.

[0012] Figure 2 A top view of another example power supply circuit according to another aspect of the disclosure is illustrated.

[0013] Figure 3 A top view of another example power supply circuit according to another aspect of the present disclosure is illustrated.

[0014] Figure 4A A side perspective view of an example thin film inductor (TFI) according to another aspect of the present disclosure is illustrated.

[0015] Figure 4B Another aspect of the present disclosure is illustrated. Figure 4A Cross-sectional view of an example thin film inductor (TFI).

[0016] Figure 4C A side perspective view of an example integrated circuit (IC) package according to another aspect of the disclosure is illustrated.

[0017] FIG. 5A to FIG. 5B An orthogonal cross-sectional view of an example integrated circuit (IC) package including a power management integrated circuit (PMIC) die and a thin film inductor (TFI) disposed over the PMIC die according to another aspect of the present disclosure is illustrated.

[0018] FIG. 6A to FIG. 6G Cross-sectional views of an example integrated circuit (IC) package at various stages of an example manufacturing method according to another aspect of the present disclosure are illustrated.

[0019] 7A to 7E Cross-sectional views of another example integrated circuit (IC) package at various stages of another example manufacturing method are illustrated in accordance with another aspect of the present disclosure. DETAILED DESCRIPTION

[0020] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0021] Figure 1 1 is a block diagram of an example power supply circuit 100 according to one aspect of the present disclosure. The power supply circuit 100 includes a power management integrated circuit (PMIC) 110, which includes an input terminal coupled to a battery (or other voltage source) to receive an input voltage VIN. The PMIC 110 can be configured to respectively provide power to a set of input / output (I / O) ports I / O1 to I / O2 based on the input voltage VIN. N The voltage set V1 to V N .

[0022] The power supply circuit 100 includes a set of input / output ports I / O1 to I / O2 coupled in series. N and a collection of power (supply voltage) rail input terminals VDD1 to VDD2 of an integrated circuit (IC) 150 such as a system on chip (SOC). N The set of inductors between L1 to L N The power supply circuit 100 includes power rail input terminals VDD1 to VDD2 coupled to the SOC 150.N and a lower voltage rail (e.g., ground) between the set of shunt capacitors C1 to C N .

[0023] SOC 150 includes a set of power rail input terminals VDD1 to VDD N The functional circuit is configured to respectively receive the power rail input terminals VDD1 to VDD N The dynamic current is drawn from the PMIC 110. The dynamic current can change relatively quickly and significantly. Therefore, if it is unstable, the set of power rail voltages V DD1 To V DDN will vary significantly, thereby increasing noise and potentially causing functional problems in and / or damage to the SOC 150. Thus, despite the dynamic current demand from the SOC 150, the inductor / capacitor set L1 / C1 to L N / C N Helps maintain the power rail voltage V DD1 To V DDN Basically stable.

[0024] Figure 2 A top view of another example power supply circuit 200 according to another aspect of the present disclosure is illustrated. The power supply circuit 200 may be an example of a physical implementation of at least a portion of the previously discussed power supply circuit 100. The power supply circuit 200 includes a PMIC die 220 mounted on a printed circuit board (PCB) 210. The PMIC die 220 may correspond to the PMIC 110 of the power supply circuit 100.

[0025] The power supply circuit 200 also includes a set of inductors L (depicted by dashed lines surrounding the inductors L) and a set of capacitors C (depicted by short dashed lines surrounding the capacitors C). The set of inductors L and capacitors C are mounted on the PCB 210 near and substantially around the PMIC die 220. The set of inductors L and the set of capacitors C may correspond to the sets L1 to L2 of the series inductors of the power supply circuit 100, respectively. N and the set of shunt capacitors C1 to C N .

[0026] A disadvantage of the power supply circuit 200 is that the set of inductors L and the set of capacitors C occupy a relatively large footprint of the PCB 210, which generally increases the cost of the power supply circuit 200 and / or limits the number of components that can be mounted on the PCB 210. Another disadvantage of the power supply circuit 200 is that there is a relatively long electrical path length between the PMIC die 220 and the set of inductors L and the set of capacitors C, which generally has a significant impact on the set of supply voltages VDD1 to VDD2 provided to the SOC 150. N The associated stability, noise and other performance characteristics are adversely affected.

[0027] Figure 3 A top view of another example power supply circuit 300 according to another aspect of the present disclosure is illustrated. The power supply circuit 300 may be an example of a physical implementation of at least a portion of the previously discussed power supply circuit 100. The power supply circuit 300 includes a PMIC die 320 mounted on a printed circuit board (PCB) 310. The PMIC die 320 may correspond to the PMIC 110 of the power supply circuit 100.

[0028] The power supply circuit 300 also includes a set of capacitors C (depicted by short dashed lines surrounding the capacitors C). The power supply circuit 300 includes an array or set 330 of thin film inductors (TFIs) formed on top of the PMIC die 320. The set 330 of TFIs and the set of capacitors C may correspond to the sets L1 to L2 of the series inductors of the power supply circuit 100, respectively. N and the set of shunt capacitors C1 to C N .

[0029] The advantage of the power supply circuit 300 over the power supply circuit 200 is that the set of TFIs 330 is formed on the PMIC die 320; and thus, does not occupy any additional PCB footprint. Therefore, the cost of the power supply circuit 300 can be reduced compared to the power supply circuit 200. In addition, since the set of TFIs 330 is located on top of the PMIC die 320, the electrical path length between the I / O port of the PMIC die 320 and the set of TFIs 330 is substantially shorter than the electrical path length of the power supply circuit 200. Therefore, the set of supply voltages VDD1 to VDD2 provided to the SOC 150 can be significantly improved. N associated stability, noise, and other performance characteristics.

[0030] Figure 4AA side perspective view of an example thin film inductor (TFI) 400 according to another aspect of the present disclosure is illustrated. TFI 400 can be an example of one TFI in a set 330 of TFIs. As previously mentioned, TFI 400 can be formed on an integrated circuit (IC) die 410, such as a power management integrated circuit (PMIC) die or other type of IC die (e.g., memory).

[0031] Specifically, TFI 400 includes a first electrically insulating layer 420 (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), a polymer (e.g., polyimide, polybenzoxazole (PBO), or other items), etc.) formed over IC die 410. It should be understood that the term "over" refers to a specific orientation of TFI 400 or any other TFI or IC package described herein; and the orientation of such items is not critical to the concepts described herein. Thus, in one orientation, a first material may be described as being over a second material, and in another orientation (e.g., inverted), the first material is under the second material - both describing the same item.

[0032] TFI 400 also includes a first magnetic layer (MAG1) 422 disposed on the first electrical insulating layer 420. Examples of such magnetic materials include cobalt-zirconium-tantalum (CZT), cobalt-zirconium-tantalum-boron (CZTB), or other items. TFI 400 also includes a first metal (e.g., copper (Cu)) redistribution layer (RDL) 424 formed on the first magnetic layer (MAG1) 422 and the first electrical insulating layer 420. Although Figure 4A Not shown, a thin electrically insulating layer may electrically isolate the first RDL 424 from the first magnetic layer ( MAG1 ) 422 .

[0033] Additionally, the TFI 400 includes an electrically insulating dome (e.g., a polymer (e.g., polyimide, PBO, or other)) 426 formed over a portion of a first RDL 424 located over the first magnetic layer (MAG1) 422. Additionally, the TFI 400 includes a second magnetic layer (MAG2) 428 formed over the electrically insulating dome 426. Thus, the electrically insulating dome 426 electrically isolates the second (or upper) magnetic layer (MAG2) 428 from the first (lower) magnetic layer (MAG1) 422 and the RDL 424. The first portion of the RDL 424 is electrically conductive in a first direction (eg, toward the Figure 4A 4 (to the left of the dome shown in FIG. 4 ) extends beyond the dome 426, and a second portion of the RDL 424 extends in a second direction opposite to the first direction (towards FIG. 4 ). Figure 4A ) extends beyond dome 426.

[0034] Figure 4BA cross-sectional view of a portion of an example thin film inductor (TFI) 400 along line BB according to another aspect of the present disclosure is illustrated. As shown, a first (lower) magnetic layer (MAG1) 422, an electrically insulating dome 426, and a second (upper) magnetic layer (MAG2) 428 form a tunnel through which a Cu RDL 424 extends. One side of the Cu RDL 424 (e.g., Figure 4A The left side of the tunnel shown in FIG. 4 ) forms at least a portion of the first terminal of TFI 400, and the other or opposite side of Cu RDL 424 (e.g., Figure 4A The right side of the tunnel shown in FIG. 4 ) forms at least another part of the second terminal of TFI 400.

[0035] Figure 4C A side perspective view of an example integrated circuit (IC) package 450 according to another aspect of the present disclosure is illustrated. The IC package 450 includes a PMIC die 410 and a TFI 400 formed over the PMIC die 410. The electrical connection between the PMIC die 410 and the TFI 400 includes a topmost metallization layer 412 (also referred to as an aluminum (AP) layer), and a first metallization via (Via 1) 414 formed over and electrically coupled to the AP layer 412 through an electrically insulating layer 420. The first (eg, Cu RDL 424) of the TFI 400 is connected to the PMIC die 410. Figure 4C The left side (shown in FIG. 1 ) end portion is formed over the first metallized via (Via 1) 414 and is electrically coupled to the first metallized via (Via 1).

[0036] The TFI 400 also includes a first passivation layer (PA1) 432 (e.g., a polymer (e.g., polyimide, PBO, or other items), epoxy molding compound, or other items) formed over the electrical insulating layer 420, the Cu RDL 424, the dome 426, and the second magnetic layer (MAG2) 428. In addition, the TFI 400 includes a second passivation layer (PA2) 434 (e.g., a polymer (e.g., polyimide, PBO, or other items), epoxy molding compound, or other items) formed over the first passivation layer (PA1) 432. The TFI 400 also includes a second passivation layer (PA2) 434 (e.g., a polymer (e.g., polyimide, PBO, or other items), epoxy molding compound, or other items) formed over the first passivation layer (PA1) 432. Figure 4C4. The TFI 400 includes a second metallization via (via 2) 436 formed on the second passivation layer (PA2) 434 and on the second metallization via (via 2) 436 and electrically coupled to the second end. In addition, the TFI 400 includes a second metal (Cu) RDL 438 formed on the second passivation layer (PA2) 434 and on the second metallization via (via 2) 436 and electrically coupled to the second metallization via (via 2). In addition, the TFI 400 includes an under bump metal (UBM) 440 formed on the second Cu RDL 438 and a solder bump (e.g., solder ball) 442 formed on the UBM 440. The solder bump 442 can be coupled to a shunt capacitor and a SOC, as in the power supply circuit 100.

[0037] FIG. 5A to FIG. 5B An orthogonal cross-sectional view of an example integrated circuit (IC) package 500 according to another aspect of the present disclosure is illustrated. The manufacture of the IC package 500 typically requires first manufacturing a power management integrated circuit (PMIC) die 510. The manufacturing time for manufacturing the PMIC die 510 can be about eight (8) weeks. Then, after manufacturing the PMIC die 510, a thin film inductor (TFI) is manufactured over the PMIC die 510. The manufacturing time for the TFI over the PMIC die 510 can take another six (6) to seven (7) weeks. Thus, the lead time for the IC package 500 can be about 15 weeks. The manufacture of the TFI on top of the PMIC die 510 can be as follows:

[0038] According to the manufacturing method, a first electrical insulating layer (e.g., SiO2, Si3N4, polymer (e.g., polyimide, PBO or other items), etc.) 520 is formed over the PMIC die 510 including the PMIC I / O pad 512 (also referred to as the aluminum (AP) layer of the PMIC die 510) and the top passivation layer 514. Then, a first magnetic layer (MAG1) 522 (e.g., CZT, CZTB or other items) is formed over the first electrical insulating layer (e.g., SiO2, Si3N4, polymer (e.g., polyimide, PBO or other items), etc.) 520. Then, a second electrical insulating layer (e.g., SiO2, Si3N4, polymer (e.g., polyimide, PBO or other items), etc.) 524 is formed over the first electrical insulating layer 520 and the first magnetic layer (MAG1) 522. Then, a first metallized via (Via 1) 526 is formed through the first and second electrically insulating layers 520 and 524 down to the PMIC I / O pad 512. Thus, there is a plurality of dielectric materials 520 and 524 surrounding the metallized via (Via 1) 526.

[0039] Then, according to the TFI manufacturing method, a first metal (e.g., Cu) redistribution layer (RDL) 528 is formed over the second electrically insulating layer 524 and the first metallized via (Via 1) 526. In this configuration, the first RDL 528 is electrically coupled to the PMIC I / O pad 512 through the metallized via (Via 1) 526. Then, an electrically insulating dome 530 (e.g., a polymer (e.g., polyimide, PBO, or other items)) is formed over the first RDL 528 and the second electrically insulating layer 524. Then, a second magnetic layer (e.g., CZT, CZTB, or other items) 532 is formed over the electrically insulating dome 530. Note that as shown within the dashed circle, and with reference to the interface of the first magnetic layer (MAG1) 522, the second electrically insulating layer 524, and the second magnetic layer (MAG2) 532 at the side trailing edge of these layers as seen in the tunnel or longitudinal axis perspective of the TFI, at the interface, the layers 522, 524, and 532 are substantially smoothly inclined in parallel. As previously discussed, the TFI includes the first magnetic layer (MAG 1) 522, the second electrically insulating layer 524, the first RDL 528, the electrically insulating dome 530, and the second magnetic layer 532.

[0040] To electrically couple the TFI to components external to the IC package 500, the TFI also includes a first passivation layer (PA1) 534 (e.g., an electrical insulator such as a polymer (e.g., polyimide, PBO, or other items), epoxy molding compound, or other items) formed over the second electrically insulating layer 524, the first RDL 528, the electrically insulating dome 530, and the second magnetic layer (MAG2) 532. A second metallized via (Via 2) 536 is then formed through the first passivation layer (PA1) 534 down to the first RDL 528. In this configuration, the first RDL 528 is disposed to the left of the dome 530 (e.g., the magnetic layer 532 is electrically insulating). Figure 5B The portion extending from the first RDL 528 (where the first metallized via (Via 1) forms a contact) can be regarded as the first terminal of the TFI, and the right side of the first RDL 528 to the dome 530 (as shown in FIG. Figure 5B The portion extending from (shown in ) (where the second metallized via (Via 2) forms contact) can be regarded as the second terminal of the TFI.

[0041] In addition, according to the manufacturing method, a second metal (e.g., Cu) RDL 538 is formed on the first passivation layer (PA1) 534 and on the second metallization via (Via 2) 536 and electrically coupled to the second metallization via (Via 2). Then, a second passivation layer (PA2) 540 (e.g., an electrical insulator, such as a polymer (e.g., polyimide, PBO or other items), epoxy resin molding compound or other items) is formed on the first passivation layer (PA1) 534 and the second RDL 538. Then, an under-bump metal (UBM) 542 is formed through the second passivation layer (PA2) 540 down to the second RDL 538. Then, a solder bump 544 is formed on the UBM 542 to complete the PMIC-TFIIC package 500. Likewise, because the fabrication of the PMIC die 510 and the TFI over the PMIC die 510 are in series, the fabrication time for the IC package 500 may take approximately 14-15 weeks, which may be undesirably long.

[0042] FIG. 6A to FIG. 6G Cross-sectional views of example integrated circuit (IC) packages 600-1 to 600-6A or 600-6B at various stages of a manufacturing method according to another aspect of the present disclosure are illustrated. The manufacturing method can be based on three-dimensional (3D) fan-out wafer level processing (FOWLP). At least a portion of the manufacturing method can be performed at the same time as the manufacturing method of the PMIC die (and / or other IC dies) to reduce the lead time of producing the IC package 600-6A or 600-6B.

[0043] First reference Fig. 6A According to the 3D FOWLP method, at an early stage, the IC package 600-1 may include a first dummy carrier wafer 605 (e.g., a transparent material such as glass), an adhesive (glue) layer 610 disposed (e.g., spin-coated) on the first dummy carrier wafer 605, and an electrical insulating layer (e.g., SiO2, Si3N4, polymer, etc.) 615 disposed on the adhesive layer 610. A thin film inductor (TFI) (or an array or set thereof) (such as reference 1) may be formed on (e.g., on top of) the electrical insulating layer 615. FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5B Thus, the electrically insulating layer 615 may correspond to the electrically insulating layers 520 and / or 524 of the PMIC-TFI IC package 500 discussed previously.

[0044] Next reference Figure 6BAccording to the 3D FOWLP method, the IC package 600-2 (and specifically, the electrical insulation layer 615) may undergo a deep reactive ion etching (DRIE) process to form a channel to accommodate the first magnetic layer 620. Then, the first magnetic layer 620 (e.g., CZT, CZTB, or other items) is deposited and patterned over the channel within the first electrical insulation layer 615. Then, a first metallized via (Via 1) 625 and a first metal (e.g., Cu) redistribution layer (RDL) 630 are formed (e.g., by plating). The first metal RDL 630 is formed over the first magnetic layer 620. Referring to the PMIC-TFI IC package 500, the first magnetic layer 620 may correspond to the first magnetic layer 522, the first metallized via (Via 1) 625 may correspond to the first metallized via (Via 1) 526, and the first RDL 630 may correspond to the first RDL 528.

[0045] Next reference Figure 6C According to the 3D FOWLP method, the IC package 600-3 may further include an electrically insulating dome 635 (e.g., a polymer (e.g., polyimide, PBO, or other items)) formed on the first RDL 630, a second magnetic layer 640 (e.g., CZT, CZTB, or other items) formed on the electrically insulating dome 635, a first passivation layer (e.g., SiO2, Si3N4, a polymer (e.g., polyimide, PBO, or other items), etc.) 645 formed on the second magnetic layer 640 (including portions of layers 615, 630, and 635), a second metallized via (Via 2) 650 formed through the first passivation layer 645 down to the first RDL 630, and a second metal (e.g., Cu) redistribution layer (RDL) 655 formed on the second metallized via (Via 2) 650.

[0046] For example, the redistribution layer (RDL) 655 may be attached using alloy solder for later die attachment. Referring to the PMIC-TFIIC package 500, the electrically insulating dome 635 may correspond to the electrically insulating dome 530, the second magnetic layer 640 may correspond to the second magnetic layer 532, the first passivation layer 645 may correspond to the first passivation layer 534, the second metallization via 650 may correspond to the second metallization via 536, and the second RDL 655 may correspond to the second RDL 538.

[0047] Next reference Fig.6DAccording to the 3D FOWLP method, the IC package 600-4 also includes at least one PMIC die 660, which includes an I / O pad (e.g., aluminum or AP layer) attached to a second RDL 655 corresponding to the TFI. It should be understood that the TFI can be flipped. In other words, the second RDL 655 can make contact with the solder bump 675 (see Fig. 6E ), and the metallized via (via 1) 625 of the TFI may make contact with at least one PMIC die 660. An adhesive (glue) layer 665 is formed (spin-coated) over the PMIC die 660 and the TFI to enable attachment of the TFI to a second dummy carrier wafer 670 (e.g., a transparent material such as glass) disposed over the adhesive layer 665.

[0048] refer to Fig. 6E According to the 3D FOWLP method, the IC package 600-5 removes (e.g., debonds) the first adhesive layer 610 and the first dummy carrier wafer 605 by subjecting the first adhesive layer 610 to laser power through the first glass (transparent) dummy carrier wafer 605. Then, at least one solder bump (e.g., solder ball) 675 is attached to the first metallized via (Via 1) 625 of the TFI. Note that, compared to the IC package 500, the PMIC die 660 is attached from "above" (e.g., attached to the upper RDL 655); while the PMIC die 510 is attached from below (e.g., attached to the first metallized via (Via 1) 526).

[0049] Next reference Fig. 6F According to the 3D FOWLP method, the IC package 600-6A removes (e.g., debonds) the second adhesive layer 665 and the second dummy carrier wafer 670 by subjecting the second adhesive layer 665 to laser power via the second glass (transparent) dummy carrier wafer 670. The IC package 600-6A is then diced to separate different PMIC-TFI IC packages.

[0050] In an alternative implementation, the IC package 600-6B may include Fig.6D Two or more different types of IC dies 660A and 660B (eg, a PMIC and a memory die) are attached to a TFI during the attachment manufacturing stage depicted in FIG. Figure 6G According to the 3D FOWLP method, the IC package 600-6B removes (debonds) the second adhesive layer 665 and the second dummy carrier wafer 670 by subjecting the second adhesive layer 665 to a laser through the second glass (transparent) dummy carrier wafer 670. The IC package 600-6B is then diced to produce separate IC die packages.

[0051] 7A to 7ECross-sectional views of another example integrated circuit (IC) package 700-1 to 700-4A or 700-4B at various stages of another example manufacturing method according to another aspect of the present disclosure are illustrated. The manufacturing method can be based on 2.5D fan-out wafer level processing (FOWLP). At least a portion of the manufacturing method can be performed at the same time as the manufacturing method of the PMIC die (and / or other IC dies) to reduce the lead time of producing the IC package 700-4A or 700-7B.

[0052] First reference Fig. 7A According to the 2.5D FOWLP method, at an early stage, the IC package 700-1 may include a through silicon via (TSV) 710, which includes a set 714 of metallized vias formed through a silicon wafer 712. Figure 7B According to the 2.5D FOWLP method, the IC package 700 - 2 includes an upper redistribution layer (RDL) 720 formed over an upper side of the TSV 710 and a lower redistribution layer (RDL) 730 formed under a lower side of the TSV 710 .

[0053] Further references Figure 7C According to the 2.5D FOWLP method, a thin film inductor (TFI) (or an array or set thereof) may be formed on the upper RDL 720 or under the lower RDL 730. Figure 7C In the example of FIG. 7 , IC package 700-3 includes a TFI 740 formed below and attached to lower RDL 730. TFI 740 may be formed by any of the previously discussed processes, such as those discussed with reference to IC packages 500 and 600.

[0054] Further references Fig.7D According to the 2.5D FOWLP method, the IC package 700-4A includes at least one solder bump 750 formed under the TFI 740 and a collection of one or more IC dies 760 and 765 surface mounted to the top RDL 720. As an alternative, referring to Fig. 7E , IC package 700-4B includes a TFI 740 formed over TSV 710 and a set of one or more IC dies 760, 765, and 770 surface mounted to the upper side of TFI 740. The set of one or more IC dies 760, 765, and 770 may be different types of dies (e.g., PMIC dies, memory dies, and other types of dies).

[0055] The following provides an overview of various aspects of the disclosure:

[0056] Aspect 1: A method for forming an integrated circuit (IC) package, comprising: forming a thin film inductor (TFI) on a first dummy carrier wafer; attaching an integrated circuit (IC) die to the TFI and above the TFI; attaching a second dummy carrier wafer to the IC die and above the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to the TFI and under the TFI; and removing the second dummy carrier wafer from the IC die.

[0057] Aspect 2: The method according to aspect 1, further comprising: forming a first adhesive layer on the first dummy carrier wafer; and forming a first electrical insulation layer on the first adhesive layer.

[0058] Aspect 3: The method according to aspect 2, wherein the first electrically insulating layer comprises silicon dioxide (SiO2), silicon nitride (Si3N4) or a polymer.

[0059] Aspect 4: A method according to Aspect 2 or 3, wherein forming the TFI on the first dummy carrier wafer includes: forming a first magnetic layer on the first electrically insulating layer; forming a first redistribution layer (RDL) on the first magnetic layer; forming an electrically insulating dome on the first RDL; and forming a second magnetic layer on the electrically insulating dome.

[0060] Aspect 5: The method of aspect 4, wherein the first magnetic layer comprises cobalt-zirconium-tantalum (CZT).

[0061] Aspect 6: The method of aspect 4, wherein the first magnetic layer comprises cobalt-zirconium-tantalum-boron (CZTB).

[0062] Aspect 7: The method of any one of aspects 4 to 6, wherein the second magnetic layer comprises cobalt-zirconium-tantalum (CZT).

[0063] Aspect 8: The method of any one of aspects 4 to 6, wherein the second magnetic layer comprises cobalt-zirconium-tantalum-boron (CZTB).

[0064] Aspect 9: The method of any one of aspects 4 to 8, wherein the first RDL comprises copper.

[0065] Aspect 10: The method of any one of aspects 4 to 9, wherein the electrically insulating dome comprises a polymer.

[0066] Aspect 11: The method of any one of aspects 4 to 10, further comprising: forming a first metallization via into the first electrically insulating layer, wherein the first RDL is electrically coupled to the first metallization via.

[0067] Aspect 12: The method according to any one of Aspects 4 to 11 further includes: forming a first passivation layer over the first RDL; forming a metallized through-hole through the first passivation layer; and forming a second RDL over the first passivation layer and the metallized through-hole, wherein the second RDL is electrically coupled to the first RDL through the metallized through-hole.

[0068] Aspect 13: The method according to Aspect 12 also includes: forming a second passivation layer over the second RDL; forming an under bump metal (UBM) through the second passivation layer and over the second RDL; and forming a solder bump over the UBM, wherein the solder bump is electrically coupled to the first RDL via the UBM, the second RDL and the metallized through hole.

[0069] Aspect 14: A method according to any one of Aspects 1 to 13, wherein the second dummy carrier wafer is attached to the IC die and attached above the IC die, the method comprising: forming an adhesive layer above the IC die; and placing the second dummy carrier wafer above the adhesive layer.

[0070] Aspect 15: The method of aspect 14, wherein the second dummy carrier wafer comprises a transparent material, and wherein removing the second dummy carrier wafer from the IC die comprises subjecting the adhesive layer to a laser via the second dummy carrier wafer to debond the adhesive layer from the IC die.

[0071] Aspect 16: A method according to any one of Aspects 1 to 15, wherein the TFI is attached to the first dummy carrier wafer via an adhesive layer, wherein the first dummy carrier wafer comprises a transparent material, and wherein removing the first dummy carrier wafer from the TFI comprises subjecting the adhesive layer to a laser via the first dummy carrier wafer to debond the adhesive layer from the TFI.

[0072] Aspect 17: A method according to any one of Aspects 1 to 16, wherein the TFI includes a collection of TFIs, wherein the IC die includes a collection of IC dies respectively electrically coupled to the collection of TFIs, and the method further includes: dicing the IC package to separate different pairs of TFIs and IC dies.

[0073] Aspect 18: The method of any one of Aspects 1 to 17, wherein the IC die comprises a power management integrated circuit (PMIC).

[0074] Aspect 19: The method of any one of aspects 1 to 18, wherein the IC die comprises a set of two or more different IC dies.

[0075] Aspect 20: A method according to any one of Aspects 1 to 19, wherein the TFI comprises a set of TFIs, wherein the IC die comprises a set of different IC dies, wherein at least one of the sets of different IC dies is electrically coupled to the set of TFIs, respectively, and the method further comprises: dicing the IC package to separate different pairs of the TFI and the set of different IC dies.

[0076] Aspect 21: A method of forming an integrated circuit (IC) package, comprising: forming a first redistribution layer (RDL) above a through silicon via (TSV); forming a second RDL under the TSV; forming a thin film inductor (TFI) above the first RDL; and attaching at least one integrated circuit (IC) die to the second RDL or the TFI.

[0077] Aspect 22: A method according to Aspect 21, wherein forming the TFI above the first RDL includes: forming an electrically insulating layer above the first RDL; forming a first magnetic layer above the electrically insulating layer; forming a third redistribution layer (RDL) above the first magnetic layer; forming an electrically insulating dome above the third RDL; and forming a second magnetic layer above the electrically insulating dome.

[0078] Aspect 23: The method of aspect 22, wherein the first magnetic layer comprises cobalt-zirconium-tantalum (CZT).

[0079] Aspect 24: The method of aspect 22, wherein the first magnetic layer comprises cobalt-zirconium-tantalum-boron (CZTB).

[0080] Aspect 25: The method of any one of Aspects 22 to 24, wherein the second magnetic layer comprises cobalt-zirconium-tantalum (CZT).

[0081] Aspect 26: The method of any one of aspects 22 to 24, wherein the second magnetic layer comprises cobalt-zirconium-tantalum-boron (CZTB).

[0082] Aspect 27: The method of any one of Aspects 22 to 26, wherein the third RDL comprises copper.

[0083] Aspect 28: The method of any one of Aspects 22 to 26, wherein the electrically insulating dome comprises a polymer.

[0084] Aspect 29: The method of any one of aspects 22 to 28, further comprising: forming a metallized via into the electrically insulating layer, wherein the first RDL and the third RDL are electrically coupled to the metallized via.

[0085] Aspect 30: The method according to any one of Aspects 22 to 29 further includes: forming a first passivation layer over the third RDL; forming a metallized through-hole through the first passivation layer; and forming a fourth RDL over the first passivation layer and the metallized through-hole, wherein the fourth RDL is electrically coupled to the third RDL through the metallized through-hole.

[0086] Aspect 31: The method according to Aspect 30 further includes: forming a second passivation layer over the fourth RDL; forming an under bump metal (UBM) through the second passivation layer and over the fourth RDL; and forming a solder bump over the UBM, wherein the solder bump is electrically coupled to the third RDL via the UBM, the fourth RDL, and the metallized through hole.

[0087] Aspect 32: The method of aspect 30, wherein attaching the at least one IC die to the TFI comprises attaching the at least one IC die to the fourth RDL.

[0088] Aspect 33: The method of any one of Aspects 21 to 32, wherein the at least one IC die comprises a power management integrated circuit (PMIC).

[0089] Aspect 34: The method according to any one of aspects 21 to 33, wherein forming the TFI above the first RDL includes: forming a set of TFIs above the first RDL.

[0090] Aspect 35: The method of any one of Aspects 21 to 34, wherein attaching at least one IC die comprises attaching a set of IC dies to the second RDL or the set of TFIs, wherein the set of IC dies are electrically coupled to the set of TFIs, respectively.

[0091] Clause 36: The method of Clause 35, wherein the set of IC dies comprises a set of at least two or more different types of IC dies.

[0092] Aspect 37: The method of aspect 4, wherein the first magnetic layer and the second magnetic layer are tilted substantially smoothly and in parallel at the edge of the TFI.

[0093] Aspect 38: The method according to Aspect 2 also includes: forming a second electrical insulation layer above the first electrical insulation layer; and forming a metallized through-hole through the first insulation layer and the second insulation layer, wherein the first electrical insulation layer and the second electrical insulation layer surround the metallized through-hole.

[0094] Aspect 39: The method of aspect 1, wherein: the IC die is attached to the TFI and the TFI is attached to a redistribution layer (RDL); or the IC die is attached to the RDL and the RDL is attached to the TFI.

[0095] Aspect 40: An integrated circuit (IC) package comprising: at least one thin film inductor (TFI); a collection of integrated circuit (IC) dies, the collection of integrated circuit (IC) dies coupled to the at least one TFI; and a collection of solder bumps, the collection of solder bumps coupled to the at least one TFI.

[0096] Aspect 41: The IC package of aspect 40, wherein at least one IC die in the set of IC dies comprises an aluminum (AP) layer coupled to the first terminal of the at least one TFI.

[0097] Aspect 42: The IC package of aspect 41, wherein at least one solder bump in the set of solder bumps is coupled to a second terminal of the at least one TFI.

[0098] Aspect 43: An IC package according to Aspect 42, wherein the at least one TFI includes: a first magnetic layer; a first redistribution layer (RDL), the first redistribution layer (RDL) is located above the first magnetic layer and electrically isolated from the first magnetic layer, wherein a first portion and a second portion of the first RDL on opposite sides of the first magnetic layer are respectively used as the first terminal and the second terminal of the at least one TFI; an electrically insulating dome, the electrically insulating dome is located above the first RDL and the first magnetic layer; and a second magnetic layer, the second magnetic layer is located above the electrically insulating dome, wherein the electrically insulating dome electrically isolates the second magnetic layer from the first RDL.

[0099] Aspect 44: The IC package of aspect 42 or 43, wherein the AP layer is coupled to the first terminal of the at least one TFI via a metallized via passing through an electrically insulating layer.

[0100] Aspect 45: An IC package according to any one of Aspects 42 to 44, wherein at least one of the set of solder bumps is coupled to the second terminal of the TFI via an under bump metallization (UBM), a second redistribution layer (RDL), and a metallized via through a passivation layer.

[0101] Aspect 46: An integrated circuit (IC) package, comprising: a thin film inductor (TFI); an integrated circuit (IC) die, the integrated circuit (IC) die coupled to a first terminal of the TFI; a solder bump, the solder bump coupled to a second terminal of the TFI; and a through silicon via (TSV), through which the IC die or the solder bump is coupled to the first terminal or the second terminal of the TFI, respectively.

[0102] Aspect 47: The IC package of aspect 46, wherein the IC die is coupled to the first terminal of the TFI through the TSV.

[0103] Aspect 48: The IC package of aspect 47, wherein the IC die is further coupled to the first terminal of the TFI through a first redistribution layer (RDL).

[0104] Aspect 49: The IC package of aspect 48, wherein the solder bump is coupled to the second terminal of the TFI through a second redistribution layer (RDL).

[0105] Aspect 50: The IC package of aspect 46, wherein the solder bump is coupled to the second terminal of the TFI through the TSV.

[0106] Aspect 51: The IC package of aspect 50, wherein the solder bump is further coupled to the second terminal of the TFI through a first redistribution layer (RDL).

[0107] Aspect 52: The IC package of aspect 51, wherein the IC is coupled to the first terminal of the TFI through a second redistribution layer (RDL).

[0108] Aspect 53: An integrated circuit package comprising: a through silicon via (TSV), the through silicon via (TSV) having a first RDL formed on a first side thereof and a second RDL formed on a second side thereof; a thin film inductor, the thin film inductor formed on the first RDL; and an integrated circuit die, the integrated circuit die coupled to the second RDL or the TFI.

[0109] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of forming an integrated circuit (IC) package, comprising: forming a thin film inductor (TFI) on the first dummy carrier wafer; attaching an integrated circuit (IC) die to and over the TFI; attaching a second dummy carrier wafer to and over the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to and beneath the TFI; as well as The second dummy carrier wafer is removed from the IC die.

2. The method according to claim 1, further comprising: forming a first adhesive layer on the first dummy carrier wafer; as well as A first electrically insulating layer is formed over the first adhesive layer.

3. The method of claim 2, wherein forming the TFI on the first dummy carrier wafer comprises: forming a first magnetic layer over the first electrically insulating layer; forming a first redistribution layer (RDL) over the first magnetic layer; forming an electrically insulating dome over the first RDL; as well as A second magnetic layer is formed over the electrically insulating dome.

4. The method according to claim 3, further comprising: A metallized via is formed into the first electrically insulating layer, wherein the first RDL is electrically coupled to the metallized via.

5. The method according to claim 3, further comprising: forming a first passivation layer over the first RDL; forming a metallized through hole through the first passivation layer; as well as A second RDL is formed over the first passivation layer and the metallized vias, wherein the second RDL is electrically coupled to the first RDL through the metallized vias.

6. The method according to claim 5, further comprising: forming a second passivation layer over the second RDL; forming an under bump metallization (UBM) through the second passivation layer and over the second RDL; as well as A solder bump is formed over the UBM, wherein the solder bump is electrically coupled to the first RDL via the UBM, the second RDL, and the metallized through-via.

7. The method of claim 1 , wherein attaching the second dummy carrier wafer to and over the IC die comprises: forming an adhesive layer over the IC die; as well as The second dummy carrier wafer is placed over the adhesive layer.

8. The method of claim 7, wherein the second dummy carrier wafer comprises a transparent material, and wherein removing the second dummy carrier wafer from the IC die comprises subjecting the adhesive layer to a laser via the second dummy carrier wafer to debond the adhesive layer from the IC die.

9. The method of claim 1 , wherein the TFI is attached to the first dummy carrier wafer by an adhesive layer, wherein the first dummy carrier wafer comprises a transparent material, and wherein removing the first dummy carrier wafer from the TFI comprises subjecting the adhesive layer to a laser via the first dummy carrier wafer to debond the adhesive layer from the TFI.

10. The method of claim 1, wherein the TFI comprises a collection of TFIs, wherein the IC die comprises a collection of IC dies respectively electrically coupled to the collection of TFIs, and the method further comprises: The IC package is diced to separate the different pairs of TFI and IC die.

11. The method of claim 1 , wherein the TFI comprises a set of TFIs, wherein the IC die comprises a set of different IC dies, wherein at least one of the sets of different IC dies is respectively electrically coupled to the set of TFIs, and the method further comprises: The IC package is diced to separate different pairs of TFIs and sets of different IC dies.

12. An integrated circuit (IC) package, comprising: at least one thin film inductor (TFI); a collection of integrated circuit (IC) dies, the collection of integrated circuit (IC) dies coupled to the at least one TFI; and A set of solder bumps is coupled to the at least one TFI.

13. The IC package of claim 12, wherein at least one IC die in the set of IC dies comprises an aluminum (AP) layer coupled to the first terminal of the at least one TFI.

14. The IC package of claim 13, wherein at least one solder bump in the set of solder bumps is coupled to the second terminal of the at least one TFI.

15. The IC package of claim 14, wherein the at least one TFI comprises: a first magnetic layer; a first redistribution layer (RDL) overlying and electrically isolated from the first magnetic layer, wherein a first portion and a second portion of the first RDL on opposite sides of the first magnetic layer serve as the first terminal and the second terminal of the at least one TFI, respectively; an electrically insulating dome located over the first RDL and the first magnetic layer; and A second magnetic layer is located on the electrically insulating dome, wherein the electrically insulating dome electrically isolates the second magnetic layer from the first RDL.

16. The IC package of claim 14, wherein the at least one solder bump in the set of solder bumps is coupled to the second terminal of the TFI through an under bump metallization (UBM), a second redistribution layer (RDL), and a metallized via through a passivation layer.

17. A method of forming an integrated circuit (IC) package, comprising: forming a first redistribution layer (RDL) over the through silicon via (TSV); forming a second RDL under the TSV; forming a thin film inductor (TFI) on the first RDL; as well as At least one integrated circuit (IC) die is attached to the second RDL or the TFI.

18. The method of claim 17, wherein forming the TFI over the first RDL comprises: forming an electrically insulating layer over the first RDL; forming a first magnetic layer over the electrically insulating layer; forming a third redistribution layer (RDL) over the first magnetic layer; forming an electrically insulating dome over the third RDL; as well as A second magnetic layer is formed over the electrically insulating dome.

19. The method of claim 18, wherein the electrically insulating dome comprises a polymer.

20. The method of claim 18, further comprising: A metallized through-hole is formed into the electrically insulating layer, wherein the first RDL and the third RDL are electrically coupled to the metallized through-hole.

21. The method of claim 18, further comprising: forming a first passivation layer over the third RDL; forming a metallized through hole through the first passivation layer; as well as A fourth RDL is formed over the first passivation layer and the metallized vias, wherein the fourth RDL is electrically coupled to the third RDL through the metallized vias.

22. The method according to claim 21, further comprising: forming a second passivation layer over the fourth RDL; forming an under bump metallization (UBM) through the second passivation layer and over the fourth RDL; as well as A solder bump is formed over the UBM, wherein the solder bump is electrically coupled to the third RDL via the UBM, the fourth RDL, and the metallized through-via.

23. The method of claim 22, wherein attaching the at least one IC die to the TFI comprises attaching the at least one IC die to the fourth RDL.

24. An integrated circuit (IC) package, comprising: Thin Film Inductor (TFI); an integrated circuit (IC) die coupled to a first terminal of the TFI; a solder bump coupled to a second terminal of the TFI; and A through silicon via (TSV) through which the IC die or the solder ball is coupled to the first terminal or the second terminal of the TFI, respectively.

25. The IC package of claim 24, wherein the IC die is coupled to the first terminal of the TFI through the TSV.

26. The IC package of claim 25, wherein the IC die is further coupled to the first terminal of the TFI through a first redistribution layer (RDL).

27. The IC package of claim 26, wherein the solder bump is coupled to the second terminal of the TFI through a second redistribution layer (RDL).

28. The IC package of claim 24, wherein the solder bump is coupled to the second terminal of the TFI through the TSV.

29. The IC package of claim 28, wherein the solder bump is further coupled to the second terminal of the TFI through a first redistribution layer (RDL).

30. The IC package of claim 29, wherein the IC is coupled to the first terminal of the TFI through a second redistribution layer (RDL).

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