Semiconductor device, manufacturing method thereof, and electronic device

Abstract

The present invention relates to a semiconductor device, a method for manufacturing the same, and an electronic device, wherein both the formation of a capacitance element and the reduction of parasitic capacitance can be realized. The semiconductor device includes: an internal electrode formed on a first surface side of a semiconductor substrate; a through hole formed in the semiconductor substrate at a position corresponding to the internal electrode; a first redistribution line formed on a second surface side of the semiconductor substrate opposite to the first surface side, and connected to the internal electrode via a via hole; a second redistribution line connected to the first redistribution line and formed closer to the external connection terminal than the first redistribution line; and an interlayer insulating film formed between the first redistribution line and the second redistribution line. Two internal electrodes including a first internal electrode and a second internal electrode are provided, and a capacitor is configured by a first redistribution line connected to the first internal electrode, a second redistribution line connected to the second internal electrode, and an interlayer insulating film. This disclosure can be applied, for example, to a solid-state imaging device or the like.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a manufacturing method thereof, and an electronic device, and more particularly to a semiconductor device, a manufacturing method thereof, and an electronic device capable of achieving both formation of a capacitance element and reduction of parasitic capacitance. Background Art

[0002] In the past, in order to achieve miniaturization of semiconductor devices, chip-size packaging has been adopted. Specifically, in a chip-size packaging type solid-state imaging device for achieving miniaturization of a camera module, a configuration has been adopted in which a logic substrate such as a driving element is bonded to the rear surface of an image sensor substrate, and a rewiring connected to an external connection terminal formed on the rear surface side of the logic substrate is connected to an internal electrode on the logic substrate side via a through hole penetrating a silicon substrate housing portion. At this time, the rewiring and the silicon substrate housing portion are electrically separated by an insulating film, but there are problems of signal delay due to parasitic capacitance between the rewiring and the silicon substrate housing portion, and changes in input / output response speed.

[0003] In order to suppress signal delay, it is conceivable to stabilize the potential by connecting a capacitance element to an internal electrode of a power supply voltage of a solid-state imaging device. For example, Patent Document 1 discloses a technique of forming a capacitance element in a through hole.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-141090 Summary of the invention

[0007] Problems to be solved by the present invention

[0008] However, the structure of the capacitor element disclosed in Patent Document 1 uses a wiring structure dedicated to the capacitor element formation, and in the case where these wirings are used for signal input and output, the parasitic capacitance of the wiring increases. In order to reduce the parasitic capacitance of the wiring, although it is necessary to increase the thickness of the insulating film between the electrodes, it is necessary to reduce the thickness of the capacitor in order to store charge, and both cannot be achieved.

[0009] The present disclosure has been made in view of such circumstances, and aims to achieve both formation of a capacitive element and reduction of parasitic capacitance.

[0010] Solution to the problem

[0011] A semiconductor device according to a first aspect of the present disclosure includes: an internal electrode formed on a first surface side of a semiconductor substrate;

[0012] a through hole formed at a position corresponding to an internal electrode of the semiconductor substrate;

[0013] a first redistribution wiring formed on a second surface side opposite to the first surface side of the semiconductor substrate and connected to the internal electrode via a through hole;

[0014] a second redistribution wiring connected to the first redistribution wiring and formed on a side closer to the external connection terminal than the first redistribution wiring; and

[0015] An interlayer insulating film is formed between the first redistribution wiring and the second redistribution wiring, wherein

[0016] Both a first internal electrode and a second internal electrode are provided as internal electrodes, and

[0017] The first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor.

[0018] A method for manufacturing a semiconductor device according to a second aspect of the present invention includes:

[0019] forming an internal electrode, the internal electrode being formed on the first surface side of the semiconductor substrate,

[0020] forming a through hole, the through hole being formed at a position corresponding to the internal electrode of the semiconductor substrate,

[0021] forming a first redistribution wiring which is formed on a second surface side opposite to the first surface side of the semiconductor substrate and is connected to the internal electrode via a through hole,

[0022] forming a second redistribution wiring which is connected to the first redistribution wiring and is formed on a side closer to the external connection terminal than the first redistribution wiring; and

[0023] An interlayer insulating film is formed between the first redistribution wiring and the second redistribution wiring, wherein

[0024] The first internal electrode and the second internal electrode are both formed as internal electrodes, and

[0025] The first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor.

[0026] An electronic device according to a third aspect of the present disclosure includes a semiconductor device, the semiconductor device including:

[0027] an internal electrode formed on the first surface side of the semiconductor substrate;

[0028] a through hole formed at a position corresponding to an internal electrode of the semiconductor substrate;

[0029] a first redistribution wiring formed on a second surface side opposite to the first surface side of the semiconductor substrate and connected to the internal electrode via a through hole;

[0030] a second redistribution wiring connected to the first redistribution wiring and formed on a side closer to the external connection terminal than the first redistribution wiring; and

[0031] an interlayer insulating film formed between the first redistribution wiring and the second redistribution wiring;

[0032] Both the first inner electrode and the second inner electrode are provided as inner electrodes, and

[0033] The first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor.

[0034] In the first to third aspects of the present invention, an internal electrode is formed on a first surface side of a semiconductor substrate; a through hole is formed at a position corresponding to the internal electrode of the semiconductor substrate; a first redistribution is formed on a second surface side opposite to the first surface side of the semiconductor substrate and is connected to the internal electrode via the through hole; a second redistribution is connected to the first redistribution and is formed on a side closer to an external connection terminal than the first redistribution; and an interlayer insulating film is formed between the first redistribution and the second redistribution, wherein both the first internal electrode and the second internal electrode are formed as internal electrodes, and the first redistribution connected to the first internal electrode, the second redistribution connected to the second internal electrode, and the interlayer insulating film constitute a capacitor.

[0035] A semiconductor device according to a fourth aspect of the present disclosure includes:

[0036] a first electrode connected to a redistribution wiring formed on the rear surface side of the semiconductor substrate;

[0037] a second electrode surrounding the periphery of the first electrode in a plan view; and

[0038] an insulating film between the first electrode and the second electrode, wherein

[0039] The first electrode, the second electrode, and the insulating film constitute a capacitor.

[0040] A method for manufacturing a semiconductor device according to a fifth aspect of the present invention includes:

[0041] forming a first electrode connected to a redistribution wiring formed on the rear surface side of the semiconductor substrate,

[0042] forming a second electrode, the second electrode surrounding the periphery of the first electrode in a plan view, and

[0043] An insulating film is formed between the first electrode and the second electrode, wherein

[0044] The first electrode, the second electrode, and the insulating film constitute a capacitor.

[0045] In the fourth and fifth aspects of the present disclosure, a first electrode connected to a rewiring formed on the rear surface side of a semiconductor substrate, a second electrode surrounding the first electrode in a plan view, and an insulating film between the first electrode and the second electrode are provided, and a capacitor is formed by the first electrode, the second electrode and the insulating film.

[0046] A semiconductor device according to a sixth aspect of the present disclosure includes:

[0047] a trench formed in the semiconductor substrate and having a side surface inclined at a predetermined angle;

[0048] At least two electrode films, a first electrode film and a second electrode film, are stacked in the trench; and

[0049] The dielectric film is formed at least between the first electrode film and the second electrode film, wherein

[0050] A first electrode film formed along the side surface of the trench is connected to a first redistribution wiring on the semiconductor substrate,

[0051] A second electrode film formed along a side surface of the trench is connected to another first redistribution wiring on the semiconductor substrate, and

[0052] The capacitor is formed by stacking a first electrode film, a dielectric film, and a second electrode film.

[0053] A seventh aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0054] forming a trench having a side surface inclined at a predetermined angle in a semiconductor substrate;

[0055] forming at least two electrode films, a first electrode film and a second electrode film, stacked in the groove;

[0056] A dielectric film is formed at least between the first electrode film and the second electrode film, wherein

[0057] forming a first electrode film formed along a side surface of the trench to be connected to a first redistribution wiring on the semiconductor substrate, and forming a second electrode film formed along a side surface of the trench to be connected to another first redistribution wiring on the semiconductor substrate, and

[0058] A capacitor is formed by stacking a first electrode film, a dielectric film, and a second electrode film.

[0059] In the sixth and seventh aspects of the present invention, a groove is provided, which is formed in a semiconductor substrate and has a side surface inclined at a predetermined angle; at least two electrode films, the at least two electrode films are a first electrode film and a second electrode film stacked in the groove, and also include a dielectric film formed at least between the first electrode film and the second electrode film, the first electrode film formed along the side surface of the groove is connected to a first redistribution wiring on the semiconductor substrate, the second electrode film formed along the side surface of the groove is connected to another first redistribution wiring on the semiconductor substrate, and a capacitor, a dielectric film and a second electrode film are formed by stacking the first electrode film.

[0060] Semiconductor devices and electronic devices may be independent devices or modules incorporated into other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 It is a cross-sectional view of the overall configuration of a first embodiment of a solid-state imaging device to which the present technology is applied.

[0062] Figure 2 is a cross-sectional view showing a detailed structure of a capacitor according to a first configuration example.

[0063] Figure 3 2 is a diagram for describing a method of manufacturing a capacitor according to a first configuration example.

[0064] Figure 4 2 is a diagram for describing a method of manufacturing a capacitor according to a first configuration example.

[0065] Figure 5 2 is a diagram for describing a method of manufacturing a capacitor according to a first configuration example.

[0066] Figure 6 is a cross-sectional view showing a detailed structure of a capacitor according to a second configuration example.

[0067] Figure 7 2 is a diagram describing a first method of manufacturing a solid-state imaging device including a capacitor according to a second configuration example.

[0068] Figure 8 2 is a diagram describing a first method of manufacturing a solid-state imaging device including a capacitor according to a second configuration example.

[0069] Fig. 9 2 is a diagram describing a second method of manufacturing the solid-state imaging device including the capacitor according to the second configuration example.

[0070] Fig.10 2 is a diagram describing a second method of manufacturing the solid-state imaging device including the capacitor according to the second configuration example.

[0071] Fig.11 2 is a diagram for describing a third method of manufacturing the solid-state imaging device including the capacitor according to the second configuration example.

[0072] Fig.12 2 is a diagram for describing a third method of manufacturing the solid-state imaging device including the capacitor according to the second configuration example.

[0073] Fig.13 is a cross-sectional view showing a detailed structure of a capacitor according to a third configuration example.

[0074] Fig.14 2 is a diagram for describing a method of manufacturing a solid-state imaging device including a capacitor according to a third configuration example.

[0075] Fig.15 2 is a diagram for describing a method of manufacturing a solid-state imaging device including a capacitor according to a third configuration example.

[0076] Fig.16 is a cross-sectional view showing a detailed structure of a capacitor according to a fourth configuration example.

[0077] Fig.17 2 is a diagram for describing a method of manufacturing a solid-state imaging device including a capacitor according to a fourth configuration example.

[0078] Fig.18 2 is a diagram for describing a method of manufacturing a solid-state imaging device including a capacitor according to a fourth configuration example.

[0079] Fig.19 is a cross-sectional view showing a detailed structure of a capacitor according to a fifth configuration example.

[0080] Fig. 20 2 is a diagram for describing a method of manufacturing a solid-state imaging device including a capacitor according to a fifth configuration example.

[0081] Fig.21 is a cross-sectional view showing a detailed structure of a capacitor according to a sixth configuration example.

[0082] Fig. 22 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a sixth configuration example.

[0083] Fig.23 is a cross-sectional view showing a detailed structure of a capacitor according to a seventh configuration example.

[0084] Fig.24 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a seventh configuration example.

[0085] Fig.252 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a seventh configuration example.

[0086] Fig.26 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a seventh configuration example.

[0087] Fig. 27 is a cross-sectional view showing a detailed structure of a capacitor according to an eighth configuration example.

[0088] Fig.28 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eighth configuration example.

[0089] Fig.29 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eighth configuration example.

[0090] Fig.30 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eighth configuration example.

[0091] Fig.31 is a cross-sectional view showing a detailed structure of a capacitor according to a ninth configuration example.

[0092] Fig.32 is a plan view of a capacitor according to a ninth configuration example.

[0093] Fig.33 It is a cross-sectional view of the entire configuration of a tenth embodiment of a solid-state imaging device to which the present technology is applied.

[0094] Fig.34 is a plan view of a solid-state imaging device 1 according to a tenth embodiment.

[0095] Fig.35 is a cross-sectional view of a solid-state imaging device having a stacked structure in which three substrates are stacked.

[0096] Fig.36 is a cross-sectional view showing a detailed structure of a capacitor according to an eleventh configuration example.

[0097] Fig.37 is a cross-sectional view showing a detailed structure of a capacitor according to an eleventh configuration example.

[0098] Fig.38 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0099] Fig.39 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0100] Fig.40 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0101] Fig.41 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0102] Fig.42 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0103] Fig.43 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0104] Fig.44 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0105] Fig.45 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0106] Fig.46 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to an eleventh configuration example.

[0107] Fig.47 is a cross-sectional view of a solid-state imaging device according to a twelfth embodiment.

[0108] Fig.48 When viewed from the rear surface side of the solid-state imaging device Fig.47 A plan view of the vicinity of the capacitor in FIG.

[0109] Fig.49 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0110] Fig.50 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0111] Fig.51 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0112] Fig.52 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0113] Fig.53 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0114] Fig.54 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0115] Fig.55 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0116] Fig.56 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0117] Fig.57 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a twelfth configuration example.

[0118] Fig.58 is a cross-sectional view showing a detailed structure of a first modification example of the capacitor according to the twelfth configuration example.

[0119] Fig.59 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0120] Fig.60 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0121] Fig.61 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0122] Fig.62 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0123] Fig.63 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0124] Fig.64 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0125] Fig.65 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0126] Fig.66 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0127] Fig.67 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0128] Fig.68 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a first modification example of the twelfth configuration example.

[0129] Fig.69 is a cross-sectional view showing a detailed structure of a second modification example of the capacitor according to the twelfth configuration example.

[0130] Fig.70 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a second modification example of the twelfth configuration example.

[0131] Fig.71 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a second modification example of the twelfth configuration example.

[0132] Fig.72 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a second modification example of the twelfth configuration example.

[0133] Fig.73 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a second modification example of the twelfth configuration example.

[0134] Fig.74 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a second modification example of the twelfth configuration example.

[0135] Fig.75 2 is a diagram describing a method of manufacturing a solid-state imaging device including a capacitor according to a second modification example of the twelfth configuration example.

[0136] Fig.76 is a cross-sectional view showing a detailed structure of a third modification example of the capacitor according to the twelfth configuration example.

[0137] Fig.77 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a third modification example of the twelfth configuration example.

[0138] Fig.78 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a third modification example of the twelfth configuration example.

[0139] Fig.792 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a third modification of the twelfth configuration example.

[0140] Fig.80 2 is a view describing a method of manufacturing a solid-state imaging device including a capacitor according to a third modification example of the twelfth configuration example.

[0141] Fig.81 is a cross-sectional view of a solid-state imaging device according to a thirteenth embodiment.

[0142] Fig.82 It is shown Fig.81 A cross-sectional view of a first configuration example of the internal electrodes on the left side.

[0143] Fig.83 It is a plan view of the grid pattern wiring.

[0144] Fig.84 It is shown in Fig.81 A cross-sectional view of a second configuration example of the internal electrode on the left side.

[0145] Fig.85 It is shown Fig.81 A cross-sectional view of a first configuration example of the internal electrodes on the right side.

[0146] Fig.86 It passes through Fig.85 A plan view of a grid pattern wiring in a cross-sectional view.

[0147] Fig.87 It is shown Fig.81 The right side is a cross-sectional view of a second configuration example of the internal electrode.

[0148] Fig.88 It is shown Fig.81 2 is a cross-sectional view of a third configuration example of the internal electrode on the right side.

[0149] Fig.89 It is shown Fig.81 2 is a cross-sectional view of a fourth configuration example of the internal electrode on the right side.

[0150] Fig.90 It passes through Fig.89 A plan view of a predetermined grid pattern wiring of internal electrodes.

[0151] Fig.91 It is a cross-sectional view of a cylindrical MIM capacitor.

[0152] Fig.92 yes Fig.91 Simplified conceptual diagram of a cylindrical MIM capacitor.

[0153] Fig.93 Is a description Fig.91 FIG. 1 is a view of a manufacturing method of a cylindrical MIM capacitor.

[0154] Fig.94 Is a description Fig.91 FIG. 1 is a view of a manufacturing method of a cylindrical MIM capacitor.

[0155] Fig.95 Is a description Fig.91 FIG. 1 is a view of a manufacturing method of a cylindrical MIM capacitor.

[0156] Fig.96 Is a description Fig.91 FIG. 1 is a view of a manufacturing method of a cylindrical MIM capacitor.

[0157] Fig.97 Is a description Fig.91 FIG. 1 is a view of a manufacturing method of a cylindrical MIM capacitor.

[0158] Fig.98 Is a description Fig.91 FIG. 1 is a view of a manufacturing method of a cylindrical MIM capacitor.

[0159] Fig.99 Is a description Fig.91 FIG. 1 is a view of a manufacturing method of a cylindrical MIM capacitor.

[0160] Fig.100 It is a cross-sectional view of a cylindrical MIM double-layer capacitor.

[0161] Fig.101 Is a description Fig.100 FIG. 1 is a view of a manufacturing method of a cylindrical MIM double-layer capacitor. FIG.

[0162] Fig.102 Is a description Fig.100 FIG. 1 is a view of a manufacturing method of a cylindrical MIM double-layer capacitor. FIG.

[0163] Fig.103 Is a description Fig.100 FIG. 1 is a view of a manufacturing method of a cylindrical MIM double-layer capacitor. FIG.

[0164] Fig.104 Is a description Fig.100 FIG. 1 is a view of a manufacturing method of a cylindrical MIM double-layer capacitor. FIG.

[0165] Fig.105 Is a description Fig.100 FIG. 1 is a view of a manufacturing method of a cylindrical MIM double-layer capacitor. FIG.

[0166] Fig.106 Is a description Fig.100 FIG. 1 is a view of a manufacturing method of a cylindrical MIM double-layer capacitor. FIG.

[0167] Fig.107 For description Fig.100 FIG. 1 is a view of a manufacturing method of a cylindrical MIM double-layer capacitor. FIG.

[0168] Fig.108 is a cross-sectional view showing an example in which a cylindrical MIM capacitor is applied to a single-plate front surface irradiation type solid-state imaging device.

[0169] Fig.109 is a cross-sectional view of a solid-state imaging device according to a fourteenth embodiment.

[0170] Fig.110 is an enlarged view showing a detailed structure of a capacitor according to a fourteenth configuration example.

[0171] Fig.111 2 is a view describing a method of manufacturing a capacitor according to a fourteenth configuration example.

[0172] Fig.112 2 is a view describing a method of manufacturing a capacitor according to a fourteenth configuration example.

[0173] Fig.113 2 is a view describing a method of manufacturing a capacitor according to a fourteenth configuration example.

[0174] Fig.114 2 is a view describing a method of manufacturing a capacitor according to a fourteenth configuration example.

[0175] Fig.115 2 is a view describing a method of manufacturing a capacitor according to a fourteenth configuration example.

[0176] Fig.116 is a cross-sectional view of a capacitor according to a modification of the fourteenth configuration example.

[0177] Fig.117 is a cross-sectional view of a capacitor according to a modification of the fourteenth configuration example.

[0178] Fig.118 To show Fig.110 A plan view of an example configuration in which capacitors are connected in parallel.

[0179] Fig.119 2 is a view showing another configuration example of the capacitor according to the fourteenth configuration example.

[0180] Fig.120 It is a cross-sectional view showing a modification of the solid-state imaging device according to the fourteenth embodiment.

[0181] Fig.121 is a diagram describing a usage example of an image sensor.

[0182] Fig.122 It is a block diagram showing a configuration example of an imaging device as an electronic device to which the technology of the present disclosure is applied.

[0183] Fig.123 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0184] Fig.124 is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU).

[0185] Fig.125 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0186] Fig.126 It is an explanatory diagram for explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0187] Hereinafter, a mode for carrying out the technology of the present disclosure (hereinafter, referred to as an embodiment) will be described with reference to the drawings. The description will be given in the following order.

[0188] 1. First Embodiment of Solid-State Imaging Device

[0189] 2. Detailed configuration of the first configuration example of the capacitor

[0190] 3. Method of manufacturing capacitor according to first configuration example

[0191] 4. Second configuration example of capacitor

[0192] 5. First Manufacturing Method of Capacitor According to Second Configuration Example

[0193] 6. Second Manufacturing Method of Capacitor According to Second Configuration Example

[0194] 7. Third Manufacturing Method of Capacitor According to Second Configuration Example

[0195] 8. Third configuration example of capacitor

[0196] 9. Method of manufacturing capacitor according to third configuration example

[0197] 10. Fourth configuration example of capacitor

[0198] 11. Method for manufacturing capacitor according to fourth configuration example

[0199] 12. Fifth configuration example of capacitor

[0200] 13. Method of manufacturing capacitor according to fifth configuration example

[0201] 14. Sixth configuration example of capacitor

[0202] 15. Manufacturing method of capacitor according to sixth configuration example 16. Seventh configuration example of capacitor

[0203] 17. Manufacturing method of capacitor according to seventh configuration example 18. Eighth configuration example of capacitor

[0204] 19. Manufacturing method of capacitor according to eighth configuration example 20. Ninth configuration example of capacitor

[0205] 21. Tenth Embodiment of Solid-State Imaging Device

[0206] 22. Overview of the First to Tenth Embodiments

[0207] 23. Three-layer stack configuration example

[0208] 24. Eleventh Configuration Example of Capacitor 25. Method of Manufacturing Capacitor According to Eleventh Configuration Embodiment 26. Twelfth Configuration Example of Capacitor

[0209] 27. Manufacturing method of capacitor according to twelfth configuration example 28. Modification 1 of twelfth configuration example

[0210] 29. Method for manufacturing capacitor of variation 1 of the twelfth configuration example 30. Variation 2 of the twelfth configuration example

[0211] 31. Method for manufacturing capacitor of variation 2 of twelfth configuration example 32. Variation 3 of twelfth configuration example

[0212] 33. Method for manufacturing capacitor of variation 3 of twelfth configuration example 34. Configuration example of 13 capacitor 35. Cross section of lead-out electrode connection of cylindrical MIM capacitor Fig.36 .Method for manufacturing cylindrical MIM capacitor 37.Connection cross section of lead electrode of cylindrical MIM double layer capacitor Fig.38 .Method for manufacturing cylindrical MIM double-layer capacitor 39. Fourteenth configuration example of capacitor

[0213] 40. Method for manufacturing capacitor according to fourteenth configuration example

[0214] 41. Modification of the Fourteenth Configuration Example

[0215] 42. Combination of the capacitor according to the fourteenth configuration example and another capacitor

[0216] 43.Examples of using image sensors

[0217] 44.Application examples of electronic devices

[0218] 45.Application examples of endoscopic surgery systems

[0219] 46. ​​Application examples of mobile objects

[0220] It should be noted that in the drawings mentioned in the following description, the same or similar parts are represented by the same or similar reference numerals, and their description will not be repeated as appropriate. The drawings are schematic, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. are different from the actual. In addition, the drawings may include parts with different size relationships and ratios.

[0221] In addition, the definition of directions in the following description (such as up and down directions, etc.) is only for the convenience of description and does not limit the technical concept of the present disclosure. For example, when observing an object by rotating the object by 90°, up and down are converted into left and right and read as left, and when observing an object by rotating the object by 180°, up and down are reversed and read.

[0222] Hereinafter, an embodiment of a solid-state imaging device to which the present technology is applied will be described, but the present technology can be applied to all semiconductor devices.

[0223] <1. First Embodiment of Solid-State Imaging Device>

[0224] Figure 1 It is a cross-sectional view of the overall configuration of a first embodiment of a solid-state imaging device to which the present technology is applied.

[0225] Figure 1 The solid-state imaging device 1 shown in FIG. 1 is a chip size package type CMOS solid-state imaging device configured by stacking a sensor substrate 11 and a logic substrate 12. The sensor substrate 11 and the logic substrate 12 are bonded via surfaces indicated by a one-dot chain line.

[0226] The sensor substrate 11 includes a semiconductor substrate 21 (hereinafter, referred to as a silicon substrate 21) composed of, for example, silicon (Si), and a photodiode 22 as a photoelectric conversion element is formed in units of pixels on the silicon substrate 21. In the drawings, a planarization film 23, a lens layer 24, an interlayer insulating film 25, a bonding resin 26, and a light-transmitting substrate 27 are stacked on one surface of the silicon substrate 21 on the upper side.

[0227] In the lens layer 24 on the upper side of the photodiode 22 formed in units of pixels, an on-chip lens 28 is formed in units of pixels. The on-chip lens 28 is formed on the upper side of the planarization film 23 formed on the upper surface of the silicon substrate 21, and the upper side of the on-chip lens 28 is formed flatly by the interlayer insulating film 25. The interlayer insulating film 25 is formed of a material having a refractive index lower than that of the material of the on-chip lens 28, and a refractive index difference is set between the on-chip lens 28 and the interlayer insulating film 25 on the on-chip lens 28, thereby increasing the light collecting capability of the on-chip lens 28.

[0228] The light-transmitting substrate 27 is bonded to the upper side of the interlayer insulating film 25 via a bonding resin 26. The light-transmitting substrate 27 is a light-transmitting substrate such as a glass substrate. The light-transmitting substrate 27 also has a function of protecting the on-chip lens 28.

[0229] The surface on which the on-chip lens 28 and the like are formed is the front surface of the sensor substrate 11 and is a light incident surface on which incident light is to be incident. The logic substrate 12 is bonded to the rear surface side of the sensor substrate 11 .

[0230] The logic substrate 12 includes a semiconductor substrate 31 (hereinafter, referred to as a silicon substrate 31) composed of, for example, silicon (Si), and a multilayer wiring layer 32 is formed on a first surface side (sensor substrate 11 side) of the silicon substrate 31, the first surface side being the upper side in the figure. The multilayer wiring layer 32 includes a plurality of metal wiring layers (not shown) including at least an internal electrode 33 and an interlayer insulating film 34 therebetween. Figure 1 In the example of , two internal electrodes 33A and 33B are formed. The internal electrodes 33A and 33B are used as receiving portions in the logic substrate 12 corresponding to the solder bumps 47A and 47B, which are external connection terminals formed on the rear surface of the logic substrate 12, respectively.

[0231] Two interlayer insulating films and two redistribution wirings are formed on the second surface side opposite to the first surface side of the silicon substrate 31 on which the multilayer wiring layer 32 is formed. Specifically, a first interlayer insulating film 41, a first redistribution wiring 42, a second interlayer insulating film 43, and a second redistribution wiring 44 are formed in sequence from the silicon substrate 31 side. The first surface side of the silicon substrate 31 on which the multilayer wiring layer 32 is formed corresponds to the front side of the silicon substrate 31, and the second surface side on which the two interlayer insulating films and the redistribution wirings are formed corresponds to the rear surface side of the silicon substrate 31.

[0232] exist Figure 1, corresponding to the two internal electrodes 33A and 33B, the reference numerals of the first redistribution 42, the second redistribution 44, and the solder bump 47 are distinguished. Specifically, the first redistribution 42, the second redistribution 44, and the solder bump 47 connected to the internal electrode 33A are the first redistribution 42A, the second redistribution 44A, and the solder bump 47A, and the first redistribution 42, the second redistribution 44, and the solder bump 47 connected to the internal electrode 33B are the first redistribution 42B, the second redistribution 44B, and the solder bump 47B.

[0233] In a plan view, the solid-state imaging device 1 is divided into a pixel region 71 at the center of a rectangular chip region and a peripheral region 72 at the periphery thereof. In the pixel region 71, pixels having photodiodes 22 are arranged in a matrix form, and in the peripheral region 72, for example, a drive control unit (not shown) that drives each pixel and the like are arranged. Figure 1 In the example of FIG. 1 , the solder bumps 47 as the external connection terminals are arranged in the peripheral area 72 , but the solder bumps 47 may be arranged in the entire area of ​​the rear surface of the logic substrate 12 .

[0234] In the silicon substrate 31, a through hole 45 as a through silicon via (TSV) is formed corresponding to the internal electrode 33 in the multilayer wiring layer 32 formed on the front surface side. More specifically, a through hole 45A is formed at a position corresponding to the internal electrode 33A, and a through hole 45B is formed at a position corresponding to the internal electrode 33B.

[0235] The first interlayer insulating film 41 is formed on the side wall (inner peripheral surface) of the through hole 45A, and the through hole 45A is formed at a position corresponding to the internal electrode 33A and the rear surface side of the silicon substrate 31. The first interlayer insulating film 41 electrically insulates the first redistribution wiring 42A from the silicon substrate 31. The first redistribution wiring 42A is formed on the rear surface side of the silicon substrate 31 and the side wall (inner peripheral surface) of the through hole 45A, and is connected to the internal electrode 33A formed in the multilayer wiring layer 32 on the front surface side. In addition, the first redistribution wiring 42A is also connected to the second redistribution wiring 44A embedded in the through hole 46A penetrating the second interlayer insulating film 43. The solder bump 47A is formed on the upper surface ( Figure 1 on a portion of the lower surface of the .

[0236] Therefore, the first redistribution 42A is connected to the internal electrode 33A formed on the front surface side of the silicon substrate 31, and is also connected to the solder bump 47A via the second redistribution 44A. For the first redistribution 42B, the second redistribution 44B, the through hole 46B, and the solder bump 47B connected to the internal electrode 33B, similarly, the first redistribution 42B is connected to the internal electrode 33B formed on the front surface side of the silicon substrate 31, and is also connected to the solder bump 47B via the second redistribution 44B. The area other than the solder bumps 47A and 47B on the rear surface side of the logic substrate 12 is covered with a protective film 48. As a material of the protective film 48, for example, a solder resist is used, which is an organic material.

[0237] The internal electrodes 33A and 33B, the first redistribution wirings 42A and 42B, and the second redistribution wirings 44A and 44B may be formed of, for example, copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium-tungsten alloy (TiW), polysilicon, etc. The first interlayer insulating film 41 and the second interlayer insulating film 43 are formed of, for example, a SiO2 film, a Low-k film (low dielectric constant insulating film), a SiOC film, etc.

[0238] Solder bumps 47A and 47B are external connection terminals for inputting and outputting power supply voltage, ground line (GND) or various signals (e.g., pixel signals and control signals) to and from an external module board.

[0239] For example, in Figure 1 The solder bump 47A on the left side is an external connection terminal that receives a power supply voltage from an external module board. Since the internal electrode 33A is connected to the solder bump 47A via the first redistribution layer 42A and the second redistribution layer 44A, the power supply voltage supplied to the solder bump 47A is absorbed into the internal electrode 33A on the multilayer wiring layer 32 side.

[0240] On the other hand, the right solder bump 47B is an external connection terminal for outputting a signal to an external module board, for example. Since the internal electrode 33B is connected to the solder bump 47B via the first redistribution 42B and the second redistribution 44B, the signal generated in the solid-state imaging device 1 is output from the solder bump 47B to the outside.

[0241] When the left solder bump 47A side to which the power supply voltage is supplied is compared with the solder bump 47B side to which the signal is output, the capacitor 51A is formed on the solder bump 47A side. The capacitor 51A includes a first redistribution 42A, another second redistribution 44C formed in the same layer as the second redistribution 44A, and a second interlayer insulating film 43 therebetween. That is, the capacitor 51A is a parallel plate capacitor (MIM capacitor) using the first redistribution 42A and the second redistribution 44C formed on the rear surface side of the logic substrate 12 (silicon substrate 31) as capacitor electrodes. The second redistribution 44C is connected to another internal electrode 33C ( Figure 2 ) will be referenced later. Figure 2 Detailed description.

[0242] The first rewiring 42B and the second rewiring 44B which are rewiring connected to the solder bump 47B which serves as the signal output terminal are electrically separated from the silicon substrate 31 by the first interlayer insulating film 41, but are affected by the signal delay (increase in signal rise time and signal fall time) and noise of the silicon substrate 31 due to the parasitic capacitance therebetween, and jitter may occur.

[0243] As a method of suppressing the influence of signal delay and jitter, there is a method of connecting a capacitive element to the internal electrode 33A of the power supply voltage to stabilize the potential. The solid-state imaging device 1 has a configuration in which a planar capacitor 51A is formed by a first redistribution wiring 42A connected to the internal electrode 33A connected to the power supply voltage, a second redistribution wiring 44C formed in the same layer as the second redistribution wiring 44A, and a second interlayer insulating film 43 therebetween, thereby improving signal delay and jitter.

[0244] The capacitor 51A is the capacitor 51 included in the solid-state imaging device 1 of the first embodiment, and is a first configuration example of the capacitor 51, which uses the first rewiring 42 connected to the internal electrode 33A connected to the power supply voltage as one of the capacitance electrodes. Similarly, the capacitors 51 included in the solid-state imaging devices 1 of the second to tenth embodiments will be referred to as the second to tenth configuration examples of the capacitor 51, and will be described using different reference numerals such as capacitors 51B to 51K.

[0245] <2. Detailed Configuration of First Configuration Example of Capacitor>

[0246] Figure 2 : is a cross-sectional view showing a detailed structure of a capacitor 51A according to a first configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the first embodiment. Figure 2 is a cross-sectional view of only the logic substrate 12, and corresponds to a cross-sectional view from a different Figure 1 Viewed from the direction Figure 1 5A is a cross-sectional view of capacitor 51A.

[0247] The capacitor 51A is configured such that the first redistribution 42A and the second redistribution 44C face each other via the second interlayer insulating film 43. The material of the second interlayer insulating film 43 may be, for example, a silicon oxide film, and the film thickness of the second interlayer insulating film 43 is, for example, about 5 μm to 10 μm. The first redistribution 42A constituting one of the pair of capacitor electrodes is connected to the internal electrode 33A via a through hole 45A opened in the silicon substrate 31. Figure 1 The second redistribution wiring 44A and the solder bump 47A connected to the first redistribution wiring 42A are located from Figure 2 Areas that cannot be seen in the cross-sectional direction are not shown.

[0248] The other second redistribution 44C constituting a pair of capacitor electrodes is connected to the first redistribution 42C via a through hole 46C penetrating the second interlayer insulating film 43, and the first redistribution 42C is connected to the internal electrode 33C via a through hole 45C opened in the silicon substrate 31. Therefore, the second redistribution 44C constituting the other capacitor electrode of the capacitor 51A is a second redistribution of the internal electrode 33C different from the internal electrode 33A.

[0249] As mentioned above, through Figure 1 The solder bump 47A and the second rewiring 44A in the capacitor 51A provide a power supply voltage to the first rewiring 42A constituting one capacitor electrode of the capacitor 51A. On the other hand, the second rewiring 44C constituting the other capacitor electrode of the capacitor 51A is connected to the ground line, and the capacitor 51A functions as a capacitor element for suppressing fluctuations in the power supply voltage.

[0250] As a capacitor element for suppressing fluctuations in power supply voltage, for example, a method of forming a capacitor element in the multilayer wiring layer 32 of the logic substrate 12 is considered. However, the logic substrate 12 has a large area limitation, and mounting a large capacitor element has a large influence on the high integration of the circuit, and therefore, it is easy to assume that there is a problem in future chip size reduction, etc. Therefore, it is desirable to reduce the mounting area of ​​the capacitor element as much as possible.

[0251] The capacitor 51A is not formed in the multilayer wiring layer 32 but is formed on the external connection terminal side, so it does not affect the high integration of the circuit formed in the multilayer wiring layer 32. By replacing the capacitive element formed in the multilayer wiring layer 32 with the capacitor 51A, the circuit area of ​​the multilayer wiring layer 32 can be effectively utilized. In addition, when the capacitor 51A is added to the capacitive element formed in the multilayer wiring layer 32, a higher capacitance can be achieved.

[0252] <3. Method of Manufacturing Capacitor According to First Configuration Example>

[0253] Next, we will refer to Figures 3 to 5 Description includes Figure 2 The method for manufacturing the solid-state imaging device 1 of the capacitor 51A shown in FIG. Figures 3 to 5 The cross-sectional view shown in Figure 1 and Figure 2 Shown in the same direction (i.e., in the direction in which the light incident surface of the solid-state imaging device 1 is the upper surface), in the manufacturing step, since the surface of the silicon substrate 31 on one side of which the solder bump 47 is formed as an external connection terminal is processed as the upper surface, the lower surface of the substrate or film in the drawings will also be referred to as the upper surface.

[0254] First, if Figure 3 As shown in FIG. 1A , a multilayer wiring layer 32 is formed on a first surface of a silicon substrate 31 on the sensor substrate 11 side. The multilayer wiring layer 32 includes a plurality of metal wiring layers (not shown) including at least two internal electrodes 33A and 33C and an interlayer insulating film 34 therebetween.

[0255] Next, if Figure 3 As shown in FIG. 1B , through holes 45A and 45C penetrating the silicon substrate 31 are formed at positions corresponding to the internal electrodes 33A and 33C, respectively. The through holes 45A and 45C are formed to reach the internal electrodes 33A and 33C, respectively, and a portion of the upper surface of the internal electrodes 33A and 33C is exposed.

[0256] Then, if Figure 3 As shown in FIG. C, a first interlayer insulating film 41 is formed on the upper surface of the silicon substrate 31 and the side walls of the through holes 45A and 45C. For example, the first interlayer insulating film 41 may be formed by forming the first interlayer insulating film 41 on the entire upper surface of the silicon substrate 31 and the bottom surfaces and side walls of the through holes 45A and 45C, and then etching back to remove only the bottom surfaces of the through holes 45A and 45C.

[0257] Next, if Figure 4 As shown in A, the first redistribution 42A connected to the internal electrode 33A and the first redistribution 42C connected to the internal electrode 33C are formed at the same time. The material of the first redistribution 42A and 42C is, for example, copper. In this case, for example, the first redistribution 42A and 42C can be formed by forming a resist material having an opening pattern in a predetermined area, and using the formed resist material as a mask, forming a copper film by electroplating. The film thickness of the first redistribution 42A and 42C is, for example, about several μm to several tens of μm.

[0258] Then, if Figure 4As shown in FIG. 1B, a second interlayer insulating film 43 is formed on the upper surface of the first redistribution wiring 42A, 42C, and on the upper surface of the first interlayer insulating film 41 where the first redistribution wiring 42A, 42C is not formed. As the material of the second interlayer insulating film 43, an organic material such as a solder resist, an inorganic material such as a silicon oxide film (SiO2 film), etc. can be used. The solder resist can be formed using a coating device, and the silicon oxide film can be formed using, for example, vapor phase growth (chemical vapor deposition, hereinafter referred to as CVD), atomic layer deposition (atomic layer deposition, hereinafter referred to as ALD), etc.

[0259] The second interlayer insulating film 43 is formed so as to be deposited in the through holes 45A and 45C with a uniform film thickness.

[0260] The film thickness of the second interlayer insulating film 43 may be several nm to several tens of μm.

[0261] Then, if Figure 4 As shown in C, a through hole 46C penetrating the second interlayer insulating film 43 is formed in a prescribed area of ​​the first redistribution wiring 42C. In the case where the second interlayer insulating film 43 is a solder resist of a photosensitive material or the like, the through hole 46C can be formed by photolithography. In addition, for example, in the case where the second interlayer insulating film 43 is a silicon oxide film, the through hole 46C can be formed by forming a resist pattern by photolithography and dry etching the second interlayer insulating film 43 using the resist pattern as a mask. Note that although Figure 4 C is not shown, through hole 46A ( Figure 1 ) is also formed on the first redistribution wiring 42A on the internal electrode 33A side simultaneously with the through hole 46C.

[0262] Then, if Figure 5 As shown in A, a second redistribution 44C is formed in a predetermined area of ​​the second interlayer insulating film 43 and inside the through hole 46C. Similar to the first redistribution 42A, the material of the second redistribution 44C can also be copper. The method for forming the second redistribution 44C is also the same as the method for forming the first redistribution 42A. The film thickness of the second redistribution 44C is, for example, several μm to several tens of μm. Note that although Figure 5 Although not shown in A, the second redistribution wiring 44A on the internal electrode 33A side is also formed simultaneously with the second redistribution wiring 44C.

[0263] Then, if Figure 5 As shown in FIG. 1B, a protective film 48 is formed on the upper surface of the second redistribution wiring 44C and on the upper surface of the second interlayer insulating film 43 where the second redistribution wiring 44C is not formed. As a material of the protective film 48, for example, a solder resist is used, which is an organic material. As the solder resist, it is desirable to use a photosensitive solder resist to provide an insulating film opening for arranging the solder bump 47 in the next step.

[0264] Next, although not shown, an insulating film opening is formed by opening the protective film 48 in the region where the solder bumps 47A and 47B are arranged, and the solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0265] Through the above steps, manufacturing includes Figure 2 The logic substrate 12 of the capacitor 51A of the first configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0266] In the manufacturing method of the solid-state imaging device 1 including the capacitor 51A according to the first configuration example, the first redistribution wiring 42A and the second redistribution wiring 44C are a pair of capacitor electrodes, and the second interlayer insulating film 43 formed between the redistribution wirings is a capacitor film, so that the formation of the capacitor 51A and the formation of the wiring to the solder bump 47 serving as the external connection terminal can be performed simultaneously without adding a dedicated process for forming the capacitor.

[0267] <4. Second Configuration Example of Capacitor>

[0268] Figure 6 2 is a cross-sectional view showing a detailed structure of a capacitor 51B according to a second configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the second embodiment.

[0269] Among the second to ninth configuration examples of the capacitor 51 described below, only the capacitor corresponding to the first configuration example is shown. Figure 2 The cross-sectional view of Figure 1 The electrical connection between the solder bump 47 and the internal electrode 33 is similar to Figure 1 The electrical connections are similar to those in the first configuration example shown in FIG. Figure 6 In the following drawings, the same reference numerals are given to the same components as those of the solid-state imaging device 1 of the first embodiment, and the description of the components will be appropriately omitted, and different portions will be focused on and described.

[0270] Figure 6 The capacitor 51B of the illustrated second configuration example is common to the capacitor 51A of the first configuration example in that the first redistribution wiring 42A and the second redistribution wiring 44C are a pair of capacitance electrodes, and the second interlayer insulating film 43 formed between these redistributions is a capacitance film.

[0271] On the other hand, the capacitor 51B according to the second configuration example is different from the first configuration example in which the film thickness of the second interlayer insulating film 43 is the same as the film thickness of the second interlayer insulating film 43 in another region in that the capacitor includes an interlayer thin film portion 111 in which the film thickness of the second interlayer insulating film 43 is formed to be thinner than the film thickness of the second interlayer insulating film 43 in another region. The film thickness of the thin second interlayer insulating film 43 of the capacitor 51B is equal to or less than 500 nm, and preferably about 10 nm to 200 nm.

[0272] According to the capacitor 51B of the second configuration example thus constituted, since the film thickness of the second interlayer insulating film 43 as a capacitance film is formed to be thin, a high electrostatic capacitance can be obtained compared to the first configuration example. The parasitic capacitance between the first rewiring 42A and the second rewiring 44C in the region other than the capacitor 51B does not change from the first configuration example. Therefore, the capacitance of the capacitance element can be increased for stabilizing the power supply voltage while suppressing the signal delay caused by the parasitic capacitance of the rewiring.

[0273] <5. First Manufacturing Method of Capacitor According to Second Configuration Example>

[0274] Next, we will refer to Figure 7 and Figure 8 Description includes Figure 6 A first manufacturing method of the solid-state imaging device 1 of the capacitor 51B of the second configuration example shown in FIG.

[0275] After the first rewiring lines 42A and 42C are formed in the capacitor 51A of the first configuration example described above, Figure 7 A and Figure 4 The same as A. Until the formation Figure 7 The steps of the first rewiring 42A and 42C in A are similar to those of the first configuration example. Figure 3 A to Figure 4 The steps described in A.

[0276] Then, if Figure 7 As shown in FIG. 1B, a second interlayer insulating film 43 is formed on the upper surface of the first redistribution wiring 42A, 42C and on the upper surface of the first interlayer insulating film 41 where the first redistribution wiring 42A, 42C is not formed. As a material for the second interlayer insulating film 43, an organic material such as a solder resist, an inorganic material such as a silicon oxide film, etc. can be used. The solder resist can be formed using a coating device, and the silicon oxide film can be formed using, for example, CVD, ALD, etc. The film thickness of the second interlayer insulating film 43 can be several nm to several tens of μm.

[0277] Then, if Figure 7As shown in FIG. 5C, the interlayer thin film portion 111 is formed by thinning the second interlayer insulating film 43 in the formation region of the capacitor 51B. For example, the interlayer thin film portion 111 can be formed by forming a resist pattern on the second interlayer insulating film 43 other than the region serving as the interlayer thin film portion 111 and performing dry etching using the resist pattern as a mask.

[0278] Then, if Figure 8 As shown in A, a through hole 46C is formed in a prescribed area of ​​the first redistribution wiring 42C. This step is similar to that in the first configuration example. Figure 4 The steps in C.

[0279] Then, if Figure 8 As shown in FIG. 2B, a second redistribution wiring 44C is formed in a predetermined region of the second interlayer insulating film 43 and inside the through hole 46C. This step is similar to that in the first configuration example. Figure 5 The step of A is the same as that of FIG. 1 , but in the second configuration example, since the interlayer thin film portion 111 is formed, a step corresponding to the interlayer thin film portion 111 is formed on the second redistribution wiring 44C.

[0280] Then, if Figure 8 As shown in FIG. 4C, a protective film 48 is formed on the upper surface of the second redistribution wiring 44C and on the upper surface of the second interlayer insulating film 43 where the second redistribution wiring 44C is not formed. This step is similar to Figure 5 Follow the steps in B in the first configuration example.

[0281] Figure 8 The steps after C in are similar to those in the first configuration example. That is, an insulating film opening is formed in a predetermined region of the uppermost protection film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0282] Through the above steps, manufacturing includes Figure 6 The capacitor 51B of the second configuration example shown is a logic substrate 12. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1.

[0283] According to the first manufacturing method of the solid-state imaging device 1 including the capacitor 51B according to the second configuration example, the second interlayer insulating film 43 as a capacitance film can be formed to have a small film thickness, and the capacitor 51B having a high electrostatic capacitance can be formed.

[0284] <6. Second Manufacturing Method of Capacitor According to Second Configuration Example>

[0285] Next, we will refer to Fig. 9 and Fig.10 Description includes Figure 6A second manufacturing method of the solid-state imaging device 1 of the capacitor 51B of the second configuration example shown in FIG.

[0286] Fig. 9 A shows the following state: Figure 7 Similar to B, a second interlayer insulating film 43X is formed on the upper surfaces of the first redistribution wirings 42A and 42C and on the upper surface of the first interlayer insulating film 41 on which the first redistribution wirings 42A and 42C are not formed. Figure 7 The difference of B is that in Figure 7 In B, the film thickness of the second interlayer insulating film 43X is formed to be thinner than the film thickness of the second interlayer insulating film 43. The steps until the second interlayer insulating film 43X is formed are similar to those of the first configuration example. Figure 3 A to Figure 4 The steps described in B.

[0287] Next, if Fig. 9 As shown in FIG. 1B, the second interlayer insulating film 43X in the region of the capacitor 51B that will become the interlayer thin film portion 111 is removed. For example, a resist pattern is formed on the second interlayer insulating film 43 other than the region that will become the interlayer thin film portion 111 by photolithography, and dry etching is performed using the resist pattern as a mask to remove the second interlayer insulating film 43X in the region that will become the interlayer thin film portion 111.

[0288] Next, if Fig. 9 As shown in FIG. 1C, in the region to be the interlayer thin film portion 111, the second interlayer insulating film 43Y is formed on the entire surface including the first redistribution wiring 42A and the upper surface of the second interlayer insulating film 43X. In the interlayer thin film portion 111, only the second interlayer insulating film 43Y is formed, and the region other than the interlayer thin film portion 111 is a laminated film of the second interlayer insulating films 43X and 43Y. The laminated film of the second interlayer insulating films 43X and 43Y is equivalent to Figure 6 The second configuration example shown has a thicker second interlayer insulating film 43. The second interlayer insulating films 43X and 43Y may be formed of the same material or different materials.

[0289] Then, if Fig.10 As shown in FIG. 1A, a through hole 46C penetrating the second interlayer insulating film 43X, 43Y is formed in a prescribed region of the first redistribution wiring 42C. This step is similar to that in the first configuration example. Figure 4 The steps in C.

[0290] Then, if Fig.10 As shown in FIG. 1B, a second redistribution wiring 44C is formed in a predetermined region of the second interlayer insulating film 43Y including the interlayer thin film portion 111 and in the through hole 46C. This step is similar to that in the first configuration example. Figure 5The step of A is the same as that of FIG. 1 , but in the second configuration example, since the interlayer thin film portion 111 is formed, a step corresponding to the interlayer thin film portion 111 is formed on the second redistribution wiring 44C.

[0291] Fig.10 The steps after B in are similar to those in the first configuration example. That is, after forming the protective film 48 at the uppermost layer, an insulating film opening is formed in a predetermined region of the protective film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0292] Through the above steps, manufacturing includes Figure 6 The capacitor 51B of the second configuration example shown is a logic substrate 12. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1.

[0293] According to the second manufacturing method of the solid-state imaging device 1 including the capacitor 51B according to the second configuration example, the second interlayer insulating film 43 as the capacitance film can be formed to have a small film thickness, and the capacitor 51B having a high electrostatic capacitance can be formed. Compared with the above-mentioned first manufacturing method, since the film thickness of the second interlayer insulating film 43 of the interlayer thin film portion 111 is determined by the growth film thickness of the second interlayer insulating film 43Y, the controllability of the film thickness is high compared to the case of thinning by etching processing or the like, and the capacitance variation of the capacitor 51B can be suppressed.

[0294] <7. Third Manufacturing Method of Capacitor According to Second Configuration Example>

[0295] Next, we will refer to Fig.11 and Fig.12 Description includes Figure 6 A third method of manufacturing the solid-state imaging device 1 of the capacitor 51B of the second configuration example shown in FIG.

[0296] Fig.11 A shows something like Fig. 9 A state of the second manufacturing method of the present invention is a state in which the second interlayer insulating film 43X is formed on the upper surface of the first redistribution wirings 42A and 42C and on the upper surface of the first interlayer insulating film 41 on which the first redistribution wirings 42A and 42C are not formed. The film thickness of the second interlayer insulating film 43X is formed to be less than Figure 7 The steps until the second interlayer insulating film 43X is formed are similar to those of the first configuration example. Figure 3 A to Figure 4 The steps described in B.

[0297] Next, if Fig.11As shown in FIG. 1B, a second interlayer insulating film 43Y' is formed on the entire surface of the second interlayer insulating film 43X. Thus, a stacked film of the second interlayer insulating films 43X and 43Y' is formed. In the above-mentioned second manufacturing method, the second interlayer insulating films 43X and 43Y may be formed of the same material or different materials, but a material having an etching rate different from that of the second interlayer insulating film 43X is used for the second interlayer insulating film 43Y' formed by the third manufacturing method. For example, an inorganic material film such as a silicon oxide film is used for the second interlayer insulating film 43X, and an organic material film such as a photosensitive solder resist is used for the second interlayer insulating film 43Y'.

[0298] Next, if Fig.11 As shown in C, the second interlayer insulating film 43Y' in the region of the interlayer thin film portion 111 serving as the capacitor 51B and the second interlayer insulating film 43Y' in the region 141 serving as the through hole 46C (hereinafter, referred to as the through hole region 141) are removed. In the case where the second interlayer insulating film 43Y' is an organic material film (e.g., a photosensitive solder resist), the second interlayer insulating film 43Y' is removed by a photolithography method. Because the second interlayer insulating films 43X and 43Y' are materials having different etching rates, only the second interlayer insulating film 43Y' can be removed while leaving the second interlayer insulating film 43X.

[0299] Next, if Fig.12 As shown in FIG. 1A, the second interlayer insulating film 43X in the through hole region 141 is removed by etching, and a through hole 46C penetrating the second interlayer insulating films 43X and 43Y' is formed. The stacked film of the second interlayer insulating films 43X and 43Y' corresponds to Figure 6 The second interlayer insulating film 43 in the second configuration example shown has a large film thickness.

[0300] Then, if Fig.12 As shown in FIG. 1B, a second redistribution wiring 44C is formed on the second interlayer insulating film 43Y including the interlayer thin film portion 111 and in the through hole 46C. This step is similar to that in the first configuration example. Figure 5 The step of A is the same as that of FIG. 1 , but in the second configuration example, since the interlayer thin film portion 111 is formed, a step corresponding to the interlayer thin film portion 111 is formed on the second redistribution wiring 44C.

[0301] exist Fig.13 The steps after B in FIG. 1 are similar to those in the first configuration example. That is, after forming the protective film 48 at the uppermost layer, an insulating film opening is formed in a predetermined region of the protective film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0302] Through the above steps, manufacturing includes Figure 6The capacitor 51B of the second configuration example shown is a logic substrate 12. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1.

[0303] According to the third manufacturing method of the solid-state imaging device 1 including the capacitor 51B according to the second configuration example, the second interlayer insulating film 43 as the capacitance film can be formed to have a small film thickness, and the capacitor 51B having a high electrostatic capacitance can be formed. Compared with the above-mentioned first manufacturing method, since the film thickness of the second interlayer insulating film 43 of the interlayer thin film portion 111 is determined by the growth film thickness of the second interlayer insulating film 43Y, the controllability of the film thickness is high compared to the case of thinning by etching processing or the like, and the capacitance variation of the capacitor 51B can be suppressed.

[0304] <8. Third Configuration Example of Capacitor>

[0305] Fig.13 : is a cross-sectional view showing a detailed structure of a capacitor 51C according to a third configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the third embodiment.

[0306] according to Fig.13 The capacitor 51C of the third configuration example shown is different from the first and second configuration examples described above in that the space between the first rewiring 42A and the second rewiring 44C as the capacitor electrode pair is not the second interlayer insulating film 43, but a high dielectric film 161. The high dielectric film 161 can be a tantalum oxide film, an aluminum oxide film, a hafnium oxide film, a titanium oxide film, a zirconium oxide film, a niobium oxide film, a silicon nitride film, etc., by using, for example, CVD, ALD, sputtering, etc., or can be a stacked film of two or more thereof. In addition, the titanium nitride film can be formed on the upper and lower layers of the single-layer film or on the stacked film of these dielectric films. The film thickness of the high dielectric film 161 can be several nm to several hundred nm. For example, when tantalum oxide (Ta2O5) is used as the material of the high dielectric film 161 and the film thickness is 100nm, the relative dielectric constant εr is about 20 to 25 (εr=20-25).

[0307] The high dielectric film 161 is formed not only in the region of the capacitor 51C but also on the entire upper surface of the silicon substrate 31 in a plan view. In the region other than the region of the capacitor 51C, the second interlayer insulating film 43 is formed on the high dielectric film 161, and the through hole 46C penetrates the high dielectric film 161 and the second interlayer insulating film 43. The film thickness of the second interlayer insulating film 43 between the first redistribution wiring 42 and the second redistribution wiring 44 except for the region of the capacitor 51C can be, for example, about 20 μm.

[0308] According to the capacitor 51C according to the third configuration example configured as described above, since the high dielectric film 161 is used as the capacitance film, a high electrostatic capacitance can be achieved compared to the first configuration example. The second interlayer insulating film 43 is formed in the region other than the capacitor 51B of the high dielectric film 161 formed on the entire surface, and the parasitic capacitance between the first redistribution wiring 42 and the second redistribution wiring 44 does not increase. Therefore, the capacitance of the capacitance element can be increased for stabilizing the power supply voltage while suppressing the signal delay due to the parasitic capacitance of the redistribution wiring.

[0309] <9. Manufacturing Method of Capacitor According to Third Configuration Example>

[0310] Next, we will refer to Fig.14 and Fig.15 Description includes Fig.13 A method for manufacturing the solid-state imaging device 1 of the capacitor 51C of the third configuration example shown in FIG.

[0311] like Fig.14 As shown in A of FIG. 1 , a high dielectric film 161 is formed on the entire upper surface of the silicon substrate 31. In the region where the first redistribution wirings 42A and 42C are formed, the high dielectric film 161 is formed on the upper surface of the first redistribution wirings 42A and 42C, and in the region where the first redistribution wirings 42A and 42C are not formed, the high dielectric film 161 is formed on the upper surface of the first interlayer insulating film 41. The process before forming the high dielectric film 161 is the same as that in the first configuration example. Figure 3 A to Figure 4 The process is similar to that described in A.

[0312] Then, if Fig.14 As shown in B, a second interlayer insulating film 43 is formed on the upper surface of the high dielectric film 161. As the material of the second interlayer insulating film 43, an organic material such as a solder resist, an inorganic material such as a silicon oxide film (SiO2 film), etc. can be used. In this example, the material of the second interlayer insulating film 43 is, for example, a solder resist having photosensitivity. The film thickness of the second interlayer insulating film 43 can be several nm to several tens of μm. This step is similar to that in the first configuration example. Figure 4 Steps in B.

[0313] Next, if Fig.14 As shown in FIG. C, the second interlayer insulating film 43 in the region 181 to be the capacitor 51C and the region 182 to be the via 46C is removed. When the material of the second interlayer insulating film 43 is a solder resist having photosensitivity, the second interlayer insulating film 43 in the regions 181 and 182 can be removed by photolithography.

[0314] Next, if Fig.15As shown in FIG. 1A , the high dielectric film 161 in the region 182 of the through hole 46C is removed by dry etching or the like using a resist pattern formed by a photolithography method as a mask, thereby forming the through hole 46C. Note that although Fig.15 A is not shown, through hole 46A ( Figure 1 ) is also formed on the first redistribution wiring 42A on the internal electrode 33A side simultaneously with the through hole 46C.

[0315] Next, if Fig.15 As shown in FIG. 1B, a second redistribution wiring 44C is formed on the high dielectric film 161 in the region 181 to be the capacitor 51C and in the region including the inside of the through hole 46C. This step is similar to Figure 5 The step in A in the first configuration example is performed, but in the third configuration example, a step corresponding to the presence or absence of the second interlayer insulating film 43 is formed.

[0316] exist Fig.15 The steps after B in are similar to those in the first configuration example. That is, after forming the protective film 48 at the uppermost layer, an insulating film opening is formed in a predetermined region of the protective film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0317] Through the above steps, manufacturing includes Fig.13 The logic substrate 12 of the capacitor 51C of the third configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0318] According to the method of manufacturing the solid-state imaging device 1 including the capacitor 51C according to the third configuration example, the capacitor 51C having a high electrostatic capacitance can be formed by using the high dielectric film 161 as a capacitance film.

[0319] <10. Fourth Configuration Example of Capacitor>

[0320] Fig.16 : is a cross-sectional view showing a detailed structure of a capacitor 51D according to a fourth configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the fourth embodiment.

[0321] Fig.16 The capacitor 51C according to the fourth configuration example shown in FIG. Fig.13 The capacitor 51C according to the third configuration example shown in FIG. 5 is common in that the first redistribution wiring 42A and the second redistribution wiring 44C are a pair of capacitance electrodes, and a high dielectric film 161 is formed between these redistributions.

[0322] on the other hand, Fig.16 The fourth configuration example shown is Fig.13The third configuration example shown is different in that the high dielectric film 161 is not formed on the entire surface on the silicon substrate 31, but is formed only in the region where the first redistribution wiring 42A and the second redistribution wiring 44C constituting the capacitor 51D overlap. Since the high dielectric film 161 is generally a material having a high film stress, in the case of being formed on the entire upper surface of the silicon substrate 31, warpage may occur in the entire solid-state imaging device 1. By forming the high dielectric film 161 only in the region of the capacitor 51D, warpage of the entire device can be suppressed and connection reliability with a module board to be mounted can be enhanced.

[0323] According to the capacitor 51D according to the fourth configuration example configured as described above, since the high dielectric film 161 is used as the capacitance film, a high electrostatic capacitance can be achieved compared to the first configuration example. Since the high dielectric film 161 is formed only in the region of the capacitor 51D, warping of the entire device can be suppressed, and connection reliability with the mounting substrate can be improved.

[0324] The second interlayer insulating film 43 is formed in the region other than the capacitor 51D and does not increase the parasitic capacitance between the first redistribution wiring 42 and the second redistribution wiring 44. Therefore, the capacitance of the capacitance element can be increased for stabilizing the power supply voltage while suppressing the signal delay due to the parasitic capacitance of the redistribution wiring.

[0325] <11. Manufacturing Method of Capacitor According to Fourth Configuration Example>

[0326] Next, we will refer to Fig.17 and Fig.18 Description includes Fig.16 A method of manufacturing the solid-state imaging device 1 of the capacitor 51D of the fourth configuration example shown in FIG.

[0327] like Fig.17 As shown in A, the high dielectric film 161 is formed on the entire upper surface of the silicon substrate 31. This step is similar to that in the third configuration example. Fig.14 The steps are similar to those described in A.

[0328] Next, if Fig.17 As shown in FIG. 1B, the high dielectric film 161 in other regions is removed so that only the region where the high dielectric film 161 becomes the capacitance film of the capacitor 51D remains. The high dielectric film 161 except for the region to become the capacitor 51D can be removed by forming a resist pattern in the region to be retained, masking the resist pattern, and performing dry etching.

[0329] Then, if Fig.17As shown in C, a second interlayer insulating film 43 is formed on the entire top layer. The second interlayer insulating film 43 is formed on the upper surface of the high dielectric film 161 in a region where the uppermost layer is the high dielectric film 161, on the upper surfaces of the first redistribution wirings 42A and 42C in a region where the uppermost layer is the first redistribution wirings 42A and 42C, and on the upper surface of the first interlayer insulating film 41 in a region where the uppermost layer is the first interlayer insulating film 41. This step is the same as in the third configuration example. Fig.14 The steps are similar to those described in B.

[0330] Then, if Fig.18 As shown in A, the second interlayer insulating film 43 in the region 201 that becomes the capacitor 51D is removed, and the second interlayer insulating film 43 in a predetermined region on the first redistribution wiring 42C is also removed to form a through hole 46C. When the material of the second interlayer insulating film 43 is a solder resist having photosensitivity, the second interlayer insulating film 43 in a desired region can be removed by photolithography.

[0331] Next, if Fig.18 As shown in FIG. 1B, in the region 201 to be the capacitor 51D and in the region including the inside of the through hole 46C, a second redistribution wiring 44C is formed on the high dielectric film 161. This step is similar to Figure 5 The step in A in the first configuration example is performed, but in the fourth configuration example, a step corresponding to the presence or absence of the second interlayer insulating film 43 is formed.

[0332] Fig.18 The steps after B are similar to those in the first configuration example. That is, after forming the protection film 48 at the uppermost layer, an insulating film opening is formed in a predetermined region of the protection film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0333] Through the above steps, manufacturing includes Fig.16 The logic substrate 12 of the capacitor 51D of the fourth configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1.

[0334] According to the manufacturing method of the solid-state imaging device 1 including the capacitor 51D according to the fourth configuration example, the capacitor 51D having high electrostatic capacitance can be formed by using the high dielectric film 161 as a capacitance film. Compared with the capacitor 51C according to the third configuration example, since processing is performed to leave only the region to be the capacitance film of the capacitor 51D immediately after the high dielectric film 161 is once deposited on the entire surface, it is not necessary to remove the high dielectric film 161 when forming the through hole 46C. Fig.18In the step in A of , since the through hole 46C can be formed while removing the second interlayer insulating film 43 in the region 201 to be the capacitor 51D, the step can be performed more easily than the capacitor 51C according to the third configuration example.

[0335] <12. Fifth Configuration Example of Capacitor>

[0336] Fig.19 2 is a cross-sectional view showing a detailed structure of a capacitor 51E according to a fifth configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the fifth embodiment.

[0337] Fig.19 The capacitor 51E of the fifth configuration example shown is Figure 2 The capacitor 51A of the illustrated first configuration example is different in that the second redistribution wiring 221 is used instead of the second redistribution wiring 44C.

[0338] according to Figure 2 The second redistribution wiring 44C of the capacitor 51A of the first configuration example is not formed inside the through hole 45A penetrating the silicon substrate 31 , and is formed as a flat plate only on the flat surface portion on the rear surface side of the silicon substrate 31 .

[0339] on the other hand, Fig.19 The second redistribution 221 of the capacitor 51E in the embodiment is formed not only in the plane portion on the rear surface side of the silicon substrate 31 but also in the through hole 45A. Thus, compared with the first configuration example, the area of ​​the second redistribution 221 opposite to the first redistribution 42A via the second interlayer insulating film 43 is increased, and a high electrostatic capacitance can be achieved. The element area dedicated to the capacitor is not increased.

[0340] According to the capacitor 51E according to the fifth configuration example configured as described above, since the area of ​​the second redistribution 221 facing the first redistribution 42A is increased, a high electrostatic capacitance can be achieved compared to the first configuration example. Therefore, the capacitance of the capacitance element can be increased for stabilizing the power supply voltage while suppressing the signal delay caused by the parasitic capacitance of the redistribution.

[0341] In the capacitor 51E, when the plate-shaped capacitor in the upper portion of the rear surface of the silicon substrate 31 is referred to as a planar capacitor, and the capacitor portion inside the through hole 45A is referred to as a cylindrical capacitor, Fig.19 The capacitor 51E in has a configuration in which a planar capacitor and a cylindrical capacitor are connected in series. The capacitor 51E may have a configuration in which a planar capacitor and a cylindrical capacitor are connected in parallel.

[0342] <13. Method of Manufacturing Capacitor According to Fifth Configuration Example>

[0343] Next, we will refer to Fig. 20 Description includes Fig.19 A method of manufacturing the solid-state imaging device 1 of the capacitor 51E of the fifth configuration example shown in FIG.

[0344] Fig. 20 A and the capacitor 51A in the above-mentioned first configuration example Figure 4 The same as C. Fig. 20 The steps until the second interlayer insulating film 43 and the through hole 46C are formed are similar to those of the first configuration example. Figure 3 A to Figure 4 The steps described in C.

[0345] Then, if Fig. 20 As shown in FIG. 4B, a second redistribution 221 is formed in a predetermined region of the second interlayer insulating film 43 and inside the through hole 46C. The second redistribution 221 is also formed to extend inside the through hole 45A. The material of the second redistribution 221 is also copper like the first redistribution 42A. The method of forming the second redistribution 221 is also similar to the method of forming the first redistribution 42A. The film thickness of the second redistribution 221 is, for example, about several μm to several tens of μm.

[0346] Then, if Fig. 20 As shown in FIG. 3C, a protective film 48 is formed on the upper surface of the second redistribution wiring 221 and on the upper surface of the second interlayer insulating film 43 where the second redistribution wiring 221 is not formed. This step is similar to Figure 5 Follow the steps in B in the first configuration example.

[0347] Fig. 20 The steps after C in are similar to those in the first configuration example. That is, an insulating film opening is formed in a predetermined region of the protective film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0348] Through the above steps, manufacturing includes Fig.19 The logic substrate 12 of the capacitor 51E of the fifth configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0349] According to the manufacturing method of the solid-state imaging device 1 including the capacitor 51E according to the fifth configuration example, high electrostatic capacitance can be achieved by enlarging the area of ​​the capacitor electrode compared to the first configuration example. Compared to the first configuration example, the area of ​​the capacitor electrode can be enlarged without increasing the number of steps.

[0350] <14. Sixth Configuration Example of Capacitor>

[0351] Fig.212 is a cross-sectional view showing a detailed structure of a capacitor 51F according to a sixth configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the sixth embodiment.

[0352] In accordance with Fig.21 In the capacitor 51F of the sixth configuration example shown, according to Fig.19 Compared with the capacitor 51E of the fifth configuration example shown, the second redistribution line 221 is replaced with the second redistribution line 241. The capacitor 51F is common to the capacitor 51E in that a planar capacitor and a cylindrical capacitor are connected in series.

[0353] However, in Fig.19 In the cylindrical capacitor of the capacitor 51E of the fifth configuration example shown, a protective film 48 is embedded inside the second redistribution wiring 221 formed along the inner wall of the through hole 45A. On the other hand, in the cylindrical capacitor of the capacitor 51F of the sixth configuration example, a protective film 48 is not embedded in the through hole 45A. Instead of embedding the protective film 48, the second redistribution wiring 241 is embedded in a plug shape. The plug shape is a columnar or conical shape. The upper surface of the second redistribution wiring 241 embedded in the through hole 46C is also formed to be flat.

[0354] According to the capacitor 51F according to the sixth configuration example configured as described above, since the area of ​​the second rewiring 221 facing the first rewiring 42A is increased, a high electrostatic capacitance can be achieved compared to the first configuration example. Therefore, the capacitance of the capacitance element can be increased for stabilizing the power supply voltage while suppressing the signal delay caused by the parasitic capacitance of the rewiring.

[0355] Furthermore, by embedding the second redistribution 241 in the through hole 45A in a plug shape, stable capacitance characteristics can be obtained, and there is less concern about disconnection of the second redistribution 241. In addition, since the protective film 48 is not embedded in the through hole 45A, no voids in the protective film 48 are generated in the through hole 45A, and the generation of defects such as damage to the protective film 48 caused by the expansion of the gas in the void can be suppressed.

[0356] <15. Manufacturing Method of Capacitor According to Sixth Configuration Example>

[0357] Next, we will refer to Fig. 22 Description includes Fig.21 A method for manufacturing the solid-state imaging device 1 of the capacitor 51F of the sixth configuration example shown in FIG.

[0358] Fig. 22 A and the capacitor 51A in the above-mentioned first configuration example Figure 4 The same as C. Fig. 22 The steps until the second interlayer insulating film 43 and the through hole 46C are formed are similar to those in the first configuration example. Figure 3 A to Figure 4 The steps described in C.

[0359] Then, if Fig. 22 As shown in FIG. 1B, a second redistribution 241 is formed in a predetermined region of the second interlayer insulating film 43 and in the through hole 46C. The second redistribution 241 is embedded in the through hole 45A in a plug shape. In addition, the upper surface of the second redistribution 241 embedded in the through hole 46C is also formed to be flat. The material of the second redistribution 241 is also copper like the first redistribution 42A. The second redistribution 241 is formed by a method having good coverage.

[0360] Then, if Fig. 22 As shown in FIG. 3C, a protective film 48 is formed on the upper surface of the second redistribution wiring 241 and on the upper surface of the second interlayer insulating film 43 where the second redistribution wiring 241 is not formed. This step is similar to Figure 5 Follow the steps in B in the first configuration example.

[0361] Fig. 22 The steps after C are similar to those in the first configuration example. That is, an insulating film opening is formed in a predetermined region of the protective film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0362] Through the above steps, manufacturing includes Fig.21 The logic substrate 12 of the capacitor 51F of the sixth configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1.

[0363] According to the manufacturing method of the solid-state imaging device 1 including the capacitor 51E according to the sixth configuration example, a high electrostatic capacitance can be achieved by expanding the area of ​​the capacitor electrode compared to the first configuration example. Since the second redistribution material used as the capacitor electrode is completely embedded in the through hole 45A in a plug shape, the second redistribution can be formed without worrying about the step coverage characteristics in the opening of the protective film 48 to be deposited later.

[0364] <16. Seventh Configuration Example of Capacitor>

[0365] Fig.23 2 is a cross-sectional view showing a detailed structure of a capacitor 51G according to a seventh configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the seventh embodiment.

[0366] exist Fig.23 In the capacitor 51G of the seventh configuration example shown, Figure 2Compared to the capacitor 51A of the first configuration example shown, the cross-sectional shapes of the first rewiring 261 and the second rewiring 262 constituting a pair of capacitor electrodes are concave and convex. Specifically, grooves 263A and 263B dug to a predetermined depth are formed in a portion of the planar region of the silicon substrate 31 where the capacitor 51G is formed, and the cross-sectional shapes of the first rewiring 261 and the second rewiring 262 have steps at a deep position of the portion where the grooves 263A and 263B are formed, and have steps at a shallow position of the portion where the grooves 263A and 263B are not formed. As described above, the first rewiring 261 and the second rewiring 262 are formed into a concave and convex cross-sectional shape along the grooves 263A and 263B, thereby increasing the relative area between the first rewiring 261 and the second rewiring 262.

[0367] According to the capacitor 51G according to the seventh configuration example configured as described above, since the opposing area of ​​the first redistribution wiring 261 and the second redistribution wiring 262 can be increased compared to the first configuration example, the effective capacitor area is increased, and the electrostatic capacitance can be increased.

[0368] <17. Method for Manufacturing Capacitor According to Seventh Configuration Example>

[0369] Next, we will refer to Figure 24 to Figure 26 Description includes Fig.23 A method for manufacturing the solid-state imaging device 1 of the capacitor 51G of the seventh configuration example shown in FIG.

[0370] First, if Fig.24 As shown in FIG. 1A , a multilayer wiring layer 32 is formed on a first surface of a silicon substrate 31 on the sensor substrate 11 side. The multilayer wiring layer 32 includes a plurality of metal wiring layers (not shown) including at least two internal electrodes 33A and 33C and an interlayer insulating film 34 therebetween.

[0371] Then, if Fig.24 As shown in FIG. 8B , trenches 263A and 263B are formed in a portion of the planar region of the silicon substrate 31 where the capacitor 51G is formed.

[0372] Next, if Fig.24 As shown in FIG. 3C, through holes 45A and 45C penetrating the silicon substrate 31 are formed at positions corresponding to the internal electrodes 33A and 33C, respectively. The through holes 45A and 45C are formed to reach the internal electrodes 33A and 33C, respectively, and a portion of the upper surface of the internal electrodes 33A and 33C is exposed.

[0373] Then, if Fig.25As shown in FIG. 1A, a first interlayer insulating film 41 is formed on the upper surface of the silicon substrate 31, the inner wall and bottom surface of the grooves 263A and 263B, and the side walls of the through holes 45A and 45C. For example, the first interlayer insulating film 41 is formed on the entire upper surface of the silicon substrate 31 including the bottom and side walls of the grooves 263A and 263B and the through holes 45A and 45C, and then only the bottom surface of the through holes 45A and 45C is dry-etched using photolithography. The first interlayer insulating film 41 is formed into a concave-convex cross-sectional shape along the grooves 263A and 263B.

[0374] Next, if Fig.25 As shown in B, the first redistribution 261 connected to the internal electrode 33A and the first redistribution 42C connected to the internal electrode 33C are formed at the same time. The material of the first redistribution 261 and 42C is, for example, copper. In this case, for example, the first redistribution 261 and 42C can be formed by forming a resist material having an opening pattern in a predetermined area, and using the formed resist material as a mask, forming a copper film by electroplating. The film thickness of the first redistribution 261, 42C is, for example, several μm to tens of μm. The first redistribution 261 is formed in a concave-convex shape along the grooves 263A, 263B.

[0375] Then, if Fig.25 As shown in C, a second interlayer insulating film 43 is formed on the upper surface of the first redistribution 261, 42C, and on the upper surface of the first interlayer insulating film 41 where the first redistribution 261, 42C is not formed. As the material of the second interlayer insulating film 43, an organic material such as a solder resist, an inorganic material such as a silicon oxide film (SiO2 film), etc. can be used. The solder resist can be formed using a coating device, and the silicon oxide film can be formed using, for example, CVD, ALD, etc. The second interlayer insulating film 43 is formed with a uniform film thickness inside the through holes 45A, 45C and the grooves 263A, 263B. The film thickness of the second interlayer insulating film 43 can be several nm to tens of μm.

[0376] Then, if Fig.26 As shown in A of FIG. 1 , a through hole 46C penetrating the second interlayer insulating film 43 is formed in a prescribed region of the first redistribution wiring 42C. In the case where the second interlayer insulating film 43 is a solder resist of a photosensitive material or the like, the through hole 46C can be formed by photolithography. In addition, for example, in the case where the second interlayer insulating film 43 is a silicon oxide film, the through hole 46C can be formed by forming a resist pattern by photolithography and dry etching the second interlayer insulating film 43 using the resist pattern as a mask. Note that although Fig.26 A is not shown, through hole 46A ( Figure 1 ) is also formed simultaneously with the through hole 46C on the first redistribution wiring 42A on the internal electrode 33A side.

[0377] Then, if Fig.26 As shown in FIG. 1B, a second redistribution 262 is formed in a predetermined area including the grooves 263A and 263B on the second interlayer insulating film 43 and inside the through hole 46C. Like the first redistribution 261, the material of the second redistribution 262 is also copper. The method of forming the second redistribution 262 is also the same as the method of forming the first redistribution 261. The film thickness of the second redistribution 262 is, for example, several μm to several tens of μm. Note that although Fig.26 Although not shown in FIG. 1B, the second redistribution line 44A on the inner electrode 33A side is also formed simultaneously with the second redistribution line 262. The second redistribution line 262 is also formed in a concave-convex cross-sectional shape along the grooves 263A and 263B.

[0378] Then, if Fig.26 As shown in FIG. 2C, a protective film 48 is formed on the upper surface of the second redistribution wiring 262 and on the upper surface of the second interlayer insulating film 43 where the second redistribution wiring 262 is not formed. As a material of the protective film 48, for example, a solder resist is used, which is an organic material. As the solder resist, it is desirable to use a photosensitive solder resist to provide an insulating film opening for arranging the solder bump 47 in the next step.

[0379] Fig.26 The steps after C in are similar to those in the first configuration example. That is, an insulating film opening is formed in a predetermined region of the uppermost protection film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0380] Through the above steps, manufacturing includes Fig.23 The logic substrate 12 of the capacitor 51G of the seventh configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0381] According to the method of manufacturing the solid-state imaging device 1 including the capacitor 51G according to the seventh configuration example, the capacitor 51G having a large capacitor area and a high electrostatic capacitance can be formed.

[0382] <18. Eighth Configuration Example of Capacitor>

[0383] Fig. 27 2 is a cross-sectional view showing a detailed structure of a capacitor 51H according to an eighth configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the eighth embodiment.

[0384] Fig. 27 The capacitor 51H of the eighth configuration example shown is connected to Fig.23The capacitor 51G of the seventh configuration example shown has a common point in that the first redistricting 281 and the second redistricting 282 constituting a pair of capacitance electrodes have a non-uniform cross-sectional shape along the grooves 284A, 284B.

[0385] On the other hand, the capacitor 51H of the eighth configuration example is Fig.23 The capacitor 51G of the seventh configuration example shown is different in that the grooves 284A, 284B are not formed by digging through a part of the silicon substrate 31, but are through holes that penetrate the silicon substrate 31. In the multilayer wiring layer 32 in the region where the grooves 284A and 284B are formed, stopper films 283A and 283B serving as stoppers during trench processing are formed in the same layer as the internal electrodes 33A and 33C.

[0386] According to the capacitor 51H of the eighth configuration example constructed as described above, by setting the depth of the grooves 284A and 284B to the same depth as the through holes 45A and 45B, the steps of the concave and convex of the first redistribution wiring 281 and the second redistribution wiring 282 are increased, and the relative area of ​​the first redistribution wiring 281 and the second redistribution wiring 282 can be further increased compared to the seventh configuration example. Compared to the seventh configuration example, the effective capacitor area is increased, so the electrostatic capacitance can be further increased.

[0387] <19. Method for Manufacturing Capacitor According to Eighth Configuration Example>

[0388] Next, we will refer to Figures 28 to 30 Description includes Fig. 27 A method for manufacturing the solid-state imaging device 1 of the capacitor 51H of the eighth configuration example shown in FIG.

[0389] First, if Fig.28 As shown in FIG. 1A , a multilayer wiring layer 32 is formed on the first surface of the silicon substrate 31 on the sensor substrate 11 side. In the multilayer wiring layer 32, at least two internal electrodes 33A and 33C, stopper films 283A and 283B, and an interlayer insulating film 34 are formed. The stopper films 283A and 283B may be formed of the same material as the internal electrodes 33A and 33C.

[0390] Next, if Fig.28As shown in FIG. 1B, through holes 45A and 45C penetrating the silicon substrate 31 are formed at positions corresponding to the internal electrodes 33A and 33C, and grooves 284A and 284B penetrating the silicon substrate 31 are formed at positions corresponding to the stopper films 283A and 283B. The through holes 45A and 45C and the grooves 284A and 284B are formed simultaneously, the internal electrodes 33A and 33C function as etching stoppers when forming the through holes 45A and 45C, and the stopper films 283A and 283B function as etching stoppers when forming the grooves 284A and 284B.

[0391] Next, if Fig.28 As shown in FIG. 3C , the first interlayer insulating film 41 is formed on the entire upper surface of the silicon substrate 31 , the bottom surface and side walls of the through holes 45A and 45C, and the bottom surface and side walls of the trenches 284A and 284B.

[0392] Next, if Fig.29 As shown in FIG. 8A , the first interlayer insulating film 41 on the bottom surfaces of the through holes 45A and 45C and on the bottom surfaces of the trenches 284A and 284B is removed by etching back or the like.

[0393] Next, if Fig.29 As shown in FIG. 1B, the first redistribution wiring 281 connected to the internal electrode 33A and the first redistribution wiring 42C connected to the internal electrode 33C are formed simultaneously. Fig.25 The steps of the seventh configuration example described in B are similar. However, since the grooves 284A and 284B are formed at the same depth as the through hole 45A, the step of the unevenness of the cross-sectional shape of the first rewiring 42A is the same as the step of the through hole 45A and is deeper than the step of the seventh configuration example.

[0394] Then, if Fig.29 As shown in FIG. 3C, a second interlayer insulating film 43 is formed on the upper surface of the first redistribution wiring 281 and 42C and on the upper surface of the first interlayer insulating film 41 where the first redistribution wiring 281 and 42C are not formed. This step is similar to the step in FIG. Fig.25 The steps of the seventh configuration example described in C are similar. In addition, the second interlayer insulating film 43 is also formed into a concavo-convex cross-sectional shape along the trenches 284A, 284B.

[0395] Then, if Fig.30 As shown in A of FIG. 1 , a through hole 46C penetrating the second interlayer insulating film 43 is formed in a prescribed region of the first redistribution wiring 42C. In the case where the second interlayer insulating film 43 is a solder resist of a photosensitive material or the like, the through hole 46C can be formed by photolithography. In addition, for example, in the case where the second interlayer insulating film 43 is a silicon oxide film, the through hole 46C can be formed by forming a resist pattern by photolithography and dry etching the second interlayer insulating film 43 using the resist pattern as a mask. Note that although Fig.30 A is not shown, through hole 46A ( Figure 1 ) is also formed on the first redistribution wiring 42A on the internal electrode 33A side simultaneously with the through hole 46C.

[0396] Then, if Fig.30 As shown in FIG. 1B, a second redistribution 282 is formed in a predetermined area of ​​the second interlayer insulating film 43 including the grooves 284A and 284B and inside the through hole 46C. Like the first redistribution 281, the material of the second redistribution 282 is also copper. The method for forming the second redistribution 282 is also the same as the method for forming the first redistribution 281. The film thickness of the second redistribution 282 is, for example, several μm to several tens of μm. Note that although Fig.30 Although not shown in FIG. 1B, the second redistribution wiring 44A on the inner electrode 33A side is also formed simultaneously with the second redistribution wiring 282. In addition, the second redistribution wiring 282 is also formed into a concave-convex cross-sectional shape along the grooves 284A and 284B.

[0397] Then, if Fig.30 As shown in FIG. 2C, a protective film 48 is formed on the upper surface of the second redistribution wiring 282 and the upper surface of the second interlayer insulating film 43 where the second redistribution wiring 282 is not formed. As a material of the protective film 48, for example, a solder resist is used, which is an organic material. As the solder resist, it is desirable to use a photosensitive solder resist to provide an insulating film opening for arranging the solder bump 47 in the next step.

[0398] Fig.30 The steps after C are similar to those in the first configuration example. That is, an insulating film opening is formed in a predetermined region of the uppermost protection film 48, and solder bumps 47A and 47B are formed on the exposed second redistribution wirings 44A and 44B, respectively.

[0399] Through the above steps, manufacturing includes Fig. 27 The logic substrate 12 of the capacitor 51H of the eighth configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0400] According to the manufacturing method of the solid-state imaging device 1 including the capacitor 51H according to the eighth configuration example, the capacitor 51H having a large capacitor area and a high electrostatic capacitance can be formed. Since the stopper films 283A and 283B serving as stoppers are formed when the grooves 284A and 284B are processed, the depth of the grooves 284A and 284B can be controlled with high precision, so that the change in capacitance can be suppressed, and a stable capacitance value can be obtained.

[0401] <20. Ninth Configuration Example of Capacitor>

[0402] Fig.312 is a cross-sectional view showing a detailed structure of a capacitor 51J according to a ninth configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the ninth embodiment.

[0403] exist Fig.31 In the capacitor 51J according to the ninth configuration example shown, the planar shape of the first rewiring 301 and the second rewiring 302 constituting the capacitor electrode pair is formed into a comb-tooth shape. More specifically, the first rewiring 301 includes a first wiring 301A and a second wiring 301B capacitively coupled in the planar direction. The second rewiring 302 includes a first wiring 302A and a second wiring 302B capacitively coupled in the planar direction.

[0404] Fig.32 A is a plan view of a first wiring 301A and a second wiring 301B constituting the first heavy wiring 301 . Fig.32 B is a plan view of a first wiring 302A and a second wiring 302B constituting the second heavy wiring 302 .

[0405] Fig.32 The first wiring 301A and the second wiring 301B of the first heavy wiring 301 shown in A are each formed in a comb-tooth shape. The comb-tooth-shaped wiring of the second wiring 301B is arranged in the gap of the comb-tooth-shaped wiring of the first wiring 301A, and the comb-tooth-shaped wiring of the first wiring 301A and the comb-tooth-shaped wiring of the second wiring 301B are alternately arranged to face each other. Different potentials are provided to the comb-shaped wiring of the first wiring 301A and the comb-shaped wiring of the second wiring 301B, and a capacitance element including the first wiring 301A and the second wiring 301B as capacitance electrodes is configured.

[0406] Fig.32 The first wiring 302A and the second wiring 302B of the second heavy wiring 302 shown in B are each formed into a comb-tooth shape. The comb-tooth-shaped wiring of the second wiring 302B is arranged in the gap of the comb-tooth-shaped wiring of the first wiring 302A, and the comb-tooth-shaped wiring of the first wiring 302A and the comb-tooth-shaped wiring of the second wiring 302B are alternately arranged to face each other. Different potentials are provided to the comb-tooth-shaped wiring of the first wiring 302A and the comb-tooth-shaped wiring of the second wiring 302B, and a capacitance element including the first wiring 302A and the second wiring 302B as capacitance electrodes is configured.

[0407] Therefore, the first wiring 301A and the second wiring 301B of the first heavy wiring 301 are capacitively coupled in the planar direction, and the first wiring 302A and the second wiring 302B of the second heavy wiring 302 are capacitively coupled in the planar direction.

[0408] In addition, if Fig.31As is clear from the cross-sectional view, the first wiring 301A and the second wiring 301B of the first heavy wiring 301 and the first wiring 302A and the second wiring 302B of the second heavy wiring 302 also constitute capacitive elements in the vertical direction (stacking direction).

[0409] With the capacitor 51J according to the ninth configuration example configured as described above, the first redistribution wiring 301 and the second redistribution wiring 302 function as capacitance elements in the planar direction of the same layer and in the vertical direction between different layers, whereby a capacitor having high capacitance can be realized.

[0410] <21. Tenth Embodiment of Solid-State Imaging Device>

[0411] Fig.33 It is a cross-sectional view of the entire configuration of a tenth embodiment of a solid-state imaging device to which the present technology is applied.

[0412] Fig.33 The solid-state imaging device 1 shown in FIG. 1 is different in that the configuration of the capacitor 51 is changed from the capacitor 51A according to the first configuration example to the capacitor 51K according to the tenth configuration example, and is common in other points.

[0413] Fig.33 The capacitor 51K in FIG. 4 includes a first redistribution wiring 331, another second redistribution wiring 332 formed in the same layer as the second redistribution wiring 44A, and a second interlayer insulating film 43 therebetween. Figure 1 As shown, the capacitor 51A according to the first configuration example is formed only in a portion of the pixel region 71 at the center of the chip region. On the other hand, the first redistribution wiring 331 and the second redistribution wiring 332 of the capacitor 51K are formed on the entire surface of the pixel region 71.

[0414] Fig.34 is a plan view of a solid-state imaging device 1 according to a tenth embodiment. Fig.34 The plan view of is a plan view of the rear surface side on which the solder bumps 47 and the like are formed.

[0415] exist Fig.34 In the plan view of FIG. 1 , the solid-state imaging device 1 includes a pixel region 71 at the center of a rectangular chip region and a peripheral region 72 outside the pixel region. A plurality of solder bumps 47 are formed in the peripheral region 72 .

[0416] exist Fig.34 In the plan view of FIG. 5 , the capacitor region 351 indicated by the dotted line outside the pixel region 71 indicates the region where the first redistribution wiring 331 and the second redistribution wiring 332 of the capacitor 51K overlap. The capacitor region 351 includes the entire region of the pixel region 71 in the plan view, and is formed to cover the entire lower portion of the pixel region 71 with a larger planar area than the pixel region 71.

[0417] Since the capacitor region 351 is set to cover the entire lower portion of the pixel region 71, infrared light (IR light) can be prevented from entering from the rear surface side of the solid-state imaging device 1. In addition, since a large area of ​​the first and second redistribution wirings 331 and 332 can be ensured to become capacitor electrodes, high capacitance can be achieved.

[0418] Note that in the above example, the first and second rewiring lines 331 and 332 constituting the capacitor 51K are formed of one flat metal film, but each of the first and second rewiring lines 331 and 332 may be divided into a plurality of regions with a gap shorter than the wavelength of light.

[0419] <22. Overview of First to Tenth Embodiments>

[0420] The solid-state imaging device 1 according to the first embodiment to the tenth embodiment includes: an internal electrode 33, which is formed on the first surface side (light incident surface side) of the silicon substrate 31; a through hole 45, which is formed at a position corresponding to the internal electrode 33 of the silicon substrate 31; a first redistribution wiring 42, which is formed on the second surface side opposite to the first surface side of the silicon substrate 31 and is connected to the internal electrode 33 via the through hole 45, and a second redistribution wiring 44, which is connected to the first redistribution wiring 42 and is formed on the side closer to the solder bump 47 than the first redistribution wiring 42; and an interlayer insulating film 43, which is formed between the first redistribution wiring 42 and the second redistribution wiring 44.

[0421] The capacitors 51A to 51K are formed by using two redistribution layers of the first redistribution 42 and the second redistribution 44. For example, the capacitor 51A according to the first configuration example includes the first redistribution 42A connected to the internal electrode 33A as the first internal electrode 33, the second redistribution 44C connected to the internal electrode 33C as the second internal electrode 33, and the interlayer insulating film 43 formed therebetween. The power supply voltage is supplied from the solder bump 47A to the internal electrode 33A and the first redistribution 42A, and the internal electrode 33C and the second redistribution 44C are connected to the ground line.

[0422] As described above, by forming capacitor 51 using two redistribution layers of first redistribution layer 42 and second redistribution layer 44, capacitor 51 can be formed not in the multilayer wiring layer 32 formed on the first surface side of silicon substrate 31, but on the second surface side on the external connection terminal side, so that there is no effect on the high integration of the circuit formed in the multilayer wiring layer 32.

[0423] In addition, the two-layer rewiring layer portion of the first rewiring 42 and the second rewiring 44 forming the capacitor 51 can realize a configuration in which the second interlayer insulating film 43 is thinned, a high dielectric film 161 is set, or the capacitance is increased. On the other hand, the two-layer rewiring layer portion of the first rewiring 42 and the second rewiring 44 except the capacitor 51 can fully ensure the film thickness of the second interlayer insulating film 43, thereby realizing both the formation of a capacitor element by two rewiring layers and the reduction of parasitic capacitance.

[0424] By connecting the capacitor 51 to the internal electrode 33A connected to the power supply voltage to stabilize the potential, signal delay and jitter can be improved.

[0425] The capacitor 51 may adopt a configuration in which two or more of the above-described first to tenth configuration examples are arbitrarily combined.

[0426] <23. Three-layer stacking configuration example>

[0427] In the above embodiment, the case where the solid-state imaging device 1 has a double-plate stacked structure in which two substrates of the sensor substrate 11 and the logic substrate 12 are stacked has been described. However, the capacitor 51 described above can also be applied to a solid-state imaging device 1 having a stacked structure in which three or more substrates are stacked.

[0428] Fig.35 A configuration example is shown in which the capacitor 51 is formed in the solid-state imaging device 1 having a stacked structure in which three substrates are stacked.

[0429] Fig.35 The solid-state imaging device 1 shown in FIG. 1 is configured by stacking a sensor substrate 11 as a first substrate, a first logic substrate 12A as a second substrate, and a second logic substrate 12B as a third substrate in this order from the incident surface side of incident light.

[0430] exist Fig.35 In , the upper side of the solid-state imaging device 1 corresponds to the light incident surface side on which incident light is incident, and the lower side of the solid-state imaging device 1 corresponds to the rear surface of the solid-state imaging device 1 as a semiconductor chip. Fig.35 In FIG. 1 , a bonding surface between the sensor substrate 11 and the first logic substrate 12A and a bonding surface between the first logic substrate 12A and the second logic substrate 12B are indicated by single-dot chain lines.

[0431] The sensor substrate 11 includes a silicon substrate 21. On the silicon substrate 21, a photodiode 22 as a photoelectric conversion element is formed in units of pixels. In the figure, a color filter 401 and an on-chip lens 28 are formed for each pixel on the light incident surface side of the silicon substrate 21 on the upper side. Fig.35 In, omitted Figure 1The planarization film 23, the interlayer insulating film 25, the bonding resin 26 and the light-transmitting substrate 27 are shown. Figure 1 As shown in FIG. 1 , the light-transmitting substrate 27 may be provided on the on-chip lens 28 via the bonding resin 26, or as shown in FIG. Fig.35 As shown, the light-transmitting substrate 27 may be omitted.

[0432] The wiring layer 402 including a multilayer metal wiring 421 and an insulating layer 422 is formed on the circuit forming surface side (lower side in the figure) opposite to the light incident surface side of the silicon substrate 21. The number of layers of the metal wiring 121 is not limited. A plurality of bonding electrodes 424 are formed on the bonding surface of the first logic substrate 12A as the lower surface of the wiring layer 402. The junction electrode 424 is connected to the internal electrode 423 provided in the same layer as the bottommost metal wiring 421 in the wiring layer 402. The internal electrode 423 is formed of, for example, the same material as the metal wiring 421, but may be formed of a different material. In addition, the junction electrode 424 is metal-bonded (for example, Cu-Cu bonded) to the junction electrode 443 of the first logic substrate 12A, and electrically connects the sensor substrate 11 and the first logic substrate 12A. As the material of the metal wiring 421 and the junction electrode 424, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. may be used. In the present embodiment, the metal wiring 421 and the junction electrode 424 are formed of copper. The insulating layer 422 is composed of, for example, a SiO 2 film, a Low-k film (low dielectric constant insulating film), a SiOC film, etc. The insulating layer 422 may include a plurality of insulating films composed of different materials.

[0433] The first logic substrate 12A includes a semiconductor substrate 431 using, for example, silicon (Si) as a semiconductor. The first logic substrate 12A has a wiring layer 432 on the front surface side of the sensor substrate 11 side of the semiconductor substrate 431, and has a junction layer 433 on the rear surface side of the second logic substrate 12B side of the semiconductor substrate 431. The wiring layer 432 includes a multilayer metal wiring 441 and an insulating layer 442. The number of layers of the metal wiring 441 is not limited. A plurality of bonding electrodes 443 are formed on a bonding surface with the sensor substrate 11, which is the upper surface of the wiring layer 432. The junction electrode 443 is metal-bonded to the junction electrode 424 of the sensor substrate 11, and electrically connects the sensor substrate 11 and the first logic substrate 12A. The junction electrode 443 is connected to an internal electrode 441A disposed in the same layer as the uppermost metal wiring 441 in the wiring layer 432. In the same layer as the bottom metal wiring 441 in the wiring layer 432, an internal electrode 441B connected to a through electrode (through silicon via (TSV)) 434 that penetrates the semiconductor substrate 431 is formed. The internal electrodes 441A and 441B are formed of, for example, the same material as the metal wiring 441, but may be formed of a different material. As materials for the metal wiring 441 and the junction electrode 443, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. may be used. In the present embodiment, the metal wiring 441 and the junction electrode 443 are formed of copper. The insulating layer 442 is composed of, for example, a SiO2 film, a Low-k film (low dielectric constant insulating film), a SiOC film, etc. The insulating layer 442 may include a plurality of insulating films composed of different materials.

[0434] The junction layer 433 formed on the rear surface side of the semiconductor substrate 431 on the second logic substrate 12B side includes one or more metal wirings 451 and an insulating layer 452. The number of layers of the metal wiring 451 is not limited. The internal electrode 451A provided in the same layer as the metal wiring 451 in the junction layer 433 is connected to the through electrode 434 and the junction electrode 453. The through electrode 434 is connected to the internal electrode 441B in the wiring layer 432 on the sensor substrate 11 side of the first logic substrate 12A, and electrically connects the wiring layer 432 and the junction layer 433 of the first logic substrate 12A. The junction electrode 453 is metal-bonded to the junction electrode 484 of the second logic substrate 12B, and electrically connects the first logic substrate 12A and the second logic substrate 12B. The materials of the metal wiring 451, the internal electrode 451A, the insulating layer 252 and the junction electrode 453 are similar to those of the metal wiring 441, the internal electrode 441A, the insulating layer 442 and the junction electrode 443 on the wiring layer 432 side.

[0435] The second logic substrate 12B has a semiconductor substrate 471 using, for example, silicon (Si) as a semiconductor. The second logic substrate 12B has a wiring layer 472 on the front surface side of the first logic substrate 12A side as the semiconductor substrate 471. The wiring layer 472 includes a multilayer metal wiring 481 and an insulating layer 482. The number of layers of the metal wiring 481 is not limited. A plurality of bonding electrodes 484 are formed on the bonding surface with the first logic substrate 12A as the upper surface of the wiring layer 472. The junction electrode 484 is metal-bonded to the junction electrode 453 of the first logic substrate 12A, and electrically connects the first logic substrate 12A and the second logic substrate 12B. The junction electrode 484 is connected to an internal electrode 483 disposed in the same layer as the uppermost metal wiring 481 in the wiring layer 472. The internal electrode 483 is formed, for example, of the same material as the metal wiring 481, but may be formed of a different material. As the material of the metal wiring 481 and the junction electrode 484, for example, copper (Cu), tungsten (W), aluminum (Al), gold (Au), etc. may be used. In this embodiment, the metal wiring 481 and the junction electrode 484 are formed of copper. The insulating layer 482 is composed of, for example, a SiO2 film, a Low-k film (low dielectric constant insulating film), a SiOC film, etc. The insulating layer 482 may include a plurality of insulating films composed of different materials.

[0436] In the second logic substrate 12B, capacitors 51LA and 51LB are formed as MIM capacitors that penetrate at least the semiconductor substrate 471. The capacitor 51LA includes a first redistribution 501A and a second redistribution 502A as capacitor electrodes, and a second interlayer insulating film 492A therebetween. The capacitor 51LB includes a first redistribution 501B and a second redistribution 502B as capacitor electrodes, and a second interlayer insulating film 492B therebetween. The capacitors 51LA and 51LB have a configuration in which a planar capacitor formed on the rear surface side of the semiconductor substrate 471 and a bottom ( 493A or 493B) of a through hole 493 (493A or 493B) formed on the side surface and at least penetrating the semiconductor substrate 471 are Fig.35 The cylindrical capacitors 51LA and 51LB are connected in series. The capacitors 51LA and 51LB are electrically isolated from the semiconductor substrate 471 by the first interlayer insulating film 491.

[0437] The capacitor 51LA penetrates the semiconductor substrate 471 and is connected to the internal electrode 483 in the wiring layer 472 of the second logic substrate 12B. The capacitor 51LB penetrates the semiconductor substrate 471 and the wiring layer 472 of the second logic substrate 12B and the junction layer 433 and the semiconductor substrate 431 of the first logic substrate 12A, and is connected to the internal electrode 441A in the wiring layer 432 of the first logic substrate 12A. In the capacitor 51LB, since the area of ​​the side surface of the through hole 493B is increased compared with the capacitor 51LA, the electrostatic capacitance can be further increased.

[0438] The capacitors 51LA and 51LB are connected to a power supply voltage, a ground line (GND), or a solder bump 47 (not shown) that inputs and outputs various signals (eg, pixel signals and control signals) on the rear surface of the second logic substrate 12B. Fig.35 In FIG. 1 , the second interlayer insulating film 43 and the protective film 48 covering the rear surface of the solid-state imaging device 1 are not shown.

[0439] In the solid-state imaging device 1 having a stacked structure in which the above three substrates are stacked, whether to connect to the internal electrode 483 in the wiring layer 472 of the second logic substrate 12B in the capacitor 51LA or to connect to the internal electrode 441A in the wiring layer 432 of the first logic substrate 12A in the capacitor 51LB can be determined by the arrangement of an interface (IF) circuit that performs, for example, format conversion of input and output signals. For example, in the case where the IF circuit is provided in the wiring layer 472 of the second logic substrate 12B, the configuration of the capacitor 51LA can be adopted, and in the case where the IF circuit is provided in the wiring layer 432 of the first logic substrate 12A, the configuration of the capacitor 51LB can be adopted.

[0440] In the solid-state imaging device 1 having a stacked structure in which the above three substrates are stacked, the capacitor 51L (51LA or 51LB) can be formed in both the through hole 493B of the internal electrode 441A connected to the first logic substrate 12A and the through hole 493A of the internal electrode 483 connected to the second logic substrate 12B, and the electrostatic capacitance can be increased by forming a deeper through hole 493.

[0441] Fig.35 An example of a stacked structure in which three substrates are stacked is shown, but the capacitor 51L in the solid-state imaging device 1 may of course be configured to have a stacked structure in which four or more substrates are stacked. In this case, the internal electrode connected to the external connection terminal via the capacitor 51L may be an internal electrode of any wiring layer of the four substrates.

[0442] <24. Eleventh Configuration Example of Capacitor>

[0443] Fig.362 is a cross-sectional view showing a detailed structure of a capacitor 51M according to an eleventh configuration example, which is the capacitor 51 included in the solid-state imaging device 1 of the eleventh embodiment.

[0444] exist Fig.36 In the eleventh configuration example, for example, as in Figure 2 In the second configuration example, only the configuration of the logic substrate 12 is shown in the solid-state imaging device 1 configured by stacking the sensor substrate 11 and the logic substrate 12. Figure 2 In the second configuration example, on the rear surface of the solid-state imaging device 1, the solder bump 47 is an external connection terminal formed in the direction of the lower side of the silicon substrate 31, but Fig.36 In the eleventh configuration example, the rear surface (land 531) of the solid-state imaging device 1 is formed thereon. Fig.36 , the external connection terminal formed as the external connection terminal other than the solder bump 47 is shown in the direction of the upper side of the silicon substrate 31. That is, Fig.36 The up and down directions in Figure 2 The up and down directions are opposite. Fig.36 In the eleventh configuration example, portions corresponding to those of the above-described respective configuration examples are denoted by the same reference numerals, and description thereof will be appropriately omitted.

[0445] like Fig.36 As shown, the capacitor 51M according to the eleventh configuration example includes a first rewiring 42A, a second rewiring 44C, and a high dielectric film 161 therebetween. The capacitor 51M has a configuration in which a planar capacitor formed on the rear surface side of the silicon substrate 31 and a cylindrical capacitor formed on the side surface and bottom of a through hole 45D that penetrates the silicon substrate 31 are connected in series. The difference between the capacitor 51M and the capacitor 51M of the other configuration examples described above is that the side surface (inner peripheral surface) of the through hole 45D is formed into a scallop shape, and the first rewiring 42A, the high dielectric film 161, and the second rewiring 44C on the side surface of the through hole 45D are also formed into a scallop shape accordingly. Scallop shape refers to a concave-convex shape in which an arc-shaped recess is repeated in multiple stages.

[0446] That is, in the silicon substrate 31, through holes 45 are formed corresponding to the internal electrodes 33 formed in the multilayer wiring layer 32 on the front surface side. A through hole 45D is formed at a position corresponding to the internal electrode 33A, and a through hole 45E is formed at a position corresponding to the internal electrode 33C. The side surfaces of the through holes 45D and 45E have an uneven shape in which arc-shaped recesses are repeated in multiple stages.

[0447] The first interlayer insulating film 41 is formed on the side surface of the through hole 45D formed at the position corresponding to the internal electrode 33A and the rear surface side of the silicon substrate 31. The first interlayer insulating film 41 electrically insulates the first redistribution wiring 42A from the silicon substrate 31. The first redistribution wiring 42A is formed on the rear surface side of the silicon substrate 31 and the side surface of the through hole 45D, and is connected to the internal electrode 33A formed in the multilayer wiring layer 32 on the front surface side. The first redistribution wiring 42A includes, for example, a seed metal 521A and a Cu wiring 522A containing a barrier metal and a Cu seed film. As the material of the barrier metal film, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), their nitride films, their carbide films, etc. can be used.

[0448] As in Fig.13 In the third configuration example, the high dielectric film 161 is formed not only in the region of the capacitor 51M but also on the entire upper surface of the silicon substrate 31. The second interlayer insulating film 43 is formed on the high dielectric film 161 in the region other than the capacitor 51M.

[0449] The second redistribution 44C is formed on the high dielectric film 161 in the region of the capacitor 51M, and is formed on the second interlayer insulating film 43 in the region other than the capacitor 51M. The second redistribution 44C is composed of, for example, a seed metal 523 containing a barrier metal and a Cu seed film, and a Cu wiring 524. The material of the barrier metal is similar to that described above. The pillar 531 is formed and exposed in a partial region of the upper surface of the second redistribution 44C, and the other regions are covered by the protective film 48. In addition, the second redistribution 44C is also connected to the first redistribution 42C connected to the internal electrode 33C.

[0450] The pillar 531 includes a seed metal 525 and copper (Cu) 526 embedded in the seed metal, and the seed metal 525 includes a barrier metal for preventing the diffusion of a metal material and a Cu seed film. As a material of the barrier metal, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), ruthenium (Ru), their nitride films (e.g., TaN or TiN), their carbide films, etc. can be used. Instead of copper (Cu) 526, a metal material such as tungsten (W), aluminum (Al), gold (Au), silver (Ag), or nickel (Ni) can be used to form it.

[0451] The first rewiring 42C is formed between the side surface of the through hole 45E formed at the position corresponding to the internal electrode 33C and the rear surface side of the silicon substrate 31 ( Fig.36The first interlayer insulating film 41 electrically insulates the first redistribution wiring 42C from the silicon substrate 31. The first redistribution wiring 42C includes, for example, a seed metal 521C including a barrier metal and a Cu seed film and a Cu wiring 522C. The material of the barrier metal is similar to that described above. The side surface of the through hole 45E has a scallop shape similar to that of the through hole 45D, and the first interlayer insulating film 41, the first redistribution wiring 42C and the high dielectric film 161 are also formed in a scallop shape. Note that although the central portion of the through holes 45D and 45E is formed by a cavity in which the second interlayer insulating film 43 or the protective film 48 is not embedded, the second interlayer insulating film 43 or the protective film 48 may be embedded as in the above-mentioned other configuration examples.

[0452] According to the capacitor 51M of the 11th configuration example constructed as described above, the side surface of the through hole 45D is formed into a scallop shape, and the first rewiring 42A, the high dielectric film 161 and the second rewiring 44C are also formed into a scallop shape. Thus, compared with the case where the side surface of the through hole 45D is a smooth surface, the relative area between the first rewiring 42A and the second rewiring 44C can be increased, and the electrostatic capacitance can be increased. Therefore, the capacitance of the capacitor element can be increased to stabilize the power supply voltage while suppressing the signal delay caused by the parasitic capacitance of the rewiring. That is, signal delay and jitter can be improved. Between the planar capacitor and the cylindrical capacitor, the electrostatic capacitance of the capacitor 51M increases on the cylindrical capacitor side close to the logic circuit (IF circuit) in the multilayer wiring layer 32 of the logic substrate 12, so that the signal waveform is more stable and can contribute to high-speed transmission.

[0453] In addition, Fig.36 In the 11th configuration example, an example is described in which all side surfaces in the depth direction from the rear surface (second surface) of the silicon substrate 31 to the front surface (first surface) are formed in a scallop shape in the through holes 45D and 45E formed in the silicon substrate 31. However, as Fig.37 As shown, only a portion of the side surface of the through holes 45D and 45E in the depth direction, in other words, half the depth from the rear surface (second surface) of the silicon substrate 31 toward the front surface (first surface) may be formed into a scallop shape, and the side surface deeper than this depth may be formed into a smooth surface. Moreover, in this case, the electrostatic capacitance can be increased compared to the case where the entire side surface of the through hole 45D is a smooth surface.

[0454] Fig.38 4 is a cross-sectional view describing a modification of the side surface shape of the through hole 45D in which the capacitor 51M is formed.

[0455] exist Fig.36 In the 11th configuration example, Fig.38As shown in FIG. 1A , an example in which the side surface of the through hole 45D is formed in a scallop shape in which arc-shaped recesses are repeatedly formed in multiple stages is described. The side surface of the through hole 45D only needs to have a shape that can ensure a larger area than in the case of a smooth surface, and may have, for example, Fig.38 The triangular shape shown in B or Fig.38 The side surface of the through hole 45D only needs to have a plurality of deep concave-convex shapes in the side surface direction perpendicular to the depth direction of the silicon substrate 31 (the plane direction of the silicon substrate 31) when viewed in cross section. Fig.38 As shown in A, the concavo-convex shape of the side surface of the through hole 45D is formed as a concave portion dug out in the side surface direction with a depth equal to or greater than 0.3 μm relative to the smooth surface of the apex of the connecting protrusion.

[0456] <25. Method for manufacturing capacitor according to eleventh configuration embodiment>

[0457] Next, we will refer to Figures 39 to 46 Description includes Fig.36 A method for manufacturing the solid-state imaging device 1 of the capacitor 51M of the eleventh configuration example shown in FIG.

[0458] First, if Fig.39 As shown, a photoresist 541 is patterned on the back surface (second surface) of the silicon substrate 31 on the side opposite to the side of the sensor substrate 11 where the multilayer wiring layer 32 is formed. In the photoresist 541, openings 542A and 542C are formed at positions corresponding to the two internal electrodes 33A and 33C, respectively.

[0459] Then, if Fig.40 As shown, the silicon substrate 31 in the region of the openings 542A and 542C is etched using the Bosch process according to the patterned photoresist 541, thereby forming through holes 45D and 45E whose side surfaces are formed in a scalloped shape. The Bosch process is a dry etching technique for digging the silicon substrate 31 in the depth direction (vertical direction) by repeating the three steps of (1) isotropic etching of silicon, (2) deposition of a protective film, and (3) anisotropic etching of Si (removal of the protective film on the bottom surface).

[0460] Next, if Fig.41 As shown, after removing the photoresist 541, as shown in Fig.42As shown, a first interlayer insulating film 41 is formed on the upper surface of the silicon substrate 31 and the side walls of the through holes 45D and 45E. For example, the first interlayer insulating film 41 can be formed by forming the first interlayer insulating film 41 on the entire upper surface of the silicon substrate 31 and the bottom surface and side walls of the through holes 45D and 45E, and then etching back to remove only the bottom surface of the through holes 45D and 45E. As the material of the first interlayer insulating film 41, an organic material such as a solder resist, an inorganic material such as a silicon oxide film (SiO2 film), etc. can be used. The solder resist can be formed using a coating device, and the silicon oxide film can be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0461] Next, if Fig.43 As shown, the first redistribution 42A connected to the internal electrode 33A and the first redistribution 42C connected to the internal electrode 33C are formed at the same time. More specifically, the first redistribution 42A includes, for example, a seed metal 521A including a barrier metal using a Ti and Cu seed film, and a Cu wiring 522A. The first redistribution 42C includes, for example, a seed metal 521C including a barrier metal using a Ti and Cu seed film, and a Cu wiring 522C. The seed metals 521A and 521C can be formed by, for example, sputtering, and the Cu wirings 522A and 522C can be formed by, for example, electroplating.

[0462] Then, if Fig.44 As shown, after forming the high dielectric film 161 on the entire upper surface of the silicon substrate 31, the second redistribution 44C is formed above the first redistribution 42A. In the region where the first redistribution 42A and 42C are formed, the high dielectric film 161 is formed on the upper surface of the first redistribution 42A and 42C, and in the region where the first redistribution 42A and 42C are not formed, the high dielectric film 161 is formed on the upper surface of the first interlayer insulating film 41. The second redistribution 44C is composed of, for example, a seed metal 523 including a barrier metal using Ti and a Cu seed film, and a Cu wiring 524. The formation method of the second redistribution 44C is the same as the formation method of the first redistribution 42C. Thus, a capacitor 51M including the first redistribution 42A, the second redistribution 44C and the high dielectric film 161 therebetween is formed.

[0463] Next, if Fig.45 As shown, a second interlayer insulating film 43 is formed on the upper surface of the high dielectric film 161. As a material of the second interlayer insulating film 43, an organic material such as a solder resist, an inorganic material such as a silicon oxide film (SiO2 film), etc. can be used. This step is similar to that in the first configuration example. Figure 4In the step of B. Furthermore, on the upper surface of the second interlayer insulating film 43, a seed metal 523 as a second redistribution wiring 44C is formed except for a portion constituting the planar capacitor and the Cu wiring 524.

[0464] Next, if Fig.46 As shown, a column 531 is formed as an external connection terminal instead of the solder bump 47 and the protective film 48, and the Fig.36 The logic substrate 12 shown. As the material of the protective film 48, for example, a photosensitive solder resist is used. The pillar 531 is formed, for example, by opening a partial area of ​​the protective film 48 and stacking and adding a metal material by chemical plating. The metal material of the pillar 531 is preferably Cu, but may be a metal material other than Cu, such as Ni or Au. The surface (upper surface) of the pillar 531 and the protective film 48 is flattened by CMP.

[0465] Through the above steps, manufacturing includes Fig.36 The logic substrate 12 of the capacitor 51M of the eleventh configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0466] According to the manufacturing method of the solid-state imaging device 1 including the capacitor 51M according to the eleventh configuration example, the capacitor 51 having increased electrostatic capacitance can be manufactured compared to the case where the entire side surface of the through hole 45D is a smooth surface.

[0467] <26. Twelfth Configuration Example of Capacitor>

[0468] Fig.47 is a cross-sectional view of a solid-state imaging device 1 according to a twelfth embodiment.

[0469] Fig.47 The solid-state imaging device 1 shown in FIG. 1 is a chip size package type CMOS solid-state imaging device configured by stacking a sensor substrate 11 and a logic substrate 12. The sensor substrate 11 and the logic substrate 12 are bonded by a surface indicated by a single dot chain line. However, Fig.47 The sensor substrate 11 is provided on the lower side and the logic substrate 12 is provided on the upper side, and the vertical direction of the solid-state imaging device 1 is Figure 1 The vertical direction is opposite.

[0470] Because the configuration of the sensor substrate 11 is Figure 1 The interlayer insulating film 25, the bonding resin 26, and the light-transmitting substrate 27 of the sensor substrate 11 may be omitted. The logic substrate 12 includes a capacitor 51N, which is the capacitor 51 according to the twelfth configuration example.

[0471] Fig.481 is a plan view of the vicinity of the capacitor 51N when viewed from the rear surface side of the solid-state imaging device 1 . Fig.47 Corresponding to along Fig.48 The cross-sectional view is taken along the line X-X' in FIG. Fig.48 In the plan view of FIG. 5 , in order to facilitate description of the structure of the capacitor 51N, a portion of the second interlayer insulating film 43, the protective film 48, etc. are omitted.

[0472] like Fig.47 As shown in , the capacitor 51N according to the twelfth configuration example is a ring capacitor composed of a column 571A, a ring wiring 572R surrounding the periphery of the column, and a high dielectric film 573 therebetween. The capacitor 51N is a MIM capacitor, the column 571A corresponds to the first electrode of the MIM capacitor, the ring wiring 572R corresponds to the second electrode of the MIM capacitor, and the high dielectric film 573 corresponds to the insulating film of the MIM capacitor. The high dielectric film 573 is, for example, a film having a relative dielectric constant higher than that of the SiO2 film, and is a material having a relative dielectric constant εr greater than 3.8 (εε83.8). As a specific material of the high dielectric film 573, the same material as the high dielectric film 161 of each of the above-mentioned configuration examples can be used, for example, a tantalum oxide film, an aluminum oxide film, a hafnium oxide film, a titanium oxide film, a zirconium oxide film, a niobium oxide film, a silicon nitride film, or a stacked film of two or more thereof can be used. Note that the insulating film between the pillar 571A and the ring wiring 572R is preferably a high dielectric film 573, but may be formed of an organic material such as a solder resist or an inorganic material such as a silicon oxide film (SiO 2 film), of course.

[0473] The pillar 571A is formed using a metal material such as copper (Cu), tungsten (W), aluminum (Al), gold (Au), silver (Ag) or nickel (Ni). In the present embodiment, when copper is used, the pillar 571A includes a seed metal 564A and copper (Cu) 565A, and the seed metal 564A includes a barrier metal for preventing the diffusion of the metal material and the Cu seed film. As the material of the barrier metal, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), ruthenium (Ru), their nitride films (e.g., TaN or TiN), their carbide films, etc. can be used.

[0474] The pillar 571A is connected to the first redistribution wiring 42D and is connected to the internal electrode 33E below the through hole 45D via the first redistribution wiring 42D. The first redistribution wiring 42D is formed on the rear surface side of the silicon substrate 31 ( Fig.47The first redistribution wiring 42D is formed on the upper side of the through hole 45D (in the upper side) and the side surface (inner peripheral surface) of the through hole 45D, and is connected to the internal electrode 33E formed in the multilayer wiring layer 32 on the front surface side. The first redistribution wiring 42D includes, for example, a barrier metal 561A, a Cu seed film 562A, and a Cu wiring 563A. As a material of the first redistribution wiring 42D, other materials similar to the above-mentioned first redistribution wiring 42A can be used.

[0475] The ring wiring 572R can also use the metal material exemplified for the pillar 571A, and can have the same material or a different material as the pillar 571A. In this embodiment, if the same material is used, the ring wiring 572R includes a seed metal 566A including a barrier metal and a Cu seed film, and copper (Cu) 567A.

[0476] like Fig.48 As shown, the ring wiring 572R is formed in a circular shape around the column 571A via a high dielectric film 573 of a predetermined film thickness (width). However, the planar shape of the ring wiring 572R is consistent with the planar shape of the pillar 571A. For example, when the planar shape of the pillar 571A is a hexagonal polygon, the planar shape of the ring wiring 572R is also a hexagonal polygon. The ring wiring 572R is a wiring that surrounds the pillar 571A in a ring shape, and is connected to another adjacent pillar 571B via the first rewiring 574. The pillar 571A is connected to the internal electrode 33E ( Fig.47 ), and the pillar 571B is connected to the internal electrode 33E below the through hole 45E via the first redistribution wiring 42E. A high dielectric film 573 is also formed on the periphery of the ring wiring 572R and the pillar 571B. The structure in which the ring wiring 572R surrounds the pillar 571A in a ring shape can increase the relative area and increase the electrostatic capacitance.

[0477] When the column 571A is the first column 571A and the adjacent column 571B is the second column 571B, different potentials are provided to the first column 571A and the second column 571B. For example, a power supply voltage is provided to the first column 571A, and a ground line (GND) is provided to the second column 571B. Thus, the capacitor 51N as a ring capacitor can have an electrostatic capacitance. Note that since the first column 571A and the second column 571B are external connection terminals, various signals such as pixel signals and control signals can be input and output.

[0478] like Fig.47As shown in the cross-sectional view of , on the upper surface of the first redistribution 42D and the upper surface of the first interlayer insulating film 41, except for the area where the capacitor 51N is formed, a second interlayer insulating film 43 is formed. The second interlayer insulating film 43 is composed of, for example, a SiO2 film, a Low-k film (low dielectric constant insulating film), a SiOC film, a SiN film, a SiON film, etc. The second interlayer insulating film 43 is preferably composed of an insulating film having higher insulation than that of the SiO2 film, such as a SiN film, a SiON film, etc. The outermost surface other than the pillar 571 (571A, 571B) is covered by a protective film 48. That is, only the pillar 571 as an external connection terminal is exposed, and the entire rear surface of the solid-state imaging device 1 except the pillar 571 is covered by the protective film 48. As a material for the protective film 48, for example, a solder resist is used, which is an organic material.

[0479] As described above, the capacitor 51N according to the twelfth configuration example includes a first columnar body 571A as a first electrode, a ring wiring 572R as a second electrode surrounding the periphery of the first electrode, and a high dielectric film 573 as an insulating film therebetween on the rear surface side (second surface side) of the silicon substrate 31. Because the configuration of the planar capacitor and the cylindrical capacitor depends on the position of the through hole and the position of the rewiring, there is a possibility that the electrostatic capacitance cannot be increased due to the design layout, and there is a possibility that the effect of high-speed transmission cannot be fully obtained. By having a capacitor 51N with a ring capacitor configuration, the capacitor can be formed on any rewiring, and the degree of freedom of design can be increased. Capacitors with necessary capacitance can be arranged without limiting the circuit design of the rewiring.

[0480] Since the high dielectric film 573 is formed only at the portion of the loop wiring 572R forming the capacitor 51N, chip warping can also be suppressed. Since the loop wiring 572R is covered with the second interlayer insulating film 43 where metal is hardly diffused except for a portion, the semiconductor element has high reliability.

[0481] The first pillar 571A as the first electrode is an external connection terminal, and the ring wiring 572R as the second electrode is connected to the second pillar 571B as the adjacent external connection terminal via the first rewiring 574. The first pillar 571A is connected to the internal electrode 33E of the multilayer wiring layer 32 via the first rewiring layer 42D. In the lower layer of the ring wiring 572R as the second electrode, the first rewiring 42D is formed via the high dielectric film 573, and the ring wiring 572R, the first rewiring 42D and the high dielectric film 573 therebetween also constitute a capacitor in the vertical direction.

[0482] <27. Manufacturing Method of Capacitor According to Twelfth Configuration Example>

[0483] Next, we will refer to Figures 49 to 57 Description includes Fig.47 and Fig.48 A method of manufacturing the solid-state imaging device 1 of the capacitor 51M of the twelfth configuration example shown in FIG.

[0484] like Fig.49 As shown in FIG. , a step is created until a through hole 45D is formed at a position connected to the internal electrode 33E of the multilayer wiring layer 32, and on the rear surface side ( Fig.49 The first redistribution wiring 42D connected to the internal electrode 33E is formed on the upper side of the through hole 45D and inside the through hole 45D. The first redistribution wiring 42D includes, for example, a barrier metal 561A, a Cu seed film 562A, and a Cu wiring 563A. After the barrier metal 561A and the Cu seed film 562A are formed by, for example, sputtering, and the Cu wiring 563A is formed by, for example, electrolytic plating, the barrier metal 561A, the Cu seed film 562A, and the Cu wiring 563A in the area other than the desired area are removed by wet etching or the like, thereby entering Fig.49 The status shown in .

[0485] Then, if Fig.50 As shown, a second interlayer insulating film 43 as an insulating film is formed on the upper surface of the first redistribution wiring 42D and the first interlayer insulating film 41. As the material of the second interlayer insulating film 43, an organic material such as a solder resist, an inorganic material such as a SiO2 film, a SiN film, or a SiON film, etc. can be used. SiN film and SiON film with higher insulation than SiO2 film are preferred. SiO2 film, SiN film, SiON film, etc. can be formed using, for example, CVD, ALD, etc.

[0486] Next, if Fig.51 As shown, the second interlayer insulating film 43 in the region 581 where the capacitor 51N is formed on the first redistribution wiring 42D is removed by dry etching until the first redistribution wiring 42D is exposed.

[0487] Then, if Fig.52 As shown, after the high dielectric film 573 is embedded in the formation region 581, a necessary amount is etched back. The high dielectric film 573 is a film having a dielectric constant higher than that of the SiO2 film, for example, a material having a dielectric constant εr greater than 3.8 (εr>3.8).

[0488] Next, if Fig.53 As shown, the high dielectric film 573 in the region 582 to be the pillar 571A is removed by dry etching, and then Fig.54As shown, the high dielectric film 573 in the region 583 to become the ring wiring 572R is removed by dry etching. The dry etching of the high dielectric film 573 is performed by masking the region other than the etching target region with a photoresist. In the region 582 to become the pillar 571A, the high dielectric film 573 is removed until the first redistribution wiring 42D is exposed, but in the region 583 to become the ring wiring 572R, the high dielectric film 573 is removed so as to remain on the first redistribution wiring 42D with a predetermined film thickness. Fig.54 The high dielectric film 573 remaining in the state eventually becomes an insulating film between the column 571A of the capacitor 51N and the ring wiring 572R.

[0489] Next, if Fig.55 As shown, a column 571A including a seed metal 564A containing a barrier metal and a Cu seed film and copper 565A' is formed in a region 582, and a ring wiring 572R including a seed metal 566A containing a barrier metal and a Cu seed film and copper 567A is formed in a region 583. As a material of the barrier metal, for example, Ta, TaN, Ti, TiN, Ru, etc. can be used. The barrier metal and the Cu seed film are formed, for example, by sputtering, and the embedding of copper is performed by electroplating. After embedding copper, unnecessary metal on the upper surface is removed and it is flattened by CMP.

[0490] Next, if Fig.56 As shown, a protective film 48 is formed and masked in a region other than the upper surface of the pillar 571A, and then Fig.57 As shown, copper is further stacked on the upper part of copper 565A' by chemical plating. The upper surfaces of copper 565A and protective film 48 formed by stacking are flattened by CMP. As a material of protective film 48, for example, photosensitive solder resist is used. The metal material of column 531 is preferably Cu, but may be a metal material other than Cu, such as Ni or Au.

[0491] Through the above steps, manufacturing includes Fig.47 The logic substrate 12 of the capacitor 51N of the twelfth configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0492] According to the method of manufacturing the solid-state imaging device 1 including the capacitor 51N according to the twelfth configuration example, the capacitor 51 having necessary capacitance can be formed on any rewiring line.

[0493] <28. First Variation of the Twelfth Configuration Example>

[0494] Fig.58 2 is a cross-sectional view showing a detailed structure of a first modification example of the capacitor 51N according to the twelfth configuration example.

[0495] exist Fig.58 in Fig.47 Portions corresponding to those of the twelfth configuration example shown in are denoted by the same reference numerals, and descriptions thereof will be appropriately omitted, and different portions will be described.

[0496] Fig.58 The first variant shown in FIG. 1 includes a Fig.47 The capacitor 51N of the annular capacitor configuration shown in FIG. Fig.19 Capacitor 51P is a combination of a planar capacitor and a cylindrical capacitor as described.

[0497] The capacitor 51P having a planar capacitor and a cylindrical capacitor includes a first redistribution wiring 42D, a second redistribution wiring 44D, and a high dielectric film 161 interposed therebetween. The first redistribution wiring 42D is composed of the above Fig.47 The three layers of the barrier metal 561A, the Cu seed film 562A and the Cu wiring 563A are shown, but Fig.58 , the stack of the barrier metal 561A and the Cu seed film 562A is represented by one layer of the seed metal 561A'. Fig.13 , the high dielectric film 161 is formed on the entire rear surface side of the silicon substrate 31. That is, in the region where the first repeated wiring 42D is formed, the high dielectric film 161 is formed on the upper surface of the first redistribution wiring 42D, and in the region where the first redistribution wiring 42D is not formed, the high dielectric film is formed on the upper surface of the first interlayer insulating film 41. The second interlayer insulating film 43 is formed on the high dielectric film 161 except for the planar capacitor region of the capacitor 51P. The second redistribution wiring 44D includes: a seed metal 801A' as a stack of a barrier metal and a Cu seed film; and a Cu wiring 803A.

[0498] The second rewiring 44D is connected to the capacitor 51N of the annular capacitor structure, and is connected to the first rewiring 42D formed in the through hole 45D different from the through hole 45D formed by the cylindrical capacitor of the capacitor 51P. The potential of the pillar 571A as one capacitor electrode of the capacitor 51N and the potential of the second rewiring 44D as one capacitor electrode of the capacitor 51P are the same potential, and the potential of the ring wiring 572R as another capacitor electrode of the capacitor 51N and the potential of the first rewiring 42D as another capacitor electrode of the capacitor 51P are the same potential. In the capacitor 51N with the annular capacitor configuration, a high dielectric film 573 is formed as an insulating film sandwiched between a pair of capacitor electrodes. The high dielectric film 573 is not only formed between the pillar 571A and the ring wiring 572R and between the second rewiring 44D and the ring wiring 572R, but also formed on the entire upper surface of the silicon substrate 31 including the upper side of the second rewiring 44D and the second interlayer insulating film 43. The upper surface of the high dielectric film 573 and the upper surface of the ring wiring 572R are covered with the protective film 48, and only the upper surface of the support 571A serving as the external connection terminal is exposed.

[0499] As described above, the capacitor 51M according to the twelfth configuration example can be used together with the capacitor 51P including the planar capacitor and the cylindrical capacitor. Thus, the electrostatic capacitance can be further increased, so high-speed transmission can be performed.

[0500] <29. Method for Manufacturing Capacitor According to First Modification Example of Twelfth Configuration Example>

[0501] Next, refer to Figure 59 to Figure 68 , the description includes Fig.58 A method of manufacturing the solid-state imaging device 1 of the capacitors 51N and 51P of the first modification example of the twelfth configuration example shown in FIG.

[0502] like Fig.59 As shown in FIG. , a step is created until a through hole 45D is formed at a position connected to the internal electrode 33E of the multilayer wiring layer 32, and on the rear surface side ( Fig.59 A first redistribution wiring 42D connected to the internal electrode 33E is formed on the upper side of the through hole 45D and inside the through hole 45D. The first redistribution wiring 42D includes, for example, a seed metal 561A' and a Cu wiring 563A.

[0503] Then, if Fig.60 As shown, a high dielectric film 161 is formed on the entire upper surface of the silicon substrate 31. In the region where the first redistribution wiring 42D is formed, the high dielectric film 161 is formed on the upper surface of the first redistribution wiring 42D, and in the region where the first redistribution wiring 42D is not formed, the high dielectric film 161 is formed on the upper surface of the first interlayer insulating film 41.

[0504] Next, if Fig.61 As shown, after the second interlayer insulating film 43 is formed on the upper surface of the high dielectric film 161, the second interlayer insulating film 43 in the region 821 serving as the capacitor 51P and the region 822 connecting the second redistribution 44D and the first redistribution 42D is removed. In the region 822 connecting the second redistribution 44D and the first redistribution 42D, the high dielectric film 161 is also etched. As the material of the second interlayer insulating film 43, an organic material such as a solder resist, an inorganic material such as a silicon oxide film (SiO2 film), etc. can be used. In the case where the material of the second interlayer insulating film 43 is a solder resist having photosensitivity, the second interlayer insulating film 43 in the regions 821 and 822 can be removed by photolithography.

[0505] Then, if Fig.62 As shown, the second redistribution wiring 44D is formed in a prescribed region on the second interlayer insulating film 43 including the region 821 and the region 822. The second redistribution wiring 44D includes: a seed metal 801A' which is a stack of a barrier metal and a Cu seed film; and a Cu wiring 803A.

[0506] Then, if Fig.63 As shown, a high dielectric film 573 is formed on the upper surfaces of the second redistribution wiring 44D and the second interlayer insulating film 43. The high dielectric film 573 can be formed by using, for example, CVD, ALD, sputtering, or the like.

[0507] Next, if Fig.64 As shown, the second interlayer insulating film 43 in the region 823 where the capacitor 51N on the second redistribution wiring 44D is formed is removed by dry etching until the second redistribution wiring 44D is exposed.

[0508] Next, if Fig.65 As shown, the high dielectric film 573 in the region 824 that will become the ring wiring 572R around the region 823 that will become the pillar 571A is removed by dry etching. In the region 823 that will become the pillar 571A, the high dielectric film 573 is removed until the second redistribution wiring 44D is exposed, but in the region 824 that will become the ring wiring 572R, the high dielectric film 573 is removed to maintain a prescribed film thickness on the second redistribution wiring 44D. Fig.65 The high dielectric film 573 remaining in the state eventually becomes an insulating film between the column 571A of the capacitor 51N and the ring wiring 572R.

[0509] Next, if Fig.66As shown in FIG. 8 , a column 571A including a seed metal 564A containing a barrier metal and a Cu seed film and copper 565A′ is formed in a region 823, and a ring wiring 572R including a seed metal 566A containing a barrier metal and a Cu seed film and copper 567A is formed in a region 824. As a material of the barrier metal, for example, Ta, TaN, Ti, TiN, Ru, etc. can be used. The barrier metal and the Cu seed film are formed, for example, by sputtering, and the embedding of copper is performed by electroplating. After embedding copper, unnecessary metal on the upper surface is removed and it is flattened by CMP.

[0510] Next, if Fig.67 As shown, the pillar 571A is formed of the copper 565A obtained by further stacking copper on the upper portion of the copper 565A' by electroless plating and the seed metal 564A. Fig.68 As shown, after the protective film 48 is formed in the region other than the pillar 571A, the upper surface of the pillar 571A and the protective film 48 is flattened by CMP. Fig.56 and Fig.57 In the manufacturing method of the twelfth configuration example described, the protective film 48 is first formed and then copper is stacked by chemical plating, but as Fig.67 and Fig.68 As shown, a protective film 48 may be formed after copper is stacked. Copper may be stacked by electroless plating or a semi-additive method.

[0511] Through the above steps, manufacturing includes Fig.58 The logic substrate 12 of the capacitors 51N and 51P of the first modification of the twelfth configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0512] <30. Modification 2 of the twelfth configuration example>

[0513] Fig.69 2 is a cross-sectional view showing a detailed structure of a second modification example of the capacitor 51N according to the twelfth configuration example.

[0514] exist Fig.69 in Fig.58 Portions corresponding to those of the first modification example shown in FIG. 1 are denoted by the same reference numerals, and descriptions thereof will be appropriately omitted, and different portions will be described.

[0515] Fig.69 The second modification shown in Fig.58 The first variant shown in FIG. 1 has the same feature as that a Fig.47 The capacitor 51N of the annular capacitor configuration shown in FIG. Fig.19 The capacitor 51P is a combination of the planar capacitor and the cylindrical capacitor described in FIG. Fig.58 The first modification shown is different in that a portion of the high dielectric film 573 is replaced by a third interlayer insulating film 831. Fig.58 In the first modification shown, the high dielectric film 573 is formed not only between the pillar 571A and the ring wiring 572R and between the second redistribution wiring 44D and the ring wiring 572R, but also on the entire upper surface of the silicon substrate 31 including the upper side of the second redistribution wiring 44D and the second interlayer insulating film 43. Fig.69 In the second modification example, the high dielectric film 573 is formed only between the second redistribution wiring 44D and the ring wiring 572R and between the pillar 571A and the ring wiring 572R, which are regions constituting the capacitor 51N, and the third interlayer insulating film 831 is formed on the upper surface of the other second redistribution wiring 44D and the second interlayer insulating film 43. As the third interlayer insulating film 831, the same type of material as that of the second interlayer insulating film 43 can be used. The third interlayer insulating film 831 and the second interlayer insulating film 43 can be formed of the same material or different materials.

[0516] As described above, the capacitor 51M according to the twelfth configuration example can be used together with the capacitor 51P including the planar capacitor and the cylindrical capacitor. Thus, the electrostatic capacitance can be further increased, so high-speed transmission can be performed.

[0517] <31. Method for Manufacturing Capacitor According to Second Modification of Twelfth Configuration Example>

[0518] Next, we will refer to Figure 70 to Figure 75 Description includes Fig.69 A method of manufacturing the solid-state imaging device 1 of the capacitors 51N and 51P of the second modification example of the twelfth configuration example shown in FIG.

[0519] Until the formation Fig.70 The steps of the second redistribution wiring 44D shown are the same as those of the first modification example described above. Fig.70 is the same as the first variant Fig.62 Same status.

[0520] Then, if Fig.71 As shown, a third interlayer insulating film 831 is formed on the upper surfaces of the second redistribution wiring 44D and the second interlayer insulating film 43. The third interlayer insulating film 831 may be a SiO2 film, a SiN film, a SiON film, etc. formed by, for example, CVD, ALD, etc. Thereafter, the third interlayer insulating film 831 in the region 841 where the capacitor 51N on the second redistribution wiring 44D is formed is removed by dry etching until the second redistribution wiring 44D is exposed.

[0521] Then, if Fig.72As shown, after the high dielectric film 573 is embedded in the opening region 841, the entire upper surface is flattened by CMP. The high dielectric film 573 may be, for example, a tantalum oxide film, an aluminum oxide film, a hafnium oxide film, a titanium oxide film, a zirconium oxide film, a niobium oxide film, a silicon nitride film, or the like, or may be a stacked film of two or more thereof. The high dielectric film 573 may be formed by using, for example, CVD, ALD, sputtering, or the like.

[0522] Next, if Fig.73 As shown, the high dielectric film 573 in the region 842 to be the pillar 571A is removed by dry etching until the second redistribution wiring 44D is exposed.

[0523] Then, if Fig.74 As shown, the high dielectric film 573 in the region 843 to be the ring wiring 572R around the region 842 to be the pillar 571A is removed by dry etching. In the region 842 to be the pillar 571A, the high dielectric film 573 is removed until the second redistribution wiring 44D is exposed, but in the region 843 to be the ring wiring 572R, the high dielectric film 573 is removed so as to remain on the second redistribution wiring 44D with a predetermined film thickness. Fig.74 The high dielectric film 573 remaining in the state eventually becomes an insulating film between the column 571A of the capacitor 51N and the ring wiring 572R.

[0524] Next, if Fig.75 As shown, a column 571A including a seed metal 564A containing a barrier metal and a Cu seed film and copper 565A' is formed in a region 842, and a ring wiring 572R including a seed metal 566A containing a barrier metal and a Cu seed film and copper 567A is formed in a region 843. As a material of the barrier metal, for example, Ta, TaN, Ti, TiN, Ru, etc. can be used. The barrier metal and the Cu seed film are formed, for example, by sputtering, and the embedding of copper is performed by electroplating. After embedding copper, unnecessary metal on the upper surface is removed and it is flattened by CMP.

[0525] The pillar 571A is formed by stacking copper on the copper 565A' and Fig.75 The step of forming the protective film 48 in the region other than the pillar 571A in the subsequent figures is similar to that in reference numeral 571A. Fig.56 and Fig.57 Described steps or references Fig.67 and Fig.68 described steps and are therefore omitted.

[0526] Through the above steps, manufacturing includes Fig.69The logic substrate 12 of the capacitors 51N and 51P of the second modification of the twelfth configuration example shown in FIG. The logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time to complete the solid-state imaging device 1 .

[0527] <32. Modification 3 of the twelfth configuration example>

[0528] Fig.76 2 is a cross-sectional view showing a detailed structure of a third modification example of the capacitor 51N according to the twelfth configuration example.

[0529] exist Fig.76 In, corresponding to Fig.58 The parts of those of the first modification example shown in are denoted by the same reference numerals, and the description thereof will be appropriately omitted, and the different parts will be described.

[0530] Fig.76 The third modification shown in Fig.58 The first variant shown in the figure has the common feature of providing a Fig.47 The annular capacitor configuration shown in FIG. 51N includes capacitors 51N and Fig.19 The capacitor 51P is a combination of the planar capacitor and the cylindrical capacitor described in FIG. Fig.58 The first modification example shown is different in that the high dielectric film 161, the second interlayer insulating film 43, and the high dielectric film 573 of the first modification example are replaced with a high dielectric film 851. As the high dielectric film 851, the same type of material as the high dielectric film 161 or the high dielectric film 573 can be used. The high dielectric film 161 or the high dielectric film 573 can be formed of the same material or can be formed of different materials. In addition, in Fig.58 In the first modification shown in FIG. 5 , the capacitor 51N and the capacitor 51P are formed in different regions in a plan view, but in FIG. Fig.76 In the third modification example, the capacitor 51N and the capacitor 51P are formed in a partially overlapping region in a plan view. This is because the capacitor 51N can be formed at any position of the second redistribution wiring 44D as long as it is electrically connected to the second redistribution wiring 44D.

[0531] As described above, the capacitor 51M according to the twelfth configuration example can be used together with the capacitor 51P including the planar capacitor and the cylindrical capacitor. Thus, the electrostatic capacitance can be further increased, so high-speed transmission can be performed.

[0532] <33. Method for Manufacturing Capacitor According to Third Modification Example of Twelfth Configuration Example>

[0533] Next, refer to Figures 77 to 80 , the description includes Fig.76A method of manufacturing the solid-state imaging device 1 of the capacitors 51N and 51P of the third modification example of the twelfth configuration example shown in FIG.

[0534] like Fig.77 As shown in the second modification example described above, the first redistribution wiring 42D connected to the internal electrode 33E is formed on the rear surface side of the silicon substrate 31 ( Fig.77 After forming the high dielectric film 851A on the entire upper surface of the silicon substrate 31 including the upper surface of the first redistribution wiring 42D, the high dielectric film 851A in the region 861 connecting the second redistribution wiring 44D and the first redistribution wiring 42D is removed by etching. The high dielectric film 851A is formed to have the same film thickness as the high dielectric film 161 of the second modification example.

[0535] Then, if Fig.78 As shown, the second redistribution 44D is formed in the region 861 where the first redistribution 42D is exposed and in a predetermined region on the high dielectric film 851A. The second redistribution 44D includes a seed metal 801A' which is a stack of a barrier metal and a Cu seed film, and a Cu wiring 803A.

[0536] Then, if Fig.79 As shown in FIG. 1 , a high dielectric film 851B having the same film thickness as the high dielectric film 573 of the first modification example is formed on the upper surface of the second redistribution 44D and the high dielectric film 851A by CVD, ALD, sputtering, etc. The high dielectric film 851B having such a film thickness and the high dielectric film 851A constituting the insulating film of the capacitor 51P constitute a Fig.76 High dielectric film 851.

[0537] Afterwards, if Fig.80 As shown, capacitor 51N having a ring capacitor configuration and protective film 48 are formed. Since the method of forming capacitor 51N and protective film 48 is similar to the method of the above-mentioned twelfth configuration example and the first and second modifications, the description thereof is omitted.

[0538] <Comparison of First to Third Modifications>

[0539] Fig.58 The first variant example, Fig.69 The second variant and Fig.76 The third variant of the present invention has the following features in common: Fig.47 The capacitor 51N of the annular capacitor configuration shown is included in Fig.19 Capacitor 51P is a combination of a planar capacitor and a cylindrical capacitor described in FIG.

[0540] On the other hand, the difference is that in Fig.58In the first modification example, the thick film between the first interlayer insulating film 41 and the protective film 48 on the rear surface of the silicon substrate 31 includes two layers of the second interlayer insulating film 43 and the high dielectric film 573. Fig.69 In the second modification example, the second interlayer insulating film 43 and the third interlayer insulating film 831 are included. Fig.76 In the third variation example, a high dielectric film 851 is included.

[0541] In the first modification, since the high dielectric film 573 does not need to be limited to a portion of the region of the capacitor 51N having the annular capacitor configuration and other regions in a plan view, the manufacturing process is simplified and the manufacturing cost can be suppressed.

[0542] On the other hand, in the second variant, it is necessary to form a high dielectric film 573 and a third interlayer insulating film 831 in the area of ​​the capacitor 51N having a ring capacitor configuration and other areas in the plan view, respectively, but by minimizing the area of ​​the high dielectric film 573, the warping of the entire chip caused by the high dielectric film can be suppressed and the reliability can be improved.

[0543] The third modification is a modification of the arrangement of the capacitor 51N having a ring capacitor configuration. This is an example in which the high dielectric film 851 is not divided into the region of the capacitor 51N and other regions as in the first modification, but they can be divided as in the second modification.

[0544] <34. Thirteenth Configuration Example of Capacitor>

[0545] Fig.81 is a cross-sectional view of a solid-state imaging device 1 according to a thirteenth embodiment.

[0546] Fig.81 The solid-state imaging device 1 shown in FIG. 1 is a chip size package type CMOS solid-state imaging device configured by stacking a sensor substrate 11 and a logic substrate 12. The sensor substrate 11 and the logic substrate 12 are bonded by a surface indicated by a single dot chain line. However, Fig.81 The sensor substrate 11 is arranged on the lower side and the logic substrate 12 is arranged on the upper side, and the vertical direction of the solid-state imaging device 1 is shown. Figure 1 The vertical direction in the opposite direction. The pillar (soldering area) 531 (which is an external connection terminal other than the solder bump 47) is formed on Fig.81 On the rear surface side of the solid-state imaging device 1 on the upper side in FIG.

[0547] Because the configuration of the sensor substrate 11 is Figure 1The interlayer insulating film 25, the bonding resin 26, and the light-transmitting substrate 27 of the sensor substrate 11 may be omitted. The logic substrate 12 includes a capacitor 51P, and the capacitor 51P includes Fig.58 A combination of planar capacitors and cylindrical capacitors as shown in FIG.

[0548] The capacitor 51P includes a first redistribution wiring 42D, a second redistribution wiring 44D, and a high dielectric film 901 therebetween. Fig.81 In the embodiment, the first redistribution wiring 42D includes a seed metal 561A' which is a stack of a barrier metal 562A and a Cu seed film 561A, and a Cu wiring 563A. The first redistribution wiring 42D is formed on the rear surface side ( Fig.81 ) and Fig.81 The high dielectric film 901 is formed on the side surface (inner peripheral surface) and bottom of the through hole 45G on the right side of the through hole 45G, and is connected to the internal electrode 33G below the through hole 45G. The high dielectric film 901 is, for example, a high dielectric film having a relative dielectric constant higher than that of a SiO2 film, but may also be a SiO2 film. The material of the high dielectric film 901 is similar to that of the above-mentioned Fig.58 . The materials of the high dielectric films 161 and 573 of the twelfth configuration example shown in . Similar to the high dielectric film 161 of the twelfth configuration example, the high dielectric film 901 is formed on the entire rear surface side of the silicon substrate 31. That is, in the region where the first repeated wiring 42D is formed, the high dielectric film 901 is formed on the upper surface of the first redistribution wiring 42D, and in the region where the first redistribution wiring 42D is not formed, the high dielectric film 901 is formed on the upper surface of the first interlayer insulating film 41. The second interlayer insulating film 43 is formed on the high dielectric film 901 except for the planar capacitor region of the capacitor 51P. The second redistribution wiring 44D includes: a seed metal 801A' as a stack of a barrier metal and a Cu seed film; and a Cu wiring 803A.

[0549] The pillar 531 is formed and exposed in a partial area of ​​the upper surface of the second rewiring 44D, and the other areas are covered by the protective film 48. The pillar 531 includes a seed metal 525 and copper (Cu) 526 embedded in the seed metal, and the seed metal 525 includes a barrier metal for preventing the diffusion of metal materials and Cu seed films. As the material of the barrier metal, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), ruthenium (Ru), their nitride films (e.g., TaN or TiN), their carbide films, etc. can be used. Instead of copper (Cu) 526, a metal material such as tungsten (W), aluminum (Al), gold (Au), silver (Ag) or nickel (Ni) can be used to form it.

[0550] Formed in Fig.81The first redistribution 42D on the side surface and bottom of the through hole 45F on the left side is connected to the internal electrode 33F below the through hole 45F. The first redistribution 42D connects the front surface side and the rear surface side of the silicon substrate 31, and is also connected to the pillar 531 via the second redistribution 44D to electrically connect the pillar 531 and the internal electrode 33F.

[0551] Fig.81 The internal electrode 33F below the through hole 45F on the left side has, for example, Fig.82 The multi-layer wiring structure shown in FIG.

[0552] Fig.82 It is shown Fig.81 2 is a cross-sectional view of a first configuration example of an internal electrode 33F in FIG. 1 , and is an enlarged cross-sectional view of the vicinity of the internal electrode 33F.

[0553] Fig.81 The multilayer wiring layer 32 in the embodiment includes a plurality of metal wiring layers 911 and an interlayer insulating film 34 interposed therebetween. The internal electrode 33F has a multilayer wiring structure in which the lattice pattern wirings D1 to D5 are arranged in the substrate depth direction ( Fig.82 The layers are stacked in a vertical direction (in the vertical direction), and the upper and lower parts are connected by a contact wiring 912.

[0554] like Fig.83 As shown in the plan view of , each of the grid-pattern wirings D1 to D5 has a grid-pattern shape, and is arranged so that the positions of the openings are staggered (alternately shifted) between adjacent grid-pattern wirings Dx (x=any one of 1 to 5). Fig.83 The diagram shows the relationship between the grid pattern wiring D1 and the grid pattern wiring D2 among the grid pattern wirings D1 to D5. The openings of the grid pattern wirings D3 and D5 are arranged at the same positions as the grid pattern wiring D1, and the opening of the grid pattern wiring D4 is arranged at the same position as the grid pattern wiring D2.

[0555] exist Fig.82 In the embodiment, among the grid pattern wirings D1 to D5, the upper surface (first surface) of the grid pattern wiring D1 closest to the silicon substrate 31 is connected to the first redistribution wiring 42D (seed metal 561A' and Cu wiring 563A) formed at the bottom portion of the through hole 45F, thereby electrically connecting the internal electrode 33F and the first redistribution wiring 42D. A first interlayer insulating film 41 that electrically insulates the silicon substrate 31 from the first redistribution wiring 42D is formed on the side surface of the through hole 45F. A shallow trench isolation (STI) 921 is formed between the silicon substrate 31 and the internal electrode 33F around the plane region connected to the first redistribution wiring 42D, and the shallow trench isolation (STI) 921 is electrically insulated.

[0556] As described above, in the solid-state imaging device 1 according to the thirteenth embodiment, the internal electrode 33F has a multilayer wiring structure in which a plurality of grid pattern wirings Dx are arranged so that the positions of the openings are staggered. Therefore, the internal electrode 33F can be connected to the first redistribution wiring 42D with low resistance.

[0557] Fig.84 It is shown Fig.81 2 is a cross-sectional view of a second configuration example of an internal electrode 33F in FIG. 1 , and is an enlarged cross-sectional view of the vicinity of the internal electrode 33F.

[0558] exist Fig.82 In the internal electrode 33F of the first configuration example shown, the bottom of the first redistribution wiring 42D (seed metal 561A′ and Cu wiring 563A) is formed flat, and the first redistribution wiring 42D is connected only to the upper surface of the grid pattern wiring D1 closest to the silicon substrate 31 .

[0559] On the other hand, Fig.84 In the second configuration example, the first redistribution wiring 42D is embedded in the upper surface of the grid pattern wiring D2 through the opening of the grid pattern wiring D1, whereby the bottom of the first redistribution wiring 42D is formed into a concave-convex shape. Compared with the case where the bottom of the first redistribution wiring 42D of the first configuration example has a flat shape, the depth 922 of the protrusion is formed to be, for example, about 200 nm. The first redistribution wiring 42D is connected at the upper surface of the grid pattern wiring D1, the side surface of the opening, and the upper surface of the grid pattern wiring D2, and the connection surface area between the internal electrode 33F and the first redistribution wiring 42D can be increased.

[0560] Fig.85 It is shown in Fig.81 2 is a sectional view of a first configuration example of an internal electrode 33G on the right side of FIG. 1 , to which a first rewiring 42D of a capacitor 51P including a cylindrical capacitor is connected, and is an enlarged sectional view of the vicinity of the internal electrode 33G.

[0561] As in Fig.84 In the second configuration example of the internal electrode 33F shown in FIG. Fig.85 The internal electrode 33G of the first configuration example shown in has a configuration in which the grid pattern wirings D1 to D5 and the grid pattern wiring Dx vertically adjacent to each other are connected by a contact wiring 912 , and is connected to the metal wiring layer 911 in the multilayer wiring layer 32 .

[0562] The first rewiring 42D includes Fig.81 The seed metal 561A' and Cu wiring 563A shown in FIG. Fig.85A high dielectric film 901 is formed on the upper surface of the first redistribution wiring 42D, and a second redistribution wiring 44D including a seed metal 801A″ and a Cu wiring 803A is formed on the upper surface of the high dielectric film 901.

[0563] The second redistribution wiring 44D, the high dielectric film 901, and the first redistribution wiring 42D are embedded in the upper surface of the grid pattern wiring D2 through the opening of the grid pattern wiring D1 to form a concave-convex shape. The second redistribution wiring 44D, the high dielectric film 901, and the first redistribution wiring 42D dug out below the upper surface of the grid pattern wiring D1 are referred to as the cylindrical capacitor protrusion 941 of the capacitor 51P. The first redistribution wiring 42D is connected to the upper surface of the grid pattern wiring D1, the side surface of the opening, and the upper surface of the grid pattern wiring D2. Fig.86 Shown in Fig.85 A plan view observed in a plane passing through the grid pattern wiring D1 in the cross-sectional view of FIG.

[0564] The internal electrode 33G of the first configuration example also has a multilayer wiring structure, so that the connection area of ​​the capacitor 51P including a combination of a planar capacitor and a cylindrical capacitor with the first redistribution wiring 42D can be increased and low resistance can be achieved.

[0565] Fig.87 is a diagram showing that the first rewiring 42D of the capacitor 51P is connected to Fig.81 2 is a sectional view of a second configuration example of the internal electrode 33G on the right side of FIG. 1 , and is an enlarged sectional view of the vicinity of the internal electrode 33G.

[0566] exist Fig.85 In the internal electrode 33G of the first configuration example shown, the grid pattern wirings D1 to D5 having a grid pattern shape are arranged so that the positions of the openings are staggered (alternately offset) between the adjacent upper grid pattern wirings Dx and lower grid pattern wirings Dx (x=any one of 1 to 5). Then, the cylindrical capacitor protrusion 941 of the capacitor 51P is embedded in the upper surface of the grid pattern wiring D2 through the opening of the grid pattern wiring D1.

[0567] on the other hand, Fig.87The internal electrodes 33G of the second configuration example shown in are arranged so that the positions of all openings of the grid pattern shape of the grid pattern wirings D1 to D5 coincide with each other and overlap with each other when viewed in a plan view. Then, the cylindrical capacitor protrusion 941 of the capacitor 51P is embedded in the upper surface of the metal wiring layer 911 through all openings of the grid pattern wirings D1 to D5. The first heavy wiring 42D is connected to the upper surface of the grid pattern wiring D1, the side surface of the opening portion of the grid pattern wirings D1 to D5, and the upper surface of the metal wiring layer 911. Compared with the case where the bottom of the first heavy wiring 42D has a planar shape, the depth 923 of the cylindrical capacitor protrusion 941 is formed to be, for example, about 0.1 to 10 μm.

[0568] The internal electrode 33G of the second configuration example also has a multilayer wiring structure, so that the connection area of ​​the capacitor 51P including a combination of a planar capacitor and a cylindrical capacitor with the first redistribution wiring 42D can be increased and low resistance can be achieved.

[0569] Fig.88 is a diagram showing that the first rewiring 42D of the capacitor 51P is connected to Fig.81 2 is a sectional view of a third configuration example of the internal electrode 33G on the right side of FIG. 1 , and is an enlarged sectional view in the vicinity of the internal electrode 33G.

[0570] Fig.88 The internal electrode 33G of the third configuration example shown in FIG. Fig.85 The structure in which the grid pattern wirings D1 to D5 are staggered and the Fig.87 The structure in which all the grid pattern wirings D1 to D5 shown in are arranged at the same position is combined. That is, the grid pattern wirings D1 to D3 are configured in a manner that the openings of the grid pattern wirings Dx are located at the same position, and the grid pattern wirings D4 and D5 are configured in a manner that the openings of the grid pattern wirings Dx are staggered. In the top view, the grid pattern wiring D5 has the same configuration as the grid pattern wirings D1 to D3. The cylindrical capacitor protrusion 941 of the capacitor 51P is embedded in the upper surface of the grid pattern wiring D4 through the openings of the grid pattern wirings D1 to D3. The first heavy wiring 42D is connected to the upper surface of the grid pattern wiring D1, the side surfaces of the openings of the grid pattern wirings D1 to D3, and the upper surface of the grid pattern wiring D4.

[0571] In this way, by staggering or aligning the positions of the openings of the grid pattern wirings D1 to D5 , the cylindrical capacitor protrusion 941 of the capacitor 51P can be embedded at an arbitrary depth in the multilayer wiring structure having the grid pattern wirings D1 to D5 . Fig.88An example is an example in which the cylindrical capacitor protrusion 941 of the capacitor 51P is embedded until the upper surface of the grid pattern wiring D4, and the patterns of the grid pattern wirings D1 to D3 are arranged in the same position, but it goes without saying that a configuration of embedding until the upper surface of the grid pattern wiring D3 or a configuration of embedding until the upper surface of the grid pattern wiring D5 is also possible.

[0572] The internal electrode 33G of the third configuration example also has a multilayer wiring structure, so that the connection area of ​​the capacitor 51P including a combination of a planar capacitor and a cylindrical capacitor with the first redistribution wiring 42D can be increased and low resistance can be achieved.

[0573] Fig.89 is a diagram showing that the first rewiring 42D of the capacitor 51P is connected to Fig.81 2 is a sectional view of a fourth configuration example of the internal electrode 33G on the right side of FIG. 1 , and is an enlarged sectional view of the vicinity of the internal electrode 33G.

[0574] The capacitor 51P has a plurality of cylindrical capacitor protrusions 941 having different diameters and depths, and Fig.89 The internal electrode 33G of the fourth configuration example shown in has a structure electrically connected at multiple depth positions to a plurality of cylindrical capacitor protrusions 941 having different diameters and depths.

[0575] Specifically, the capacitor 51P includes a first cylindrical capacitor protrusion 941A having a first diameter and a depth, and a second cylindrical capacitor protrusion 941B having a second diameter and a depth different from the first diameter and the depth. The diameter of the first cylindrical capacitor protrusion 941A is greater than the diameter of the second cylindrical capacitor protrusion 941B, and the depth of the first cylindrical capacitor protrusion 941A is shallower than the depth of the second cylindrical capacitor protrusion 941B. The first cylindrical capacitor protrusion 941A is embedded in the upper surface of the grid pattern wiring D4 through the opening of the grid pattern wiring D1 to D3. The first heavy wiring 42D of the first cylindrical capacitor protrusion 941A is connected to the upper surface of the grid pattern wiring D1, the side surface of the opening of the grid pattern wiring D1 to D3, and the upper surface of the grid pattern wiring D4. The second cylindrical capacitor protrusion 941B is embedded in the upper surface of the metal wiring layer 911 through the opening of the grid pattern wiring D1 to D5. The first redistribution wiring 42D of the second cylindrical capacitor protrusion 941B is connected to the upper surface of the grid pattern wiring D1 , the side surfaces of the openings of the grid pattern wirings D1 to D5 , and the upper surface of the metal wiring layer 911 .

[0576] Fig.90 The diagram shows the situation when viewed from a plane passing through the grid pattern wiring D1. Fig.89 A plan view of the internal electrode 33G.

[0577] The first cylindrical capacitor protrusion 941A is formed in a rectangular planar shape, and the second cylindrical capacitor protrusion 941B is formed in a circular planar shape. For example, the first cylindrical capacitor protrusion 941A and the second cylindrical capacitor protrusion 941B may be arranged alternately, such as Fig.90 However, the first cylindrical capacitor protrusions 941A and the second cylindrical capacitor protrusions 941B do not necessarily need to be arranged alternately and may be arranged randomly, and the ratio of the number of the first cylindrical capacitor protrusions 941A and the number of the second cylindrical capacitor protrusions 941B is also arbitrary.

[0578] As described above, the capacitor 51P has a plurality of cylindrical capacitor protrusions 941 (941A and 941B) having different diameters, depths, and planar shapes, and the internal electrode 33G of the fourth configuration example may have a multilayer wiring structure electrically connected at a predetermined depth position to the plurality of cylindrical capacitor protrusions 941. The internal electrode 33G according to the first to fourth configuration examples can increase the connection area of ​​the capacitor 51P and the first redistribution wiring 42D to achieve low resistance.

[0579] <35. Cross-sectional view of the lead-out electrode connection of a cylindrical MIM capacitor>

[0580] Fig.91 It is a cross-sectional view of a cylindrical MIM capacitor.

[0581] exist Fig.91 In the above Fig.87 The corresponding parts in the figure are denoted by the same reference numerals, and their description will be appropriately omitted.

[0582] Fig.91 1 is a cross-sectional view of a cylindrical MIM capacitor, in which a planar capacitor formed on a silicon substrate 31 is omitted in a capacitor 51P constituted by a combination of a planar capacitor and a cylindrical capacitor. A first redistribution 42D is connected to a first electrode (OUT electrode) 961A on the silicon substrate 31, and a second redistribution 44D is connected to a second electrode (IN electrode) 961B on the silicon substrate 31.

[0583] Fig.92 yes Fig.91 Simplified conceptual diagram of a cylindrical MIM capacitor.

[0584] like Fig.92 As shown, Fig.91The cylindrical MIM capacitor in has an MIM structure of a first redistribution 42D, a high dielectric film (insulating film) 901, and a second redistribution 44D. A first electrode (OUT electrode) 961A is an extraction electrode of the first redistribution 42D formed outside the through hole 45G with the high dielectric film 901 interposed therebetween, and a second electrode (IN electrode) 961B is an extraction electrode of the second redistribution 44D formed inside the through hole 45G with the high dielectric film 901 interposed therebetween.

[0585] and Fig.87 similar, Fig.91 The cylindrical MIM capacitor has a structure in which the cylindrical capacitor protrusion 941 is embedded until reaching the upper surface of the metal wiring layer 911 through all the openings of the grid pattern wirings D1 to D5. The first electrode 961A is connected to the first redistribution wiring 42D via the seed metal 962A on the upper surface of the silicon substrate 31, and the second electrode 961B is connected to the second redistribution wiring 44D via the seed metal 962B on the upper surface of the silicon substrate 31. The area other than the connection point between the first electrode 961A and the first redistribution wiring 42D and the connection point between the second electrode 961B and the second redistribution wiring 44D is covered with a protective film 963 of, for example, a solder resist (which is an organic material).

[0586] <36. Method for manufacturing cylindrical MIM capacitor>

[0587] Next, refer to Figure 93 to Figure 99 , described in Fig.91 The manufacturing method of the cylindrical MIM capacitor shown in FIG.

[0588] First, if Fig.93 As shown, a through hole 45G is formed from the rear surface side opposite to the front surface side of the silicon substrate 31 on which the internal electrode 33G of the multilayer wiring structure is formed. The interlayer insulating film 34 in the opening portion of the grid pattern wiring D1 to D5 of the internal electrode 33G of the multilayer wiring structure is also etched as a part of the through hole 45G until the metal wiring layer 911 is exposed. In addition, grooves 1001A and 1001B dug to a predetermined depth are formed outside the through hole 45G. The groove 1001A is a region that becomes a connection point between the first electrode 961A and the first heavy wiring 42D, and the groove 1001B is a region that becomes a connection point between the second electrode 961B and the second heavy wiring 44D.

[0589] Then, if Fig.94As shown, in the formed through hole 45G and trench 1001 (1001A and 1001B), the first interlayer insulating film 41, the first redistribution wiring 42D and the high dielectric film 901 are sequentially formed. For example, the first interlayer insulating film 41 is formed by forming a film on the entire surface including the through hole 45G and the trench 1001 using CVD or the like, and then etching to leave the side surface and upper surface of the STI 921 and the side surface and upper surface of the silicon substrate 31. Similarly, the first redistribution wiring 42D and the high dielectric film 901 are patterned on the side surface and bottom of the through hole 45G (including the inside of the internal electrode 33G). As shown in FIG. Fig.94 As shown, the first redistribution wiring 42D and the high dielectric film 901 are formed up to the inside of the trench 1001A on the first electrode 961A side, but are not formed in the trench 1001B on the second electrode 961B side. On the second electrode 961B side, the first redistribution wiring 42D and the high dielectric film 901 extend to the side surface of the through hole 45G and are insulated by the first interlayer insulating film 41. The region where the first redistribution wiring 42D and the high dielectric film 901 are not formed partially remains in the trench 1001A on the first electrode 961A side.

[0590] Next, if Fig.95 As shown, a seed metal 801A' and a Cu wiring 803A are formed on the high dielectric film 901. The seed metal 801A' is formed by, for example, sputtering, and the Cu wiring 803A can be formed by, for example, electrolytic plating until the silicon substrate 31 has a predetermined film thickness. The seed metal 801A' and the Cu wiring 803A are also embedded in the openings of the lattice pattern wirings D1 to D5 in the internal electrode 33G, thereby forming a cylindrical capacitor protrusion 941.

[0591] Then, if Fig.96 As shown, the entire rear surface side of the silicon substrate 31 is removed and planarized by CMP to the extent that the high dielectric film 901 formed in the groove 1001A on the first electrode 961A side is removed. Therefore, the first redistribution wiring 42D is exposed in the groove 1001A on the first electrode 961A side, and the seed metal 801A' of the second redistribution wiring 44D is exposed in the groove 1001B on the second electrode 961B side.

[0592] Then, if Fig.97 As shown, after forming a protective film 963 on the entire rear surface side of the silicon substrate 31 using a photosensitive solder resist or the like, a region 1002A which is a connection point between the first electrode 961A and the first redistribution wiring 42D and a region 1002B which is a connection point between the second electrode 961B and the second redistribution wiring 44D are opened. Then, for example, a seed metal 962 is formed on the upper surface of the opening regions 1002A and 1002B and the protective film 963 by sputtering.

[0593] Then, if Fig.98 Specifically, after the photoresist 1003 is patterned by photolithography so as to open regions where the first electrode 961A and the second electrode 961B are to be formed, Cu is stacked on the open regions by, for example, electrolytic plating, thereby forming the first electrode 961A and the second electrode 961B.

[0594] Finally, if Fig.99 As shown, the photoresist 1003 and the seed metal 962 formed in the region other than the region of the first electrode 961A and the second electrode 961B are removed by wet etching or the like, thereby completing Fig.91 The cylindrical MIM capacitor shown.

[0595] Fig.91 The cylindrical MIM capacitor shown can be manufactured as described above.

[0596] <37. Cross-sectional view of the lead-out electrode connection of a cylindrical MIM double-layer capacitor>

[0597] Fig.100 is a cross-sectional view of a cylindrical MIM double-layer capacitor in which the cylindrical MIM is multilayered into two layers.

[0598] exist Fig.100 In, corresponding to Fig.91 Parts of those of the cylindrical type MIM capacitor shown in FIG. 1 are denoted by the same reference numerals, and descriptions thereof will be appropriately omitted.

[0599] like Fig.101 As shown in the simplified conceptual diagram, Fig.100 The cylindrical MIM double-layer capacitor has a two-layer MIM structure in which a first redistribution 1011, a high dielectric film 1021 as a first insulating film, a second redistribution 1012, a high dielectric film 1022 as a second insulating film, and a third redistribution 1013 are stacked in this order. The first redistribution 1011 and the third redistribution 1013 are connected to the first electrode (OUT electrode) 961A, and the second redistribution 1012 is connected to the second electrode (IN electrode) 961B.

[0600] As described above, in the cylindrical MIM capacitor, the MIM structure may be multilayered by connecting odd-numbered redistributions (first redistribution 1011 and third redistribution 1013) to the first electrode 961A and even-numbered redistributions (second redistribution 1012) to the second electrode 961B. The MIM structure may have three or more layers.

[0601] return Fig.100The cylindrical MIM double layer capacitor has a structure in which the cylindrical capacitor protrusion 941 is embedded until it reaches the upper surface of the metal wiring layer 911 through all the openings of the grid pattern wirings D1 to D5, and Fig.87 The first electrode 961A is connected to the first redistribution 1011 and the embedded Cu 1014 via the seed metal 962A on the upper surface of the silicon substrate 31, and the embedded Cu 1014 is connected to the third redistribution 1013. The second electrode 961B is connected to the second redistribution 1012 via the seed metal 962B on the upper surface of the silicon substrate 31. For example, a solder resist (which is an organic material) is used to cover the area other than the connection point between the first electrode 961A and the first redistribution 1011 and the embedded Cu 1014 and the connection point between the second electrode 961B and the second redistribution 1012 with a protective film 963.

[0602] <38. Method for manufacturing cylindrical MIM double-layer capacitor>

[0603] Next, refer to Figures 102 to 107 , described in Fig.100 A method for manufacturing a cylindrical MIM double-layer capacitor is shown in FIG.

[0604] First, if Fig.102 As shown, the steps until the through hole 45G and the trench 1041 (1041A and 1041B) are formed in the silicon substrate 31, and the first interlayer insulating film 41, the first redistribution wiring 1011 and the high dielectric film 1021 are sequentially formed in the formed through hole 45G and the trench 1041 are similar to those of reference 1. Fig.93 and 94 Description Fig.91 Those steps of cylindrical MIM capacitors.

[0605] Then, if Fig.103 As shown, the second redistribution 1012, the high dielectric film 1022, and the third redistribution 1013 are sequentially formed on the upper layer of the high dielectric film 1021, and the embedded Cu 1014 is stacked on the silicon substrate 31 until a prescribed film thickness is obtained. The third redistribution 1013 can be used as a seed metal for electroplating. The first redistribution 1011, the high dielectric film 1021, the second redistribution 1012, the high dielectric film 1022, the third redistribution 1013, and the embedded Cu 1014 are also embedded in the openings of the lattice pattern wirings D1 to D5 in the internal electrode 33G, thereby forming a cylindrical capacitor protrusion 941.

[0606] Then, if Fig.104As shown, the entire rear surface side of the silicon substrate 31 is removed and planarized by CMP to the extent that the high dielectric film 1021 formed in the groove 1041A on the first electrode 961A side is removed. As a result, the first redistribution wiring 1011 is exposed in the groove 1041A on the first electrode 961A side, and the second redistribution wiring 1012 is exposed in the groove 1041B on the second electrode 961B side.

[0607] Then, if Fig.105 As shown, after forming a protective film 963 on the entire rear surface side of the silicon substrate 31 using a photosensitive solder resist or the like, a region 1042A serving as a connection point between the first electrode 961A and the first redistribution wiring 1011, a region 1042C serving as a connection point between the first electrode 961A and the embedded Cu 1014, and a region 1042B serving as a connection point between the second electrode 961B and the second redistribution wiring 1012 are opened. Then, a seed metal 962 is formed on the upper surfaces of the opening regions 1042A, 1042B, and 1042C and the protective film 963 by, for example, sputtering.

[0608] Then, if Fig.106 Specifically, after the photoresist 1043 is patterned by photolithography to open regions where the first electrode 961A and the second electrode 961B are to be formed, Cu is stacked on the open regions by, for example, electrolytic plating, thereby forming the first electrode 961A and the second electrode 961B.

[0609] Finally, if Fig.107 As shown, the photoresist 1043 and the seed metal 962 formed in the region other than the region of the first electrode 961A and the second electrode 961B are removed by wet etching or the like, thereby completing Fig.100 The cylindrical MIM double-layer capacitor shown.

[0610] Fig.100 The cylindrical MIM double-layer capacitor shown in can be manufactured as described above.

[0611] <Solid-state imaging device for single-board front surface illumination>

[0612] In the above example, an example has been described in which the cylindrical MIM capacitor is applied to the rear surface irradiation type solid-state imaging device 1 configured by stacking the sensor substrate 11 and the logic substrate 12, but the cylindrical MIM capacitor can also be applied to the solid-state imaging device 1 using one silicon substrate (single-plate semiconductor substrate) 31. In addition, the present invention can also be applied to the front surface irradiation type solid-state imaging device 1 that photoelectrically converts light incident from the front surface side of the silicon substrate 31 on which the multilayer wiring layer 32 is formed.

[0613] Fig.108: is a cross-sectional view showing an example in which a cylindrical MIM capacitor is applied to a single-plate front surface irradiation type solid-state imaging device 1 .

[0614] Fig.108 The solid-state imaging device 1 in FIG. 1 is a single-board front surface illumination type solid-state imaging device including a multilayer wiring layer 32 , a color filter 401 , an on-chip lens 28 , and the like on the front surface side of one silicon substrate 31 .

[0615] The cylindrical MIM capacitor 1081 has a MIM structure including a first rewiring line 1061, a high dielectric film 1062, a second rewiring line 1063, and an embedded Cu 1064. The cylindrical MIM capacitor 1081 has a cylindrical capacitor protrusion 1082 embedded in the metal wiring layer 1091 of the internal electrode 33 through the opening of the STI 921. The cylindrical capacitor protrusion 1082 can be formed by forming the pattern shape of the STI 921 into a grid pattern shape similar to the above-mentioned grid pattern wiring Dx.

[0616] <39. Fourteenth Configuration Example of Capacitor>

[0617] Fig.109 is a cross-sectional view of a solid-state imaging device 1 according to a fourteenth embodiment.

[0618] Fig.109 The solid-state imaging device 1 shown in FIG. 1 is a chip size package type CMOS solid-state imaging device configured by stacking a sensor substrate 11 and a logic substrate 12. The sensor substrate 11 and the logic substrate 12 are bonded by a surface indicated by a single dot chain line. However, Fig.109 The sensor substrate 11 is provided on the lower side and the logic substrate 12 is provided on the upper side, and the vertical direction of the solid-state imaging device 1 is Figure 1 The vertical direction in the opposite direction. Pillars (connection pads) 1143 (1143H and 1143J) (which are external connection terminals other than solder bumps 47) are formed on Fig.109 On the rear surface side of the solid-state imaging device 1 on the upper side.

[0619] Because the configuration of the sensor substrate 11 is Figure 1 The interlayer insulating film 25, the bonding resin 26, and the light-transmitting substrate 27 of the sensor substrate 11 may be omitted.

[0620] The logic substrate 12 includes a semiconductor substrate 1110 using, for example, silicon (Si) as a semiconductor. The semiconductor substrate 1110 may be a substrate using a compound semiconductor such as InGaP, InAlP, InGaAs, or InAlAs, but in the present embodiment, the semiconductor substrate is described as a silicon substrate 1110 according to the above-mentioned other configuration examples. In the figure, a multilayer wiring layer 32 is formed on the first surface side (sensor substrate 11 side) of the silicon substrate 1110 as the lower side. On the second surface side of the silicon substrate 1110 opposite to the first surface side on which the multilayer wiring layer 32 is formed, a first interlayer insulating film 41, a second interlayer insulating film 1111, a first redistribution ring 42 (42H and 42J), a third interlayer insulating film 1112, and a protective film 1113 are formed from the side closer to the silicon substrate 1110. The first redistribution 42 and the third interlayer insulating film 1112 are formed in the same layer, and the third interlayer insulating film 1112 is formed in a region where the first redistribution 42 is not formed. The pillars 1143 (1143H and 1143J) are connected to the first rewiring 42, and the rear surface of the solid-state imaging device 1 in the area where the pillars 1143 are not formed is covered with a protective film 1113. The first surface side of the silicon substrate 1110 formed with the multilayer wiring layer 32 is equivalent to the front side of the silicon substrate 1110, and the second surface side formed with two interlayer insulating films and rewiring is equivalent to the rear surface side of the silicon substrate 1110. As the material of the second interlayer insulating film 1111 and the third interlayer insulating film 1112, a material similar to the above-mentioned second interlayer insulating film 43 can be used, such as SiO2 film, low-k film, SiOC film, SiN film, SiON film, etc. As the material of the protective film 1113, a material similar to the above-mentioned protective film 48 can be used, for example, a solder resist as an organic material.

[0621] Two internal electrodes 33H and 33J are formed in a predetermined region of the multilayer wiring layer 32 of the silicon substrate 1110. On the silicon substrate 1110, through holes 45H and 45J are formed at positions corresponding to the internal electrodes 33H and 33J, respectively.

[0622] The first interlayer insulating film 41 is formed on the side surface (inner peripheral surface) of the through hole 45H, which is formed at a position corresponding to the internal electrode 33H and the rear surface side of the silicon substrate 1110. The first interlayer insulating film 41 electrically insulates the first redistribution wiring 42H from the silicon substrate 1110. The first redistribution wiring 42H is formed on the rear surface side of the silicon substrate 1110 and the side surface (inner peripheral surface) of the through hole 45H, and is connected to the internal electrode 33H formed in the multilayer wiring layer 32 on the front surface side. In addition, the pillar 1143H is formed on a part of the upper surface of the first redistribution wiring 42H. The first redistribution wiring 42H includes, for example, a seed metal 1131H containing a barrier metal and a Cu seed film and a Cu wiring 1132H. As a material of the barrier metal film, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), their nitride films, their carbide films, etc. can be used.

[0623] The first interlayer insulating film 41 is formed on the side surface (inner peripheral surface) of the through hole 45J, which is formed at a position corresponding to the internal electrode 33J and the rear surface side of the silicon substrate 1110. The first interlayer insulating film 41 electrically insulates the first rewiring 42J from the silicon substrate 1110. The first rewiring 42J is formed on the rear surface side of the silicon substrate 1110 and the side surface (inner peripheral surface) of the through hole 45J, and is connected to the internal electrode 33J formed in the multilayer wiring layer 32 on the front surface side. In addition, the pillar 1143J is formed on a part of the upper surface of the first rewiring 42J. The first rewiring 42J includes, for example, a seed metal 1131J containing a barrier metal and a Cu seed film, and a Cu wiring 1132J. The material of the barrier metal is similar to that described above.

[0624] Capacitor 51Q is formed between pillars 1143H and 1143J. Different potentials are provided to pillars 1143H and 1143J. Thus, capacitor 51Q can have an electrostatic capacitance. Fig.110 The detailed structure of capacitor 51Q is described.

[0625] Fig.110 1 is an enlarged diagram showing a detailed structure of a capacitor 51Q according to a fourteenth configuration example, which is the capacitor 51 of the solid-state imaging device 1 of the fourteenth embodiment. Fig.110 A shows the plan view, and Fig.110 B shows a cross-sectional view.

[0626] The capacitor 51Q is formed in the groove 1231 on the rear surface side of the silicon substrate 1110, and the first redistribution wiring 42H and 42J are formed in the groove 1231. The side surface of the groove 1231 is inclined so that the upper portion equal to the interface of the silicon substrate 1110 has a large plane area and the hollowed-out bottom has a small plane area. The inclination angle α of the groove 1231 is, for example, 45 degrees to 70 degrees relative to the surface parallel to the silicon substrate 1110.

[0627] In the trench 1231, the first insulating film 1211A, the second insulating film 1211B, the first electrode film 1221A, the dielectric film 1222A, the second electrode film 1221B, the dielectric film 1222B, the third electrode film 1221C, and the third insulating film 1211C are stacked in order from the bottom to the top. Specifically, the first insulating film 1211A is formed at the bottom of the trench 1231, the second insulating film 1211B is formed on the first insulating film 1211A, and the third insulating film 1211C is formed at the uppermost part of the trench 1231. Then, between the second insulating film 1211B and the third insulating film 1211C, the first electrode film 1221A, the dielectric film 1222A, the second electrode film 1221B, the dielectric film 1222B, and the third electrode film 1221C are stacked in order from the bottom of the trench 1231 to the top. Each of the first electrode film 1221A, the dielectric film 1222A, the second electrode film 1221B, the dielectric film 1222B, and the third electrode film 1221C has an inclination of an angle α similar to the inclination of the trench 1231 , and refracts toward the interface of the silicon substrate 1110 along the side surface of the trench 1231 .

[0628] The first electrode film 1221A and the third electrode film 1221C are connected to the seed metal 1131H of the first rewiring 42H on the left side in the figure. The first electrode film 1221A is connected to (the seed metal 1131H of) the first rewiring 42H through a linear electrode connection surface 1223A. The third electrode film 1221C is connected to (the seed metal 1131H of) the first rewiring 42H through a linear electrode connection surface 1223C. The second electrode film 1221B is connected to the seed metal 1131J of the first rewiring 42J on the right side in the figure. The second electrode film 1221B is connected to (the seed metal 1131J of) the first rewiring 42J through a linear electrode connection surface 1223B. As shown in the plan view, the three linear electrode connection surfaces 1223A, 1223B, and 1223C are arranged side by side in parallel, in other words, arranged side by side in the same axial direction (for example, in the Y-axis direction).

[0629] The dielectric film 1222A between the first electrode film 1221A and the second electrode film 1221B and the dielectric film 1222B between the second electrode film 1221B and the third electrode film 1221C are connected under the first redistribution 42H using the same material. A first potential (e.g., a power supply voltage) is provided to the first electrode film 1221A and the third electrode film 1221C via the first redistribution 42H, and a second potential (e.g., a ground) different from the first potential (e.g., a power supply voltage) is provided to the second electrode film 1221B via the first redistribution 42J. That is, the capacitor 51Q has a capacitor structure of two parallel-connected flat plate capacitors.

[0630] As materials for the first insulating film 1211A and the second insulating film 1211B, for example, SiO2 film, low-k film, SiOC film, SiN film, SiON film, etc. can be used. However, different materials are used for the materials of the first insulating film 1211A and the second insulating film 1211B so that a selectivity ratio can be obtained. The first insulating film 1211A can be connected to the second interlayer insulating film 1111 ( Fig.109 ) together formed.

[0631] The material of the first electrode film 1221A, the second electrode film 1221B and the third electrode film 1221C only needs to be any metal material that can be processed by dry etching or wet etching, and for example, titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), gold (Au), etc. can be used.

[0632] The dielectric films 1222A and 1222B may be, of course, silicon oxide films (SiO2 films), and may be, for example, tantalum oxide films, aluminum oxide films, hafnium oxide films, titanium oxide films, zirconium oxide films, niobium oxide films, silicon nitride films, etc., or may be films in which two or more thereof are stacked. The dielectric films 1222A and 1222B may be the same material or different materials.

[0633] As described above, the capacitor 51Q according to the fourteenth configuration example is configured such that the inclined groove 1231 is provided between two adjacent rewirings 42 (42H and 42J), and a plurality of electrode films 1221 (1221A, 1221B, and 1221C) and dielectric films 1222 (1222A and 1222B) are stacked and embedded in the groove. Therefore, electrostatic capacitance can be provided, and higher-speed transmission can be performed.

[0634] For example, in Fig.19In the case of the capacitor 51E shown, the formation positions of the planar capacitor and the cylindrical capacitor are limited to the position of the through hole 45A and the position of the first redistribution wiring 42A on the silicon substrate 31. In the case of the capacitor 51Q according to the fourteenth configuration example, the capacitor can be formed at a desired position without being limited by the existing wiring pattern or the underlying semiconductor (semiconductor substrate 1110).

[0635] <40. Method for Manufacturing Capacitor According to Fourteenth Configuration Example>

[0636] Next, refer to Figures 111 to 116 , described according to Fig.110 A manufacturing method of the capacitor 51Q of the fourteenth configuration example shown in FIG.

[0637] First, if Fig.111 As shown in FIG. 1A , the photoresist 1241 is patterned to open the region 1240 of the silicon substrate 1110 where the capacitor 51Q is formed, and then, as shown in FIG. Fig.111 As shown in FIG. 1B , the silicon substrate 1110 is dry-etched or wet-etched to form a groove 1231 inclined at a predetermined angle α in the silicon substrate 1110. After the groove 1231 is formed, the photoresist 1241 is removed by wet etching or ashing.

[0638] Next, if Fig.111 As shown in C, a first insulating film 1211A, a second insulating film 1211B, and a first electrode film 1221A are sequentially formed on the upper surface of the trench 1231. Each of the first insulating film 1211A, the second insulating film 1211B, and the first electrode film 1221A can be formed using, for example, CVD, physical vapor deposition (PVD), etc. The first insulating film 1211A and the second insulating film 1211B have different materials so as to have a selection ratio. For example, the first insulating film 1211A can be formed of a SiN film, and the second insulating film 1211B can be formed of a SiO2 film.

[0639] Next, if Fig.112 As shown in A, in a state where a region required as the first electrode film 1221A is masked with a photoresist 1242, unnecessary first electrode film 1221A is removed by dry etching or wet etching. After etching, the photoresist 1242 is removed by wet etching or ashing and is allowed to enter the Fig.112 The state shown in B.

[0640] Next, if Fig.112 As shown in FIG. C, a dielectric film 1222A and a second electrode film 1221B are formed in this order on the patterned first electrode film 1221A. Each of the dielectric film 1222A and the second electrode film 1221B can be formed by using, for example, CVD, PVD, or the like.

[0641] Then, if Fig.113 As shown in A, similar to the first electrode film 1221A, in a state where a necessary area is masked with the photoresist 1243, the unnecessary second electrode film 1221B is removed by dry etching or wet etching. After etching, the photoresist 1243 is removed by wet etching or ashing and the photoresist 1243 is allowed to enter the Fig.113 The state shown in B.

[0642] In addition, if Fig.113 As shown in FIG. 1C, the dielectric film 1222B and the third electrode film 1221C are formed in this order, and an unnecessary region of the third electrode film 1221C is removed by dry etching or wet etching. Each of the dielectric film 1222B and the third electrode film 1221C can be formed by using, for example, CVD, PVD, or the like.

[0643] Next, if Fig.114 As shown in FIG. 1A, the third insulating film 1211C is formed by using CVD, PVD, etc. to fill the groove of the third electrode film 1221C on the uppermost layer, and then, as shown in FIG. Fig.114 As shown in FIG. 1B, planarization is performed by CMP to a level at which the upper surface of the first insulating film 1211A is exposed. The selectivity between the first insulating film 1211A and the second insulating film 1211B is ensured, and the planarization process ends at a level at which the first insulating film 1211A serves as a CMP stop film and the upper surface of the first insulating film 1211A is exposed. Fig.110 As shown in the plan view of FIG. 12A , the first electrode film 1221A, the second electrode film 1221B, and the third electrode film 1221C are exposed to be linearly arranged on the same plane as the upper surface of the first insulating film 1211A.

[0644] Then, if Fig.114 As shown in FIG. 3C , a seed metal 1131 including a barrier metal and a Cu seed film is formed by, for example, PVD, and then, a photoresist 1244 is patterned in a region other than a region of the first redistribution wiring 42H or the first redistribution wiring 42J.

[0645] Then, if Fig.115 As shown in A, Cu wirings 1132H and 1132J are formed on the seed metal 1131 not covered by the photoresist 1244, for example, by electrolytic plating.

[0646] Finally, if Fig.115As shown in FIG. 1B , the photoresist 1244 is removed by wet etching or ashing, and the seed metal 1131 under the photoresist 1244 is removed by wet etching. By removing the seed metal 1131 under the photoresist 1244, the left and right remaining seed metals 1131 become the seed metals 1131H and 1131J of the first heavy wiring 42H and 42J, respectively.

[0647] Through the above steps, a Fig.110 The capacitor 51Q of the fourteenth configuration example shown in . After the logic substrate 12 on which the capacitor 51Q is formed is completed, the logic substrate 12 is bonded to the sensor substrate 11 at an appropriate time, and the solid-state imaging device 1 is completed.

[0648] According to the structure of the capacitor 51Q, there is no need to form a contact wiring step of the capacitor element, and the film formed on the silicon substrate 1110 is flattened by CMP, and the connection portion (electrode connection surface 1223) with the redistribution wiring 42 can be formed at one time. Therefore, the capacitor 51 can be formed by a simple process.

[0649] <41. Modification of the Fourteenth Configuration Example>

[0650] A modification example of the capacitor 51Q according to the fourteenth configuration example will be described. Note that in the following modification example, Fig.110 Components corresponding to those of the capacitor 51Q shown in FIG. 5 are denoted by the same reference numerals, and descriptions of these components are omitted as appropriate. Fig.110 The configuration of the capacitor 51Q shown in is referred to as a basic configuration example of the capacitor 51Q.

[0651] Fig.116 A is a cross-sectional view of a capacitor 51Qa which is a first modification example of the capacitor 51Q.

[0652] In the capacitor 51Qa according to the first modification, Fig.110 Compared with the basic configuration of the capacitor 51Q shown in FIG. 1 , the third electrode film 1221C connected to the seed metal 1131H of the first redistribution wiring 42H on the left side is omitted. That is, the capacitor 51Qa according to the first modification example includes two electrode films 1221, namely, the first electrode film 1221A connected to the first redistribution wiring 42H on the left side and the second electrode film 1221B connected to the first redistribution wiring 42J on the right side, and dielectric films 1222A and 1222B. Fig.110 The basic configuration of the capacitor 51Q shown in has a capacitor structure in which two parallel plate capacitors are connected in parallel, but the capacitor 51Qa according to the first modification example has a structure of one parallel plate capacitor.

[0653] Fig.116B is a cross-sectional view of a capacitor 51Qb which is a second modification example of the capacitor 51Q.

[0654] In the capacitor 51Qb according to the second modification, Fig.110 Compared with the basic configuration of the capacitor 51Q shown in FIG. 1 , the third electrode film 1221C connected to the seed metal 1131H of the first rewiring 42H on the left side is omitted. Fig.116 The difference of A in the capacitor 51Qa according to the first modification is the distance (thickness) between the first electrode film 1221A and the second electrode film 1221B. Fig.116 In the capacitor 51Qa according to the first modification example of A, the distance between the first electrode film 1221A and the second electrode film 1221B is short, and the dielectric film 1222A is also formed below the first electrode film 1221A. On the other hand, in the capacitor 51Qb according to the second modification example, the dielectric film 1222 is not formed below the first electrode film 1221A, and the distance between the first electrode film 1221A and the second electrode film 1221B is ensured to be greater than that of the capacitor 51Qa according to the first modification example.

[0655] As described above, the electrostatic capacitance of the capacitor 51Q can be arbitrarily designed by changing the distance between the electrode films 1221 of the capacitor 51Q, the number and arrangement of the electrode films 1221, and the like.

[0656] Fig.117 A is a cross-sectional view of a capacitor 51Qc according to a third modification example of the capacitor 51Q.

[0657] and Fig.116 Compared to the configuration of the capacitor 51Qb of the second modification example shown in B, the capacitor 51Qc according to the third modification example has a configuration in which a third electrode film 1221C that is not connected to any of the first rewiring lines 42 is added between the first electrode film 1221A and the second electrode film 1221B. The capacitor 51Qc has a capacitor structure in which two parallel plate capacitors are connected in series. The capacitor 51Q may have a structure in which a plurality of stacked electrode films 1221 are connected in series as described above, or may have a structure in which they are connected in parallel.

[0658] Fig.117 B is a cross-sectional view of a capacitor 51Qd according to a fourth modification example of the capacitor 51Q.

[0659] exist Fig.110In the basic configuration of the capacitor 51Q shown in FIG, the same material is used for the dielectric film 1222A between the first electrode film 1221A and the second electrode film 1221B and the dielectric film 1222B between the second electrode film 1221B and the third electrode film 1221C. On the other hand, in the capacitor 51Qd according to the fourth modification, different materials are used for the dielectric film 1222A and the dielectric film 1222B. By changing the materials of the dielectric film 1222A and the dielectric film 1222B, the electrostatic capacitance of the capacitor 51Q can be arbitrarily designed.

[0660] <Other configuration examples>

[0661] Fig.118 Shows Fig.110 42H and 42J. The two capacitors 51Q shown in FIG. 4 are connected in parallel through the first rewiring 42H and the first rewiring 42J. The two capacitors 51Q are configured to have different plane sizes and different sizes of electrostatic capacitance, but can be formed to have the same size, and two capacitors 51Q with the same electrostatic capacitance can be connected in parallel. In addition, instead of connecting the two capacitors 51Q in parallel, the first rewiring 42H and the first rewiring 42J can be connected in series. A configuration example in which a plurality of, three or more capacitors 51Q are connected in parallel or in series through the first rewiring 42 can be used.

[0662] Fig.119 1 and 2 are a plan view and a cross-sectional view showing another configuration example of the capacitor 51Q. Fig.119 The left side of FIG. 1 shows a plan view of a capacitor 51Q according to another configuration example, and Fig.119 The right side of shows cross-sectional views taken along lines AA' and BB' of the plan view.

[0663] Fig.119The capacitor 51Q is formed by stacking four layers of electrode films 1251H, 1251J, 1251K, 1251L and a dielectric film 1261 in the groove 1231. The groove 1231 is in the shape of a quadrangular pyramid. The four electrode films 1251H, 1251J, 1251K and 1251L are respectively connected to different first rewirings 42. Specifically, the electrode film 1251H is connected to the first rewiring 42H, and the electrode film 1251J is connected to the first rewiring 42J. The electrode film 1251K is connected to the first rewiring 42K, and the electrode film 1251L is connected to the first rewiring 42L. The electrode film 1251H and the first rewiring 42H are connected through the electrode connection surface 1281H on the semiconductor substrate 1110. The electrode film 1251J and the first rewiring 42J are connected through the electrode connection surface 1281J on the semiconductor substrate 1110. The electrode film 1251K and the first redistribution 42K are connected via an electrode connection surface 1281K on the semiconductor substrate 1110. The electrode film 1251L and the first redistribution 42L are connected via an electrode connection surface 1281L on the semiconductor substrate 1110. On the semiconductor substrate 1110, the electrode connection surfaces 1281H, 1281J, 1281K, and 1281L are formed into a substantially quadrilateral shape in plan view. Here, a substantially quadrilateral shape refers to a quadrilateral whose four corners are not connected.

[0664] exist Fig.110 In the basic configuration example of the capacitor 51Q shown and its modified examples described above, the linear electrode connection surfaces 1223A, 1223B and 1223C at the interface of the silicon substrate 1110 are arranged in parallel, in other words, arranged in the same axial direction (for example, in the Y-axis direction).

[0665] On the other hand, Fig.119 In the capacitor 51Q in FIG. 1 , two opposing electrode connection surfaces 1281H and 1281J are arranged to be orthogonal to the other two opposing electrode connection surfaces 1281K and 1281L, and are arranged to form a substantially quadrilateral shape.

[0666] As described above, the capacitor 51Q can be configured such that the number of layers of the electrode film 1251 stacked in the groove 1231 is 4 or more layers, and the planar shape of the electrode connection surface 1281 on the silicon substrate 1110 where the plurality of electrode films 1251 are respectively connected to the first redistribution wiring 42 is a substantially polygonal shape of a quadrilateral or more. The groove 1231 is in the shape of a polygonal truncated pyramid. For example, in the case where the number of layers of the electrode film 1251 stacked in the groove 1231 is 6 layers, the planar shape of the electrode connection surface 1281 where each of the plurality of electrode films 1251 on the silicon substrate 1110 is connected to the first redistribution wiring 42 can be formed into a substantially hexagonal shape. The groove 1231 has a hexagonal truncated pyramid shape. In each of the plurality of electrode films 1251 having a substantially polygonal electrode connection surface 1281, different potentials are applied to the electrode films 1251 adjacent at least in the vertical direction or in the planar direction. A different potential may be applied to each of the plurality of electrode films 1251 having a substantially polygonal electrode connection surface 1281 .

[0667] <42. Combination of Capacitor and Another Capacitor According to Fourteenth Configuration Example>

[0668] Fig.120 It is a cross-sectional view showing a modification of the solid-state imaging device 1 according to the fourteenth embodiment.

[0669] exist Fig.120 in Fig.109 Portions corresponding to those of the solid-state imaging device 1 shown in are denoted by the same reference numerals, and description of the portions will be appropriately omitted, and different portions will be described.

[0670] Fig.120 The solid-state imaging device 1 shown in FIG. Fig.109 The capacitor 51Q shown in FIG. Fig.19 Capacitor 51R is a combination of a planar capacitor and a cylindrical capacitor described in FIG.

[0671] The capacitor 51R having a planar capacitor and a cylindrical capacitor includes a first redistribution wiring 42J, a second redistribution wiring 44J, and a third interlayer insulating film 1112 therebetween. The second redistribution wiring 44J is composed of, for example, a seed metal 1133J including a barrier metal and a Cu seed film, and a Cu wiring 1134J.

[0672] As described above, the capacitor 51Q according to the fourteenth configuration example can be used together with the capacitor 51R including the planar capacitor and the cylindrical capacitor. Thus, the electrostatic capacitance can be further increased, so high-speed transmission can be performed.

[0673] The solid-state imaging device 1 may adopt a configuration in which two or more capacitors 51 in the first to fourteenth configuration examples are arbitrarily combined.

[0674] <43. Example of using image sensor>

[0675] Fig.121 : is a diagram showing a usage example of an image sensor using the above-described solid-state imaging device 1 .

[0676] For example, in the following various cases of sensing light such as visible light, infrared light, ultraviolet light, X-rays, etc., an image sensor using the above-described solid-state imaging device 1 can be used.

[0677] - Devices that capture images to be viewed, such as digital cameras and portable devices with camera functionality

[0678] -Devices for traffic purposes, such as on-board sensors that capture images of the front, rear, surroundings, interior, etc. of a car, monitoring cameras for monitoring moving vehicles and roads, and ranging sensors that measure the distance between vehicles, etc. for safe driving (such as automatic stopping, identification of driver conditions, etc.).

[0679] - Devices for home appliances (such as televisions, refrigerators, and air conditioners) that capture images of user gestures and perform device operations according to the gestures;

[0680] - Devices for medical and health care such as endoscopes and devices for performing angiography by receiving infrared light

[0681] -Devices for security, such as security surveillance cameras and personal authentication cameras

[0682] - Devices for beauty care, such as skin measurement instruments for capturing skin images and microscopes for capturing scalp images

[0683] -Devices for sports, such as action cameras or wearable cameras for sports applications

[0684] -Devices for use in agriculture, such as cameras for monitoring the conditions of fields and crops.

[0685] <44. Application examples of electronic devices>

[0686] The present technology is not limited to application to solid-state imaging devices. That is, the present technology can be applied to all electronic devices using a solid-state imaging device for an image capture unit (photoelectric conversion unit), such as an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function, or a copier using a solid-state imaging device in an image reading unit. The solid-state imaging device may be formed as one chip, or may be in the form of a module having an imaging function in which an image pickup unit and a signal processing section or an optical system are packaged together.

[0687] Fig.122 is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

[0688] Fig.122 The imaging device 600 in the embodiment includes: an optical unit 601 including a lens group, etc.; a solid-state imaging device (imaging device) 602, wherein a Figure 1 ; and a digital signal processor (DSP) circuit 603, which is a camera signal processing circuit. In addition, the imaging device 600 further includes a frame memory 604, a display section 605, a recording unit 606, an operation unit 607, and a power supply unit 608. The DSP circuit 603, the frame memory 604, the display section 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via a bus 609.

[0689] The optical unit 601 captures incident light (image light) from a subject and forms an image on an imaging surface of the solid-state imaging device 602. The solid-state imaging device 602 converts the light amount of the incident light imaged on the imaging surface by the optical unit 601 into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal. As the solid-state imaging device 602, a Figure 1 A solid-state imaging device 1, i.e., a solid-state imaging device in which a capacitor 51 is formed using two redistribution layers of a first redistribution 42 and a second redistribution 44 and the potential is stabilized by connecting the capacitor 51 to an internal electrode 33A connected to a power supply voltage, thereby improving signal delay and jitter.

[0690] The display section 605 includes, for example, a thin display such as a liquid crystal display (LCD) or an organic electroluminescent (EL) display, and displays a moving image or a still image captured by the solid-state imaging device 602. The recording unit 606 records the moving image or the still image captured by the solid-state imaging device 602 on a recording medium such as a hard disk or a semiconductor memory.

[0691] The operation unit 607 issues operation commands regarding various functions of the imaging device 600 under user operation. The power supply unit 608 appropriately supplies various power sources used as operation power sources for the DSP circuit 603, frame memory 604, display section 605, recording unit 606, and operation unit 607 to these supply targets.

[0692] As described above, by using the solid-state imaging device 1 to which the above-described various embodiments are applied as the solid-state imaging device 602, signal delay and jitter can be improved. Therefore, even in the imaging device 600 (e.g., a video camera, a digital still camera, or a camera module for a mobile device (e.g., a mobile phone or other device)), an increased rate of capturing images can be achieved.

[0693] <45. Application examples of endoscopic surgery systems>

[0694] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0695] Fig.123 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0696] Fig.123 The figure shows a state where a surgeon (doctor) 11131 performs surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 on which the endoscope 11100 is supported, and a cart 11200 on which various endoscopic surgery devices are installed.

[0697] The endoscope 11100 includes a lens barrel 11101 and a camera head 11102 connected to the proximal end of the lens barrel 11101, and the lens barrel 11101 has a region of a predetermined length from its distal end to be inserted into a body cavity of a patient 11132. In the illustrated example, the endoscope 11100 is shown as a rigid endoscope having a rigid lens barrel 11101. However, the endoscope 11100 may be additionally included as a flexible endoscope having a flexible lens barrel 11101.

[0698] The lens barrel 11101 has an opening at its distal end, and the objective lens is mounted in the opening. The light source device 11203 is connected to the endoscope 11100, so that the light generated by the light source device 11203 is introduced into the front end of the lens barrel 11101 by the light guide extending inside the lens barrel 11101, and irradiated toward the observation object in the body cavity of the patient 11132 via the objective lens. In addition, the endoscope 11100 can be either a direct-view endoscope, an oblique-view endoscope, or a side-view endoscope.

[0699] The optical system and the image pickup element are arranged inside the camera head 11102, so that the reflected light (observation light) from the observation target is focused on the image pickup element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as RAW data.

[0700] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102 and performs various image processing for displaying an image based on the image signal, such as, for example, development processing (demosaic processing), on the image signal.

[0701] The display device 11202 displays an image thereon based on an image signal on which image processing has been performed under the control of the CCU 11201 .

[0702] The light source device 11203 includes a light source such as a light emitting diode (LED), and provides irradiation light for imaging a surgical area or the like to the endoscope 11100 .

[0703] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user inputs instructions to change the imaging conditions of the endoscope 11100 (type of irradiation light, magnification, focal length, etc.).

[0704] The treatment tool control device 11205 controls the drive of the energy device 11112 for cauterizing or cutting tissues, sealing blood vessels, etc. In order to ensure the field of view of the endoscope 11100 and the operating space of the surgeon, the pneumoperitoneum device 11206 provides gas to the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms (such as text, images, or graphics).

[0705] In addition, the light source device 11203 that provides irradiation light when imaging the surgical area to the endoscope 11100 may also include a white light source, which is composed of, for example, an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing can be controlled with high precision for each color (each wavelength), the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, if the laser beams from each RGB laser light source are irradiated on the observation target in a time-sharing manner and the drive of the image pickup element of the camera 11102 is controlled synchronously with the irradiation timing. Then, images corresponding to the R, G, and B colors, respectively, can also be captured in a time-sharing manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0706] In addition, the light source device 11203 can be controlled so that the intensity of the light to be output is changed every predetermined time. By controlling the drive of the image pickup element of the camera 11102 synchronously with the timing of the light intensity change to acquire images in time division and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be generated.

[0707] In addition, the light source device 11203 can be configured to provide light of a predetermined wavelength band prepared for special light observation. In special light observation, by utilizing the wavelength dependence of the absorption of light by the biological tissue to irradiate light of a narrower band than the irradiation light (i.e., white light) during normal observation, narrow-band light observation (narrow-band light observation) is performed to image a predetermined tissue such as blood vessels in the surface layer of the mucosa with high contrast. Alternatively, in special light observation, fluorescence observation can also be performed to obtain an image from the fluorescence generated by irradiation with excitation light. In fluorescence observation, it is possible to observe fluorescence from biological tissue by irradiating excitation light to the biological tissue (autofluorescence observation), or to obtain a fluorescence image by locally injecting a reagent such as indocyanine green (ICG) into the biological tissue and irradiating the biological tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for special light observation as described above.

[0708] Fig.124 It is shown Fig.123 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 is shown in FIG.

[0709] The camera 11102 includes a lens unit 11401, an image pickup unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 for communication with each other.

[0710] The lens unit 11401 is an optical system, and is provided at a connection position with the lens barrel 11101. Observation light acquired from the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0711] The image pickup unit 11402 includes an image pickup element. The number of image pickup elements included in the image pickup unit 11402 may be one (single-board type) or multiple (multi-board type). In the case where the image pickup unit 11402 is configured as a multi-board type image pickup unit, for example, image signals corresponding to each R, G, and B are generated by the image pickup element, and the image signals may be synthesized to obtain a color image. Alternatively, the image pickup unit 11402 may include a pair of image pickup elements for acquiring a right-eye image signal and a left-eye image signal corresponding to a three-dimensional (3D) display. In the case of a 3D display, the surgical operator 11131 can more accurately grasp the depth of the biological tissue in the surgical area. It should be noted that in the case where the image pickup unit 11402 is configured as a stereoscopic type image pickup unit, a plurality of system lens units 11401 are provided corresponding to a single image pickup element.

[0712] In addition, the image pickup unit 11402 is not necessarily provided on the camera head 11102. For example, the image pickup unit 11402 may be provided inside the lens barrel 11101 just behind the objective lens.

[0713] The driving unit 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. As a result, the magnification and focus of the image picked up by the image pickup unit 11402 can be appropriately adjusted.

[0714] The communication unit 11404 includes a communication device for sending and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the image pickup unit 11402 to the CCU 11201 through the transmission cable 11400 as RAW data.

[0715] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes information related to image pickup conditions, such as information specifying a frame rate of a picked-up image, information specifying an exposure value at the time of image pickup, and / or information specifying a magnification and a focus of a picked-up image.

[0716] It should be noted that image pickup conditions such as frame rate, exposure value, magnification, or focus may be specified by a user or may be automatically set based on an acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are incorporated in the endoscope 11100.

[0717] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal from the CCU 11201 received through the communication unit 11404 .

[0718] The communication unit 11411 includes a communication device for sending and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera 11102 through the transmission cable 11400.

[0719] In addition, the communication unit 11411 sends a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, etc.

[0720] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data sent thereto from the camera 11102 .

[0721] The control unit 11413 performs various controls related to the imaging of the operation area, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the operation area, etc. For example, the control unit 11413 creates a control signal for controlling the driving of the camera head 11102 .

[0722] In addition, the control unit 11413 controls the display device 11202 to display a picked-up image of the surgical area, etc., based on the image signal on which the image processing unit 11412 has performed image processing. Thus, the control unit 11413 can use various image recognition technologies to recognize various objects in the picked-up image. For example, the control unit 11413 can recognize surgical tools such as forceps, a specific living area, bleeding, fog when using the energy device 11112, etc. by detecting the shape, color, etc. of the edge of the object included in the picked-up image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical support information in a manner overlapping with the image of the surgical area. In the case where the surgical support information is displayed in an overlapping manner and prompted to the surgical operator 11131, the burden of the surgical operator 11131 can be reduced, and the surgical operator 11131 can reliably perform the operation.

[0723] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable prepared for communication of electric signals, an optical fiber prepared for optical communication, or a composite cable prepared for both electric communication and optical communication.

[0724] Here, although in the depicted example, communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0725] An example of an endoscopic surgical system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the lens unit 11401 and the image pickup unit 11402 of the camera 11102 in the above configuration. Specifically, the solid-state imaging device 1 according to each embodiment can be applied as the lens unit 11401 and the image pickup unit 11402. By applying the technology according to the present disclosure to the lens unit 11401 and the image pickup unit 11402, a clearer surgical field image can be obtained while reducing the size of the camera 11102.

[0726] It should be noted that an endoscopic surgical system has been described herein as an example, but the technology according to the present disclosure can be applied to a microsurgery system or the like, for example.

[0727] <46. Application examples of mobile objects>

[0728] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device installed on any kind of mobile body (such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot).

[0729] Fig.125 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0730] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.125 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0731] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0732] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0733] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the image outside the vehicle and receive the imaged image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface based on the received image, or detect the distance thereof.

[0734] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0735] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0736] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0737] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0738] In addition, the microcomputer 12051 can output a control instruction to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for preventing glare by controlling the headlights to change from high beam to low beam based on the position of the front vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0739] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.125 In the example of FIG. 12064 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as examples of output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0740] Fig.126 12031 is a view showing an example of the installation position of the imaging unit 12031.

[0741] exist Fig.126 In the figure, vehicle 12100 includes imaging units 12101, 12102, 12103, 12104 and 12105 as imaging unit 12031.

[0742] The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 disposed at the front nose inside the vehicle and the imaging unit 12105 disposed at the upper portion of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed to the side mirrors mainly obtain images of the side surfaces of the vehicle 12100. The imaging unit 12104 disposed to the rear bumper or rear door mainly obtains images of the rear portion of the vehicle 12100. The front images obtained by the imaging units 12101 and 12105 are mainly used to detect front vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0743] Please note that Fig.126 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 set to the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 set to the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 set to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0744] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0745] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting objects that exist on the driving path of the vehicle 12100 and are traveling in the same direction as the vehicle 12100 at a prescribed speed (e.g., equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can pre-set the following distance to keep ahead of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As a result, coordinated control for automatic driving that allows the vehicle to travel automatically without relying on the driver's operation, etc., can be performed.

[0746] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0747] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaged images of the imaging units 12101 to 12104 as infrared cameras and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the imaged images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0748] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. Specifically, the solid-state imaging device 1 according to each embodiment can be applied as the imaging unit 12031. By applying the technology according to the embodiment of the present disclosure to the imaging unit 12031, a captured image that is easier to view can be obtained while reducing the size. In addition, by using the captured image obtained, the fatigue of the driver can be reduced and the safety of the driver and the vehicle can be increased.

[0749] In addition, the present technology is not limited to being applied to solid-state imaging devices that detect the distribution of the amount of incident visible light and capture the distribution as an image, and can be applied to all solid-state imaging devices (physical quantity distribution detection devices), such as solid-state imaging devices that capture the distribution of the amount of incident infrared rays, X-rays, particles, etc. as images, fingerprint detection sensors that detect the distribution of other physical quantities (such as pressure, capacitance, etc.) and capture the distribution as an image in a broad sense, and the like.

[0750] Furthermore, the present technology can be applied not only to solid-state imaging devices but also to general semiconductor devices having other semiconductor integrated circuits.

[0751] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the present technology.

[0752] For example, a mode obtained by combining all or some of the above-described plural embodiments may be adopted.

[0753] It should be noted that the effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0754] It should be noted that the technology of the present disclosure may have the following configurations. (1)

[0756] A semiconductor device comprising:

[0757] an internal electrode formed on the first surface side of the semiconductor substrate;

[0758] a through hole formed at a position corresponding to an internal electrode of the semiconductor substrate;

[0759] a first redistribution wiring formed on a second surface side opposite to the first surface side of the semiconductor substrate and connected to the internal electrode via a through hole;

[0760] a second redistribution wiring connected to the first redistribution wiring and formed on a side closer to the external connection terminal than the first redistribution wiring; and

[0761] An interlayer insulating film is formed between the first redistribution wiring and the second redistribution wiring, wherein

[0762] Both a first internal electrode and a second internal electrode are provided as internal electrodes, and

[0763] The first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor. (2)

[0765] The semiconductor device according to (1) above, further comprising:

[0766] The photoelectric conversion elements are arranged in a matrix on the first surface side of the semiconductor substrate. (3)

[0768] The semiconductor device according to (1) or (2) above, wherein the first internal electrode is connected to the external connection terminal via the first redistribution wiring and the second redistribution wiring. (4)

[0770] The semiconductor device according to (3) above, wherein

[0771] Supply power voltage or ground to external connection terminals. (5)

[0773] The semiconductor device according to any one of (1) to (4) above, wherein the first redistribution wiring and the second redistribution wiring constituting the capacitor include a planar capacitor formed on the second surface side of the semiconductor substrate. (6)

[0775] The semiconductor device according to any one of (1) to (5) above, wherein:

[0776] The first and second redistributions constituting the capacitors include a cylindrical capacitor formed in a through hole. (7)

[0778] The semiconductor device according to the above (6), wherein the second redistribution wiring is embedded in the through hole in a plug shape. (8)

[0780] The semiconductor device according to (6) above, wherein:

[0781] The side surface of the through hole where the cylindrical capacitor is formed is formed in a concavo-convex shape. (9)

[0783] The semiconductor device according to (6) above, wherein:

[0784] The side surface of the through hole formed with the cylindrical capacitor is formed in any one of a circular arc shape, a triangular shape, and a quadrangular shape in a cross-sectional view. (10)

[0786] The semiconductor device according to (6) above, wherein:

[0787] The amount of the concave portion on the side surface of the through hole is equal to or greater than 0.3 μm with respect to the smooth surface connecting the apex of the convex portion. (11)

[0789] The semiconductor device according to (6) above, wherein:

[0790] Only a portion in the depth direction of the side surface of the through hole where the cylindrical capacitor is formed is formed in a concavo-convex shape. (12)

[0792] The semiconductor device according to (1) above, wherein

[0793] The internal electrode has a multilayer wiring structure in which a plurality of grid-pattern wirings are stacked. (13)

[0795] The semiconductor device according to (12) above, wherein

[0796] The internal electrode has a multilayer wiring structure in which a plurality of grid-pattern wirings are stacked by interlacing. (14)

[0798] The semiconductor device according to (12) above, wherein

[0799] The internal electrode has a multilayer wiring structure in which a plurality of grid-pattern wirings are stacked by interlacing. (15)

[0801] The semiconductor device according to (6) above, wherein:

[0802] The internal electrode has a multilayer wiring structure in which a plurality of grid-pattern wirings are stacked so as to overlap one another in a plan view. (16)

[0804] The semiconductor device according to (6) above, wherein:

[0805] A bottom portion of the first redistribution wiring of the cylindrical capacitor is formed in a concavo-convex shape. (17)

[0807] The semiconductor device according to (6) above, wherein:

[0808] The internal electrode has a multilayer wiring structure in which a plurality of grid-pattern wirings are stacked, and

[0809] The cylindrical capacitor has protrusions embedded in openings of one or more grid-pattern wirings. (18)

[0811] The semiconductor device according to (17) above, wherein

[0812] The cylindrical capacitor includes a plurality of protrusions having different diameters and depths. (19)

[0814] The semiconductor device according to (17) above, wherein

[0815] The protrusion of the cylindrical capacitor is formed in a circular or rectangular planar shape. (20)

[0817] The semiconductor device according to (1) above, further comprising:

[0818] a first electrode connected to a redistribution wiring formed on the second surface side of the semiconductor substrate;

[0819] a second electrode surrounding the periphery of the first electrode in a plan view; and

[0820] an insulating film between the first electrode and the second electrode, wherein

[0821] The first electrode, the second electrode, and the insulating film constitute a capacitor. (twenty one)

[0823] The semiconductor device according to (1) above, further comprising:

[0824] a trench formed in the semiconductor substrate and having a side surface inclined at a predetermined angle;

[0825] At least two electrode films, a first electrode film and a second electrode film, are stacked in the trench; and

[0826] The dielectric film is formed at least between the first electrode film and the second electrode film, wherein

[0827] The first electrode film is connected to the first redistribution wiring on the semiconductor substrate along the side surface of the trench,

[0828] The second electrode film is connected to another first redistribution wiring on the semiconductor substrate along the side surface of the trench, and

[0829] A capacitor is formed by stacking a first electrode film, a dielectric film, and a second electrode film. (twenty two)

[0831] The semiconductor device according to any one of (1) to (7) above, wherein:

[0832] The capacitor is composed of a planar capacitor and a cylindrical capacitor connected in series or in parallel, the planar capacitor is formed by a first redistribution wiring and a second redistribution wiring on the second surface side of the semiconductor substrate, and the cylindrical capacitor is formed by a first redistribution wiring and a second redistribution wiring in a through hole. (twenty three)

[0834] The semiconductor device according to any one of (1) to (8) above, wherein:

[0835] The capacitor includes an interlayer thin film portion in which a film thickness of an interlayer insulating film between a first redistribution wiring and a second redistribution wiring is formed to be thinner than a film thickness of another interlayer insulating film. (twenty four)

[0837] The semiconductor device according to (23) above, wherein

[0838] The film thickness of the interlayer insulating film of the interlayer thin film portion is equal to or less than 500 nm, and

[0839] The film thickness of the other interlayer insulating film is 5 μm to 10 μm. (25)

[0841] The semiconductor device according to any one of (1) to (10) above, wherein:

[0842] An interlayer insulating film between the first redistribution wiring and the second redistribution wiring constituting the capacitor is formed of a high dielectric film. (26)

[0844] The semiconductor device according to (25) above, wherein

[0845] The high dielectric film is formed on the entire surface in a plan view. (27)

[0847] The semiconductor device according to (25) above, wherein

[0848] The high dielectric film is formed only in a region where the first redistribution wiring and the second redistribution wiring constituting the capacitor overlap with each other. (28)

[0850] The semiconductor device according to any one of (1) to (13) above, wherein:

[0851] The semiconductor substrate has a trench dug to a predetermined depth, and

[0852] In the first and second redistribution wirings constituting the capacitor, steps are formed in the trenches of the semiconductor substrate. (29)

[0854] A semiconductor device according to (28) above, wherein:

[0855] The groove is formed at the same depth as the through hole. (30)

[0857] The semiconductor device according to any one of (1) to (15) above, wherein:

[0858] The first rewiring includes a first wiring and a second wiring capacitively coupled in a planar direction, and

[0859] The second rewiring includes a third wiring and a fourth wiring which are capacitively coupled in the planar direction. (31)

[0861] The semiconductor device according to (30) above, wherein

[0862] The first wiring and the second wiring each have a comb-teeth shape in plan view, and the third wiring and the fourth wiring each have a comb-teeth shape in plan view. (32)

[0864] The semiconductor device according to any one of (1) to (17) above, wherein the first redistribution wiring and the second redistribution wiring constituting the capacitor are formed in a region overlapping with the entire region of the pixel region. (33)

[0866] A method for manufacturing a semiconductor device, the method comprising:

[0867] forming an internal electrode, the internal electrode being formed on the first surface side of the semiconductor substrate,

[0868] forming a through hole, the through hole being formed at a position corresponding to the internal electrode of the semiconductor substrate,

[0869] forming a first redistribution wiring which is formed on a second surface side opposite to the first surface side of the semiconductor substrate and is connected to the internal electrode via a through hole,

[0870] forming a second redistribution wiring which is connected to the first redistribution wiring and is formed on a side closer to the external connection terminal than the first redistribution wiring; and

[0871] An interlayer insulating film is formed, wherein the interlayer insulating film is formed between the first redistribution wiring and the second redistribution wiring, wherein

[0872] The first internal electrode and the second internal electrode are both formed as internal electrodes, and

[0873] The first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor. (34)

[0875] An electronic device includes a semiconductor device, wherein the semiconductor device includes:

[0876] an internal electrode formed on the first surface side of the semiconductor substrate;

[0877] a through hole formed at a position corresponding to an internal electrode of the semiconductor substrate;

[0878] a first redistribution wiring formed on a second surface side opposite to the first surface side of the semiconductor substrate and connected to the internal electrode via a through hole;

[0879] a second redistribution wiring connected to the first redistribution wiring and formed on a side closer to the external connection terminal than the first redistribution wiring; and

[0880] An interlayer insulating film is formed between the first redistribution wiring and the second redistribution wiring, wherein

[0881] Both a first internal electrode and a second internal electrode are provided as internal electrodes, and

[0882] The first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor.

[0883] <1A>

[0884] A semiconductor device comprising:

[0885] a first electrode connected to a redistribution wiring formed on the rear surface side of the semiconductor substrate;

[0886] a second electrode surrounding the periphery of the first electrode in a plan view; and

[0887] an insulating film between the first electrode and the second electrode, wherein

[0888] The first electrode, the second electrode, and the insulating film constitute a capacitor.

[0889] <2A>

[0890] The semiconductor device according to <1A> above, wherein

[0891] The insulating film includes a high dielectric film having a relative dielectric constant higher than that of the silicon oxide film.

[0892] <3A>

[0893] The semiconductor device according to <1A> or <2A> above, wherein:

[0894] The first electrode is an external connection terminal, and

[0895] The second electrode is connected to an external connection terminal different from the first electrode.

[0896] <4A>

[0897] The semiconductor device according to any one of <1A> to <3A> above, wherein

[0898] The first electrode is connected to the rewiring;

[0899] An insulating film is also formed between ...

Claims

1. A semiconductor device comprising: an internal electrode formed on the first surface side of the semiconductor substrate; a through hole formed at a position corresponding to the internal electrode of the semiconductor substrate; a first redistribution wiring formed on a second surface side opposite to the first surface side of the semiconductor substrate and connected to the internal electrode via the through hole; a second redistribution wiring connected to the first redistribution wiring and formed on a side closer to the external connection terminal than the first redistribution wiring; as well as An interlayer insulating film is formed between the first redistribution wiring and the second redistribution wiring, wherein Both a first internal electrode and a second internal electrode are provided as the internal electrodes, and The first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor.

2. The semiconductor device according to claim 1, further comprising: The photoelectric conversion elements are arranged in a matrix on the first surface side of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein The first internal electrode is connected to an external connection terminal via the first redistribution wiring and the second redistribution wiring.

4. The semiconductor device according to claim 3, wherein: The external connection terminal is supplied with a power supply voltage or a ground line.

5. The semiconductor device according to claim 1, wherein The first redistribution wiring and the second redistribution wiring constituting the capacitor include a planar capacitor formed on the second surface side of the semiconductor substrate.

6. The semiconductor device according to claim 1, wherein The first and second redistribution wirings constituting the capacitors include cylindrical capacitors formed within the through-holes.

7. The semiconductor device according to claim 6, wherein: The second redistribution wiring is embedded in the through hole in a plug shape.

8. The semiconductor device according to claim 6, wherein: The side surface of the through hole formed with the cylindrical capacitor is formed in a concavo-convex shape.

9. The semiconductor device according to claim 6, wherein: The side surface of the through hole formed with the cylindrical capacitor is formed in any one of a circular arc shape, a triangular shape, and a quadrangular shape in a cross-sectional view.

10. The semiconductor device according to claim 6, wherein The amount of the concave portion on the side surface of the through hole is equal to or greater than 0.3 μm relative to the smooth surface connecting the apex of the convex portion.

11. The semiconductor device according to claim 6, wherein: Only a portion in a depth direction of a side surface of the through hole where the cylindrical capacitor is formed is formed in a concavo-convex shape.

12. The semiconductor device according to claim 1, wherein The internal electrode has a multilayer wiring structure in which a plurality of grid-pattern wirings are stacked.

13. The semiconductor device according to claim 12, wherein: The internal electrode has a multilayer wiring structure in which a plurality of grid pattern wirings are stacked by interlacing.

14. The semiconductor device according to claim 12, wherein: The internal electrode has a multilayer wiring structure in which a plurality of grid pattern wirings are stacked by interlacing.

15. The semiconductor device according to claim 6, wherein: The internal electrode has a multilayer wiring structure in which a plurality of grid-pattern wirings are stacked so as to overlap one another in a plan view.

16. The semiconductor device according to claim 6, wherein: A bottom portion of the first redistribution wiring of the cylindrical capacitor is formed in a concavo-convex shape.

17. The semiconductor device according to claim 6, wherein: The internal electrode has a multilayer wiring structure in which a plurality of grid-pattern wirings are stacked, and The cylindrical capacitor has a protrusion embedded in one or more openings of the grid pattern wiring.

18. The semiconductor device according to claim 17, wherein: The cylindrical capacitor includes a plurality of the protrusions having different diameters and depths.

19. The semiconductor device according to claim 17, wherein: The protrusion of the cylindrical capacitor is formed in a circular or rectangular planar shape.

20. The semiconductor device according to claim 1, further comprising: a first electrode connected to a redistribution wiring formed on the second surface side of the semiconductor substrate; a second electrode surrounding the periphery of the first electrode in a plan view; as well as an insulating film between the first electrode and the second electrode, wherein The first electrode, the second electrode, and the insulating film constitute a capacitor.

21. The semiconductor device according to claim 1, further comprising: a groove formed in the semiconductor substrate and having a side surface inclined at a predetermined angle; At least two electrode films, a first electrode film and a second electrode film, are stacked in the groove; as well as a dielectric film formed at least between the first electrode film and the second electrode film, wherein: The first electrode film is connected to the first redistribution wiring on the semiconductor substrate along the side surface of the groove, The second electrode film is connected to another of the first redistribution wirings on the semiconductor substrate along a side surface of the trench, and A capacitor is formed by stacking the first electrode film, the dielectric film, and the second electrode film.

22. The semiconductor device according to claim 1, wherein The capacitor is composed of a planar capacitor and a cylindrical capacitor connected in series or in parallel, wherein the planar capacitor is formed by the first rewiring and the second rewiring on the second surface side of the semiconductor substrate, and the cylindrical capacitor is formed by the first rewiring and the second rewiring in the through hole.

23. The semiconductor device according to claim 1, wherein The capacitor includes an interlayer thin film portion in which a film thickness of the interlayer insulating film between the first redistribution wiring and the second redistribution wiring is formed to be thinner than a film thickness of the other interlayer insulating film.

24. The semiconductor device according to claim 23, wherein: The film thickness of the interlayer insulating film of the interlayer thin film portion is equal to or less than 500 nm, and The other interlayer insulating film has a film thickness of 5 μm to 10 μm.

25. The semiconductor device according to claim 1, wherein The interlayer insulating film between the first redistribution wiring and the second redistribution wiring constituting the capacitor is formed of a high dielectric film.

26. The semiconductor device according to claim 25, wherein The high dielectric film is formed on the entire surface in a plan view.

27. The semiconductor device according to claim 25, wherein: The high dielectric film is formed only in a region where the first redistribution wiring and the second redistribution wiring constituting the capacitor overlap with each other.

28. The semiconductor device according to claim 1, wherein The semiconductor substrate has a trench dug to a predetermined depth, and In the first redistribution wiring and the second redistribution wiring constituting the capacitor, a step is formed in the trench of the semiconductor substrate.

29. The semiconductor device according to claim 28, wherein: The groove is formed at the same depth as the through hole.

30. The semiconductor device according to claim 1, wherein The first rewiring includes a first wiring and a second wiring capacitively coupled in a planar direction, and The second redistribution wiring includes a third wiring and a fourth wiring that are capacitively coupled in the planar direction.

31. The semiconductor device according to claim 30, wherein: The first wiring and the second wiring each have a comb-teeth shape in a planar shape, and the third wiring and the fourth wiring each have a comb-teeth shape in a planar shape.

32. The semiconductor device according to claim 1, wherein: The first redistricting wiring and the second redistricting wiring constituting the capacitor are formed in a region including the entire region of a pixel region in a plan view.

33. A method for manufacturing a semiconductor device, the method comprising: forming an internal electrode formed on the first surface side of the semiconductor substrate, forming a through hole formed at a position corresponding to the internal electrode of the semiconductor substrate, forming a first redistribution wiring which is formed on a second surface side opposite to the first surface side of the semiconductor substrate and is connected to the internal electrode via the through hole, forming a second redistribution wiring which is connected to the first redistribution wiring and is formed on a side closer to an external connection terminal than the first redistribution wiring; as well as forming an interlayer insulating film, the interlayer insulating film being formed between the first redistribution wiring and the second redistribution wiring, wherein Both the first inner electrode and the second inner electrode are formed as the inner electrodes, and the first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor.

34. An electronic device comprising a semiconductor device, the semiconductor device comprising: an internal electrode formed on the first surface side of the semiconductor substrate; a through hole formed at a position corresponding to the internal electrode of the semiconductor substrate; a first redistribution wiring formed on a second surface side opposite to the first surface side of the semiconductor substrate and connected to the internal electrode via the through hole; a second redistribution wiring connected to the first redistribution wiring and formed on a side closer to the external connection terminal than the first redistribution wiring; as well as An interlayer insulating film is formed between the first redistribution wiring and the second redistribution wiring, wherein Both a first internal electrode and a second internal electrode are provided as the internal electrodes, and The first redistribution wiring connected to the first inner electrode, the second redistribution wiring connected to the second inner electrode, and the interlayer insulating film constitute a capacitor.

35. A semiconductor device comprising: a first electrode connected to a redistribution wiring formed on the rear surface side of the semiconductor substrate; a second electrode surrounding the periphery of the first electrode in a plan view; as well as an insulating film between the first electrode and the second electrode, wherein The first electrode, the second electrode, and the insulating film constitute a capacitor.

36. The semiconductor device according to claim 35, wherein: The insulating film includes a high dielectric film having a relative dielectric constant higher than that of a silicon oxide film.

37. The semiconductor device according to claim 35, wherein: The first electrode is an external connection terminal, and The second electrode is connected to an external connection terminal different from the first electrode.

38. The semiconductor device according to claim 35, wherein: The first electrode is connected to the rewiring; The insulating film is also formed between the second electrode and the redistribution wiring, and the capacitor includes the second electrode, the redistribution wiring, and the insulating film.

39. The semiconductor device according to claim 35, wherein: The first electrode is an external connection terminal, and A power supply voltage, a ground line or a signal is provided to the first electrode.

40. The semiconductor device according to claim 35, wherein The periphery of the first electrode is covered with a protective film, and In a plan view, the upper surface of the second electrode is covered with the protective film.

41. The semiconductor device according to claim 35, wherein The periphery of the second electrode is covered with the insulating film in a plan view.

42. The semiconductor device according to claim 35, wherein: The rear surface of the device except the first electrode is covered with a protective film.

43. The semiconductor device according to claim 35, wherein: The second electrode is a wiring that surrounds the first electrode in a ring shape in a plan view.

44. The semiconductor device according to claim 35, wherein: The first electrode has a circular shape or a polygonal shape in a plan view, and the second electrode is a wiring that annularly surrounds the first electrode having the circular shape or the polygonal shape.

45. The semiconductor device according to claim 35, wherein The first electrode and the second electrode each have a barrier metal on a side surface, and The material of the barrier metal includes any one of Ta, TaN, Ti, TiN and Ru.

46. ​​A method for manufacturing a semiconductor device, the method comprising: forming a first electrode connected to a redistribution wiring formed on the rear surface side of the semiconductor substrate, forming a second electrode that surrounds the periphery of the first electrode in a plan view, and An insulating film is formed between the first electrode and the second electrode, wherein The first electrode, the second electrode, and the insulating film constitute a capacitor.

47. A semiconductor device comprising: a trench formed in the semiconductor substrate and having a side surface inclined at a predetermined angle; At least two electrode films, a first electrode film and a second electrode film, are stacked in the groove; as well as a dielectric film formed at least between the first electrode film and the second electrode film, wherein: The first electrode film formed along the side surface of the groove is connected to the first redistribution wiring on the semiconductor substrate, The second electrode film formed along the side surface of the trench is connected to another of the first redistribution wirings on the semiconductor substrate, and The capacitor is formed by stacking the first electrode film, the dielectric film, and the second electrode film.

48. The semiconductor device according to claim 47, further comprising: The third electrode film in the groove, wherein The capacitor is configured by stacking the first to third electrode films and the dielectric film.

49. The semiconductor device according to claim 48, wherein The third electrode film is configured to be connected to the first redistribution wiring on the semiconductor substrate along a side surface of the trench.

50. The semiconductor device according to claim 48, wherein The third electrode film is configured not to be connected to any of the first redistribution wirings on the semiconductor substrate.

51. The semiconductor device according to claim 48, wherein A material of a dielectric film between the first electrode film and the second electrode film is different from a material of a dielectric film between the second electrode film and the third electrode film.

52. The semiconductor device according to claim 48, wherein: The capacitor has a configuration in which two parallel plate capacitors are connected in parallel.

53. The semiconductor device according to claim 48, wherein: The capacitor has a configuration in which two parallel plate capacitors are connected in series.

54. The semiconductor device according to claim 47, wherein: The predetermined angle is in the range of 45 degrees to 70 degrees.

55. The semiconductor device according to claim 47, wherein A connection surface between the first electrode film and the first redistribution wiring and a connection surface between the second electrode film and another first redistribution wiring are linear in a plan view and are arranged in parallel.

56. The semiconductor device according to claim 47, further comprising: The third electrode film and the fourth electrode film in the groove, wherein The first to fourth electrode films are configured to be connected to different first redistribution wirings, respectively.

57. The semiconductor device according to claim 56, wherein: Four connection surfaces where the first electrode film to the fourth electrode film are connected to the first redistribution wiring are arranged in a substantially quadrilateral shape in a plan view.

58. The semiconductor device according to claim 56, wherein: Different potentials are provided to at least two adjacent electrode films among the first to fourth electrode films.

59. The semiconductor device according to claim 56, wherein: Different potentials are applied to the first to fourth electrode films.

60. The semiconductor device according to claim 56, wherein The groove has a polygonal truncated pyramid shape.

61. The semiconductor device according to claim 56, wherein: The groove has a quadrangular pyramid shape.

62. The semiconductor device according to claim 47, wherein: The plurality of capacitors are connected in parallel or in series via the first rewiring.

63. The semiconductor device according to claim 47, wherein: Two insulating films of different materials are stacked at the bottom of the trench.

64. A method for manufacturing a semiconductor device, the method comprising: forming a trench having a side surface inclined at a predetermined angle in a semiconductor substrate; forming at least two electrode films, a first electrode film and a second electrode film, stacked in the groove; A dielectric film is formed at least between the first electrode film and the second electrode film, wherein forming the first electrode film formed along the side surface of the trench to be connected to a first redistribution wiring on the semiconductor substrate, and forming the second electrode film formed along the side surface of the trench to be connected to another first redistribution wiring on the semiconductor substrate, and A capacitor is formed by stacking the first electrode film, the dielectric film, and the second electrode film.

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