Method for producing semiconductor chip and semiconductor chip

Abstract

The invention specifies a method for producing a semiconductor chip, comprising:-providing a growth substrate (1) having a growth surface (1a),-growing a buffer layer (2) on the growth surface (1a),-growing an active structure (3) on the buffer layer (2),-the active structure (3) being based on a nitride compound semiconductor material,-the buffer layer (2) being formed from InxAl1-xN,-the active structure (3) being formed from a nitride compound semiconductor material,-the buffer layer (2) being formed from InxAl1-xN, and-the active structure (3) being formed from InxAl1-xN. And-and x is at least 0.02 and at most 0.13.

Description

[0001] A method for producing a semiconductor chip and a semiconductor chip are described in detail herein.

[0002] One problem to be solved is to specify a method by which a semiconductor chip of enhanced quality can be produced. Another problem to be solved is to specify such a semiconductor chip.

[0003] The semiconductor chip produced by the method described herein is, for example, an electronic semiconductor chip or an optoelectronic semiconductor chip. The semiconductor chip comprises at least one active structure in which the main functions of the chip occur during operation of the semiconductor chip. In the case where the semiconductor chip is an optoelectronic chip, the active structure is, for example, configured to receive and / or generate electromagnetic radiation.

[0004] According to at least one aspect of the method, a growth substrate having a growth surface is provided. The growth surface of the growth substrate is a portion of the outer surface of the growth substrate, on which epitaxial growth of semiconductor material subsequently occurs, for example. For example, the growth surface is formed of sapphire or silicon. In this case, for example, the growth substrate can consist of sapphire or silicon, respectively.

[0005] In addition, the growth substrate may be a composite substrate composed of two or more regions. In this case, the growth surface may be formed of a material different from the base of the growth substrate.

[0006] According to at least one aspect of the method, a buffer layer is grown on the growth surface. For example, the buffer layer can be epitaxially grown onto the growth surface. Thus, another layer or layers can be arranged between the buffer layer and the growth surface. However, the growth surface and the buffer layer can also be in direct contact with each other at least in certain locations. For example, the buffer layer is grown directly onto a growth surface consisting of silicon. In this case, the substrate can also consist of silicon.

[0007] The buffer layer is configured to enhance the crystal quality of the semiconductor chip.

[0008] According to at least one aspect of the method, an active structure is grown on the buffer layer. The active structure is a structure that implements the function of the semiconductor chip during operation of the semiconductor chip. For example, the active structure includes a plurality of layers and is epitaxially grown onto the buffer layer. Thus, at least one further layer may be arranged between the active structure and the buffer layer. However, the active structure and the buffer layer may also be in direct contact with each other.

[0009] According to at least one aspect of the method, the active structure is configured to generate electromagnetic radiation in a wavelength range between 240 nm and 320 nm.

[0010] That is, the emitted electromagnetic radiation has, for example, a peak wavelength, and the peak wavelength is within a given wavelength range. In other words, the active structure is configured to generate UVB radiation and / or UVC radiation.

[0011] According to at least one aspect of the method, the active structure is based on a nitride compound semiconductor material.

[0012] "Based on nitride compound semiconductor materials" means in the present context that the active structure or at least a part thereof, in particular preferably at least one layer, comprises a nitride compound semiconductor material (preferably Al n Ga m In 1-n-m N, where 0≤n≤1, 0≤m≤1 and n+m≤1) or consists of a nitride compound semiconductor material. In this context, such a material does not necessarily have to have a mathematically exact composition according to the above formula. Instead, it may have, for example, one or more dopants as well as additional components. However, for the sake of simplicity, the above formula only includes the main components of the lattice (Al, Ga, In, N), even if these components may be partially replaced and / or supplemented by small amounts of other substances.

[0013] According to at least one aspect of the method, the buffer layer is composed of In x Al 1-x N is formed, and x is selected between at least 0.02 and at most 0.13.

[0014] According to at least one aspect of the method, a method for producing a semiconductor chip includes:

[0015] - providing a growth substrate having a growth surface,

[0016] - growing a buffer layer on the growth surface,

[0017] - growing an active structure on the buffer layer, wherein:

[0018] - The active structure is based on nitride compound semiconductor materials,

[0019] - the active structure is configured to generate electromagnetic radiation in the wavelength range between 240 nm and 320 nm,

[0020] - The buffer layer is composed of In x Al 1-x N formation, and

[0021] - and x is at least 0.02 and at most 0.13.

[0022] In particular, the method steps may be performed in the order specified.

[0023] The method described herein is based inter alia on the following considerations: For semiconductor chips having active structures based on nitride compound semiconductor materials, the active structures can be grown onto a growth substrate and the growth substrate can be subsequently removed, for example by laser lift-off and / or grinding and etching techniques.

[0024] In the case where the active structure comprises layers with a high aluminum content, which is necessary, for example, for the production of semiconductor chips that can act as light-emitting diodes emitting light in the UVC and / or UVB spectral range, buffer layers based on AlN can be used. However, for such buffer layers, when applying the laser lift-off technique to separate the growth substrate from the epitaxially grown layer, it is necessary to use lasers with very short wavelengths below 200 nm that can be absorbed in the AlN layer.

[0025] Such lasers are difficult to use for economical production due to different problems such as ionization of O2 requiring N2 purge, reliability of the lasers used, short lifetime of the mirrors of the lasers, etc.

[0026] Furthermore, for buffer layers based on AlN, high temperatures of more than 1300° C. are used during the epitaxy of semiconductor chips in order to achieve good crystal quality.

[0027] Furthermore, an AlGaN layer of a semiconductor chip grown on an AlN buffer layer is not lattice matched to such a buffer layer and is therefore prone to having an increased defect density and a rough surface.

[0028] One idea of ​​the present method is to now use an In based indium having an indium content x of at least 0.02 and at most 0.13. x Al 1-x A buffer layer of N. Such a buffer layer makes it possible to achieve a high crystal quality in the subsequent active structure while being relatively thin.

[0029] Furthermore, such buffer layers can be grown at significantly lower temperatures, for example AlN layers, and enable lattice-matched growth of active structures of the semiconductor chip.

[0030] Furthermore, such a buffer layer can act as a sacrificial layer for a laser lift-off process to easily remove the growth substrate to obtain a thin film semiconductor chip, such as a thin film light emitting diode with enhanced light extraction and thus higher performance. Such laser lift-off can be accomplished, for example, using a laser emitting at a wavelength of 248 nm (which is more economical to use than the lasers described above with an emission wavelength below 200 nm).

[0031] According to at least one aspect of the method, the indium content x decreases toward the growth surface of the growth substrate. That is, the indium content in the buffer layer has a gradient and decreases toward the growth substrate. Therefore, just at the interface between the growth surface and the buffer layer, the buffer layer may include a region with a low indium content that is substantially formed of AlN or formed of AlN. However, the AlN sublayer of such a buffer layer is quite thin and has a thickness of at most 5 nm. Therefore, it does not cause any problems for the subsequent laser lift-off process that occurs in the indium-containing portion of the buffer layer.

[0032] According to at least one aspect of the method, the buffer layer comprises two or more sublayers, each of which has an indium content between 0 and 30%. For example, the buffer layer comprises alternating layers with higher and lower indium contents. Thus, some of the layers may be nominally free of indium. With such a structure of the buffer layer, the indium content of the entire buffer layer can be set very precisely. However, the indium can also be uniformly distributed over the entire buffer layer.

[0033] According to at least one aspect of the method, the buffer layer is in direct contact with the growth surface at least at certain locations and / or an intermediate layer is arranged at least at certain locations between the growth surface and the buffer layer, and the intermediate layer is composed of AlN. However, in the case where such an intermediate layer is arranged between the buffer layer and the growth substrate, the intermediate layer has a relatively small thickness of at most 5 nm.

[0034] According to at least one aspect of the method, the buffer layer has a thickness of between at least 20 nm and at most 500 nm. With such a thin buffer layer, a high crystalline quality of the subsequent active structure can be achieved.

[0035] According to at least one aspect of the method, the buffer layer is annealed at a temperature of up to 1200°C. For example, the buffer layer is annealed at a temperature of up to 1150°C, in particular at a temperature of about 1100°C. The annealing is performed, for example, under an NH3 atmosphere. In particular, the annealing can be performed under an overpressure of indium. For example, the annealing is performed for at least half an hour to at most two hours. The crystal quality of the buffer layer is improved by the annealing. After the annealing, an active structure is grown on the buffer layer. The annealing is performed in situ in a MOVPE reactor, in which the active structure is subsequently grown on the buffer layer.

[0036] Due to the fact that the buffer layer comprises indium, the crystal quality can be improved by annealing at temperatures below 1200° C. This is in contrast to, for example, buffer layers consisting of AlN, which require temperatures of over 1400° C. during the annealing step. The lower process temperature also results in lower substrate bowing at the end of the process and thus contributes to improving the quality of the produced semiconductor chips.

[0037] Since the buffer layer is relatively thin, the thickness of the entire semiconductor chip is relatively low, and this also reduces substrate bending.

[0038] Semiconductor chips can thus be produced on wafers having a large diameter, for example having a diameter of 150 mm and more. This enables particularly economical production of semiconductor chips.

[0039] According to at least one aspect of the method, the active structure comprises Al 1-y Ga y N, wherein y is at least 0.30 and at most 0.40. With such an n-doped layer, for example, an active structure which is particularly suitable for emitting UV radiation during operation of the semiconductor chip can be grown. For example, in the case of a semiconductor chip which emits UVC radiation during operation, y=0.35.

[0040] For example, in the case of a semiconductor chip which emits UVB radiation during operation, y is between 0.50 and 0.7, for example 0.55 or 0.6.

[0041] Due to the InAlN-based buffer layer, the AlGaN-based n-doped layer can be grown in a lattice-matched manner. In this way, the crystal quality of the buffer layer can be maintained or even improved. Since there are fewer limiting factors for growing thick n-doped layers, the surface morphology of the active structure can also be improved. In addition, the thicker n-doped layer can effectively protect the remaining active structure from possible damage during the laser lift-off process (for example, using a laser at a wavelength of 248nm). To this end, the n-doped layer has, for example, a thickness of at least 1μm and at most 3μm. Such a thick n-doped layer also allows a particularly uniform current distribution in the active structure.

[0042] According to at least one aspect of the method, an AlGaN-based strain control layer is grown between the buffer layer and the active structure. For example, the strain control layer is nominally undoped. In the strain control layer, the content of aluminum can, for example, increase from the buffer layer in the direction of the active structure. In this way, the strain during the growth of the n-doped layer can be further reduced.

[0043] According to at least one aspect of the method, the growth surface includes grooves extending into the growth substrate, and at least some of the grooves are arranged parallel to each other. For example, the growth surface may only include grooves arranged parallel to each other and at a given distance from each other.

[0044] Alternatively, the further grooves may also be arranged at an angle of, for example, 90° or ±60°.

[0045] For example, some or all of the grooves are tempered in a direction from the growth surface into the growth substrate.

[0046] For example, adjacent grooves have a distance of between at least 1 mm and at most 10 mm from one another.

[0047] Furthermore, some or all of the grooves may have a width at the growth surface of between at least 1 μm and at most 10 μm.

[0048] Furthermore, some or all of the grooves may have a depth of between at least 1 μm and at most 3 μm. In particular, all grooves may have the same width and the same depth.

[0049] With such a prestructured substrate, the formation of cracks due to tensile strain during the growth of the semiconductor layer is mitigated. This can prove to be particularly advantageous for growth substrates consisting of silicon.

[0050] According to one aspect of the method, the active structure is configured to generate electromagnetic radiation in a wavelength range between 240 nm and 280 nm, and x is at least 0.02 and at most 0.075. The semiconductor chip is, for example, a light emitting diode or a semiconductor layer chip.

[0051] That is, the emitted electromagnetic radiation has, for example, a peak wavelength, and the peak wavelength is within a given wavelength range. In other words, the active structure is configured to generate UVC radiation.

[0052] For this radiation, an indium content between 2% and 7.5% has proven to be particularly advantageous. In this case, the n-doped layer is also composed, for example, of Al 0.65 Ga 0.35 The layer of N is formed.

[0053] According to at least one aspect of the method, the active structure is configured to generate electromagnetic radiation in a wavelength range between 280 nm and 320 nm, and x is at least 0.09 and at most 0.13. The semiconductor chip is, for example, a light emitting diode or a semiconductor layer chip.

[0054] Such an indium content has proven to be advantageous for active structures which are configured to generate UVB radiation. In this case, the n-doped layer consists, for example, of Al 0.45 Ga 0.55 The layer of N is formed.

[0055] According to one aspect of the method, the growth substrate is removed. For example, in the case where the growth substrate is formed of sapphire, the removal of the growth substrate may be performed by a laser lift-off process.

[0056] In this case, laser radiation having a wavelength of 248 nm, for example, is absorbed in the buffer layer, and the growth substrate is removed by partial decomposition of the buffer layer by the laser radiation.

[0057] In the case where the growth substrate is formed of silicon, the growth substrate is removed by, for example, etching and grinding. In this case, the buffer layer may serve as an etching stop layer.

[0058] Furthermore, a semiconductor chip is specifically described. The semiconductor chip can be produced by the method described herein. That is, all features disclosed for the method are also disclosed for the semiconductor chip, and vice versa.

[0059] According to at least one aspect of the semiconductor chip, the semiconductor chip includes at least a remaining portion of the buffer layer. That is, when the growth substrate is removed from the epitaxial growth layer, only the remaining portion of the buffer layer may still exist in the semiconductor chip. When the growth substrate is still present, the buffer layer may also be completely present in the semiconductor chip.

[0060] According to at least one aspect of the semiconductor chip, the active structure is arranged on the buffer layer. For example, the active structure is arranged directly on, for example, the remaining portion of the buffer layer. In this case, the active layer can also be exposed at least in certain locations and not covered by the remaining portion of the buffer layer.

[0061] According to one aspect of the semiconductor chip, the active structure is based on a nitride compound semiconductor material, and the buffer layer includes In x Al 1-x N and x is at least 0.02 and at most 0.13.

[0062] According to at least one aspect of a semiconductor chip, the semiconductor chip includes:

[0063] - at least a remaining portion of the buffer layer, and

[0064] - an active structure on the buffer layer, wherein

[0065] - The active structure is based on nitride compound semiconductor materials,

[0066] - Buffer layer includes In x Al 1-x N, and

[0067] - and x is at least 0.02 and at most 0.13.

[0068] The semiconductor chip may be free of a growth substrate. In this case, the semiconductor chip is a thin film chip from which the growth substrate has been removed. For example, one side of the active structure including the remaining part of the buffer layer may thus be roughened, which increases the likelihood that electromagnetic radiation leaves the semiconductor chip if the semiconductor chip is a radiation-emitting optoelectronic chip.

[0069] According to at least one aspect of the semiconductor chip, the active structure is configured to generate electromagnetic radiation in a wavelength range between 240nm and 280nm, and x is at least 0.02 and at most 0.75, or the active structure is configured to generate electromagnetic radiation in a wavelength range between 280nm and 320nm, and x is at least 0.09 and at most 0.13.

[0070] Hereinafter, the method described herein and the semiconductor chip described herein are explained in more detail in conjunction with exemplary embodiments and corresponding drawings.

[0071] Combination Figure 1 , a first specific embodiment of a semiconductor chip described herein is shown in a schematic diagram.

[0072] Combination Figure 2 , a further embodiment of a semiconductor chip described herein is shown in a schematic diagram.

[0073] Combination Figure 3A , Figure 3B , Figure 3C Schematic diagram of an embodiment for producing a semiconductor chip.

[0074] Combination Figure 4A and Figure 4B Schematic diagram showing one aspect of an implementation of the method described herein.

[0075] Combination Figure 5A and Figure 5B A graphical representation of another aspect of the method described herein is depicted.

[0076] In the exemplary embodiments and the drawings, components that are similar or have similar functions are provided with the same reference numerals. The elements shown in the drawings and their dimensional relationships to each other should not be regarded as true proportions. On the contrary, individual elements may be represented in exaggerated sizes for better representation and / or for better understanding.

[0077] Combination Figure 1 , describes in more detail a first embodiment of the optoelectronic semiconductor chip described herein. The semiconductor chip comprises a growth substrate 1. The growth substrate 1 is formed, for example, of silicon or sapphire. The growth substrate 1 has a growth surface 1a. A buffer layer 2 is epitaxially grown onto the growth substrate 1a. The buffer layer 2 is composed of In x Al 1-x N is formed, wherein x is at least 0.02 and at most 0.13.

[0078] In some embodiments of the optoelectronic device, the buffer layer 2 may include two or more sub-layers 21 , 22 , wherein each of the sub-layers has an indium content between 0 and 13%.

[0079] Therefore, the buffer layer 2 may be in direct contact with the growth surface 1a at least at some positions. At least at some positions or in the whole, an intermediate layer 12 may be arranged between the growth surface 1a and the buffer layer 2, wherein the intermediate layer is composed of AlN, for example.

[0080] Furthermore, in some embodiments, the indium content in the buffer layer may decrease toward the growth surface 1a. Thus, the indium content directly at the growth surface may also decrease to near zero or zero.

[0081] The buffer layer has, for example, a thickness D of between at least 20 nm and at most 500 nm.

[0082] During the production of the semiconductor chip, the buffer layer 2 is annealed at a temperature of at most 1200° C.

[0083] The active structure 3 is arranged on the buffer layer 2. The active structure 3 includes Al 1-y Ga y N forms an n-doped layer 31, wherein y is at least 0.3 and at most 0.4. In particular, the n-doped layer can be formed with a gallium content of 35% and thus an aluminum content of 65%. For example, this layer is doped with silicon or germanium.

[0084] The n-doped layer has, for example, a thickness between 1 μm and at most 3 μm. A thin strain control layer 13 based on AlGaN may be arranged between the buffer layer 2 and the active structure 3 .

[0085] The active structure 3 further comprises an active layer 32, which consists, for example, of a multi-quantum well structure, which is configured to emit electromagnetic radiation during operation of the semiconductor chip. Figure 1 In the embodiment, the active structure further comprises a first p-doped layer 33, the first p-doped layer 33 is composed of, for example, Al 0.85 Ga 0.15 N is formed and doped with Mg. In addition, the active structure 3 may include Al 0.65 Ga 0.35 The second p-doped layer 34 is formed of N and is also doped with Mg.

[0086] Finally, the semiconductor chip can comprise, for example, a contact 4 for contacting the semiconductor chip on the p-side of the semiconductor chip and further layers, not described in detail, such as a passivation layer.

[0087] Figure 1 The semiconductor chip of an embodiment of is configured, for example, to emit UVC radiation in a wavelength range between 240 nm and 280 nm during operation.

[0088] In the case of a semiconductor chip configured to emit UVB radiation, the active structure comprises a first p-doped layer 33, for example composed of Al 0.65 Ga 0.35 N is formed and doped with Mg. In addition, the active structure 3 may include Al 0.3 Ga 0.7 The second p-doped layer 34 is formed by N, which is also doped with Mg. The n-doped layer 31 can be formed with a gallium content of 55% and thus an aluminum content of 45%. For example, the n-doped layer 31 is doped with silicon or germanium.

[0089] Combination Figure 2 , shows a further embodiment of the optoelectronic chip described herein in more detail. In this embodiment, the growth substrate 1 is removed and only the remaining part of the buffer layer 2 remains in the semiconductor chip. The n-doped layer 31 is at least partially exposed and the semiconductor chip has a rough surface, which allows a higher probability that the radiation generated in the active region leaves the semiconductor chip.

[0090] A carrier 6 , for example made of silicon, can be arranged on the side of the semiconductor chip facing away from the n-doped layer. A bonding layer 5 and / or a mirror for reflecting radiation generated in the active region can be arranged between the carrier 6 and the contact layer 4 .

[0091] The substrate is removed by laser lift-off in the case of a sapphire substrate, or by etching and grinding in the case of the silicon substrate 1 , for example.

[0092] Combination Figure 3A , Figure 3B and Figure 3C , a further embodiment of a method for producing a semiconductor chip is described in more detail. According to the method, a substrate 1 is provided. An indium-containing buffer layer 2 described herein is grown onto the substrate, and an active structure 3 based on a nitride compound semiconductor material is subsequently grown on the buffer layer.

[0093] The active structure 3 comprises an n-doped layer 31 , an active layer 32 and p-doped layers 33 , 34 . In the next method step, a trench is formed through the p-doped layers 33 , 34 into the n-doped layer 31 . An n-contact 71 is deposited in the trench. An insulating layer 72 is formed for the deposition of the p-contact 4 .

[0094] Subsequently, the p-contact 4 is covered by a passivation layer 72 and an n-contact layer 73 is applied for contacting the n-contact 71 , see Figure 3B .

[0095] In a next method step, a bonding layer and a mirror layer 5 are deposited, and a carrier 6 is bonded to the semiconductor layer sequence.

[0096] The substrate 1 is then removed and an n-terminal layer 8 is applied to the side of the carrier 6 facing away from the substrate.

[0097] In the next method step ( Figure 3C ), defines the chip mesas and produces a roughened surface on the side facing away from the carrier 6. Furthermore, a passivation layer 10 can be applied and a p-type terminal 9 in contact with the p-type contact layer 4 can be produced.

[0098] Furthermore, the carrier 6 may be thinned and singulation into a plurality of semiconductor chips may be performed.

[0099] Figure 4A and Figure 4B The schematic diagram of shows a growth surface 1a of a growth substrate 1 that may be used in an embodiment of the method described herein. In this embodiment, the growth substrate 1 comprises grooves 11 that extend from the growth surface 1a into the growth substrate 1 and may, for example, be arranged parallel to each other.

[0100] In addition to the grooves 11 shown, further grooves may be arranged in the growth surface 1a, which extend, for example, perpendicularly or at an angle of, for example, ±60° relative to the grooves 11 shown. The grooves 11 taper in a direction from the growth surface 1a into the growth substrate 1. The distance d1 between adjacent grooves is, for example, between 1 mm and 10 mm, the width d2 of the grooves measured at the growth surface 1a is, for example, at least 1 μm and at most 10 μm, and the depth d3 of the grooves is, for example, between 1 μm and 3 μm. In particular, in the case where the substrate is made of silicon, these grooves can be used to reduce strain during the epitaxial growth of buffer layers and subsequent layers onto the substrate 1.

[0101] Figure 5A and Figure 5B The schematic diagram of FIG. 1 shows the InAlN parameters for lattice matching with the n-doped layer 31 used.

[0102] Combination Figure 5A , shows the use of Al 0.65 Ga 0.35 N lattice matching parameters. Such an n-doped layer 31 has about The lattice constant a. Figure 5A It becomes apparent that an indium content between about 2% and 7.5% allows a good lattice match to the n-doped layer 31. With such an n-doped layer 31 an active structure 3 configured to generate electromagnetic radiation in the spectral range of UVC radiation can be grown with good crystal quality.

[0103] Combination Figure 5B , shows the use of Al 0.45 Ga 0.55N lattice matching parameters. Such an n-doped layer 31 has about The lattice constant a. Figure 5B It becomes apparent that an indium content between about 9% and 13% allows a good lattice match to the n-doped layer 31. With such an n-doped layer 31 an active structure 3 configured to generate electromagnetic radiation in the spectral range of UVB radiation can be grown with good crystal quality.

[0104] The present invention is not limited to the exemplary embodiments by the description based on the exemplary embodiments. On the contrary, the present invention covers any new features and any combination of features, which particularly includes any combination of features in the patent claims and any combination of features in the exemplary embodiments, even if the feature or the combination itself is not explicitly specified in the patent claims or the exemplary embodiments.

[0105] This patent application claims the priority of German patent application 102022117307.0, the disclosure content of which is hereby incorporated by reference.

[0106] Reference numerals

[0107] 1 Growth substrate

[0108] 1a Growth surface

[0109] 2 buffer layer

[0110] 3 Active structure

[0111] 31n doped layer

[0112] 32 Active layer

[0113] 33 First p-doped layer

[0114] 34 Second p-doped layer

[0115] 4p contact layer

[0116] 5. Bonding layer

[0117] 6 Carrier

[0118] 71n contact part

[0119] 72 insulation layer

[0120] 73n contact layer

[0121] 8n terminal layer

[0122] 9p terminal

[0123] 10 Passivation layer

[0124] 11 slots

[0125] 12 Middle Layer

[0126] 13 Strain control layer

[0127] d1 distance

[0128] d2 width

[0129] d3 depth

[0130] DThickness

Claims

1. A method for producing a semiconductor chip, comprising: - providing a growth substrate (1) having a growth surface (1a), - growing a buffer layer (2) on the growth surface (1a), - growing an active structure (3) on the buffer layer (2), wherein: - the active structure (3) is based on a nitride compound semiconductor material, - the active structure (3) is configured to generate electromagnetic radiation in the wavelength range between 240 nm and 320 nm, - The buffer layer (2) is made of In x Al 1-x N formation, and - and x is at least 0.02 and at most 0.

13.

2. The method according to the preceding claim, wherein: x decreases towards the growth surface (1a).

3. The method according to one of the preceding claims, wherein: The buffer layer (2) comprises two or more sub-layers (21, 22), each of the sub-layers (21, 22) having an indium content between 0 and 13%.

4. The method according to one of the preceding claims, wherein: The buffer layer is in direct contact with the growth surface (1a) at least at certain locations, and / or an intermediate layer (12) is arranged between the growth surface (1a) and the buffer layer (2) and the intermediate layer (12) is composed of AlN.

5. The method according to one of the preceding claims, wherein: The buffer layer (2) has a thickness (D) between at least 20 nm and at most 500 nm.

6. The method according to one of the preceding claims, wherein: The buffer layer (2) is annealed at a temperature of up to 1200°C.

7. The method according to one of the preceding claims, wherein: The active structure (3) comprises Al 1-y Ga y N, and wherein y is at least 0.30 and at most 0.40, or y is at least 0.50 and at most 0.

70.

8. A method according to the preceding claim, wherein: The n-doped layer (31) has a thickness of at least 1 μm and at most 3 μm.

9. The method according to one of the preceding claims, wherein: An AlGaN-based strain control layer (13) is grown between the buffer layer (2) and the active structure (3).

10. The method according to one of the preceding claims, wherein: The growth surface (1a) comprises grooves (11) extending into the growth substrate (1), and at least some of the grooves (11) are arranged parallel to each other.

11. The method according to the preceding claim, wherein: The grooves (11) are rammed in a direction from the growth surface (1a) into the growth substrate (1).

12. The method according to the two preceding claims, wherein: Adjacent grooves (11) have a distance (d1) between each other of between at least 1 mm and at most 10 mm.

13. The method according to any one of the preceding claims, wherein: At least some of the grooves have a width (d2) of between at least 1 μm and at most 10 μm at the growth surface (1 a).

14. The method according to any one of the preceding claims, wherein: At least some of the grooves have a depth (d3) of between at least 1 μm and at most 3 μm.

15. The method according to one of the preceding claims, wherein: The active structure (3) is configured to generate electromagnetic radiation in a wavelength range between 240 nm and 280 nm, and x is at least 0.02 and at most 0.

075.

16. The method according to one of the preceding claims, wherein: The active structure (3) is configured to generate electromagnetic radiation in a wavelength range between 280 nm and 320 nm, and x is at least 0.09 and at most 0.

13.

17. The method according to one of the preceding claims, wherein: The growth substrate (1) is removed.

18. A semiconductor chip, comprising: - at least the remaining part of the buffer layer (2), and - an active structure (3) on the buffer layer (2), wherein: - the active structure (3) is based on a nitride compound semiconductor material, - the active structure (3) is configured to generate electromagnetic radiation in the wavelength range between 240 nm and 320 nm, - The buffer layer (2) includes In x Al 1-x N, and - and x is at least 0.02 and at most 0.

13.

19. The semiconductor chip according to claim 1, wherein: - the active structure (3) is configured to generate electromagnetic radiation in the wavelength range between 240 nm and 280 nm, and x is at least 0.02 and at most 0.075, or - the active structure (3) is configured to generate electromagnetic radiation in a wavelength range between 280 nm and 320 nm, and x is at least 0.09 and at most 0.13.

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