Welding assembly, semiconductor device and display panel

Abstract

The embodiment of the invention discloses a welding assembly, a semiconductor device and a display panel, and the welding assembly comprises a microelectronic device which is provided with a chip electrode; the binding substrate is provided with a substrate electrode; a third solder layer connected to one of the chip electrode and the substrate electrode; the second solder layer is connected to the other one of the chip electrode and the substrate electrode and is used for being welded with the third solder layer, and the second solder layer is a material which is welded with the third solder layer and does not generate an intermetallic compound; the first solder layer is used for being welded with the third solder layer, and the second solder layer surrounds the first solder layer; and the first solder layer is a material which can be welded with the third solder layer to generate an intermetallic compound. According to the embodiment of the invention, the welding quality of the microelectronic device can be improved, and edge stress is reduced.

Description

Welding components, semiconductor devices and display panels Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a welding assembly, a semiconductor device and a display panel. Background Art

[0002] Metal bonding technology is a key enabler for the development of Micro LED (Micro Light Emitting Diode) displays. It effectively connects the Micro LED chip to the driver substrate, providing a good current path. This allows the IC chip to control the flow of current through the driver substrate and the metal path, illuminating the Micro LED chip and creating different colors of light. However, existing metal bonding technology can be challenging due to heat and handling issues between the Micro LED chip and the substrate, resulting in stress and cracking of the metal solder. Technical issues

[0003] Therefore, there is an urgent need to provide a Micro LED welding solution to improve welding quality and reduce the problem of metal solder being susceptible to stress cracking. Technical Solutions

[0004] Therefore, to overcome at least some of the deficiencies in the prior art, embodiments of the present invention provide a soldering assembly, a semiconductor device, and a display panel that can improve the soldering quality of microelectronic devices and reduce the problem of metal solder being susceptible to stress fracture.

[0005] On the one hand, an embodiment of the present invention provides a welding assembly, comprising: a microelectronic device having a chip electrode; a binding substrate having a substrate electrode; a third solder layer connected to one of the chip electrode and the substrate electrode; a second solder layer connected to the other of the chip electrode and the substrate electrode, and used for welding with the third solder layer; the second solder layer is a material that does not produce intermetallic compounds when welded with the third solder layer; a first solder layer is used for welding with the third solder layer, the second solder layer surrounding the first solder layer; the first solder layer is a material that can produce intermetallic compounds when welded with the third solder layer.

[0006] In one embodiment, the second solder layer protrudes from one side of the first solder layer and surrounds the first solder layer to form a first groove; the third solder layer forms a protrusion matching the first solder layer; and the protrusion can be interlocked with the first groove.

[0007] In one embodiment, the first solder layer protrudes from one side of the second solder layer; the third solder layer forms a second groove matching the first solder layer; and the first solder layer and the second groove can be interlocked.

[0008] In one embodiment, the first solder layer has a first surface close to the third solder layer; the second solder layer has a second surface close to the third solder layer; and the height difference between the first surface and the second surface ranges from 0.1 to 2.5 microns.

[0009] In one embodiment, the third solder layer is selected from any one material or alloy of multiple materials of gold, tin, bismuth, copper, silver, indium and platinum; the first solder layer is selected from any one material or alloy of multiple materials of gold, tin, bismuth, copper, silver, indium and platinum; the second solder layer is selected from any one material or alloy of multiple materials of titanium, chromium, aluminum and molybdenum.

[0010] In one embodiment, the second solder layer has a middle region connected to the first solder layer and a peripheral region surrounding the middle region; an edge of the peripheral region away from the middle region has a first curved pattern.

[0011] In one embodiment, the second solder layer has a middle region connected to the first solder layer and a peripheral region surrounding the middle region; the peripheral region is formed with a hollow gap.

[0012] In one embodiment, the hollow gap has a second curved pattern.

[0013] Another embodiment of the present invention provides a semiconductor device that can be welded to an external device through an external solder layer, the semiconductor device comprising: a substrate, on which a pad layer is provided; a first solder layer, arranged on a side of the pad layer facing away from the substrate, for welding to the external solder layer; a second solder layer, arranged on a side of the pad layer facing away from the substrate; the second solder layer surrounds the first solder layer and is used for welding to the external solder layer; the first solder layer is a material that can be welded to the external solder layer to produce intermetallic compounds; the second solder layer is a material that does not produce intermetallic compounds when welded to the external solder layer.

[0014] In one embodiment, the first solder layer protrudes from a side of the second solder layer facing away from the pad layer.

[0015] In one embodiment, the second solder layer protrudes from a side of the first solder layer facing away from the pad layer and is surrounded by the first solder layer to form a first groove.

[0016] In one embodiment, the second solder layer has a middle region connected to the first solder layer and a peripheral region surrounding the middle region; an edge of the peripheral region away from the middle region has a first curved pattern.

[0017] In one embodiment, the second solder layer has a middle region connected to the first solder layer and a peripheral region surrounding the middle region; the peripheral region is formed with a hollow gap.

[0018] In one embodiment, the hollow gap has a second curved pattern.

[0019] Another embodiment of the present invention provides a display panel, comprising any one of the aforementioned welding components, wherein the microelectronic device is a micro-light-emitting chip; the binding substrate is a driving substrate, and a driving circuit electrically connected to the substrate electrode is provided on the driving substrate; the first solder layer and the second solder layer are both welded to the third solder layer. Beneficial effects

[0020] The above-mentioned embodiments of the present invention have at least one or more of the following beneficial effects: a first solder layer and a second solder layer surrounding the first solder layer are provided in a welding structure for binding a substrate or a microelectronic device (semiconductor device); by setting the materials of the first solder layer and the second solder layer to be different, the first solder layer can be welded with the external solder layer (third solder layer) to produce an intermetallic compound, while the second solder layer is welded with the external solder layer (third solder layer) without producing an intermetallic compound; due to the difference in the combination of different solders, an intermetallic compound is formed in the middle position of the weld to increase the welding strength, while no intermetallic compound is formed in the peripheral area of ​​the weld to reduce edge stress and increase welding strength, thereby achieving a more stable welding effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] FIG1 is a schematic diagram of stress distribution at a welding position in the related art.

[0023] FIG2 is a schematic structural diagram of a welding assembly provided by one embodiment of the present invention.

[0024] FIG3 is a schematic structural diagram of a welding assembly provided by another embodiment of the present invention.

[0025] FIG4 is a schematic structural diagram of the microelectronic device portion in the disassembled structure of the welding assembly shown in FIG2 .

[0026] FIG5 is a schematic structural diagram of the bonding substrate portion in the split structure of the welding assembly shown in FIG2 .

[0027] FIG6 is a schematic structural diagram of a welding assembly provided by another embodiment of the present invention.

[0028] FIG. 7 is a schematic structural diagram of the microelectronic device portion in the disassembled structure of the welding assembly shown in FIG. 6 .

[0029] FIG8 is a schematic structural diagram of the bonding substrate portion in the split structure of the welding assembly shown in FIG6 .

[0030] FIG9 is a schematic top view of the structure of the bonding substrate portion of the welding assembly in one embodiment of the present invention.

[0031] FIG10 is a schematic structural diagram of a specific embodiment of FIG9 .

[0032] FIG11 is a schematic structural diagram of another specific embodiment of FIG9 .

[0033] FIG12 is a schematic structural diagram of another specific embodiment of FIG9 .

[0034] FIG13 is a schematic structural diagram of another specific embodiment of FIG9 .

[0035] FIG14 is a schematic structural diagram of a semiconductor device provided in accordance with an embodiment of the present invention.

[0036] FIG15 is a schematic structural diagram of a semiconductor device provided in another embodiment of the present invention.

[0037] FIG16 is a schematic top view of the structure of a semiconductor device provided by one embodiment of the present invention.

[0038] FIG17 is a schematic structural diagram of a specific embodiment of FIG16 .

[0039] FIG18 is a schematic structural diagram of another specific embodiment of FIG16 .

[0040] FIG19 is a schematic structural diagram of another specific embodiment of FIG16 .

[0041] FIG20 is a schematic structural diagram of another specific embodiment of FIG16.

[0042] FIG21 is a schematic structural diagram of a display panel provided in one embodiment of the present invention.

[0043] FIG22 is a schematic structural diagram of a display panel provided in one embodiment of the present invention.

[0044] [Description of Reference Numerals]

[0045] 100: welding component; 10: microelectronic device; 11: chip electrode; 20: binding substrate; 21: substrate electrode; 22: driving circuit; 30: welding structure; 31: first solder layer; 311: first surface; 32: second solder layer; 321: second surface; 322: middle area; 323: peripheral area; 324: hollow gap; 33: third solder layer; 331: protrusion; 332: second groove; 34: first groove; 200: semiconductor device; 40: substrate; 41: pad layer; 300: display panel. Modes for Carrying Out the Invention

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0050] In the prior art, the soldering process between Micro LED chips and driver substrates is susceptible to stress and fracture due to heat and surface conditions. The IMC (Intermetallic Compound) layer formed during soldering is prone to cracking, especially in high temperature and humidity conditions. Under stress, the IMC layer also begins to crack at the edges. As shown in Figure 1, the lighter-colored area at the edge represents the location of maximum stress and the starting point of crack formation. Therefore, the present invention provides novel soldering solutions to mitigate the poor soldering quality caused by high edge stress in the prior art, thereby improving soldering yield and strength.

[0051] [First embodiment]

[0052] As shown in FIG2 , a first embodiment of the present invention provides a welding assembly 100 comprising a microelectronic device 10 and a bonding substrate 20 that can be welded together. The microelectronic device 10 is, for example, a micro-light-emitting device such as a Micro LED chip. The microelectronic device 10 has a chip electrode 11, which can be understood as the positive or negative electrode of the Micro LED chip. The bonding substrate 20 has a substrate electrode 21. The microelectronic device 10 and the bonding substrate 20 are electrically connected by welding the chip electrode 11 and the substrate electrode 21. When the microelectronic device 10 and the bonding substrate 20 are welded together, the substrate electrode 21 and the chip electrode 11 are arranged relative to each other in a first direction. The bonding substrate 20 is, for example, a driving substrate for a Micro LED chip that can drive the microelectronic device 10 to operate. The bonding substrate 20 also includes a driving circuit 22, and the substrate electrode 21 is electrically connected to the driving circuit 22, so that the bonding substrate 20 can drive the microelectronic device 10 via the driving circuit 22.

[0053] In this embodiment, the microelectronic device 10 and the binding substrate 20 can be welded between the chip electrode 11 and the substrate electrode 21 by connecting them through a welding structure 30. The welding structure 30 includes a first solder layer 31, a second solder layer 32 and a third solder layer 33. Among them, the third solder layer 33 is connected to one of the chip electrode 11 and the substrate electrode 21, and the second solder layer 32 is connected to the other of the chip electrode 11 and the substrate electrode 21. Figures 2 and 3 are schematic structural diagrams of the welding assembly 100 in two different embodiments, respectively. At this time, the microelectronic device 10 and the binding substrate 21 are in a welded state. Referring to Figure 2, it is a structure in which the third solder layer 33 is connected to the chip electrode 11 and the second solder layer 32 is connected to the substrate electrode 21. Referring to Figure 3, it is a structure in which the second solder layer 32 is connected to the chip electrode 11 and the third solder layer 33 is connected to the substrate electrode 21. Taking the soldering assembly 100 shown in FIG2 as an example, the microelectronic device 10 and the third solder layer 33 connected to the chip electrode 11 can form the microelectronic component shown in FIG4 , and the binding substrate 21 and the first solder layer 31 and second solder layer 32 connected to the substrate electrode 21 can form the binding backplane shown in FIG5 . The first solder layer 31 is used for soldering to the third solder layer 33. When the microelectronic device 10 and the binding substrate 21 are soldered together as shown in FIG2 and FIG3 , the first solder layer 31 is connected to the third solder layer 33. The second solder layer 32 surrounds the first solder layer 31 and is used for soldering to the third solder layer 33. When the microelectronic device 10 and the binding substrate 21 are soldered together as shown in FIG2 and FIG3 , the second solder layer 32 is connected to the third solder layer 33.

[0054] The first solder layer 31 is a material capable of forming an intermetallic compound (IMC) when welded with the third solder layer 33. The second solder layer 32 is a material capable of forming no IMC when welded with the third solder layer 33. For example, the third solder layer 33 may be copper solder, and the first solder layer 31 may be tin solder. The first and third solder layers 31, 33 can form an IMC layer with a Cu3Sn structure when welded together. The second solder layer 32 is, for example, chromium. The second and third solder layers 32, 33 simply fuse together when welded together, without forming an IMC. Therefore, in the soldered assembly 100, after the microelectronic device 10 and the binding substrate 21 are bonded together, the intermetallic compound (i.e., the IMC layer) formed between the first and third solder layers 31, 33 can increase bond strength, but also increase stress and brittleness. Therefore, the second solder layer 32 is selected to be a material capable of forming no IMC when welded together with the third solder layer 33, so that the second and third solder layers 32, 33 simply fuse together. The second solder layer 32 surrounds the first solder layer 31, thereby controlling the region where the IMC layer forms to the center of the soldered structure 30 and reducing stress at the edges. Therefore, this embodiment reduces stress intensity at the edges through different soldering mechanisms, maintaining stress between the materials within an acceptable range, preventing weld fractures caused by edge stress, and improving the weld strength of the soldered assembly. In some embodiments, the third solder layer 33 can be made of any one of gold (Au), tin (Sn), bismuth (Bi), copper (Cu), silver (Ag), indium (In), and platinum (Pt), or alloys thereof. The first solder layer 31 can be made of any one of gold, tin, bismuth, copper, silver, indium, and platinum, or alloys thereof. The second solder layer 32 can be made of any one of titanium (Ti), chromium (Cr), aluminum (Al), and molybdenum (Mo), or alloys thereof. It is sufficient that the first solder layer 31 and the third solder layer 33 can form an intermetallic compound upon welding, while the second solder layer 32 and the third solder layer 33 do not form an intermetallic compound upon welding.

[0055] In some embodiments, the first solder layer 31 protrudes from one side of the second solder layer 32. The third solder layer 33 forms a second groove 332 that matches the first solder layer 31. The first solder layer 31 can be interlocked with the second groove 332. Referring to Figures 4 and 5, taking the example of the third solder layer 33 being connected to the chip electrode 11 and the second solder layer 32 being connected to the substrate electrode 21, the first solder layer 31 has a first surface 311 proximal to the third solder layer 33, that is, the surface of the first solder layer 31 facing away from the substrate electrode 21 is the first surface 311. The second solder layer 32 has a second surface 321 proximal to the third solder layer 33, that is, the surface of the second solder layer 32 facing away from the substrate electrode 21 is the second surface 321. Conversely, if the third solder layer 33 is connected to the substrate electrode 21 and the second solder layer 32 is connected to the chip electrode 11, the surface of the first solder layer 31 facing away from the chip electrode 11 is the first surface 311, and the surface of the second solder layer 32 facing away from the chip electrode 11 is the second surface 321. The height difference ΔH between the first surface 311 and the second surface 321 ranges from 0.1 to 2.5 microns. The first solder layer 31 can be disposed on the side of the second solder layer 32 facing away from the substrate electrode 21. The thickness of the first solder layer 31, i.e., the height by which the first solder layer 31 protrudes from the second solder layer 32, is also the height difference ΔH between the first surface 311 and the second surface 321. Alternatively, in some embodiments, the first solder layer 31 can be directly connected to the substrate electrode 21. A hollow hole is formed in the middle of the second solder layer 32. The first solder layer 31 is disposed in the hollow hole so that the second solder layer 32 surrounds the first solder layer 31. In this case, the height of the first solder layer 31 protruding from the hollow hole is equal to the height difference ΔH between the first surface 311 and the second surface 321. The third solder layer 33 is formed with a second groove 332 recessed toward the chip electrode 11 (or toward the substrate electrode 21 if the third solder layer 33 is connected to the substrate electrode 21). This allows the portion of the first solder layer 31 protruding from the second solder layer 32 to be embedded in the second groove 332 when soldering the micro device 10 to the binding substrate 20. The IMC layer generated during soldering is also concentrated in the second groove 332, reducing edge stress. The depth of the second groove 332 corresponds to the height difference ΔH and ranges from 0.1 to 2.5 microns. The thickness of the second solder layer 32 ranges from 0.01 to 5 microns. The width of the first solder layer 31 may be 0.1 to 50 micrometers. The width of the first solder layer 31 is 0.1 to 0.8 of the width of the second solder layer 32 .

[0056] Because the electrodes of the Micro LED chip themselves form the recessed structure shown in FIG4 , when the microelectronic device 10 is a Micro LED chip, in the embodiment of FIG2 , the raised shape of the soldering structure 30 is formed on one side of the bonding substrate 20 . The recessed shape of the chip electrode 11 itself can be utilized to form a recessed third solder layer 33 to surround the protruding portion of the first solder layer 31 , thereby making the soldered assembly 100 thinner overall. It should be noted that although the recessed structures of the two chip electrodes 11 of the microelectronic device shown in FIG4 are identical, conventional Micro LED chips actually include an N electrode and a P electrode. The N electrode is electrically connected to the N-type semiconductor layer, and the P electrode is electrically connected to the P-type semiconductor layer. Therefore, when forming the N electrode, etching needs to be performed to the N-type semiconductor layer, and when forming the P electrode, etching needs to be performed to the P-type semiconductor layer. Therefore, the depths of the recessed structures formed by the two electrodes are actually different. This embodiment does not limit the recessed structures formed by the two chip electrodes 11 of the microelectronic device 10 to being identical or different.

[0057] In some embodiments, referring to Figures 6 to 8 , the second solder layer 32 protrudes from one side of the first solder layer 31 and surrounds the first solder layer 31 to form a first groove 34. The third solder layer 33 forms a protrusion 331 that matches the first solder layer 31. The protrusion 331 and the first groove 34 can interlock with each other. Figure 6 is a structural schematic diagram of the soldering state of the microelectronic device 10 and the bonding backplane 20 in the welding assembly 100, taking the third solder layer 33 connected to the chip electrode 11 and the second solder layer 32 connected to the substrate electrode 21 as an example. The microelectronic device 10 and the third solder layer 33 connected to the chip electrode 11 are combined to form the microelectronic component shown in Figure 7 , and the bonding backplane 20 and the second solder layer 32 and the first solder layer 31 connected to the substrate electrode 21 are combined to form the bonding backplane shown in Figure 8 . According to Figure 7 , the third solder layer 33 forms a protrusion 331 on the side facing away from the microelectronic device 10. If the third solder layer 33 is connected to the substrate electrode 21, a protrusion 331 is formed on the side of the third solder layer 33 facing away from the binding backplane 20. As shown in FIG8 , the first solder layer 31 is connected to the substrate electrode 21, and the second solder layer 32 is connected to the substrate electrode 21 and surrounds the first solder layer 31. The thickness of the second solder layer 32 is greater than that of the first solder layer 31. In this case, the surface of the first solder layer 31 facing away from the substrate electrode 21 is the first surface 311, and the surface of the second solder layer 32 facing away from the substrate electrode 21 is the second surface 321. Conversely, if the third solder layer 33 is connected to the substrate electrode 21, and the first solder layer 31 and the second solder layer 32 are connected to the chip electrode 11, the surface of the first solder layer 31 facing away from the chip electrode 11 is the first surface 311, and the surface of the second solder layer 32 facing away from the chip electrode 11 is 321. In the embodiment shown in Figure 8 , the height difference ΔH between the first surface 311 and the second surface 321 is the thickness difference between the second solder layer 32 and the first solder layer 31, and the range of height difference ΔH is 0.1 to 2.5 microns. The height range of the bump 331 protruding from the chip electrode 11 corresponds to the height difference ΔH, also 0.1 to 2.5 microns. When the microelectronic device 10 is soldered to the binding substrate 20, the location of the IMC layer can be controlled within the first groove 34, thereby reducing edge stress.

[0058] In some embodiments, the second solder layer 32 has a middle region 322 connected to the first solder layer 31 and a peripheral region 323 surrounding the middle region 322. Referring to the orientation shown in FIG5 , the first solder layer 31 is disposed on the second solder layer 32. The area of ​​the second solder layer 32 directly below the first solder layer 31 is the middle region 322, and the remaining area is the peripheral region 323. Alternatively, the middle region 322 and the orthographic projection of the first solder layer 31 onto the second solder layer 32 coincide. Of course, in the embodiment shown in FIG8 , the middle region 322 is a hollow structure. In some embodiments, the peripheral region 323 can be patterned to further reduce edge stress. Referring to FIG9 , which is a schematic top view of the binding backplane shown in FIG5 or FIG8 , FIG10 is a schematic diagram of a specific embodiment of FIG9 , in which the edge of the peripheral region 323 away from the middle region 322 has a first curved pattern. Referring to FIG10 , the edge of the peripheral region 323 forms an uneven, wavy pattern, which can reduce stress compared to a straight edge. FIG11 is a schematic diagram of another specific embodiment of FIG9 . Referring to FIG11 , a hollow gap 324 is formed in the peripheral region 323 , which acts as a buffer layer when the second solder layer 32 and the third solder layer 33 diffuse into each other during welding, reducing stress. FIG12 is a schematic diagram of a more specific embodiment of FIG11 , in which the hollow gap 324 has a second curved pattern. The hollow gap 324 forms an uneven, wavy curved pattern, which can further reduce edge stress and increase welding strength compared to a straight line. FIG13 is a schematic diagram of another specific embodiment of FIG9 , combining the features of FIG10 and FIG12 . The edge of the peripheral region 323 away from the middle region 322 is designed with an uneven pattern, and patterned hollow gaps 324 are also formed within the peripheral region 323 .

[0059] [Second embodiment]

[0060] A second embodiment of the present invention provides a semiconductor device 200 that can be soldered to an external device via an external solder layer. As shown in FIG14 , the semiconductor device 200 includes a substrate 40 having a pad layer 41 disposed thereon. A first solder layer 31 is disposed on the side of the pad layer 41 facing away from the substrate 40 and is used for soldering to the external solder layer. A second solder layer 32 is disposed on the side of the pad layer 41 facing away from the substrate 40. The second solder layer 32 surrounds the first solder layer 31 and is used for soldering to the external solder layer. The first solder layer 31 is made of a material that can produce intermetallic compounds when soldered to the external solder layer, while the second solder layer 32 is made of a material that does not produce intermetallic compounds when soldered to the external solder layer.

[0061] In this embodiment, the substrate 40 can be, for example, a microelectronic device such as a Micro LED chip, and the pad layer 41 is the chip electrode of the microelectronic device. In this case, the semiconductor device 200 is a microelectronic component with solder. For example, when the substrate 40 is a microelectronic device, the external device can be a binding substrate for driving the microelectronic device, and the external solder layer can be the solder on the binding substrate or another solder. The external device and the substrate 40 can be welded together by the external solder layer and the first solder layer 31 and the second solder layer 32 to achieve electrical connection. Or the substrate 40 can be, for example, a binding substrate for a Micro LED chip, and the pad layer 41 is the substrate electrode of the binding substrate. In this case, the semiconductor device 200 is a binding backplane with solder. In this case, the external device can be a microelectronic device that needs to be bound to the binding backplane. In this embodiment, two different solders, a first solder layer 31 and a second solder layer 32, are provided on the pad layer 41 of the semiconductor device 200. The first solder layer 31 forms an IMC layer during welding to enhance the bonding effect. The second solder layer 32 surrounds the first solder layer 31 and controls the area where the IMC layer can be generated to the middle position, thereby reducing edge stress. Therefore, this embodiment reduces the stress intensity at the edge through different welding mechanisms, and can maintain the stress between the materials within an acceptable numerical range, preventing the problem of weld fracture caused by edge stress, and improving the welding strength of the welded assembly. The first solder layer 31 can be made of any one of gold, tin, bismuth, copper, silver, indium and platinum, or an alloy of multiple materials. The second solder layer 32 can be made of any one of titanium (Ti), chromium (Cr), aluminum (Al) and molybdenum (Mo), or an alloy of multiple materials.

[0062] In some embodiments, as shown in FIG14 , the first solder layer 31 protrudes from the side of the second solder layer 32 facing away from the pad layer 41. In other embodiments, as shown in FIG15 , the second solder layer 32 protrudes from the side of the first solder layer 31 facing away from the pad layer 41, and the second solder layer 32 and the first solder layer 31 enclose a first groove 34. By designing the first and second solder layers 31 and 32 to have a protruding or grooved structure, the shape of the outer solder layer can be matched to achieve a mutually interlocking welding, which makes the welding more stable and ensures that the IMC layer is formed near the center of the pad layer 41, which is more conducive to reducing edge stress. The first solder layer 31 has a first surface 311 facing away from the pad layer 41, and the second solder layer 32 has a second surface 321 facing away from the pad layer 41. The height difference ΔH between the first surface 311 and the second surface 321 ranges from 0.1 to 2.5 microns. That is, the height of the first solder layer 31 protruding from the second solder layer 32 ranges from 0.1 to 2.5 microns, or the depth of the first groove 34 ranges from 0.1 to 2.5 microns. The thickness of the second solder layer 32 ranges from 0.01 to 5 microns. The width of the first solder layer 31 can be 0.1 to 50 microns. The width of the first solder layer 31 is 0.1 to 0.8 of the width of the second solder layer 32.

[0063] Referring to Figures 16 to 20, in some embodiments, the second solder layer 32 can be patterned. Figure 16 is a schematic top view of the semiconductor device 200 shown in Figures 14 and 15. Referring to Figures 14 to 16, the second solder layer 32 includes a middle region 322 connected to the first solder layer 31 and a peripheral region 323 surrounding the middle region 322. The middle region 322 coincides with the orthographic projection of the first solder layer 31 onto the second solder layer 32. Referring to Figure 17, in one embodiment, the edge of the peripheral region 323 distal from the middle region 322 has a first curved pattern. Referring to Figure 17, the edge of the peripheral region 323 forms an uneven, wavy curved pattern, which can reduce stress compared to a straight edge. Figure 18 is a schematic diagram of another embodiment of Figure 16. Referring to Figure 18, the peripheral region 323 is formed with a hollow gap 324, which acts as a buffer layer when the second solder layer 32 and the outer solder layer diffuse into each other during soldering, reducing stress. Figure 19 is a schematic diagram of a more specific embodiment of Figure 16 , in which the hollow gaps 324 have a second curved pattern. The hollow gaps 324 form an uneven, wavy pattern, which can further reduce edge stress and increase weld strength compared to a straight line. Figure 20 is a schematic diagram of another specific embodiment of Figure 16 , combining the features of Figures 17 and 19 . The edge of the peripheral region 323 away from the central region 322 is designed with an uneven pattern, and patterned hollow gaps 324 are also formed within the peripheral region 323 .

[0064] [Third embodiment]

[0065] A third embodiment of the present invention provides a display panel 300. Referring to FIG. 21 , the display panel 300 includes a soldering assembly 100 provided in any of the aforementioned embodiments, wherein the microelectronic device 10 is a micro-luminescent chip, and the binding substrate 20 is a driving substrate. The driving substrate is provided with a driving circuit 22 electrically connected to the substrate electrodes 21. Referring to FIG. 22 , in the display panel 300, the first solder layer 31 and the second solder layer 32 are both soldered to the third solder layer 33, electrically connecting the micro-luminescent chip to the driving circuit 22 on the driving substrate. The micro-luminescent chip can be controlled to emit light through the driving substrate, achieving a display effect. The display panel 300 using the soldering assembly 100 provided in the aforementioned embodiments has more stable welding, reduces edge stress, and is less prone to breakage.

[0066] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A welding assembly comprising: microelectronic devices with chip electrodes; a binding substrate having a substrate electrode; a third solder layer connected to the chip electrode and one of the substrate electrodes; a second solder layer connected to the other of the chip electrode and the substrate electrode and used for soldering with the third solder layer, wherein the second solder layer is made of a material that does not generate an intermetallic compound when soldered with the third solder layer; a first solder layer, used for soldering with the third solder layer, and the second solder layer surrounds the first solder layer; The first solder layer is made of a material that can be soldered with the third solder layer to generate an intermetallic compound.

2. The welding assembly according to claim 1, wherein The second solder layer protrudes from one side of the first solder layer and forms a first groove together with the first solder layer; the third solder layer forms a protrusion matching the first solder layer; The protrusion can be engaged with the first groove.

3. The welding assembly according to claim 1, wherein The first solder layer protrudes from one side of the second solder layer; the third solder layer forms a second groove matching the first solder layer; the first solder layer can be embedded in the second groove.

4. The welding assembly according to claim 2 or 3, wherein: The first solder layer has a first surface close to the third solder layer; the second solder layer has a second surface close to the third solder layer; and the height difference between the first surface and the second surface ranges from 0.1 to 2.5 microns.

5. The welding assembly according to claim 1, wherein The third solder layer is selected from any one material or alloy of multiple materials among gold, tin, bismuth, copper, silver, indium and platinum; the first solder layer is selected from any one material or alloy of multiple materials among gold, tin, bismuth, copper, silver, indium and platinum; the second solder layer is selected from any one material or alloy of multiple materials among titanium, chromium, aluminum and molybdenum.

6. The welding assembly of claim 1, wherein: The second solder layer has a middle area connected to the first solder layer and a peripheral area surrounding the middle area; an edge of the peripheral area away from the middle area has a first curved pattern.

7. The welding assembly of claim 1, wherein: The second solder layer has a middle area connected to the first solder layer and a peripheral area surrounding the middle area; the peripheral area is formed with a hollow gap.

8. The welding assembly of claim 7, wherein: The hollow gap has a second curved pattern.

9. A semiconductor device capable of being soldered to an external device via an external solder layer, the semiconductor device comprising: a substrate, wherein a pad layer is provided on the substrate; a first solder layer, disposed on a side of the pad layer facing away from the substrate, for soldering with the external solder layer; a second solder layer, disposed on a side of the pad layer facing away from the substrate; the second solder layer surrounds the first solder layer and is used for soldering with the outer solder layer; The first solder layer is a material that can be welded with the outer solder layer to produce an intermetallic compound; The second solder layer is made of a material that does not generate metal compounds when soldered with the outer solder layer.

10. The semiconductor device according to claim 9, wherein The first solder layer protrudes from a side of the second solder layer facing away from the pad layer.

11. The semiconductor device according to claim 9, wherein The second solder layer protrudes from a side of the first solder layer facing away from the pad layer and is surrounded by the first solder layer to form a first groove.

12. The semiconductor device according to claim 9, wherein The second solder layer has a middle area connected to the first solder layer and a peripheral area surrounding the middle area; an edge of the peripheral area away from the middle area has a first curved pattern.

13. The semiconductor device according to claim 9, wherein The second solder layer has a middle area connected to the first solder layer and a peripheral area surrounding the middle area; the peripheral area is formed with a hollow gap.

14. The semiconductor device according to claim 13, wherein The hollow gap has a second curved pattern.

15. A display panel, comprising the welding assembly according to any one of claims 1 to 8, wherein the microelectronic device is a micro-light-emitting chip; the binding substrate is a driving substrate, and a driving circuit electrically connected to the substrate electrodes is provided on the driving substrate; the first solder layer and the second solder layer are both welded to the third solder layer.

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