High-precision voltage signal isolation conditioning circuit array based on ISO (International Standard Organization)-124P chip

Abstract

The invention provides a high-precision voltage signal isolation conditioning circuit array based on an ISO (International Standard Organization)-124P chip, which comprises a mother board and a plurality of daughter boards, the daughter boards and the mother board are connected through inter-board connectors, and the plurality of mother boards can be superposed and combined. The daughter board takes an ISO124P chip circuit as a preceding-stage signal input isolation, a backward-stage signal zero compensation circuit, a filter circuit and a gain adjustment circuit are designed, the mother board is provided with an inter-board connector, a signal input / output end connector and an isolation power supply input end connector, and after the daughter board is loaded, each mother board has a multi-channel two-side isolation function and a multi-channel three-side isolation function. The high linearity, high isolation voltage and low ripple output of product test analog signal isolation are achieved, the multi-channel and low-cost design is achieved, and the high practicability and market popularization value are achieved.

Description

Technical Field

[0001] The invention belongs to the field of measurement circuit design, and in particular relates to a high-precision voltage signal isolation and conditioning circuit array based on an ISO-124P isolation chip. Background Art

[0002] During the servo product testing process, the signal conditioning process often requires amplification of the signal in order to avoid mutual interference between signals. At the same time, there is a potential difference between the control circuit of the product under test and the test system. Failure of the test equipment may cause damage to the product. In order to ensure the safety between the product under test and the test equipment and improve the common mode rejection ratio, it is often necessary to use an isolation circuit to completely isolate the two electrically.

[0003] With the continuous application of aerospace electromechanical servo products, various performance tests require that the analog output signal at the product end be electrically isolated from the acquisition end of the test system at two ends or three ends.

[0004] Traditional analog signal isolation and conversion generally adopts transformer isolation, photoelectric isolation and capacitive coupling isolation. For example, the AD202 / 203 / 204 / 208 series transformer-coupled isolation chips of AD Company have the main advantages of high isolation voltage and high precision, but their obvious disadvantages are large size, limited bandwidth, high price, and the cost of a single channel exceeds 2,000 yuan; the advantage of photoelectric isolation is that it can achieve high voltage isolation and fast transmission speed, but the disadvantage is high cost, the cost of good performance is higher, and it is greatly affected by temperature and needs to be used within a certain temperature range; capacitor-coupled isolation chips are small in size, convenient in wiring, cheap in price, and can transmit signals well, such as BB Company's ISO100 / 102 / 120 / 122 / 124 series of capacitor-coupled transmission isolation amplifiers, which amplify the input signal through the preamplifier, modulate it through the internal modulator, couple it to the output side through the capacitor, and finally drive the output after demodulation by the demodulator. Its main features are small size, convenient wiring, and low cost, but due to the use of modulation and demodulation technology in the signal transmission process, the output signal ripple is large, and the peak-to-peak value can exceed 20mV, which is subject to certain restrictions in the application occasions where high precision and low ripple are required in servo system testing. Summary of the invention

[0005] The purpose of the present invention is to provide a high-precision voltage signal isolation conditioning circuit array based on ISO-124P isolation chip. The daughter board and the mother board are connected through the inter-board connector. The daughter board uses the ISO-124P chip circuit as the front-stage signal input isolation, and designs the rear-stage signal zero point compensation circuit, filter circuit and gain adjustment circuit. The mother board is provided with an inter-board connector, a signal input / output terminal connector and an isolation power input terminal connector. After the daughter board is loaded, each mother board has multi-channel two-way isolation and three-way isolation functions, and realizes high linearity, high isolation voltage and low ripple output of product test analog signal isolation, realizes multi-channel, low-cost design, and has high practicality and market promotion value.

[0006] A single isolation motherboard is provided with multiple quick-release inter-board rectangular connectors, multiple signal input / output inter-board rectangular connectors and multiple isolated power input cold-pressed rectangular connectors, and the signal input, output and power supply connections are realized through PCB board routing.

[0007] The design principle of ISO-124P isolation daughter board circuit: by configuring the input positive power supply VCC1, negative power supply VEE1, power supply ground GND1 and output positive power supply VCC2, negative power supply VEE2, power supply ground GND2, the front-stage input signal VIN1 is isolated by U1 chip ISO-124P and then output VOUT2, capacitors C4 and C5 are used for VCC1 and VEE1 power supply filtering, capacitors C2 and C3 are used for VCC2 and VEE2 power supply filtering, and the input end U3 slide switch is used for input end zero adjustment and grounding. The post-stage buffer circuit mainly composed of U4 op amp OP07CSZ solves the problems of zero drift, range control, and signal filtering.

[0008] The beneficial effects of the present invention are as follows:

[0009] The high-precision voltage signal isolation conditioning circuit array based on the ISO-124P chip provided by the present invention has high linearity and isolation voltage, low zero drift and output ripple, and can be widely used in industrial control and measurement occasions with low signal frequency and need for electrical isolation, such as temperature control and pressure control in industrial control, and is also used in motor control, power system monitoring, computer data acquisition system, microprocessor embedded equipment, etc., with high practicality and market promotion value.

[0010] The application of the isolation board circuit array based on ISO124P isolation amplifier chip can be gradually promoted in the field of ground test equipment for aerospace electrical products, and can also be delivered to external users. It has strong scalability, high reliability, good market application prospects, can effectively improve the level of automated testing of equipment delivered to users, and has high social and economic value. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is the ISO-124P isolation board array system framework diagram;

[0012] Figure 2 This is the schematic diagram of the ISO-124P isolation chip principle;

[0013] Figure 3 This is the internal structure diagram of the ISO-124P isolation chip;

[0014] Figure 4 This is the circuit schematic diagram of the ISO-124P isolation daughter board;

[0015] Figure 5 This is the circuit schematic diagram of the ISO-124P isolation motherboard;

[0016] Figure 6 It is the PCB component side of the ISO-124P isolation daughter board;

[0017] Figure 7 It is the bottom surface of the ISO-124P isolation daughter board PCB;

[0018] Figure 8 It is the ISO-124P isolation motherboard PCB component side;

[0019] Fig. 9 It is the bottom surface of the ISO-124P isolation motherboard PCB. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0021] The present invention designs an isolation board circuit array based on the ISO124P isolation amplifier chip (capacitive coupling), which is connected in the form of a daughter board and a mother board through an inter-board connector. The daughter board uses the ISO124P chip circuit as a front-stage signal input isolation, and designs a post-stage signal zero-point compensation circuit, a filter circuit and a gain adjustment circuit. Preferably, the motherboard is provided with 16 inter-board connectors, 4 signal input / output connectors and 2 isolated power input connectors. After the daughter board is loaded, each motherboard has 16-channel two-way isolation and 8-channel three-way isolation functions. The isolation board array system framework diagram is shown in the figure below. Figure 1 shown.

[0022] (1) A motherboard can be connected to 16 isolated daughter boards through the inter-board connector, where the isolated daughter boards 1-8 are the first group and 9-16 are the second group. The first group transmits isolated signals through the input 1 terminal and the output 1 terminal, and completes the input power supply and output power supply of all 8 isolated daughter boards through the power input terminals 1 and 2; the second group is similar, such as Figure 3 shown.

[0023] (2) When two-way signal isolation is required, power supply 1 and power supply 3 can be set as the same power supply through an external multi-channel isolated power output, and the power ground can be shared with the input 1 and input 2 signal terminals; at the same time, power supply 3 and power supply 4 can be set as another group of power supplies, and the power ground can be shared with the output 1 and output 2 signal terminals. In this way, the isolation function of the input signal and the output signal is realized. Each motherboard can provide 16 isolation channels after the daughterboard is loaded.

[0024] (3) When three-way signal isolation is required, the input signal can be distributed in parallel to the input 1 and input 2 terminals. The power supply 1 and power supply 2 can be set to the same power supply through the external multi-channel isolated power output, and the power supply ground is shared with the input 1 and input 2 signal terminals; at the same time, the power supply 3 can be set as the second group of power supplies, and the power supply ground is shared with the output 1 signal terminal; the power supply 4 can be set as the third group of power supplies, and the power supply ground is shared with the output 2 signal terminal; in this way, the three-way isolation function of the input signal, the output 1 signal, and the output 2 signal can be realized. In this case, each motherboard can provide 8 isolation channels after the daughterboard is loaded.

[0025] (4) When more isolation channels are required, such as Figure 1 , multiple motherboards can be stacked and combined to achieve an increase in the number of channels to 16, 32, 48, 64, etc.

[0026] ISO-124P chip:

[0027] The ISO-124P chip is a capacitively coupled isolation amplifier. Its principle diagram is as follows Figure 2 , the internal structure of the chip is shown in Figure 3 shown.

[0028] The pins include: signal input VIN, input positive power supply +VS1, negative power supply -VS1, input ground Gnd1; signal output VOUT, output positive power supply +VS2, negative power supply -VS2, input ground Gnd2.

[0029] The internal structure of ISO-124P chip is as follows Figure 3It is mainly composed of constant current source, integrator, comparator, capacitive isolation barrier and sample-and-hold circuits. ISO-124P uses duty cycle modulation / demodulation technology to achieve signal isolation. The signal across the 2pF (2 1pF) differential capacitive isolation barrier is transmitted in a digital way. With the help of digital modulation, the characteristics of the isolation barrier will not affect the quality of the signal, ensuring the reliability and frequency response of signal transmission.

[0030] ISO-124P Isolation Daughter Board:

[0031] The schematic diagram of the ISO-124P isolation daughter board circuit design is as follows Figure 4 .

[0032] ISO-124P isolation daughter board circuit design principle:

[0033] By configuring the input positive power supply VCC1, negative power supply VEE1, power supply ground GND1 and the output positive power supply VCC2, negative power supply VEE2, power supply ground GND2, the front-stage input signal VIN1 is isolated by the U1 chip ISO-124P and then output VOUT2. Capacitors C4 and C5 are used for VCC1 and VEE1 power supply filtering, capacitors C2 and C3 are used for VCC2 and VEE2 power supply filtering, and the input end U3 slide switch is used for input zeroing and grounding. The post-stage buffer circuit mainly composed of U4 op amp OP07CSZ solves the following three problems:

[0034] ①Zero drift problem:

[0035] There are two aspects. On the one hand, the U4 op amp itself has an offset voltage. For AD's OP07CSZ, under the condition of 25℃ power supply voltage VS=±15V, the VO range is within 30~75μV. U4 itself has a zero adjustment terminal. When the common terminal 2 of the U2 and U5 slide switches are both turned to 3-point grounding, adjust the R10 potentiometer to reduce the impact of the zero-position bias voltage. On the other hand, the U1 chip ISO-124P has a zero-position bias voltage. When the input signal is zero, the VOUT2 output is approximately ±20mV~30mV, and some even reach ±(50mV~60mV), which cannot meet user needs in some applications. Therefore, a zero-point compensation circuit is designed. Figure 4 The components of the circuit are R8, R9, U6, U7, R5, R6, and R7. U6 and U7 are three-terminal precision reference voltage regulator circuits TL431, whose reference voltage is 2.5V. Figure 4 The series connection of U6 and U7 makes Ua=2.5V and Ub=-2.5V. After voltage division by R5, R6 and R7, when the slide switch of U5 is turned on, a reverse bias voltage is provided to the U4 op amp through the resistor R3. The zero drift of ISO-124P can be compensated by adjusting the potentiometer R7.

[0036] ②Range control:

[0037] Theoretically, the gain of the ISO-124P chip is 1.0, but the actual product gain has a slight error. To accurately control the gain, corresponding control measures must be adopted. Figure 4 The U5 slide switch in the circuit is turned to the ground position. Zero point compensation is not considered at this time. The relationship between the output VOUT2 of the U1 chip ISO-124P and the output VOUT1 after amplification by U4 is as follows:

[0038] VOUT1=VOUT2×(R1 / (R1+R2))×((R3+R4) / R3)......(1)

[0039] When the resistance values ​​of R1, R2, R3, and R4 are set in a certain ratio, VOUT1=(0.99-1.01)VOUT2 can be guaranteed. Therefore, by changing the size of the R1 potentiometer, the overall gain of the isolation circuit can be fine-tuned.

[0040] ③Signal filtering:

[0041] According to the working principle of ISO-124P chip, there is a 500KHz switch type constant current source inside it. In the process of modulating / demodulating the input signal, there will inevitably be 500KHz noise. Therefore, it is necessary to filter at the output end. The present invention uses a low-pass filter composed of RC circuit to filter out high-frequency interference. By reasonably configuring Figure 4 The size of the R1 potentiometer and C1 capacitor can meet the user's signal operating frequency band requirements.

[0042] ISO-124P isolation daughter board circuit calculation process:

[0043] ①Zero drift calculation:

[0044] When switch 2 of U3 is turned to the 3 signal ground terminal, switch 2 of U2 is turned to the 1VOUT2 output terminal, and switch 2 of U52 is turned to the 1 signal zero adjustment terminal, the zero drift calculation is performed in this case. Assuming that the zero voltage output by ISO-124P is VOUT2', and the zero adjustment output voltage on the R7 potentiometer is Vr7, then:

[0045] V+=VOUT2'×R2 / (R1+R2)................................(2)

[0046] V-=(VOUT1-Vr7)×R3 / (R3+R4)................................(3)

[0047] Where: V+ is the positive input voltage of U4 operational amplifier,

[0048] V- is the reverse input voltage of U4.

[0049] Since: V+=V-, from formulas (2) and (3)

[0050] (VOUT1-Vr7)×R3 / (R3+R4) / (R3+R4)=VOUT2'×R2 / (R1+R2).....(4)

[0051] When the resistance values ​​are configured so that R3 / (R3+R4)=R2 / (R1+R2)=R, the circuit of the present invention selects: R1=20KΩ potentiometer, R2=R3=1MΩ, and R4=10KΩ.

[0052] VOUT1=(Vr7+VOUT2')×R........................(5)

[0053] According to formula (5), in order to satisfy the isolation circuit output VOUT1 = 0 when zero signal is input, Vr7 = -VOUT2'. By adjusting the R7 potentiometer to output a bias voltage with the same absolute value as the VOUT2' voltage and opposite direction, the output can be zero.

[0054] ②Filter calculation:

[0055] The signal bandwidth index of the present invention is not less than 20KHz, without considering the influence of R2 on low-pass filtering. The signal output and output ratio β are:

[0056]

[0057] When β≈1, formula (6) can be equivalent to:

[0058] β=Vc / VOUT2≈Xc / (R1+Xc).............(7)

[0059]

[0060] In the above formula: Xc is the capacitive reactance, ω is the angular frequency, and f is the signal frequency.

[0061] According to the required β value and signal frequency f, the value of filter capacitor C1 can be calculated. When f=20KHz in the index of the present invention, take R1 as the middle position 10KΩ, β=0.999, then C1=80pF can be calculated.

[0062] ISO-124P isolation daughter board circuit adjustment method:

[0063] ①Zero point adjustment

[0064] U4 operational amplifier zero adjustment

[0065] Connect switches U2 and U5 to ground, connect the output positive power supply VCC2, negative power supply VEE2, and power ground GND2, use the "mV" range of the DC voltmeter to monitor the output voltage VOUT1 of the U4 operational amplifier, and adjust potentiometer R10 to make its output voltage VOUT1 zero.

[0066] U1 chip ISO-124P zero point adjustment:

[0067] Connect switch U3's 2 to 3 to ground, and switches U2 and U5's 2 to 1, to connect the input positive power supply +VS1, negative power supply -VS1, and input ground Gnd1; the output positive power supply +VS2, negative power supply -VS2, and input ground Gnd2; use the "mV" range of the DC voltmeter to monitor the VOUT1 output, and adjust the potentiometer R7 so ​​that the output voltage VOUT1 is zero.

[0068] ②Range adjustment

[0069] Connect switch U3's 2 to 1 to VIN1, and switch U2 and U5's 2 to 1, add 10V DC voltage to the input terminal VIN1, use the "V" position of the DC voltmeter to monitor the output voltage of VOUT1, and adjust the potentiometer R1 to make the output voltage VOUT1 10V; then reduce the input voltage of VIN1 to 9V, 8V... 1V, -1V... -10V in sequence, observe and record the changes in the output voltage VOUT1, and use the least squares method to calculate the linearity of the isolation channel.

[0070] ③Bandwidth test

[0071] Connect a sine wave signal of a specified frequency to the input terminal VIN1, use an oscilloscope to simultaneously collect the voltage values ​​of the input VIN1 and the output VOUT1, and observe the attenuation of the output signal amplitude.

[0072] ISO-124P Isolation Motherboard:

[0073] The schematic diagram of ISO-124P isolation motherboard circuit design is as follows Figure 5 .

[0074] ISO-124P isolation motherboard circuit principle:

[0075] A single isolation motherboard is equipped with 16 CRM222-010-211-2900 quick-release inter-board rectangular connectors, 4 signal input / output CRM222-020-211-2900 inter-board rectangular connectors and 2 isolated power input MCV1.5 / 12-GF-3.5 cold-pressed rectangular connectors. Signal input, output and power supply connections are achieved through PCB routing.

[0076] ISO-124P Isolation Sub-Board PCB Diagram as shown below: Component surface diagram and bottom diagram as shown below: Figure 6 , 7.

[0077] ISO-124P isolation motherboard PCB diagram as shown below: Component surface diagram and bottom surface diagram as shown below: Figure 8 , 9.

[0078] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip, characterized in that: It includes multiple motherboards and multiple daughterboards. Each motherboard is connected to multiple daughterboards through inter-board connectors. The isolation daughterboard uses the ISO-124P chip circuit as a front-stage signal input isolation circuit. The motherboard is provided with an inter-board connector, a signal input / output terminal connector and an isolated power input terminal connector. After the daughterboards are loaded, each motherboard has multi-channel two-way isolation and three-way isolation functions.

2. According to claim 1, a high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip, characterized in that: The isolation sub-board also includes a post-stage signal zero-point compensation circuit, a filtering circuit and a gain adjustment circuit.

3. The high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip according to claim 1, characterized in that: A single motherboard is equipped with 16 quick-release inter-board rectangular connectors, 4 signal input / output inter-board rectangular connectors and 2 isolated power input cold-pressed rectangular connectors, and the signal input, output and power supply connections are realized through PCB board routing.

4. The high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip according to claim 3 is characterized in that: The model of the quick-release inter-board rectangular connector is CRM222-010-211-2900, the model of the inter-board rectangular connector is CRM222-020-211-2900, and the model of the cold-pressed rectangular connector is MCV1.5 / 12-GF-3.

5.

5. The high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip according to claim 1, characterized in that: By setting up external multi-channel isolated power output and distributing input signals, the signal isolation function of input signals and output signals can be realized. At this time, each motherboard can provide 16 isolation channels after loading the daughter board.

6. The high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip according to claim 1, characterized in that: By setting up external multi-channel isolated power output and distributing input signals, the three-way signal isolation function of input signals and output signals is realized. At this time, each motherboard can provide 8 isolation channels after loading the daughter board.

7. The high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip according to claim 1, characterized in that: When multiple motherboards are stacked and combined, 16, 32, 48, 64...16n isolation channels can be realized, where n is a positive integer.

8. The high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip according to claim 1, characterized in that: The design principle of the isolation daughter board circuit is as follows: by configuring the input positive power supply VCC1, negative power supply VEE1, power ground GND1 and the output positive power supply VCC2, negative power supply VEE2, power ground GND2, the front-stage input signal VIN1 is isolated by the U1 chip ISO-124P and then output VOUT2. Capacitors C4 and C5 are used for VCC1 and VEE1 power supply filtering, capacitors C2 and C3 are used for VCC2 and VEE2 power supply filtering, the input end U3 sliding switch is used to adjust the input end to zero and ground, and the U4 operational amplifier OP07CSZ is mainly used to form the post-stage buffer circuit.

9. The high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip according to claim 8, characterized in that: The isolation daughter board circuit can perform zero adjustment, span adjustment and bandwidth testing.

10. The high-precision voltage signal isolation and conditioning circuit array based on ISO-124P chip according to claim 9, characterized in that: The zero point adjustment includes U4 operational amplifier zero point adjustment and U1 chip ISO-124P zero point adjustment.

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