Relay protection test processing method and device, electronic equipment and storage medium

Abstract

The invention discloses a relay protection test processing method and device, electronic equipment and a storage medium, and the method comprises the steps that a central processing unit sends configuration parameters to a field programmable gate array through a fast channel interface, and the field programmable gate array carries out clock synchronization according to the configuration parameters; after it is detected that clock synchronization is completed, receiving a power system message through the field programmable gate array, and writing the power system message into a dynamic random access memory; and the central processing unit reads the power system message from the dynamic random access memory, determines a to-be-transmitted data stream according to the power system message, and sends the to-be-transmitted data stream through the field programmable gate array. Based on the technical scheme, accurate processing and seamless switching of the digital-analog mixed signals are achieved, accurate synchronous control of the digital-analog signals is achieved, and the consistency of digital quantity output and analog quantity output is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of electric power technology, and in particular to a processing method, device, electronic equipment and storage medium for relay protection testing. Background Art

[0002] The relay protection tester is an instrument used to detect and verify relay protection devices. It plays a vital role in the power system and is used to ensure the safe and reliable operation of the power system. The relay protection tester tests and evaluates the relay protection device by simulating various signals and fault conditions in the power system. It can simulate the current, voltage and other parameters in the power system to generate various fault conditions and test scenarios.

[0003] However, traditional relay protection instruments mostly use imported chip solutions, are overly dependent on imported chips, and cannot adapt to the harsh on-site environment in actual power system application scenarios. Summary of the invention

[0004] The present invention provides a processing method, device, electronic equipment and storage medium for relay protection test, so as to realize accurate processing and seamless switching of digital-analog mixed signals, realize accurate synchronous control of digital-analog signals, and ensure the consistency of digital and analog outputs.

[0005] According to one aspect of the present invention, a method for processing a relay protection test is provided, which comprises:

[0006] The central processor sends configuration parameters to the field programmable gate array through the fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters;

[0007] After detecting that the clock synchronization is completed, receiving a power system message through the field programmable gate array, and writing the power system message into a dynamic random access memory;

[0008] The central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array.

[0009] According to another aspect of the present invention, there is provided a processing device for relay protection test, comprising:

[0010] A synchronization test module, wherein the central processor sends configuration parameters to the field programmable gate array through a fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters;

[0011] A message receiving module, configured to receive a power system message through the field programmable gate array after detecting that the clock synchronization is completed, and write the power system message into a dynamic random access memory;

[0012] The data sending module, the central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array.

[0013] According to another aspect of the present invention, there is provided an electronic device, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the processing method for relay protection testing described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the processing method for relay protection test described in any embodiment of the present invention when executed.

[0018] The technical solution of the embodiment of the present invention is to send configuration parameters to the field programmable gate array through the fast channel interface by the central processing unit, and the field programmable gate array performs clock synchronization according to the configuration parameters, and after detecting that the clock synchronization is completed, the field programmable gate array receives the power system message and writes the power system message into the dynamic random access memory, and then the central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array. Based on the above technical solution, accurate processing and seamless switching of mixed digital and analog signals are realized, and accurate synchronous control of digital and analog signals is realized, ensuring the consistency of digital and analog output.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flow chart of a processing method for relay protection test provided according to Embodiment 1 of the present invention;

[0022] Figure 2 is a schematic diagram of message reception provided according to Embodiment 1 of the present invention;

[0023] Figure 3 is a schematic diagram of data transmission provided according to Embodiment 1 of the present invention;

[0024] Figure 4 This is a field programmable gate array internal timing synchronization design diagram provided according to the first embodiment of the present invention;

[0025] Figure 5 is a structural schematic diagram of a processing device for relay protection test provided according to Embodiment 2 of the present invention;

[0026] Figure 6 It is a schematic diagram of the structure of an electronic device provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] Embodiment 1

[0030] Figure 1 A flowchart of a method for processing a relay protection test is provided for the first embodiment of the present invention. This embodiment is applicable to the case where a central processing unit and a field programmable gate array provided in a relay tester are used to process system messages and output data streams. The method can be executed by a processing device for a relay protection test. The processing device for a relay protection test can be implemented in the form of hardware and / or software. The processing device for a relay protection test can be configured in an electronic device. Figure 1 As shown, the method includes:

[0031] S110. The central processing unit sends configuration parameters to the field programmable gate array through the fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters.

[0032] The central processing unit can be understood as a computing and control core arranged in the relay tester, which is responsible for reading instructions, decoding instructions and executing instructions. The fast channel interface can be a high-speed serial computer expansion bus standard. The configuration parameters can be parameters for instructing the field programmable gate array to perform clock synchronization, and can include parameters such as clock frequency and count start value. The field programmable gate array is an SRAM field programmable gate array based on the FMSH-K7 series.

[0033] Specifically, the central processing unit sends configuration parameters to the field programmable gate array through the fast channel interface. The configuration parameters may include clock frequency, phase adjustment, data format, etc., which are used to guide the field programmable gate array to perform clock synchronization and other related operations. After the field programmable gate array receives the configuration parameters sent by the central processing unit through the fast channel interface, it performs clock synchronization according to the parameters. It should be noted that clock synchronization is the key to ensuring the coordinated work between various modules inside the field programmable gate array and between the field programmable gate array and other system components. Exemplarily, the field programmable gate array first receives the configuration parameters sent by the central processing unit through the fast channel interface, and the field programmable gate array parses the received configuration parameters to extract the key information required for clock synchronization. Then, according to the parsed configuration parameters, the field programmable gate array adjusts the frequency, phase, etc. of its internal clock to achieve clock synchronization with other system components. Exemplarily, the CPU sends parameters through PCIE, the FPGA parses the parameters, and then sets the clock source according to the parameters, adjusts the count according to the clock source, and then outputs the synchronization signal according to the clock source.

[0034] It should be noted that the relay tester in the embodiment of the present invention can be a main control core board unit composed of ARM+FPGA. ARM adopts the advanced domestic MPU manufacturer Rockchip-RK3568. RK3568 is a general-purpose SoC positioned in the middle and high end produced by Rockchip. It adopts 22nm advanced process technology, integrates 4-core arm architecture A55 processor and Mali G522EE graphics processor, and supports 4K decoding and 1080P encoding. RK3568 supports various types of peripheral interfaces such as SATA / PCIE / USB3.0. RK3568 is mainly responsible for human-machine interface, real-time algorithm, and message processing. The high-speed pcie interface provides real-time communication. FPGA is mainly responsible for protocol conversion, outputs ARM calculation results to the power amplifier through digital-to-analog conversion DAC, and outputs the calculation results in the form of messages, strictly ensuring the synchronous output of analog and digital quantities. High-precision voltage and current output, low-jitter message transmission and reception are achieved to meet the quantity increase requirements of various protection devices. Provides a rich external interface to interact with other devices. A variety of timing methods are suitable for the test requirements of multi-machine synchronization in multiple occasions. According to the requirements of relay protection test for high precision and wide bandwidth, domestic chips with 24-bit high-precision ADC and DAC are selected as core devices. The digital signal sampled by ADC is filtered and corrected through FPGA to further improve the signal-to-noise ratio and dynamic range of the sampled signal. According to different ADC characteristics and noise environments, FPGA is used to implement adaptive filtering algorithms and dynamically adjust filter parameters to achieve the best filtering effect.

[0035] S120. After detecting that the clock synchronization is completed, receiving a power system message through the field programmable gate array, and writing the power system message into a dynamic random access memory.

[0036] The power system message can be understood as a message generated during the power system fault simulation, such as FT3, SMV, GOOSE message, etc. The dynamic random access memory can be an internal memory provided in the relay tester that can directly exchange data with the central processing unit, such as a dynamic random access memory of DDR3 specification.

[0037] Specifically, the field programmable gate array first confirms that the clock synchronization has been successfully completed. It can confirm whether the clock synchronization is completed by checking the synchronization signal, phase difference or timestamp, etc., to ensure that all related components are running in the same clock domain, and then the clock synchronization is completed. After confirming that the clock synchronization is completed, the field programmable gate array is ready to receive messages from the power system. Before receiving the message, the receiving buffer can be configured, and the interrupt or polling mechanism can be set to detect the newly arrived message. The field programmable gate array receives the message from the power system through its interface, such as Ethernet interface, serial communication interface, etc. The message can contain various types of data, such as measurement values, status information, control instructions, etc. Before writing the message into the dynamic random access memory, the field programmable gate array may need to initialize or configure the dynamic random access memory first. This includes setting the working mode, refresh rate and other parameters of the dynamic random access memory. The field programmable gate array writes the verified power system message into the dynamic random access memory.

[0038] On the basis of the above technical solution, after receiving the power system message through the field programmable gate array, it also includes: the field programmable gate array adds message identification information to the header of the power system message.

[0039] The message identification information includes at least one of a time stamp, a frame count value, a channel, a rate, and a type.

[0040] Specifically, the field programmable gate array receives FT3, SMV, GOOSE and other messages, and adds time stamp, frame count value, channel, rate, type and other information to the message header to ensure the accuracy and integrity of the message.

[0041] On the basis of the above technical solution, the writing of the power system message into the dynamic random access memory includes: storing the power system message into the primary cache based on the field programmable gate array, and sending a trigger signal to the state machine after the storage is completed; the state machine writes the power system message into the dynamic random access memory according to the trigger signal.

[0042] The primary cache can be understood as a temporary storage area for message data.

[0043] Specifically, when the field programmable gate array receives a power system message, it first temporarily stores the message data in the internal primary cache (such as FIFO, dual-port RAM, etc.). The primary cache is used as a data temporary storage area to quickly receive and temporarily store message data, providing a buffer for subsequent processing. When the message data is completely stored in the primary cache, the field programmable gate array will send a trigger signal to the state machine. The trigger signal is a flag used to notify the state machine that there is new message data that needs to be further processed and written to DRAM. After receiving the trigger signal sent by the field programmable gate array, the state machine will enter the corresponding processing state. The state machine is a key component for controlling data flow and state transitions. It can determine the next operation based on the trigger signal and the current system state. Under the control of the state machine, the field programmable gate array begins to read message data from the primary cache and writes this data to DRAM through the DRAM interface.

[0044] On the basis of the above technical solution, the state machine writes the power system message into the dynamic random access memory according to the trigger signal, including: after receiving the trigger signal, the state machine determines the storage status of the secondary cache, and when the storage status is idle, transfers the power system message to the secondary cache; writes the power system message into the dynamic random access memory through the secondary cache.

[0045] Specifically, after receiving the trigger signal, the state machine checks the storage status of the secondary cache to ensure that the secondary cache has enough space to store the message data before transferring the data to the secondary cache to avoid data overflow or overwriting. If the storage status of the secondary cache is free, that is, there is enough space to store new message data, the state machine will instruct the field programmable gate array to transfer the power system message from the primary cache to the secondary cache. By temporarily storing data in the secondary cache, message data can be further buffered and data access conflicts when writing directly to DRAM can be reduced. If the storage status of the secondary cache is non-free, that is, the space is insufficient or occupied, the state machine needs to take corresponding processing measures, including waiting for the secondary cache to release space, overwriting old data (according to the importance of the data and the update strategy), or reporting an error to the system and requesting further instructions. When the power system message is successfully transferred to the secondary cache, the state machine will coordinate the data transmission between the secondary cache and DRAM, that is, the state machine will instruct the secondary cache to write the message data into DRAM. When the message data is successfully written to DRAM, the state machine will update the system status and send a write completion signal to the field programmable gate array. At the same time, the state machine will also update the storage status information of the secondary cache to process subsequent message data.

[0046] For example, Figure 2As shown in the figure, after receiving FT3, SMV, GOOSE messages, etc., a time stamp and frame count value, channel, rate, type and other information are added to the header of the message and stored in the primary RAM. After storing a burst of information, the RAM of each channel initiates a trigger signal to inform that data has arrived. Then the state machine determines whether the current secondary RAM currently has RAM storage operations on other channels. If so, the other channels wait. After the secondary RAM has data, it initiates the write data information to DDR3, notifies the CPU that there is data after writing, and waits for the CPU to fetch the data.

[0047] S130, the central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array.

[0048] The data stream to be transmitted can be understood as the data to be sent generated after the central processing unit processes the message.

[0049] Specifically, the central processor first sends a read request to the DRAM through the address bus according to the storage address of the power system message in the DRAM. After receiving the read request, the DRAM locates the corresponding storage unit according to the address information provided by the address line, and transmits the stored power system message data to the central processor through the data bus. Then, after the central processor receives the power system message data transmitted from the DRAM, it stores it in the internal register or cache. The central processor parses and processes the received power system message to extract key information, such as the format, content, and destination of the data packet. The central processor determines the data stream to be transmitted according to the content and analysis results of the power system message, including filtering out specific measurement data, status information, control instructions, etc. It should be noted that the central processor can also format, encode or encrypt the data according to the current state of the system and the requirements of the communication protocol. The central processor transmits the processed data stream to be transmitted to the field programmable gate array through the internal bus. After the field programmable gate array receives the data stream to be transmitted transmitted by the central processor, it sends these data streams to the target receiver through an external interface (such as an Ethernet interface, a serial communication interface, etc.) according to the pre-configured transmission strategy and data forwarding rules.

[0050] On the basis of the above technical solution, the central processing unit reads the power system message from the dynamic random access memory, including: the field programmable gate array sends the data reading instruction to the central processing unit when detecting that the power system message exists in the dynamic random access memory; the central processing unit responds to the data reading instruction and reads the power system message from the dynamic random access memory.

[0051] Specifically, the field programmable gate array continuously monitors the access status and data storage status of the DRAM. The field programmable gate array checks the data flag of the specific address area in the DRAM to determine whether the power system message has been stored in the DRAM. When the field programmable gate array detects that there is a power system message in the DRAM, it will generate a data read instruction, which contains the storage address of the message in the DRAM, the read length and other necessary information. The field programmable gate array sends the generated data read instruction to the central processor through the internal communication bus or other interface. After the central processor receives the data read instruction sent by the field programmable gate array, it decodes and processes the instruction to obtain the storage location and read requirements of the message in the DRAM. According to the data read instruction, the central processor sends a read request to the DRAM through the address bus and specifies the address range to be read. The RAM responds to the read request of the central processor and transmits the stored power system message data to the central processor through the data bus. The central processor receives this data and stores it in an internal register or cache.

[0052] On the basis of the above technical solution, the sending of the data stream to be transmitted through the field programmable gate array includes: the field programmable gate array divides the data stream to be transmitted according to the transmission configuration information, and stores the divided data stream to be transmitted in a cache; the field programmable gate array reads the data stream to be transmitted from the cache according to the internal timing and at the agreed time and outputs it.

[0053] Specifically, according to the transmission configuration information, the field programmable gate array divides the data stream to be transmitted into multiple smaller data blocks or data packets, and then writes the divided data packets into a cache in sequence, waiting for subsequent reading and output, and then the field programmable gate array reads the data stream to be transmitted from the cache and outputs it according to the internal running time and the agreed time. For example, Figure 3 As shown, the CPU first sends the configuration to the FPGA, and then sends the data stream. The FPGA then groups and caches the multiple data streams according to the configuration. Finally, the FPGA fetches the data and outputs it according to the agreed time based on the internal timing.

[0054] It should be noted that the present invention uses high-performance FPGA to achieve hardware acceleration and precise time control to ensure the synchronization of digital and analog signals. Figure 4As shown in the figure, the clock synchronization design ensures the precise synchronization of ADC sampling and DAC output, as well as the timing consistency of each module inside the FPGA. The built-in PLL (phase locked loop) or DCM (clock management module) of the FPGA is used to generate and distribute accurate clock signals. Through the design of the clock tree, all modules are ensured to work in the same clock domain, or the data transmission across the clock domain is ensured to be correct through clock conversion. The data buffer is used to store ADC sampling data and DAC output data to ensure the order and integrity of the data. The data buffer is implemented using the Block RAM or distributed RAM of the FPGA. The specific data structure uses FIFO to store the corresponding data to ensure the sequential processing and synchronization of the data. In order to further improve the reliability of the system, the FPGA will also filter the ADC sampling data through an adaptive filter. Among them, the adaptive filtering algorithm based on FPGA adopts the least mean square (LMS) algorithm. The LMS algorithm is an adaptive filtering algorithm suitable for FPGA implementation and is suitable for real-time signal processing. Its basic principle is to adjust the filter coefficients by minimizing the mean square value of the error signal, including: Initializing the filter coefficients: Select an initial value, usually zero or a small random number such as a value between 0 and 1, as the initial value of the filter coefficients. Sample the input signal: Read the input signal from the ADC sampling data to ensure that the sampling frequency meets the Nyquist sampling theorem to avoid aliasing. Calculate the current error signal: Calculate the difference between the output signal and the expected signal, using the formula Calculate the difference between the output signal and the desired signal, where e(n) is the error signal, d(n) is the desired signal, wk(n) is the kth filter coefficient, and x(n) is the input signal. Adjust the filter coefficients based on the error signal: Use the LMS update rule to adjust the filter coefficients. Based on the formula w k (n+1)=w k (n)+μe(n)x(nk) adjusts the filter coefficients, where μ is the step size parameter, which controls the convergence speed and stability of the algorithm. Repeat the above steps to continuously update the filter coefficients until the predetermined number of iterations is reached or the error meets the requirements. Select the appropriate step size parameter μ and filter length N.

[0055] The technical solution of the embodiment of the present invention is to send configuration parameters to the field programmable gate array through the fast channel interface by the central processing unit, and the field programmable gate array performs clock synchronization according to the configuration parameters, and after detecting that the clock synchronization is completed, the field programmable gate array receives the power system message and writes the power system message into the dynamic random access memory, and then the central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array. Based on the above technical solution, accurate processing and seamless switching of mixed digital and analog signals are realized, and accurate synchronous control of digital and analog signals is realized, ensuring the consistency of digital and analog output.

[0056] Embodiment 2

[0057] Figure 2 This is a schematic diagram of the structure of a processing device for relay protection test provided in the second embodiment of the present invention. Figure 5 As shown, the device includes: a synchronization test module 510, a message receiving module 520 and a data sending module 530; wherein,

[0058] Synchronous test module 510, the central processor sends configuration parameters to the field programmable gate array through the fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters;

[0059] A message receiving module 520, configured to receive a power system message through the field programmable gate array after detecting that the clock synchronization is completed, and write the power system message into a dynamic random access memory;

[0060] The data sending module 530, the central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array.

[0061] On the basis of the above technical solution, the message receiving module is used to store the power system message in the primary cache based on the field programmable gate array, and send a trigger signal to the state machine after the storage is completed; the state machine writes the power system message into the dynamic random access memory according to the trigger signal.

[0062] On the basis of the above technical solution, the message receiving module is used for the state machine to determine the storage status of the secondary cache after receiving the trigger signal, and when the storage status is idle, transfer the power system message to the secondary cache; and write the power system message into the dynamic random access memory through the secondary cache.

[0063] On the basis of the above technical solution, the data sending module is used for the field programmable gate array to send the data reading instruction to the central processing unit when it detects that the power system message exists in the dynamic random access memory; the central processing unit responds to the data reading instruction and reads the power system message from the dynamic random access memory.

[0064] On the basis of the above technical solution, the data sending module is used for the field programmable gate array to divide the data stream to be transmitted according to the transmission configuration information, and store the divided data stream to be transmitted in the cache; the field programmable gate array reads the data stream to be transmitted from the cache according to the internal timing and the agreed time and outputs it.

[0065] Based on the above technical solution, the message receiving module is used for the field programmable gate array to add message identification information to the header of the power system message, wherein the message identification information includes at least one of a time stamp, a frame count value, a channel, a rate, and a type.

[0066] On the basis of the above technical solution, the field programmable gate array is a SRAM field programmable gate array based on the FMSH-K7 series.

[0067] The technical solution of the embodiment of the present invention is to send configuration parameters to the field programmable gate array through the fast channel interface by the central processing unit, and the field programmable gate array performs clock synchronization according to the configuration parameters, and after detecting that the clock synchronization is completed, the field programmable gate array receives the power system message and writes the power system message into the dynamic random access memory, and then the central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array. Based on the above technical solution, accurate processing and seamless switching of mixed digital and analog signals are realized, and accurate synchronous control of digital and analog signals is realized, ensuring the consistency of digital and analog output.

[0068] The processing device for relay protection test provided in the embodiment of the present invention can execute the processing method for relay protection test provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0069] Embodiment 3

[0070] Figure 6A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0071] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0072] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0073] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the processing method of the relay protection test.

[0074] In some embodiments, the processing method of the relay protection test can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the processing method of the relay protection test described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the processing method of the relay protection test by any other appropriate means (for example, by means of firmware).

[0075] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0076] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0077] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0078] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0079] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0080] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0081] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0082] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for processing relay protection test, characterized in that: include: The central processor sends configuration parameters to the field programmable gate array through the fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters; After detecting that the clock synchronization is completed, receiving a power system message through the field programmable gate array, and writing the power system message into a dynamic random access memory; The central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array.

2. The method according to claim 1, characterized in that Writing the power system message into a dynamic random access memory comprises: storing the power system message in a primary cache based on the field programmable gate array, and sending a trigger signal to a state machine after the storage is completed; The state machine writes the power system message into a dynamic random access memory according to the trigger signal.

3. The method according to claim 2, characterized in that The state machine writes the power system message into a dynamic random access memory according to the trigger signal, comprising: After receiving the trigger signal, the state machine determines the storage state of the secondary cache, and when the storage state is idle, transfers the power system message to the secondary cache; The power system message is written into the dynamic random access memory through the secondary cache.

4. The method according to claim 1, characterized in that: The central processing unit reads the power system message from the dynamic random access memory, including: The field programmable gate array sends the data read instruction to the central processor when detecting that the power system message exists in the dynamic random access memory; The central processing unit reads the power system message from the dynamic random access memory in response to the data read instruction.

5. The method according to claim 1, characterized in that The sending the data stream to be transmitted through the field programmable gate array comprises: The field programmable gate array divides the data stream to be transmitted according to the transmission configuration information, and stores the divided data stream to be transmitted in a cache; The field programmable gate array reads the data stream to be transmitted from the cache according to the internal running time and the agreed time and outputs it.

6. The method according to claim 1, characterized in that After receiving the power system message through the field programmable gate array, the method further includes: The field programmable gate array adds message identification information to the header of the power system message, wherein the message identification information includes at least one of a time stamp, a frame count value, a channel, a rate, and a type.

7. The method according to claim 1, characterized in that The field programmable gate array is an SRAM field programmable gate array based on the FMSH-K7 series.

8. A processing device for relay protection test, characterized in that: include: A synchronization test module, wherein the central processor sends configuration parameters to the field programmable gate array through a fast channel interface, and the field programmable gate array performs clock synchronization according to the configuration parameters; A message receiving module, configured to receive a power system message through the field programmable gate array after detecting that the clock synchronization is completed, and write the power system message into a dynamic random access memory; The data sending module, the central processing unit reads the power system message from the dynamic random access memory, determines the data stream to be transmitted according to the power system message, and sends the data stream to be transmitted through the field programmable gate array.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the processing method for relay protection test according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the processing method for relay protection test according to any one of claims 1 to 7 when executed.

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