Avalanche test method with constant and controllable avalanche power

Abstract

The invention relates to an avalanche test method with constant and controllable avalanche power, which comprises the following steps of: controlling an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) switch tube S by utilizing a digital control core to adjust voltages respectively distributed by a DUT (Device Under Test) and the MOSFET switch tube S, and collecting an avalanche voltage of the DUT when the DUT enters an avalanche state and a drain voltage of the MOSFET switch tube S at the moment; the sampling resistor R2 is used for sampling to obtain an avalanche current when the DUT enters an avalanche state; processing the avalanche voltage, the drain voltage and the avalanche current to obtain a target avalanche current and a target avalanche voltage of the DUT; and analyzing the target avalanche current and the target avalanche voltage to obtain an analysis result of the DUT. According to the invention, the avalanche with constant power can be realized, the avalanche tolerance can be accurately controlled, and the automatic avalanche test can be realized without multiple manual repeated tests for repeated avalanche tests. And the efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an avalanche testing method with constant and controllable avalanche power. Background Art

[0002] With the development of power electronics technology, the voltage requirements for devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and diodes are getting higher and higher. SiC MOSFET and diodes are also developing rapidly. Due to the characteristics of SiC itself, its voltage resistance level is much higher than that of Si-based devices. However, the avalanche reliability problem is becoming increasingly serious. It is of great significance to build an avalanche test platform to perform avalanche tests on devices and analyze the avalanche mechanism of SiC devices.

[0003] However, in the prior art, the power of the avalanche test cannot be maintained and can only decrease linearly. It is impossible to analyze the avalanche failure mechanism of the device under constant avalanche power, and the avalanche tolerance in the current avalanche test cannot be controlled more accurately. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an avalanche testing method with constant and controllable avalanche power.

[0005] According to a first aspect of an embodiment of the present invention, there is provided a method for avalanche testing with constant and controllable avalanche power, the method comprising:

[0006] Using a digital control core to control the MOSFET switch tube S to adjust the voltages respectively obtained by the DUT and the MOSFET switch tube S, and collecting the avalanche voltage of the DUT and the drain voltage of the MOSFET switch tube S when the DUT enters an avalanche state;

[0007] The avalanche current when the DUT enters the avalanche state is obtained by sampling the sampling resistor R2;

[0008] Processing the avalanche voltage, the drain voltage, and the avalanche current to obtain a target avalanche current and a target avalanche voltage of the DUT;

[0009] The target avalanche current and the target avalanche voltage are analyzed to obtain an analysis result of the DUT.

[0010] Optionally, the avalanche voltage, the drain voltage and the avalanche current are obtained according to an avalanche test circuit; the avalanche test circuit includes: a power supply VDD, a variable resistor R1, the DUT, the MOSFET switch tube S, the sampling resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4; the positive electrode of the power supply VDD is connected to the first end of the variable resistor R1, the negative electrode of the power supply VDD is grounded, the second end of the variable resistor R1 is connected to the first end of the test base of the DUT, the second end of the DUT is connected to the first end of the MOSFET switch tube S, and the second end of the MOSFET switch tube S is connected to the first end of the sampling resistor R2. The first end of the resistor R3 is connected to the first end of the MOSFET switch tube S, the upper plate of the capacitor C1 is connected to the first end of the MOSFET switch tube S, the second end of the resistor R3 is connected to the first end of the resistor R4, the lower plate of the capacitor C1 is connected to the upper plate of the capacitor C2, the first end of the resistor R5 and the upper plate of the capacitor C3 are both connected to the second end of the variable resistor R1, the second end of the resistor R5 is connected to the first end of the resistor R6, the lower plate of the capacitor C3 is connected to the upper plate of the capacitor C4, the second ends of the resistor R4 and the resistor R6 are both grounded, and the lower plates of the capacitor C2 and the capacitor C4 are both grounded.

[0011] Optionally, the processing the avalanche voltage, the drain voltage, and the avalanche current to obtain a target avalanche current and a target avalanche voltage of the DUT includes:

[0012] Processing the avalanche current by an avalanche current sampling circuit to obtain the target avalanche current;

[0013] The avalanche voltage is processed by an avalanche voltage sampling circuit to obtain the target avalanche voltage.

[0014] Optionally, analyzing the target avalanche current and the target avalanche voltage to obtain an analysis result of the DUT includes:

[0015] Converting the target avalanche current and the target avalanche voltage by an analog-to-digital converter to obtain current and voltage digital signals;

[0016] The current and voltage digital signals are analyzed by the digital control core, and the obtained analysis results of the DUT are transmitted to a host computer for data display.

[0017] Optionally, before adjusting the voltages respectively obtained by the DUT and the MOSFET switch tube S through the MOSFET switch tube S and collecting the avalanche voltage of the DUT and the drain voltage of the MOSFET switch tube S when the DUT enters the avalanche state, the method further includes:

[0018] The digital control core sends a control signal to the isolation control module;

[0019] The isolation control module sends a driving signal to the MOSFET switch tube S according to the control signal to control the MOSFET switch S.

[0020] Optionally, the avalanche voltage sampling circuit includes: a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a first differential operational amplifier, a second differential operational amplifier and a third differential operational amplifier; the first end of the resistor R7 is connected to the avalanche voltage, the second end of the resistor R7 is connected to the non-inverting input end of the first differential operational amplifier, the inverting input end of the first differential operational amplifier is connected to the output end of the first differential operational amplifier, and the output end of the first differential operational amplifier is connected to the first end of the resistor R9; the first end of the resistor R8 is connected to the drain voltage, the second end of the resistor R8 is connected to the second differential operational amplifier The first differential operational amplifier is connected to the non-inverting input terminal of the first differential operational amplifier, the second differential operational amplifier is connected to the output terminal of the second differential operational amplifier, and the output terminal of the second differential operational amplifier is connected to the first end of the resistor R11; the second end of the resistor R9 is connected to the non-inverting input terminal of the third differential operational amplifier, the second end of the resistor R9 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the output terminal of the third differential operational amplifier; the second end of the resistor R11 is connected to the inverting input terminal of the third differential operational amplifier, the second end of the resistor R11 is connected to the first end of the resistor R12, and the second end of the resistor R12 is grounded.

[0021] Optionally, the avalanche current sampling circuit includes: a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a capacitor C5, a fourth differential operational amplifier and a fifth differential operational amplifier; the first end of the resistor R13 is grounded, the second end of the resistor R13 is connected to the first end of the resistor R14, the second end of the resistor R13 is connected to the inverting input end of the fourth differential operational amplifier, the second end of the resistor R14 is connected to the output end of the fourth differential operational amplifier, and the first end of the resistor R15 is connected to the sampling current generated after the avalanche current passes through the sampling resistor R2. voltage, the second end of the resistor R15 is connected to the first end of the resistor R16, the second end of the resistor R16 is grounded, the second end of the resistor R15 is connected to the non-inverting input terminal of the fourth differential operational amplifier, the output terminal of the fourth differential operational amplifier is connected to the first end of the resistor R17, the first end of the resistor R17 is connected to the upper plate of the capacitor C5, the lower plate of the capacitor C5 is grounded, the second end of the resistor R17 is connected to the non-inverting input terminal of the fifth differential operational amplifier, and the inverting input terminal of the fifth differential operational amplifier is connected to the output terminal of the fifth differential operational amplifier.

[0022] The technical solution provided by the present invention may include the following beneficial effects:

[0023] Through the above technical solution, using MOSFET switch tube S and DUT, constant power avalanche can be achieved, and the target avalanche current and target avalanche voltage can be sampled and analyzed in real time through the digital control core, which can achieve precise control of avalanche tolerance. When the expected tolerance is reached, the avalanche can be stopped. The digital control core is used to control the start and end of the avalanche. For repetitive avalanche tests, there is no need for multiple manual repeated tests, and automated avalanche tests can be achieved. This greatly improves efficiency.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 The present invention is a flow chart showing a method for avalanche testing with constant and controllable avalanche power according to an exemplary embodiment.

[0027] Figure 2 The figure is a schematic diagram of the structure of an avalanche test circuit according to an embodiment.

[0028] Figure 3The figure is an avalanche waveform diagram according to an exemplary embodiment.

[0029] Figure 4 The figure is a schematic diagram showing the structure of an avalanche voltage sampling circuit according to an exemplary embodiment.

[0030] Figure 5 The diagram is a schematic structural diagram of an avalanche current sampling circuit according to an exemplary embodiment.

[0031] Figure 6 The figure is a flow chart of an avalanche testing method with constant and controllable avalanche power according to an exemplary embodiment.

[0032] Figure 7 The diagram is a schematic diagram of the module structure of an avalanche test method with constant and controllable avalanche power according to an exemplary embodiment. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the scheme of the present invention, the relevant state of the prior art and the inventive concept of the present invention are first briefly described.

[0034] The current avalanche withstand capacity cannot be controlled more accurately, so the only way is to adjust the current first, according to the theoretical formula of avalanche withstand capacity:

[0035]

[0036] Among them, E AS is the avalanche withstand capability, L is the inductance value, I AV The maximum value reached by the inductor charging, V B is the device avalanche voltage, V DD is the power supply voltage;

[0037] Use the following formula to invert the current, and then adjust the charging time of the inductor;

[0038]

[0039] Among them, t P The time it takes for the MOS to charge the inductor.

[0040] However, these are all theoretical calculation formulas. There are various parasitic parameters in the actual circuit, which deviate from the theoretical formulas.

[0041] Therefore, the present invention proposes an avalanche testing method with constant and controllable avalanche power to solve this technical problem.

[0042] Figure 1 FIG. 1 is a flow chart of an avalanche test method with constant and controllable avalanche power according to an exemplary embodiment. Figure 1As shown, the method includes the following steps.

[0043] S101. Use the digital control core to control the MOSFET switch tube S to adjust the voltages respectively obtained by the DUT and the MOSFET switch tube S, and collect the avalanche voltage of the DUT and the drain voltage of the MOSFET switch tube S when the DUT enters the avalanche state.

[0044] Optionally, the avalanche voltage, the drain voltage and the avalanche current are obtained according to an avalanche test circuit; Figure 2 is a schematic diagram of a structure of an avalanche test circuit according to an embodiment. Figure 2 As shown, the avalanche test circuit includes: a power supply VDD, a variable resistor R1, a DUT, a MOSFET switch tube S, a sampling resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4; the positive electrode of the power supply VDD is connected to the first end of the variable resistor R1, the negative electrode of the power supply VDD is grounded, the second end of the variable resistor R1 is connected to the first end of the test base of the DUT, the second end of the DUT is connected to the first end of the MOSFET switch tube S, the second end of the MOSFET switch tube S is connected to the first end of the sampling resistor R2, and the sampling resistor R2 The second end of the resistor R3 is connected to the first end of the MOSFET switch tube S, the upper plate of the capacitor C1 is connected to the first end of the MOSFET switch tube S, the second end of the resistor R3 is connected to the first end of the resistor R4, the lower plate of the capacitor C1 is connected to the upper plate of the capacitor C2, the first end of the resistor R5 and the upper plate of the capacitor C3 are both connected to the second end of the variable resistor R1, the second end of the resistor R5 is connected to the first end of the resistor R6, the lower plate of the capacitor C3 is connected to the upper plate of the capacitor C4, the second ends of the resistor R4 and the resistor R6 are both grounded, and the lower plates of the capacitors C2 and C4 are both grounded.

[0045] It is understandable that circuit topologies such as Figure 2 As shown. Before the avalanche starts, the MOSFET switch tube S is closed, the DUT and the MOSFET switch tube S are divided (the withstand voltage of the MOSFET switch tube S must be greater than the power supply VDD voltage and the DUT withstand voltage, and the figure assumes that the switch tube divides all the voltages), and the entire loop is disconnected. Then the MOSFET switch tube S is driven to conduct, because the power supply VDD voltage is greater than the DUT withstand voltage, the DUT undergoes an avalanche breakdown, and the avalanche current at this time is:

[0046]

[0047] During an avalanche, the avalanche power of the DUT is:

[0048]

[0049] Among them, R is the resistance value of the variable resistor R1. Since each term in the formula is constant, the avalanche power of the DUT is also constant. The current can be adjusted by controlling the power supply voltage and resistance to control the size of the avalanche power. Figure 3 is an avalanche waveform diagram according to an exemplary embodiment. Figure 3 As shown, V B is the avalanche voltage of the DUT, V MOS is the drain voltage of the MOSFET switch tube S, V DUT represents the target avalanche voltage of the DUT, t AV Indicates the avalanche duration. In order to reduce costs and avoid wasting resources by repeatedly building platforms, the DUT can use the bases of diodes and MOSFETs to connect diodes or MOSFETs, which can achieve avalanche testing compatible with diodes and MOSFETs.

[0050] S102 , sampling the avalanche current when the DUT enters the avalanche state through the sampling resistor R2.

[0051] It is understandable that for the voltage sampling of the DUT, since the DUT is on the high potential side, there is a higher common mode voltage. First, the voltage between the drain of the switching MOSFET device S and the cathode (or drain) of the DUT and the ground is attenuated. The avalanche voltage of the power device is thousands of volts, and the voltage rises rapidly during avalanche, and the rising edge is fast, so it is necessary to attenuate the voltage and meet the following requirements:

[0052]

[0053] The voltage attenuation ratio can be made consistent regardless of whether the voltage is low frequency or high frequency, so that high voltage signals with faster rising edges can be collected.

[0054] S103 , processing the avalanche voltage, drain voltage and avalanche current to obtain a target avalanche current and a target avalanche voltage of the DUT.

[0055] Optionally, S103 may include:

[0056] The avalanche current is processed by an avalanche current sampling circuit to obtain a target avalanche current;

[0057] The avalanche voltage is processed by an avalanche voltage sampling circuit to obtain a target avalanche voltage.

[0058] Optionally, Figure 4 is a schematic diagram of a structure of an avalanche voltage sampling circuit according to an exemplary embodiment. Figure 4As shown, the avalanche voltage sampling circuit includes: a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a first differential operational amplifier, a second differential operational amplifier and a third differential operational amplifier; the first end of the resistor R7 is connected to the avalanche voltage, the second end of the resistor R7 is connected to the non-inverting input end of the first differential operational amplifier, the inverting input end of the first differential operational amplifier is connected to the output end of the first differential operational amplifier, and the output end of the first differential operational amplifier is connected to the first end of the resistor R9; the first end of the resistor R8 is connected to the drain voltage, the second end of the resistor R8 is connected to the second differential operational amplifier. The non-inverting input terminal of the operational amplifier and the inverting input terminal of the second differential operational amplifier are connected to the output terminal of the second differential operational amplifier, and the output terminal of the second differential operational amplifier is connected to the first end of the resistor R11; the second end of the resistor R9 is connected to the non-inverting input terminal of the third differential operational amplifier, the second end of the resistor R9 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the output terminal of the third differential operational amplifier; the second end of the resistor R11 is connected to the inverting input terminal of the third differential operational amplifier, the second end of the resistor R11 is connected to the first end of the resistor R12, and the second end of the resistor R12 is grounded.

[0059] It is understandable that the circuit is built using a differential operational amplifier to subtract the two voltages to eliminate the common-mode voltage and obtain the real voltage of the DUT. First, two voltage followers are used for impedance matching, and then a differential amplifier circuit is used to differentially measure the two voltages to obtain the DUT voltage. R7 and R8 are generally 50Ω to eliminate signal reflection. Let R9 = R 10 , R 11 =R 12 , the output formula is:

[0060] V DUT =V ALL -V MOS ;

[0061] Among them, V DUT is the target avalanche voltage.

[0062] Optionally, Figure 5 is a schematic diagram of a structure of an avalanche current sampling circuit according to an exemplary embodiment. Figure 5As shown, the avalanche current sampling circuit includes: a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a capacitor C5, a fourth differential operational amplifier and a fifth differential operational amplifier; the first end of the resistor R13 is grounded, the second end of the resistor R13 is connected to the first end of the resistor R14, the second end of the resistor R13 is connected to the inverting input end of the fourth differential operational amplifier, the second end of the resistor R14 is connected to the output end of the fourth differential operational amplifier, and the first end of the resistor R15 is connected to the avalanche current generated after passing through the sampling resistor R2 The sampling voltage is obtained, the second end of the resistor R15 is connected to the first end of the resistor R16, the second end of the resistor R16 is grounded, the second end of the resistor R15 is connected to the non-inverting input terminal of the fourth differential operational amplifier, the output terminal of the fourth differential operational amplifier is connected to the first end of the resistor R17, the first end of the resistor R17 is connected to the upper plate of the capacitor C5, the lower plate of the capacitor C5 is grounded, the second end of the resistor R17 is connected to the non-inverting input terminal of the fifth differential operational amplifier, and the inverting input terminal of the fifth differential operational amplifier is connected to the output terminal of the fifth differential operational amplifier.

[0063] It can be understood that for the collection of avalanche current, the sampling resistor R2 is used to convert the sampling current into a sampling voltage, and then the differential amplifier circuit is used to amplify the signal. Since the sampling resistor is generally in the mΩ level, its voltage is small, and the current signal is prone to high-frequency fluctuations, it needs to be filtered, and an active RC filter network is used to low-pass filter the current signal. The filter cutoff frequency is:

[0064]

[0065] S104, analyzing the target avalanche current and the target avalanche voltage to obtain the analysis result of the DUT.

[0066] Optionally, S104 may include:

[0067] The target avalanche current and the target avalanche voltage are converted by an analog-to-digital converter to obtain a current and voltage digital signal;

[0068] The current and voltage digital signals are analyzed through the digital control core, and the analysis results of the DUT are transmitted to the host computer for data display.

[0069] Optionally, before adjusting the voltages respectively obtained by the DUT and the MOSFET switch tube S through the MOSFET switch tube S and collecting the avalanche voltage of the DUT when the DUT enters the avalanche state and the drain voltage of the MOSFET switch tube S at this time, the method further includes:

[0070] The digital control core sends a control signal to the isolation control module;

[0071] The isolation control module sends a driving signal to the MOSFET switch tube S according to the control signal to control the MOSFET switch S.

[0072] In one embodiment, Figure 6 is a flow chart of a method for avalanche testing with constant and controllable avalanche power according to an exemplary embodiment. Figure 7 FIG. 1 is a schematic diagram of a module structure of an avalanche test method with constant and controllable avalanche power according to an exemplary embodiment. Figure 6 As shown, the host computer can set the parameters of each circuit, and then select the mode required for this avalanche test, including: fixed tolerance mode and fixed time mode; in the fixed tolerance mode, the digital control core drives the MOSFET switch tube S to turn on to start the avalanche of the DUT, and samples the avalanche current and avalanche voltage in real time, and stores them in the digital control core for analysis and calculation. When the avalanche tolerance reaches the preset value, the digital control core drives the MOSFET switch tube S to close. When the avalanche tolerance does not reach the preset value, the previous step is repeated until the preset value is reached; then the corresponding avalanche data (the analysis results of the target avalanche current and the target avalanche voltage) is transmitted to the host computer for display. If the avalanche needs to be repeated, continue to select the avalanche mode. If the avalanche does not need to be repeated, the avalanche ends. The operation when selecting the fixed time mode is similar to the operation in the fixed tolerance mode. For details, please refer to Figure 6 , I will not go into details here.

[0073] The avalanche test circuit of the present invention utilizes MOSFET switch tube S to be connected in series with DUT, and uses variable resistor for current limiting. Compared with the existing test circuit, it can realize constant power avalanche, and the avalanche time can be adjusted at will; by real-time sampling and analysis of avalanche current and voltage, it can realize accurate control of avalanche tolerance, and control avalanche to stop when the expected tolerance is reached; and a current and voltage acquisition circuit is built, and the data is displayed by the host computer without the need to use current and voltage probe oscilloscope and other equipment, which greatly reduces the cost and volume occupation; and a digital control core is used to control the start and end of the entire avalanche. For repetitive avalanche tests, there is no need for multiple manual repeated tests, and automated avalanche tests can be realized. Greatly improve efficiency.

[0074] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0075] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0076] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A method for avalanche testing with constant and controllable avalanche power, characterized in that: The method further comprises: Using a digital control core to control the MOSFET switch tube S to adjust the voltages respectively obtained by the DUT and the MOSFET switch tube S, and collecting the avalanche voltage of the DUT and the drain voltage of the MOSFET switch tube S when the DUT enters an avalanche state; The avalanche current when the DUT enters the avalanche state is obtained by sampling the sampling resistor R2; Processing the avalanche voltage, the drain voltage, and the avalanche current to obtain a target avalanche current and a target avalanche voltage of the DUT; The target avalanche current and the target avalanche voltage are analyzed to obtain an analysis result of the DUT.

2. The avalanche test method with constant and controllable avalanche power according to claim 1, characterized in that: The avalanche voltage, the drain voltage and the avalanche current are obtained according to an avalanche test circuit; the avalanche test circuit comprises: a power supply VDD, a variable resistor R1, the DUT, the MOSFET switch tube S, the sampling resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4; the positive electrode of the power supply VDD is connected to the first end of the variable resistor R1, the negative electrode of the power supply VDD is grounded, the second end of the variable resistor R1 is connected to the first end of the test base of the DUT, the second end of the DUT is connected to the first end of the MOSFET switch tube S, and the second end of the MOSFET switch tube S is connected to the first end of the sampling resistor R2. , the second end of the sampling resistor R2 is grounded, the first end of the resistor R3 is connected to the first end of the MOSFET switch tube S, the upper plate of the capacitor C1 is connected to the first end of the MOSFET switch tube S, the second end of the resistor R3 is connected to the first end of the resistor R4, the lower plate of the capacitor C1 is connected to the upper plate of the capacitor C2, the first end of the resistor R5 and the upper plate of the capacitor C3 are both connected to the second end of the variable resistor R1, the second end of the resistor R5 is connected to the first end of the resistor R6, the lower plate of the capacitor C3 is connected to the upper plate of the capacitor C4, the second ends of the resistor R4 and the resistor R6 are both grounded, and the lower plates of the capacitor C2 and the capacitor C4 are both grounded.

3. The avalanche test method with constant and controllable avalanche power according to claim 1, characterized in that: The processing of the avalanche voltage, the drain voltage and the avalanche current to obtain a target avalanche current and a target avalanche voltage of the DUT includes: Processing the avalanche current by an avalanche current sampling circuit to obtain the target avalanche current; The avalanche voltage is processed by an avalanche voltage sampling circuit to obtain the target avalanche voltage.

4. The avalanche testing method with constant and controllable avalanche power according to claim 1, characterized in that: The analyzing the target avalanche current and the target avalanche voltage to obtain the analysis result of the DUT includes: Converting the target avalanche current and the target avalanche voltage by an analog-to-digital converter to obtain current and voltage digital signals; The current and voltage digital signals are analyzed by the digital control core, and the obtained analysis results of the DUT are transmitted to a host computer for data display.

5. The avalanche testing method with constant and controllable avalanche power according to claim 4, characterized in that: Before adjusting the voltages respectively obtained by the DUT and the MOSFET switch tube S through the MOSFET switch tube S and collecting the avalanche voltage of the DUT and the drain voltage of the MOSFET switch tube S when the DUT enters the avalanche state, the method further includes: The digital control core sends a control signal to the isolation control module; The isolation control module sends a driving signal to the MOSFET switch tube S according to the control signal to control the MOSFET switch S.

6. The avalanche testing method with constant and controllable avalanche power according to claim 3, characterized in that: The avalanche voltage sampling circuit includes: a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a first differential operational amplifier, a second differential operational amplifier and a third differential operational amplifier; the first end of the resistor R7 is connected to the avalanche voltage, the second end of the resistor R7 is connected to the non-inverting input end of the first differential operational amplifier, the inverting input end of the first differential operational amplifier is connected to the output end of the first differential operational amplifier, and the output end of the first differential operational amplifier is connected to the first end of the resistor R9; the first end of the resistor R8 is connected to the drain voltage, the second end of the resistor R8 is connected to the output end of the second differential operational amplifier, and the output end of the first differential operational amplifier is connected to the first end of the resistor R9; The first differential operational amplifier is connected to the non-inverting input terminal of the third differential operational amplifier, the second differential operational amplifier is connected to the inverting input terminal of the second differential operational amplifier, and the output terminal of the second differential operational amplifier is connected to the first end of the resistor R11; the second end of the resistor R9 is connected to the non-inverting input terminal of the third differential operational amplifier, the second end of the resistor R9 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the output terminal of the third differential operational amplifier; the second end of the resistor R11 is connected to the inverting input terminal of the third differential operational amplifier, the second end of the resistor R11 is connected to the first end of the resistor R12, and the second end of the resistor R12 is grounded.

7. The avalanche testing method with constant and controllable avalanche power according to claim 3, characterized in that: The avalanche current sampling circuit includes: a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a capacitor C5, a fourth differential operational amplifier and a fifth differential operational amplifier; the first end of the resistor R13 is grounded, the second end of the resistor R13 is connected to the first end of the resistor R14, the second end of the resistor R13 is connected to the inverting input end of the fourth differential operational amplifier, the second end of the resistor R14 is connected to the output end of the fourth differential operational amplifier, the first end of the resistor R15 is connected to the sampling voltage generated after the avalanche current passes through the sampling resistor R2, The second end of the resistor R15 is connected to the first end of the resistor R16, the second end of the resistor R16 is grounded, the second end of the resistor R15 is connected to the non-inverting input terminal of the fourth differential operational amplifier, the output terminal of the fourth differential operational amplifier is connected to the first end of the resistor R17, the first end of the resistor R17 is connected to the upper plate of the capacitor C5, the lower plate of the capacitor C5 is grounded, the second end of the resistor R17 is connected to the non-inverting input terminal of the fifth differential operational amplifier, and the inverting input terminal of the fifth differential operational amplifier is connected to the output terminal of the fifth differential operational amplifier.

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