Silicon nitride waveguide preparation method, silicon optical chip and electronic equipment
Through the ICP machine, the polycrystalline silicon layer is subjected to high-precision etching and the planarization of the silicon nitride layer, which solves the problem of low yield in the preparation process of silicon nitride waveguides in the prior art, and improves the perpendicularity and resolution of the sidewalls of the silicon nitride waveguides.
Patent Information
- Application Number
- CN202510244368.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-03
- Publication Date
- 2025-04-01
AI Technical Summary
In the process of preparing silicon nitride waveguides in the prior art, the yield rate is low, mainly because the silicon nitride waveguide has high morphology requirements and limited etching accuracy, resulting in a non-standard sidewall angle, poor roughness, and the silicon dioxide film is easily damaged.
The polysilicon layer is patterned and etched by an ICP machine to form interlaced polysilicon strip areas and trenches. Then, the silicon nitride layer is deposited on these areas and planarized. Finally, the polysilicon strip area is back-etched through the ICP machine to remove the polysilicon strip area and expose the silicon oxide layer.
Through high-precision etching and process parameter adjustment of the ICP machine, the verticality and resolution of the sidewall of the silicon nitride waveguide are improved, the damage of the silicon dioxide film is avoided, and the yield of the silicon nitride waveguide is significantly improved.
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Figure CN119738922A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the semiconductor field, and in particular to a method for preparing a silicon nitride waveguide, a silicon photonic chip, and an electronic device. Background Art
[0002] Silicon photonic chips are integrated optical chips that combine optoelectronic devices with traditional silicon-based semiconductor processes. Silicon nitride waveguides are key components of silicon photonic chips. They are optical structures used to guide the transmission of optical signals. They are responsible for transmitting optical signals from one location to another on the chip and ensuring that the optical signals have low loss and good stability during transmission. Currently, the preparation method of silicon nitride waveguides in silicon photonic chips is usually as follows: first, a thin layer of silicon dioxide is grown on the SOI substrate, then silicon nitride of the target thickness is grown on the silicon dioxide, and finally the desired patterned area is formed by photolithography and etching.
[0003] However, the morphology of silicon nitride waveguides is very demanding during the preparation process. Currently, a CCP machine is usually used to etch silicon nitride. However, due to the limited etching accuracy of the CCP machine, the side wall angle of the silicon nitride waveguide area of the silicon photonic chip is not straight and has poor roughness after etching. In addition, since the selectivity of silicon nitride to silicon dioxide is very low, the silicon dioxide film at the bottom is easily destroyed during the etching process, resulting in a relatively low yield rate in the process of preparing silicon nitride waveguides. Summary of the invention
[0004] The present invention provides a method for preparing a silicon nitride waveguide, a silicon photonic chip and an electronic device, which solve the technical problem of low yield rate in the process of preparing silicon nitride waveguide in the prior art.
[0005] In a first aspect, the present invention provides a method for preparing a silicon nitride waveguide, the method comprising: Depositing a silicon oxide layer on a top silicon layer of an SOI substrate, wherein the SOI substrate comprises the top silicon layer, an insulating layer and a bottom silicon layer; Depositing a polysilicon layer on the silicon oxide layer, and pattern-etching the polysilicon layer by an ICP machine to form a plurality of staggered polysilicon strip regions and grooves, wherein the silicon oxide layer is exposed at the bottom of the grooves; Depositing a silicon nitride layer on the polysilicon strip region and the trench; Planarizing the silicon nitride layer so that the silicon nitride layer deposited on the groove is flush with the polysilicon strip region; The polysilicon strip region is etched back by the ICP machine to remove the polysilicon strip region and expose the silicon oxide layer.
[0006] Wherein, the step of depositing a polysilicon layer on the silicon oxide layer comprises: A polysilicon layer with a first preset thickness is deposited on the silicon oxide layer, and a value range of the first preset thickness is 50 nm to 80 nm.
[0007] The method of patterning and etching the polysilicon layer by an ICP machine to form a plurality of staggered polysilicon strip regions and grooves includes: The polysilicon layer is patterned and dry-etched by hydrogen bromide gas through an ICP machine to form a plurality of staggered polysilicon strip regions and trenches, wherein the sidewalls of the polysilicon strip regions are perpendicular to the bottoms of the trenches.
[0008] The method of patterning the polysilicon layer by dry etching with hydrogen bromide gas using an ICP machine includes: The polysilicon layer is patterned dry-etched by using an ICP machine with a preset flow rate of hydrogen bromide gas.
[0009] The preset flow rate ranges from 250 sccm to 350 sccm.
[0010] Wherein, the step of depositing a silicon nitride layer on the polysilicon strip region and the groove comprises: A silicon nitride layer with a second preset thickness is deposited on the polysilicon strip region and the groove, and a value range of the second preset thickness is 140nm~160nm.
[0011] The step of etching back the polysilicon strip region by using the ICP machine includes: The polysilicon layer is etched back by using an ICP machine with a preset flow rate of hydrogen bromide gas.
[0012] The preset flow rate ranges from 250 sccm to 350 sccm.
[0013] In a second aspect, the present invention provides a silicon photonic chip, comprising a silicon nitride waveguide, wherein the silicon nitride waveguide is prepared by the silicon nitride waveguide preparation method described in the first aspect.
[0014] In a third aspect, the present invention provides an electronic device, comprising the silicon photonic chip described in the second aspect.
[0015] As mentioned above, the present invention provides a method for preparing a silicon nitride waveguide, a silicon photonic chip and an electronic device. When preparing a silicon nitride waveguide, the present invention first deposits a silicon oxide layer on the top silicon layer of the SOI substrate, then deposits a polysilicon layer on the silicon oxide layer, and performs pattern etching on the polysilicon layer through an ICP machine to form a plurality of staggered polysilicon strip regions and grooves. Afterwards, a silicon nitride layer is deposited on the polysilicon strip regions and the grooves and flattened so that the silicon nitride layer deposited on the grooves is flush with the polysilicon strip regions. Finally, the polysilicon strip regions are backetched through an ICP machine to remove the polysilicon strip regions and expose the silicon oxide layer, thereby completing the preparation of the silicon nitride waveguide.
[0016] The present invention uses an ICP machine to etch polysilicon to prepare a silicon nitride waveguide. Compared with the method of using a CCP machine to etch silicon nitride to prepare a silicon nitride waveguide in the prior art, the IPC machine can accurately control the properties of the plasma and the etching process by adjusting multiple parameters such as power, gas flow, and pressure during the etching process, so that the process parameters can be quickly adjusted according to specific etching requirements to achieve high-precision etching, reduce etching deviation and sidewall roughness, and improve the verticality and resolution of the sidewalls of the silicon nitride waveguide region. In addition, since polysilicon has a relatively high selection of silicon oxide, it is possible to avoid destroying the silicon dioxide at the bottom during the etching process. The present invention can improve the yield rate of the silicon nitride waveguide in the preparation process, and solves the technical problem of low yield rate in the process of preparing the silicon nitride waveguide in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic diagram of the prior art for preparing a silicon nitride waveguide provided in an embodiment of the present invention.
[0018] Figure 2 A flow chart of a method for preparing a silicon nitride waveguide provided in an embodiment of the present invention.
[0019] Figure 3 FIG. 4 is a schematic diagram of depositing a polysilicon layer on a silicon oxide layer according to an embodiment of the present invention.
[0020] Figure 4 A schematic diagram of a polysilicon layer after patterning etching is provided in an embodiment of the present invention.
[0021] Figure 5 A schematic diagram of depositing a silicon nitride layer on a polysilicon strip region and a trench provided in an embodiment of the present invention.
[0022] Figure 6 A schematic diagram of planarizing a silicon nitride layer according to an embodiment of the present invention.
[0023] Figure 7A schematic diagram of a fabricated silicon nitride waveguide provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0024] The following description and accompanying drawings fully illustrate the specific embodiments of the present application so that those skilled in the art can practice them. The examples represent possible variations only. Unless explicitly required, separate components and functions are optional, and the order of operation can vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. The scope of the embodiments of the present application includes the entire scope of the claims, and all available equivalents of the claims. In this article, each embodiment may be represented individually or generally by the term "invention", which is only for convenience, and if more than one invention is disclosed in fact, it is not intended to automatically limit the scope of the application to any single invention or inventive concept. In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, without requiring or implying any actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. The various embodiments are described in a progressive manner herein, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. As for the structures, products, etc. disclosed in the embodiments, since they correspond to the parts disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.
[0025] In the prior art, the method for preparing silicon nitride waveguides in silicon photonic chips is to first grow a thin silicon dioxide layer on an SOI substrate, then grow a silicon nitride layer of target thickness on the silicon dioxide layer, and finally perform photolithography and etching on the silicon nitride layer to form the desired patterned area. For example, Figure 1 As shown, Figure 1 A schematic diagram of the prior art for preparing a silicon nitride waveguide according to an embodiment of the present invention is provided. Figure 1 Here, SIN stands for silicon nitride, OX stands for silicon oxide, and Si stands for silicon.
[0026] However, the morphology of silicon nitride waveguides is very demanding during the preparation process, requiring the sidewalls of the silicon nitride waveguide to be smooth and perpendicular to the silicon oxide layer of the SOI substrate. At present, CCP (Capacitive Coupled Plasma) machines are usually used to etch silicon nitride, but due to the limited etching accuracy of CCP machines, the sidewall angles of the silicon nitride waveguide area of the silicon photonic chip after etching are not straight and the roughness is poor. In addition, since the selectivity of silicon nitride to silicon dioxide is very low, the silicon dioxide film at the bottom is easily destroyed during the etching process. The etching selectivity refers to the ratio of the etching rates of two different materials (silicon nitride and silicon dioxide) under the same etching conditions. If the selectivity of silicon nitride to silicon dioxide is very low, it means that during the etching process, the etching rate of silicon nitride is smaller than that of silicon dioxide, and the difference between the etching rates of the two is not large. Since the etching process usually uses chemical substances to react with the surface of the material to gradually remove the material, when the selectivity of silicon nitride to silicon dioxide is low, that is, the etching effect of the etchant on silicon nitride and silicon dioxide has no obvious selectivity. While the etchant reacts with silicon nitride, it also reacts with silicon dioxide to almost the same extent. Therefore, during the etching process of silicon nitride, the silicon dioxide film at the bottom cannot be effectively protected and is easily attacked and damaged by the etchant.
[0027] In order to solve the above technical problems, an embodiment of the present invention provides a method for preparing a silicon nitride waveguide, such as Figure 2 As shown, Figure 2 A flow chart of a method for preparing a silicon nitride waveguide provided in an embodiment of the present invention. The method for preparing a silicon nitride waveguide provided in an embodiment of the present invention includes: Step 101: depositing a silicon oxide layer on a top silicon layer of an SOI substrate, wherein the SOI substrate comprises a top silicon layer, an insulating layer and a bottom silicon layer.
[0028] In this embodiment, when preparing the silicon nitride waveguide, it is necessary to prepare in advance an SOI substrate, which is a Silicon-On-Insulator substrate, and is a new type of substrate material used to manufacture semiconductor devices. The SOI substrate is generally composed of a three-layer structure, including a top silicon layer, an insulating layer, and a bottom silicon layer. The top silicon layer is a single crystal silicon layer, also known as an active layer, which is a functional layer used to manufacture various semiconductor devices. The active area of the device, such as the channel of the transistor, is located in the top silicon layer; the middle insulating layer is a silicon dioxide layer, which plays a role of electrical isolation and can reduce leakage and signal interference between devices; the bottom silicon layer mainly plays a mechanical support role, providing a stable foundation for the entire structure.
[0029] In this embodiment, when preparing the silicon nitride waveguide, it is first necessary to deposit a silicon oxide layer on the top silicon layer of the SOI substrate. Exemplarily, the silicon oxide layer can be formed by chemical vapor deposition or sputtering deposition.
[0030] When the silicon oxide layer is deposited by chemical vapor deposition, the SOI substrate is first strictly cleaned to remove impurities, oil stains, particles and other pollutants on the surface. Organic solvents, deionized water and chemical reagents are usually used for cleaning to ensure the cleanliness of the substrate surface. The cleaned substrate needs to be dried, usually by blowing with nitrogen or drying at low temperature in an oven to prevent impurities such as surface adsorption of moisture from affecting the subsequent deposition process. After that, the pre-treated SOI substrate is placed in the reaction chamber, and then reaction gases such as monosilane and oxygen are introduced into the reaction chamber. At the same time, some carrier gases such as argon may also be introduced to help the reaction gases be evenly distributed in the reaction chamber. Through a precise gas flow control system, the flow of monosilane, oxygen and carrier gas can be strictly controlled to ensure that they enter the reaction chamber in a set ratio. Finally, the substrate is heated to a specific reaction temperature, generally between several hundred degrees Celsius and thousands of degrees Celsius, so that monosilane and oxygen react chemically, and the silicon dioxide generated by the reaction is deposited in a solid form on the surface of the top silicon layer of the SOI substrate. As the reaction continues, the silicon oxide layer gradually grows and thickens. When the silicon oxide layer reaches the desired thickness, the reaction gas is stopped, the heating is stopped, and the reaction chamber is allowed to cool naturally or quickly cooled to room temperature by a cooling device. The cooled SOI substrate is taken out of the reaction chamber, and the deposition process of the silicon oxide layer is completed.
[0031] The sputtering deposition process is similar to the chemical vapor deposition method. First, the SOI substrate is cleaned and placed in the vacuum chamber of the sputtering equipment. The chamber is evacuated to a high vacuum state through the vacuum system. Generally, the vacuum degree should reach Pa is even lower to reduce the interference of gas molecules in the chamber on the sputtering process. After that, a silicon target is installed in the sputtering equipment. The silicon target is usually a high-purity silicon block. Then a certain amount of oxygen and argon are introduced into the vacuum chamber. Argon is used as a working gas to form a plasma under the action of an electric field, and oxygen is used to react with the sputtered silicon atoms to form silicon oxide. By precisely controlling the flow ratio and total flow of oxygen and argon, the chemical reaction and deposition rate during the sputtering process can be adjusted. After turning on the power of the sputtering equipment, the argon atoms are ionized to form a plasma under the action of the electric field. The argon ions bombard the surface of the silicon target at a high speed under the acceleration of the electric field. The silicon atoms on the surface of the silicon target are sputtered out under the bombardment of argon ions and react with the oxygen in the chamber to form silicon oxide. Silicon oxide is deposited on the surface of the top silicon layer of the SOI substrate, gradually forming a silicon oxide layer.
[0032] It can be understood that the specific method of depositing the silicon oxide layer can be selected according to actual needs and is not specifically limited in this embodiment.
[0033] Step 102 , depositing a polysilicon layer on the silicon oxide layer, and patterning and etching the polysilicon layer by an ICP machine to form a plurality of staggered polysilicon strip regions and trenches, with the silicon oxide layer exposed at the bottom of the trenches.
[0034] After a silicon oxide layer is deposited on the top silicon layer of the SOI substrate, a polysilicon layer needs to be further deposited on the silicon oxide layer. For example, Figure 3 As shown, Figure 3 Schematic diagram of depositing a polysilicon layer on a silicon oxide layer according to an embodiment of the present invention. Figure 3 POLY is a polysilicon layer. The method for depositing the polysilicon layer may be a low-pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or a sputtering deposition method. In one embodiment, a polysilicon layer of a first preset thickness needs to be deposited on the silicon oxide layer, and the value range of the first preset thickness is 50nm to 80nm.
[0035] After the polysilicon layer is generated, it is necessary to control the ICP (Inductive Coupled Plasma) machine to perform patterned etching on the polysilicon layer to form a plurality of staggered polysilicon strip regions and grooves, and the bottom of the groove exposes the silicon oxide layer, for example, Figure 4 As shown, Figure 4 A schematic diagram of a polysilicon layer after patterned etching is provided for an embodiment of the present invention. When patterned etching is performed on the polysilicon layer, it is first necessary to coat the surface of the polysilicon layer with photoresist, and transfer the desired pattern to the photoresist by photolithography technology to form an etching mask. Then, an ICP machine is used to generate plasma, and the polysilicon layer is etched through the chemical reaction of the gas and the physical sputtering effect. After the etching is completed, the photoresist is removed, and the etched sample is cleaned and inspected to ensure that the etching effect meets the design requirements.
[0036] In one embodiment, in step 102, the polysilicon layer is patterned and etched by an ICP machine to form a plurality of staggered polysilicon strip regions and trenches, including: The polysilicon layer is patterned and dry-etched using hydrogen bromide gas on an ICP machine to form a plurality of staggered polysilicon strip regions and trenches, wherein the side walls of the polysilicon strip regions are perpendicular to the bottom of the trenches.
[0037] Specifically, first, photoresist needs to be spin-coated on the surface of the polysilicon layer. Photoresist is a photosensitive material that transfers the designed pattern to the polysilicon layer. Then, the pattern is transferred to the photoresist using a photolithography mask and exposure equipment (or electron beam exposure). The exposed sample is placed in a developer, and the development time and temperature are controlled according to the type of photoresist and developer to form an anti-etching pattern. After that, the sample with the photoresist mask is placed in the reaction chamber of the ICP machine, and HBr etching gas is introduced into the chamber. At the same time, a small amount of auxiliary gas, such as oxygen or argon, can be added as needed. HBr is the main etchant that can react chemically with polysilicon. Adding oxygen can enhance the chemical activity of etching, and argon can provide a physical sputtering effect, which helps to form vertical sidewalls. Etching can then be performed. During the etching process, the parameters of the ICP machine, such as source power, bias power, and chamber pressure, need to be adjusted to achieve selective etching of polysilicon and obtain vertical sidewalls. Exemplarily, the settings of different parameters are as follows: Source power: usually set at 500-2000W to generate sufficient plasma density to fully ionize the HBr gas and improve the etching rate and uniformity. Bias power: in the range of 100-500W, providing sufficient energy for the ions to vertically bombard the polysilicon layer, enhancing the anisotropy of etching, thereby forming vertical sidewalls. Chamber pressure: controlled between 1-10 mTorr, the pressure will affect the density of the plasma and the mean free path of the active particles. In addition, it is also necessary to control the flow rate of hydrogen bromide gas. In this embodiment, the ICP machine uses a preset flow rate of hydrogen bromide gas to perform patterned dry etching on the polysilicon layer. In one embodiment, the preset flow rate ranges from 250sccm to 350sccm to ensure that the etching reaction proceeds stably.
[0038] After etching is completed, use a suitable photoresist remover (such as an organic solvent or oxygen plasma) to remove the residual photoresist from the sample to prevent the residual photoresist from affecting subsequent processes or causing contamination. During the etching process, by adjusting the parameters of the ICP machine, the HBr gas selectively etches the polysilicon layer in a plasma environment, and uses the photoresist as a mask to achieve patterned etching, ultimately forming polysilicon strip areas and grooves with vertical sidewalls. By controlling parameters such as source power, bias power, chamber pressure, and gas flow, the etching effect is optimized to ensure the verticality of the sidewalls of the polysilicon strip area and the flatness of the bottom of the groove, ensuring that the etched structure meets the requirements of subsequent semiconductor device manufacturing.
[0039] Step 103 : depositing a silicon nitride layer on the polysilicon strip regions and the trenches.
[0040] After etching the polysilicon layer to form polysilicon strip regions and grooves, it is necessary to further deposit a silicon nitride layer on the polysilicon strip regions and the grooves. The method for depositing the silicon nitride layer may be a chemical vapor deposition method or a sputtering deposition method, etc., which may be selected according to actual needs. Specifically, in the process of depositing the silicon nitride layer, it is necessary to deposit a silicon nitride layer of a second preset thickness on the polysilicon strip regions and the grooves. The second preset thickness ranges from 140nm to 160nm. For example, the second preset thickness may be 150nm. It is understandable that in the process of depositing the silicon nitride layer, since there is a height difference between the polysilicon strip regions and the grooves, when the silicon nitride layer is deposited, there is also a height difference in the silicon nitride layer. For example, as Figure 5 As shown, Figure 5 A schematic diagram of depositing a silicon nitride layer on a polysilicon strip region and a groove provided in an embodiment of the present invention, Figure 5 There is a height difference between the silicon nitride layer formed on the polysilicon strip area and the trench.
[0041] Step 104 : planarizing the silicon nitride layer so that the silicon nitride layer deposited on the trench is flush with the polysilicon strip region.
[0042] After the silicon nitride layer is deposited, it is necessary to planarize the silicon nitride layer to remove the silicon nitride layer whose height exceeds the height of the polysilicon strip region, so that the silicon nitride layer deposited on the groove is flush with the polysilicon strip region. Specifically, when planarizing the silicon nitride layer, a CMP (Chemical-mechanical polishing) process can be used to grind the surface of the silicon nitride layer flat. For example, Figure 6 As shown, Figure 6 A schematic diagram of planarizing a silicon nitride layer according to an embodiment of the present invention.
[0043] Step 105 , etching back the polysilicon strip region by using an ICP machine to remove the polysilicon strip region and expose the silicon oxide layer.
[0044] After the silicon nitride layer is planarized, the polysilicon strip area is etched back by the ICP machine to remove the polysilicon strip area and expose the silicon oxide layer, thereby completing the preparation of the silicon nitride waveguide. Specifically, the polysilicon layer can be etched back by the ICP machine using a preset flow rate of hydrogen bromide gas, wherein the preset flow rate ranges from 250sccm to 350sccm. The specific process can refer to the above-mentioned process of etching the polysilicon layer by the ICP machine, which will not be described in detail in this embodiment. For example, Figure 7 As shown, Figure 7 A schematic diagram of a fabricated silicon nitride waveguide provided in an embodiment of the present invention.
[0045] As described above, when preparing the silicon nitride waveguide in the embodiment of the present invention, a silicon oxide layer is first deposited on the top silicon layer of the SOI substrate, and then a polysilicon layer is deposited on the silicon oxide layer, and the polysilicon layer is patterned and etched by an ICP machine to form a plurality of staggered polysilicon strip regions and grooves. Afterwards, a silicon nitride layer is deposited on the polysilicon strip regions and the grooves and flattened so that the silicon nitride layer deposited on the grooves is flush with the polysilicon strip regions. Finally, the polysilicon strip regions are backetched by an ICP machine to remove the polysilicon strip regions and expose the silicon oxide layer, thereby completing the preparation of the silicon nitride waveguide.
[0046] The embodiment of the present invention uses an ICP machine to etch polysilicon to prepare a silicon nitride waveguide. Compared with the method of using a CCP machine to etch silicon nitride to prepare a silicon nitride waveguide in the prior art, the IPC machine can accurately control the properties of the plasma and the etching process by adjusting multiple parameters such as power, gas flow, and pressure during the etching process, so that the process parameters can be quickly adjusted according to specific etching requirements to achieve high-precision etching, reduce etching deviation and sidewall roughness, and improve the verticality and resolution of the sidewall of the silicon nitride waveguide area. In addition, since polysilicon has a relatively high selectivity for silicon oxide, it is possible to avoid damaging the silicon dioxide at the bottom during the etching process. The embodiment of the present invention can improve the yield rate of silicon nitride waveguides in the preparation process, and solves the technical problem of low yield rate in the process of preparing silicon nitride waveguides in the prior art.
[0047] The embodiment of the present invention also provides a silicon photonic chip, including a silicon nitride waveguide, and the silicon nitride waveguide is prepared by the above-mentioned silicon nitride waveguide preparation method. When preparing the silicon nitride waveguide in the embodiment of the present invention, a silicon oxide layer is first deposited on the top silicon layer of the SOI substrate, and then a polysilicon layer is deposited on the silicon oxide layer, and the polysilicon layer is patterned and etched by an ICP machine to form a plurality of staggered polysilicon strip regions and grooves. Afterwards, a silicon nitride layer is deposited on the polysilicon strip regions and the grooves and flattened so that the silicon nitride layer deposited on the grooves is flush with the polysilicon strip regions. Finally, the polysilicon strip regions are backetched by an ICP machine to remove the polysilicon strip regions and expose the silicon oxide layer, thereby completing the preparation of the silicon nitride waveguide.
[0048] The embodiment of the present invention uses an ICP machine to etch polysilicon to prepare a silicon nitride waveguide. Compared with the method of using a CCP machine to etch silicon nitride to prepare a silicon nitride waveguide in the prior art, the IPC machine can accurately control the properties of the plasma and the etching process by adjusting multiple parameters such as power, gas flow, and pressure during the etching process, so that the process parameters can be quickly adjusted according to specific etching requirements to achieve high-precision etching, reduce etching deviation and sidewall roughness, and improve the verticality and resolution of the sidewall of the silicon nitride waveguide area. In addition, since polysilicon has a relatively high selectivity for silicon oxide, it is possible to avoid damaging the silicon dioxide at the bottom during the etching process. The embodiment of the present invention can improve the yield rate of silicon nitride waveguides in the preparation process, and solves the technical problem of low yield rate in the process of preparing silicon nitride waveguides in the prior art.
[0049] The embodiment of the present invention also provides an electronic device, the electronic device includes a silicon photonic chip, the silicon photonic chip includes a silicon nitride waveguide, and the silicon nitride waveguide is prepared by the above-mentioned silicon nitride waveguide preparation method. When preparing the silicon nitride waveguide in the embodiment of the present invention, a silicon oxide layer is first deposited on the top silicon layer of the SOI substrate, and then a polysilicon layer is deposited on the silicon oxide layer, and the polysilicon layer is patterned and etched by an ICP machine to form a plurality of staggered polysilicon strip regions and grooves. Afterwards, a silicon nitride layer is deposited on the polysilicon strip regions and the grooves and flattened so that the silicon nitride layer deposited on the grooves is flush with the polysilicon strip regions. Finally, the polysilicon strip regions are backetched by the ICP machine to remove the polysilicon strip regions and expose the silicon oxide layer, thereby completing the preparation of the silicon nitride waveguide.
[0050] The embodiment of the present invention uses an ICP machine to etch polysilicon to prepare a silicon nitride waveguide. Compared with the method of using a CCP machine to etch silicon nitride to prepare a silicon nitride waveguide in the prior art, the IPC machine can accurately control the properties of the plasma and the etching process by adjusting multiple parameters such as power, gas flow, and pressure during the etching process, so that the process parameters can be quickly adjusted according to specific etching requirements to achieve high-precision etching, reduce etching deviation and sidewall roughness, and improve the verticality and resolution of the sidewall of the silicon nitride waveguide area. In addition, since polysilicon has a relatively high selectivity for silicon oxide, it is possible to avoid damaging the silicon dioxide at the bottom during the etching process. The embodiment of the present invention can improve the yield rate of silicon nitride waveguides in the preparation process, and solves the technical problem of low yield rate in the process of preparing silicon nitride waveguides in the prior art.
[0051] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the embodiments of the present invention are not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the embodiments of the present invention. Therefore, although the embodiments of the present invention are described in more detail through the above embodiments, the embodiments of the present invention are not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the embodiments of the present invention, and the scope of the embodiments of the present invention is determined by the scope of the appended claims.
Claims
1. A method for preparing a silicon nitride waveguide, characterized in that: The method comprises: Depositing a silicon oxide layer on a top silicon layer of an SOI substrate, wherein the SOI substrate comprises the top silicon layer, an insulating layer and a bottom silicon layer; Depositing a polysilicon layer on the silicon oxide layer, and pattern-etching the polysilicon layer by an ICP machine to form a plurality of staggered polysilicon strip regions and grooves, wherein the silicon oxide layer is exposed at the bottom of the grooves; Depositing a silicon nitride layer on the polysilicon strip region and the trench; Planarizing the silicon nitride layer so that the silicon nitride layer deposited on the groove is flush with the polysilicon strip region; The polysilicon strip region is etched back by the ICP machine to remove the polysilicon strip region and expose the silicon oxide layer.
2. The method for preparing a silicon nitride waveguide according to claim 1, characterized in that: The step of depositing a polysilicon layer on the silicon oxide layer comprises: A polysilicon layer with a first preset thickness is deposited on the silicon oxide layer, and a value range of the first preset thickness is 50 nm to 80 nm.
3. The method for preparing a silicon nitride waveguide according to claim 1, characterized in that: The polysilicon layer is patterned and etched by an ICP machine to form a plurality of staggered polysilicon strip regions and grooves, including: The polysilicon layer is patterned and dry-etched by using hydrogen bromide gas through an ICP machine to form a plurality of staggered polysilicon strip regions and trenches, wherein the sidewalls of the polysilicon strip regions are perpendicular to the bottoms of the trenches.
4. The method for preparing a silicon nitride waveguide according to claim 3, characterized in that: The method of patterning the polysilicon layer by dry etching with hydrogen bromide gas using an ICP machine includes: The polysilicon layer is patterned dry-etched by using an ICP machine with a preset flow rate of hydrogen bromide gas.
5. The method for preparing a silicon nitride waveguide according to claim 4, characterized in that: The preset flow rate ranges from 250sccm to 350sccm.
6. The method for preparing a silicon nitride waveguide according to claim 1, characterized in that: The step of depositing a silicon nitride layer on the polysilicon strip region and the trench comprises: A silicon nitride layer with a second preset thickness is deposited on the polysilicon strip region and the groove, and a value range of the second preset thickness is 140nm~160nm.
7. The method for preparing a silicon nitride waveguide according to claim 1, characterized in that: The step of etching back the polysilicon strip region by using the ICP machine includes: The polysilicon layer is etched back by using an ICP machine with a preset flow rate of hydrogen bromide gas.
8. The method for preparing a silicon nitride waveguide according to claim 7, characterized in that: The preset flow rate ranges from 250sccm to 350sccm.
9. A silicon photonic chip, characterized in that: It comprises a silicon nitride waveguide, and the silicon nitride waveguide is prepared by the silicon nitride waveguide preparation method according to any one of claims 1 to 8.
10. An electronic device, characterized in that: The electronic device comprises the silicon photonic chip according to claim 9.