Risk control method for aligning double-sided overlay precision and protecting back hole from being over-etched

Abstract

The invention discloses a double-sided overlay precision alignment and back hole over-etching protection risk control method, and relates to the technical field of photoetching overlay. Comprising the following steps: firstly, forming a first layer of overlay pattern and an alignment mark on the front surface of a wafer, and establishing a front surface coordinate system; and calculating local and global offset errors through overlay of coordinate information of two layers of front overlay patterns, determining a comprehensive front overlay error and correcting a front alignment system. And then, the wafer is overturned, the back overlay pattern is processed according to a front alignment mode, a back alignment system is corrected, and double-sided error correction is completed. And finally, by extracting surface characteristic parameters including a photoresist thickness distribution factor and an edge roughness factor, correcting the photoetching depth and obtaining an accurate value, accurate control of the photoetching depth is realized, the risk that the wafer back hole is over-etched is reduced, and the yield of equipment and the performance stability of a product are remarkably improved.

Description

Technical Field

[0001] The invention relates to the technical field of photolithography overlay, and in particular to a method for controlling the risk of double-sided overlay precision alignment and protecting a back hole from over-etching. Background Art

[0002] With the development of the semiconductor industry, double-sided lithography technology has been applied to micro-electro-mechanical systems (MEMS), RF device manufacturing and advanced packaging technology in the semiconductor manufacturing process. In the RF device manufacturing process, double-sided lithography technology can reduce signal attenuation caused by thick metal deposition and protect the risk of over-etching on the front side of the wafer. Double-sided lithography overlay technology directly determines the quality and performance of the product. For example, in the manufacturing process of pressure sensors, the quality and performance of the sensor depends on the alignment accuracy between the front and back process layers of the wafer; the connection pipes in advanced packaging devices need to be arranged arbitrarily, which also puts forward high-precision requirements for the alignment of the front and back of the wafer. For opaque wafers, the alignment system or contact lithography machine cannot measure the mark positions on the front and back of the wafer at the same time. The application of double-sided alignment technology in lithography equipment has derived a new double-sided alignment ("double-sided alignment" or "double-sided overlay error calibration") measurement direction. Double-sided overlay accuracy is defined as the alignment error between the front and back process layers of the wafer. The double-sided alignment measurement tool needs to have a large measurement range, covering the largest possible area on the wafer surface, and the measurement objects include a variety of materials and wafers or thin film layers of different thicknesses. Currently, through mutual feedback calibration of the wafer front alignment system and the wafer back alignment system, the positioning coordinate overlay accuracy of the TSA layer and BSA layer graphics is corrected in time, ensuring the deviation of the wafer front alignment and wafer back alignment overlay accuracy, providing protection for the subsequent metal layer from being etched through, and improving the quality and yield of wafer products.

[0003] Although the existing technologies have proposed methods for error correction through a single-sided alignment system, these technologies have limitations in complex applications of double-sided processing. For example, the front and back alignment marks cannot be completely unified, resulting in the difficulty in controlling the alignment accuracy between the front and back sides at the micron level; at the same time, there is a lack of effective control and compensation mechanisms for the risk of over-etching during the back etching process. Therefore, a more accurate and comprehensive method is needed to solve the problem of error correction and over-etching risk during double-sided overlay.

[0004] In the prior art, the publication number CN103926797A discloses a double-sided overlay system and method for a photolithography device, including step 1: forming a back pattern on the back of a substrate through a previous process; step 2: uploading the substrate to the substrate table, exposing the substrate for the first time, and obtaining a front alignment mark and a front overlay pattern; step 3: downloading the substrate and developing the substrate; step 4: obtaining the relative position error between the overlay pattern and the back pattern; step 5: uploading the substrate again, and performing front alignment according to the front alignment mark; step 6: compensating for the relative position error and exposing the substrate for the second time. However, in this scheme, the compensation of the overlay error is only completed by the front alignment mark, ignoring the help of the back alignment mark, which is prone to inaccurate compensation, especially when there is complex deformation between the front and back patterns or wafer warping. Since the spatial positions of the front alignment mark and the back pattern have not established a direct mathematical relationship, the error compensation accuracy between the front and back is limited. At the same time, no mention is made of the control of over-etching risk. This may cause interference or damage between the back pattern and the front key structure, and reduce the accuracy and effectiveness of the alignment results.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0006] The purpose of the present invention is to provide a method for double-sided overlay precision alignment and risk control of back hole protection from over-etching, so as to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions: A method for double-sided overlay precision alignment and risk control of back hole overetching protection, the specific steps comprising: Forming a first layer of front overlay pattern and alignment mark pattern on the front side of the sample wafer, wherein the alignment mark pattern includes a plurality of front alignment marks and a plurality of back alignment marks, determining position information of the front alignment marks based on a wafer front alignment system in a lithography device, and establishing a wafer front coordinate system based on the acquired position information of the front alignment marks; Based on the established wafer front coordinate system, coordinate information of the first layer of front overlay pattern is determined, and according to the obtained coordinate information of the first layer of front overlay pattern, a second layer of front overlay pattern is formed on the front of the sample wafer, and coordinate information of the second layer of front overlay pattern in the wafer front coordinate system is extracted; Based on the coordinate information of the second layer of front overlay pattern in the wafer front coordinate system and the coordinate information of the first layer of front overlay pattern, several corresponding feature points in the two layers of front overlay pattern are selected and the coordinates of the feature points are recorded, based on the obtained feature point coordinates, the local offset error coefficient and the global error coefficient of the two layers of front overlay pattern are calculated, and the comprehensive front overlay error is determined according to the local offset error coefficient and the global error coefficient; Based on the comprehensive front side overlay error, the wafer front side alignment system in the lithography device is error corrected, the sample wafer is flipped, a first layer of back side overlay pattern is overlaid on the back side of the sample wafer, and the back side overlay error is obtained by using the same processing method as the front side alignment system. Based on the back side overlay error, the wafer back side alignment system in the lithography device is error corrected, and finally, double-side overlay error correction is completed according to the double-side error between the first layer of back side overlay pattern and the first layer of front side overlay pattern; After error correction, the surface characteristic parameters of the overlay pattern are obtained. Based on the obtained surface characteristic parameters, the photoresist thickness distribution factor and the photoresist edge roughness factor are calculated. The photolithography depth is corrected according to the photoresist thickness distribution factor and the photoresist edge roughness factor to obtain the precise depth value of each photolithography point, and the over-etching risk control is completed. The surface characteristic parameters include the photolithography edge roughness and the average thickness of the photoresist.

[0008] Furthermore, based on the position information of the front alignment mark determined by the wafer front alignment system in the lithography device, the specific steps of establishing the wafer front coordinate system include: loading the wafer onto the alignment platform of the lithography machine through a robotic arm or other transmission device, and fixing the wafer on the alignment platform by using the vacuum adsorption or clamping mechanism of the lithography device. The front alignment system in the lithography device will detect the front alignment mark on the wafer through software configuration, and extract the geometric features of the mark by performing image processing on the detected mark, wherein the geometric features include the center position and edge point coordinates, the reference line between the marks is defined as the X-axis of the wafer front coordinate system, the center position of the mark is defined as the coordinate origin, and the direction perpendicular to the X-axis is the Y-axis, thereby establishing the wafer front coordinate system.

[0009] Further, based on the coordinate information of the second layer of front overlay pattern in the wafer front coordinate system and the coordinate information of the first layer of front overlay pattern, the coordinates of several corresponding feature points in the two layers of front overlay pattern are selected, wherein the logic for selecting the coordinates of several corresponding feature points in the two layers of front overlay pattern is: randomly select the first layer of front overlay pattern. feature points, record the coordinate information of each feature point, denoted as , and then overlay the pattern on the second layer to determine the corresponding feature points, record the coordinate information of each feature point, denoted as ,in is the index of the feature point, and .

[0010] Further, based on the obtained coordinates of the corresponding feature points, the local offset error coefficient and the global error coefficient of the two-layer front overlay pattern are calculated, wherein the formula for calculating the local offset error coefficient of the two-layer front overlay pattern is: ; In the formula, represents the local offset error coefficient of the i-th group of corresponding feature points, is the radial distance from the i-th group of feature points to the center of the wafer; The formula for calculating the global error coefficient of the two-layer front overlay pattern is: ; In the formula, is the global error coefficient of the two-layer front overlay pattern, is the scaling factor of the sample wafer, is the rotation angle of the sample wafer.

[0011] Furthermore, the rotation angle of the sample wafer is The calculation is based on the formula: ; In the formula, and They are the corresponding feature points of the two layers of front overlay patterns. Axis and Average offset error of the axis; in and The calculations are based on the following formulas: ; ; Among them, the scaling factor of the sample wafer is Corrected by ambient temperature and the clamping stress applied to the sample wafer, the calculation is based on the formula: ; In the formula, is the initial scaling factor of the sample wafer, is the average ambient temperature during the overlay process, is the reference temperature, is the clamping stress applied to the sample wafer, is the Young's modulus of the sample wafer, is the Poisson’s ratio of the sample wafer.

[0012] Furthermore, the comprehensive front overlay error is determined according to the local offset error coefficient and the global error coefficient, wherein the formula for calculating the comprehensive front overlay error is: ; In the formula, is the comprehensive front overlay error of the i-th feature point, and are the weight coefficients of the local offset error coefficient and the global error coefficient, respectively, where and and All are greater than 0; The calculation method of back side overlay error and double-side error is the same as that of comprehensive front side overlay error.

[0013] Further, based on the obtained surface characteristic parameters, the photoresist thickness distribution factor and the photoresist edge roughness factor are calculated, wherein the photoresist thickness distribution factor is calculated based on the formula: ; In the formula, The photoresist thickness distribution factor of the i-th feature point, is the local thickness of the photoresist at the i-th feature point, is the average thickness of the photoresist on the sample wafer surface, is the amplitude constant of the thickness distribution, is the maximum radius of the sample wafer; The formula for calculating the photoresist edge roughness factor is: ; In the formula, is the photoresist edge roughness factor of the i-th feature point, is the lithography edge roughness of the i-th feature point, is the ideal edge roughness value.

[0014] Furthermore, the photolithography depth is corrected according to the photoresist thickness distribution factor and the photoresist edge roughness factor to obtain the precise depth value of each photolithography point, wherein the formula for calculating the precise depth value of each photolithography point is: ; In the formula, is the precise depth value of the i-th feature point, is the initial overlay depth value of the i-th feature point.

[0015] Compared with the prior art, the present invention has the following beneficial effects: First, by forming alignment marks on the front side and using the front alignment system of the lithography device to establish the wafer front coordinate system, the scheme further unifies the coordinate information on the front and back sides, and realizes the precise superposition between multi-layer patterns. In particular, in the alignment process of the front and back sides, the interactive correction method of the front and back alignment marks is adopted, which significantly reduces the local offset error and global error caused by the non-uniform coordinate system in the traditional method, thereby meeting the manufacturing requirements of high-precision devices. Secondly, in view of the risk of over-etching in the back lithography process, a method for correcting the etching depth based on the surface characteristic parameters of the photoresist is proposed. By extracting the photoresist thickness distribution factor, the depth distribution of each lithography point can be calculated more accurately, and the possible etching abnormal area can be predicted by analyzing the edge roughness factor, and finally the precise control of the lithography depth can be achieved. The over-etching problem caused by uneven photoresist thickness or insufficient edge roughness control in the traditional etching process is solved, and the accuracy and stability of the etching process are significantly improved. Finally, through the comprehensive error correction of the front and back sides, not only the overall accuracy of the double-sided overlay is improved, but also the control process of the lithography depth is optimized, thereby effectively reducing the risk of over-etching of the wafer back hole. The yield of the equipment and the performance stability of the product have been significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the overall method flow of the present invention; Figure 2 A schematic diagram of the specific shape of wafer overlay marking; Figure 3 A schematic diagram of forming a first layer of front overlay pattern on the front side of a wafer; Figure 4 To determine the position of the front alignment mark, a schematic diagram of the wafer front coordinates is established; Figure 5 A schematic diagram of forming a second layer of front overlay pattern on the front side of the wafer; Figure 6 A schematic diagram for determining the overlay error on the front side of the wafer and the overlay error on the back side; Figure 7 Schematic diagram of wafer overlay error calibration. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0018] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0019] Example: See also Figure 1-Figure 7 , the present invention provides a technical solution: A method for double-sided overlay precision alignment and risk control of back hole overetching protection, the specific steps comprising: Step 1: Form a first layer of front overlay pattern and alignment mark pattern on the front side of a sample wafer, wherein the alignment mark pattern includes a plurality of front alignment marks and a plurality of back alignment marks, and determine the position information of the front alignment marks based on a wafer front alignment system in a lithography device, so as to obtain the position information of the front alignment marks and establish a wafer front coordinate system.

[0020] Based on the TSA (wafer front) and BSA (wafer back) travel range, the first set of engraving marks on the first pattern layer on the front of the wafer is made into two cross-shaped solid bar marks with a pattern of alignment marks, and the first set of engraving marks on the first pattern layer on the back of the wafer is made into two cross-shaped hollow bar marks. The cross-shaped hollow bar mark on the back is selected to be about 10um larger than the cross-shaped solid bar mark on the front. The cross-shaped engraving mark is the same as the actual pattern. All of them are engraved through the mask.

[0021] Based on the wafer front alignment system in the lithography device, the position information of the front alignment mark is determined to obtain the position information of the front alignment mark. The specific steps of establishing the wafer front coordinate system include: loading the wafer onto the alignment platform of the lithography machine through a robotic arm or other transmission device, and fixing the wafer on the alignment platform by using the vacuum adsorption or clamping mechanism of the lithography device. The front alignment system in the lithography device will detect the front alignment mark on the wafer through software configuration, and extract the geometric features of the mark by performing image processing on the detected mark. The geometric features include the center position and edge point coordinates. The reference line between the marks is defined as the X-axis of the wafer front coordinate system, the center position of the mark is defined as the coordinate origin, and the direction perpendicular to the X-axis is the Y-axis, so as to establish the wafer front coordinate system.

[0022] Step 2: Based on the established wafer front coordinate system, determine the coordinate information of the first layer of front overlay pattern, form a second layer of front overlay pattern on the front of the sample wafer according to the obtained coordinate information of the first layer of front overlay pattern, and extract the coordinate information of the second layer of front overlay pattern in the wafer front coordinate system.

[0023] Based on the coordinate information of the second layer of front overlay pattern in the wafer front coordinate system and the coordinate information of the first layer of front overlay pattern, the coordinates of several corresponding feature points in the two layers of front overlay pattern are selected, wherein the logic for selecting the coordinates of several corresponding feature points in the two layers of front overlay pattern is: randomly select feature points, record the coordinate information of each feature point, denoted as , and then overlay the pattern on the second layer to determine the corresponding feature points, record the coordinate information of each feature point, denoted as ,in is the index of the feature point, and .

[0024] Step 3: Based on the coordinate information of the second layer of front overlay pattern in the wafer front coordinate system and the coordinate information of the first layer of front overlay pattern, select several corresponding feature points in the two layers of front overlay patterns and record the feature point coordinates, and based on the obtained feature point coordinates, calculate the local offset error coefficient and the global error coefficient of the two layers of front overlay patterns, and determine the comprehensive front overlay error according to the local offset error coefficient and the global error coefficient.

[0025] Based on the corresponding feature point coordinates, the local offset error coefficient and the global error coefficient of the two-layer front overlay pattern are calculated, wherein the formula for calculating the local offset error coefficient of the two-layer front overlay pattern is: ; In the formula, represents the local offset error coefficient of the i-th group of corresponding feature points, is the radial distance from the i-th group of feature points to the center of the wafer; It should be noted that the local offset error coefficient of the i-th group of corresponding feature points is By combining geometric deviation and structural deviation, it is used to characterize the local offset error of each feature point, where the local offset error coefficient The larger the value, the more offset and the greater the error.

[0026] The radial distance from the i-th group of feature points to the wafer center In lithography and overlay, environmental factors in local areas (such as mechanical vibration, temperature gradient, or equipment accuracy) may cause additional offsets. By including local offsets, the actual error of the i-th point can be quantified more accurately, rather than relying solely on geometric offsets. The error distribution on the wafer is usually not uniform. The error in the center area may be small, while the error in the edge area may be amplified due to the influence of equipment optical distortion, mechanical error, etc. Therefore, the radial distance from the i-th group of feature points to the center of the wafer is The local offset error coefficient of the feature points corresponding to the i-th group Proportional, through the logarithmic function Indicates the radial distance from the i-th feature point to the center of the wafer when it is in the center area of ​​the wafer The influence on the local offset error coefficient gradually decreases, and the radial distance from the i-th group of feature points to the center of the wafer is is the average distance between the feature points corresponding to the first and second layer overlay patterns and the center of the wafer. The method for obtaining is: use high-precision measurement equipment (such as laser rangefinder, coordinate measuring machine or optical microscope) to directly measure the position of the feature points on the wafer, and calculate the Euclidean distance between the first layer overlay pattern and the second layer overlay pattern based on the coordinates of the feature point position and the coordinates of the wafer center. The average value of this data is used as the radial distance from the i-th group of feature points to the wafer center. .

[0027] The formula for calculating the global error coefficient of the two-layer front overlay pattern is: ; In the formula, is the global error coefficient of the two-layer front overlay pattern, is the scaling factor of the sample wafer, is the rotation angle of the sample wafer.

[0028] Among them, the global error coefficient of the two-layer front overlay pattern is By combining the scaling factor of the sample wafer and the rotation angle of the sample wafer, it is used to describe the influence of the global deformation of the wafer in the photolithography process on the overlay error. The global error coefficient of the two-layer front overlay pattern The larger the value, the greater the overlay error.

[0029] The scaling factor of the sample wafer is , which represents the dimensional change of the wafer during the lithography process due to environmental factors (such as temperature) or material properties. During the lithography process, the wafer may undergo global deformation due to the following factors: the wafer will expand or contract due to the temperature of the processing equipment; mechanical stress: for example, stretching or compression may be introduced during loading, clamping or alignment, so the expansion and contraction scale factor of the sample wafer The larger the value, the greater the interference to the wafer, and the larger the overlay error. Therefore, the scaling factor of the sample wafer is Global error coefficient of the two-layer front overlay pattern Directly proportional.

[0030] Rotation angle of sample wafer The deformation of the wafer is usually two-dimensional. The rotation angle of the wafer describes the rotation of the entire wafer during the photolithography process. Therefore, the larger the rotation angle of the wafer, the greater the deviation during the photolithography process. Therefore, the rotation angle of the sample wafer Global error coefficient of the two-layer front overlay pattern Directly proportional.

[0031] The rotation angle of the sample wafer The calculation is based on the formula: ; In the formula, and They are the corresponding feature points of the two layers of front overlay patterns. Axis and Average offset error of the axis; in and The calculations are based on the following formulas: ; ; Among them, the scaling factor of the sample wafer is Corrected by ambient temperature and the clamping stress applied to the sample wafer, the calculation is based on the formula: ; In the formula, is the initial scaling factor of the sample wafer, is the average ambient temperature during the overlay process, is the reference temperature, is the clamping stress applied to the sample wafer, is the Young's modulus of the sample wafer, is the Poisson’s ratio of the sample wafer.

[0032] Among them, the scaling factor of the sample wafer is , the initial scaling factor of the sample wafer is determined by material characteristics and ambient temperature Dynamic correction is performed.

[0033] The thermal expansion of the wafer is mainly caused by the temperature gradient, that is, the temperature difference in different areas of the wafer will lead to uneven expansion. Therefore, in the actual lithography process, the expansion ratio factor needs to be characterized in combination with the temperature distribution of the wafer. The greater the difference between the ambient temperature and the reference temperature during the overlay process, the easier it is to produce thermal expansion of the wafer. Therefore, the difference between the ambient temperature and the reference temperature during the overlay process is proportional to the expansion ratio factor of the sample wafer.

[0034] Clamping stress applied to the sample wafer The larger the value, the greater the mechanical force on the wafer, and the mechanical force will cause the wafer to deform. Therefore, the clamping stress applied to the sample wafer is Scaling factor with sample wafer Directly proportional.

[0035] Young's modulus and Poisson's ratio of the sample wafer. The larger the Young's modulus of the material, the smaller the strain (deformation) produced when the material is subjected to the same stress, and the less likely the material is to deform. For Poisson's ratio, the larger the Poisson's ratio of the material, the more obvious the material shrinks in the lateral direction. Therefore, the expansion ratio factor of the sample wafer is It is inversely proportional to the Young's modulus of the sample wafer, and the inverse relationship is expressed by a fraction; it is directly proportional to the Poisson's ratio of the sample wafer. Generally take 25 .

[0036] The comprehensive front overlay error is determined according to the local offset error coefficient and the global error coefficient, wherein the formula for calculating the comprehensive front overlay error is: ; In the formula, is the comprehensive front overlay error of the i-th feature point, and are the weight coefficients of the local offset error coefficient and the global error coefficient, respectively, where and and Both are greater than 0.

[0037] Among them, since the larger the local offset error coefficient and the global error coefficient, the larger the offset error, the greater the comprehensive front overlay error of the i-th feature point. Proportional to, where the square root form Reduce the impact of the global error coefficient on the comprehensive front overlay error.

[0038] And because the local offset error coefficient is aimed at specific feature points, and the global error coefficient is used to correct the accuracy based on the local offset error, it is set and and Both are greater than 0.

[0039] Step 4: Based on the comprehensive front side overlay error, the error of the wafer front side alignment system in the lithography device is corrected, the sample wafer is flipped over, and the first layer of back side overlay pattern is overlaid on the back side of the sample wafer. The same processing method as the front side alignment system is used to obtain the back side overlay error. Based on the back side overlay error, the error of the wafer back side alignment system in the lithography device is corrected, and finally the double-sided overlay error correction is completed according to the double-sided error between the first layer of back side overlay pattern and the first layer of front side overlay pattern.

[0040] The comprehensive front overlay error refers to the offset error between the wafer front pattern (current photolithography layer) and the manufactured pattern (bottom layer). It is the superposition result of multiple errors, including position offset, rotation error, telescopic error, etc. The front alignment system of the wafer in the lithography device is corrected according to the comprehensive front overlay error. The error correction can be achieved by equipping a modern lithography machine with a high-precision stepper motor and feedback control system. The error determination is detected by the wafer clamping device.

[0041] The front side coordinates of the substrate are established by determining the position of the front side alignment mark by using the front side alignment system; based on the front side coordinates of the substrate, a second layer of front side overlay pattern is formed on the front side of the substrate; the position error between the first layer of front side overlay pattern and the second layer of front side overlay pattern is measured; according to the position error between the first layer of front side overlay pattern and the second layer of front side overlay pattern, a first overlay error calibration is performed, i.e., the overlay error on the front side of the substrate is calibrated; then, the substrate is flipped over, and the position of the back side alignment mark is determined by using the back side alignment system, and the back side coordinates of the substrate are established; based on the back side coordinates of the substrate, a first layer of back side overlay pattern and a second layer of back side overlay pattern are formed on the back side of the substrate; the position error between the first layer of back side overlay pattern and the second layer of back side overlay pattern is measured; according to the position error between the first layer of back side overlay pattern and the second layer of back side overlay pattern, a second overlay error calibration is performed, i.e., the overlay error on the back side of the substrate is calibrated. Therefore, by flipping the substrate once, the overlay error on the front side and the overlay error on the back side of the substrate can be calibrated, that is, by flipping the substrate once, the double-sided overlay error calibration of the substrate can be achieved, the calibration efficiency is high, the overlay accuracy is high, the graphic protection is good, and the risk of over-etching of the BSA layer can be effectively reduced.

[0042] The backside overlay error and double-side error are calculated in the same way as the comprehensive frontside overlay error, and the radial distance from the feature point to the center of the wafer in the double-side error calculation uses the radial distance data described in the frontside overlay, which will not be elaborated here.

[0043] Step 5: After error correction, obtain the surface characteristic parameters of the overlay pattern. Based on the obtained surface characteristic parameters, calculate the photoresist thickness distribution factor and the photoresist edge roughness factor. According to the photoresist thickness distribution factor and the photoresist edge roughness factor, correct the photolithography depth to obtain the precise depth value of each photolithography point, and complete the over-etching risk control. The surface characteristic parameters include the photolithography edge roughness and the average thickness of the photoresist.

[0044] Based on the obtained surface characteristic parameters, the photoresist thickness distribution factor and the photoresist edge roughness factor are calculated, wherein the formula for calculating the photoresist thickness distribution factor is: ; In the formula, The photoresist thickness distribution factor of the i-th feature point, is the local thickness of the photoresist at the i-th feature point, is the average thickness of the photoresist on the sample wafer surface, is the amplitude constant of the thickness distribution, is the maximum radius of the sample wafer; Among them, the photoresist thickness distribution factor of the i-th feature point is Used to characterize the effect of photoresist thickness on overlay depth, where the photoresist thickness distribution factor of the i-th feature point is The larger it is, the thicker the photoresist thickness is at that feature point. During overlay, the overlay depth can be increased to meet actual requirements.

[0045] The local thickness of the photoresist at the i-th feature point is Directly characterize the local thickness of the photoresist, so the local thickness of the photoresist at the i-th feature point is and The photoresist thickness distribution factor of the i-th feature point is proportional to the average thickness of the photoresist, and the proportional relationship is characterized by the ratio to the average thickness of the photoresist.

[0046] It is used to describe the periodic distribution of radial thickness, especially for the non-uniformity of the edge and center of the wafer. During the wafer manufacturing process, the edge of the wafer is usually thinned and chamfered to avoid the wafer edge being too sharp (which may cause the wafer to be fragile during handling and processing). This treatment will make the thickness of the edge area slightly smaller than that of the center. Therefore, due to the slightly smaller thickness in the edge area, the overlay depth should be increased to reach the actual required depth.

[0047] The formula for calculating the photoresist edge roughness factor is: ; In the formula, is the photoresist edge roughness factor of the i-th feature point, is the lithography edge roughness of the i-th feature point, is the ideal edge roughness value.

[0048] Among them, the larger the photoresist edge roughness factor is, the rougher the photoresist edge is, resulting in reduced mask protection effect, more exposed substrate area, and deeper etching reaction. Therefore, the larger the photoresist edge roughness factor is, the lower the overlay depth should be to avoid the risk of over-etching.

[0049] The methods for obtaining the local thickness and average thickness of the photoresist include: Ellipsometer: determining the thickness of the photoresist by measuring the phase change of polarized light; Optical Interferometer: using a multi-wavelength light source for interference measurement to achieve distribution analysis of local thickness.

[0050] The method for obtaining the maximum radius of the sample wafer is as follows: during wafer manufacturing and processing, the size parameters of the wafer (including the maximum radius) are usually provided by the production equipment.

[0051] Lithography edge roughness and ideal edge roughness values ​​can be measured by scanning the edge of the lithography pattern with an electron beam to obtain a high-resolution edge morphology image, extracting the edge profile through an image processing algorithm, comparing the actual edge with the ideal edge, and calculating the edge roughness based on the degree of deviation of the edge profile. In semiconductor manufacturing, different lithography processes and equipment usually have specific ideal edge roughness reference values, which are often provided by equipment suppliers or research institutions.

[0052] Among them, the amplitude constant of the thickness distribution is Determined experimentally by spectroscopic ellipsometry, it is typically between 0.01–0.05.

[0053] The photolithography depth is corrected according to the photoresist thickness distribution factor and the photoresist edge roughness factor to obtain the precise depth value of each photolithography point. The formula for calculating the precise depth value of each photolithography point is: ; In the formula, is the precise depth value of the i-th feature point, is the initial overlay depth value of the i-th feature point.

[0054] Since the above is to illustrate the correlation between the photoresist thickness distribution factor and the photoresist edge roughness factor and the overlay depth, that is, the precise depth value of the i-th feature point It is proportional to the resist thickness distribution factor, inversely proportional to the resist edge roughness factor, and proportional to the square root of and logarithmic functions Avoid over-correction in the form of

[0055] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0056] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product. Those skilled in the art may appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein may be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software methods depends on the specific application and design constraints of the technical solution.

[0057] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0058] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A method for double-sided overlay precision alignment and back hole protection from over-etching risk control, characterized in that: The specific steps include: Forming a first layer of front overlay pattern and alignment mark pattern on the front side of the sample wafer, wherein the alignment mark pattern includes a plurality of front alignment marks and a plurality of back alignment marks, determining position information of the front alignment marks based on a wafer front alignment system in a lithography device, and establishing a wafer front coordinate system based on the acquired position information of the front alignment marks; Based on the established wafer front coordinate system, coordinate information of the first layer of front overlay pattern is determined, and according to the obtained coordinate information of the first layer of front overlay pattern, a second layer of front overlay pattern is formed on the front of the sample wafer, and coordinate information of the second layer of front overlay pattern in the wafer front coordinate system is extracted; Based on the coordinate information of the second layer of front overlay pattern in the wafer front coordinate system and the coordinate information of the first layer of front overlay pattern, several corresponding feature points in the two layers of front overlay pattern are selected and the coordinates of the feature points are recorded, based on the obtained feature point coordinates, the local offset error coefficient and the global error coefficient of the two layers of front overlay pattern are calculated, and the comprehensive front overlay error is determined according to the local offset error coefficient and the global error coefficient; Based on the comprehensive front side overlay error, the wafer front side alignment system in the lithography device is error corrected, the sample wafer is flipped, a first layer of back side overlay pattern is overlaid on the back side of the sample wafer, and the back side overlay error is obtained by using the same processing method as the front side alignment system. Based on the back side overlay error, the wafer back side alignment system in the lithography device is error corrected, and finally, double-side overlay error correction is completed according to the double-side error between the first layer of back side overlay pattern and the first layer of front side overlay pattern; After error correction, the surface characteristic parameters of the overlay pattern are obtained. Based on the obtained surface characteristic parameters, the photoresist thickness distribution factor and the photoresist edge roughness factor are calculated. The photolithography depth is corrected according to the photoresist thickness distribution factor and the photoresist edge roughness factor to obtain the precise depth value of each photolithography point, and the over-etching risk control is completed. The surface characteristic parameters include the photolithography edge roughness and the average thickness of the photoresist.

2. A method for double-sided overlay precision alignment and back hole protection from over-etching risk control according to claim 1, characterized in that: Based on the wafer front alignment system in the lithography device, the position information of the front alignment mark is determined to obtain the position information of the front alignment mark. The specific steps of establishing the wafer front coordinate system include: loading the wafer onto the alignment platform of the lithography machine through a robotic arm or other transmission device, and fixing the wafer on the alignment platform by using the vacuum adsorption or clamping mechanism of the lithography device. The front alignment system in the lithography device will detect the front alignment mark on the wafer through software configuration, and extract the geometric features of the mark by performing image processing on the detected mark. The geometric features include the center position and edge point coordinates. The reference line between the marks is defined as the X-axis of the wafer front coordinate system, the center position of the mark is defined as the coordinate origin, and the direction perpendicular to the X-axis is the Y-axis, so as to establish the wafer front coordinate system.

3. A method for double-sided overlay precision alignment and back hole protection from over-etching risk control according to claim 2, characterized in that: Based on the coordinate information of the second layer of front overlay pattern in the wafer front coordinate system and the coordinate information of the first layer of front overlay pattern, the coordinates of several corresponding feature points in the two layers of front overlay pattern are selected, wherein the logic for selecting the coordinates of several corresponding feature points in the two layers of front overlay pattern is: randomly select feature points, record the coordinate information of each feature point, denoted as , and then overlay the pattern on the second layer to determine the corresponding feature points, record the coordinate information of each feature point, denoted as ,in is the index of the feature point, and .

4. A method for double-sided overlay precision alignment and back hole protection from over-etching risk control according to claim 3, characterized in that: Based on the corresponding feature point coordinates, the local offset error coefficient and the global error coefficient of the two-layer front overlay pattern are calculated, wherein the formula for calculating the local offset error coefficient of the two-layer front overlay pattern is: ； In the formula, represents the local offset error coefficient corresponding to the i-th group of feature points, is the radial distance from the i-th group of feature points to the center of the wafer; The formula for calculating the global error coefficient of the two-layer front overlay pattern is: ； In the formula, is the global error coefficient of the two-layer front overlay pattern, is the scaling factor of the sample wafer, is the rotation angle of the sample wafer.

5. A method for double-sided overlay precision alignment and back hole protection from over-etching risk control according to claim 4, characterized in that: The rotation angle of the sample wafer The calculation is based on the formula: ； In the formula, and They are the feature points corresponding to the two layers of front overlay patterns. Axis and Average offset error of the axis; in and The calculations are based on the following formulas: ； ； Among them, the scaling factor of the sample wafer is Corrected by ambient temperature and the clamping stress applied to the sample wafer, the calculation is based on the formula: ； In the formula, is the initial scaling factor of the sample wafer, is the average ambient temperature during the overlay process, is the reference temperature, is the clamping stress applied to the sample wafer, is the Young's modulus of the sample wafer, is the Poisson’s ratio of the sample wafer.

6. A method for double-sided overlay precision alignment and back hole protection from over-etching risk control according to claim 4, characterized in that: The comprehensive front overlay error is determined according to the local offset error coefficient and the global error coefficient, wherein the formula for calculating the comprehensive front overlay error is: ； In the formula, is the comprehensive front overlay error of the i-th feature point, and are the weight coefficients of the local offset error coefficient and the global error coefficient, respectively, where and and All are greater than 0; The calculation method of back side overlay error and double-side error is the same as that of comprehensive front side overlay error.

7. A method for double-sided overlay precision alignment and back hole protection from over-etching risk control according to claim 4, characterized in that: Based on the obtained surface characteristic parameters, the photoresist thickness distribution factor and the photoresist edge roughness factor are calculated, wherein the formula for calculating the photoresist thickness distribution factor is: ； In the formula, The photoresist thickness distribution factor of the i-th feature point, is the local thickness of the photoresist at the i-th feature point, is the average thickness of the photoresist on the sample wafer surface, is the amplitude constant of the thickness distribution, is the maximum radius of the sample wafer; The formula for calculating the photoresist edge roughness factor is: ； In the formula, is the photoresist edge roughness factor of the i-th feature point, is the lithography edge roughness of the i-th feature point, is the ideal edge roughness value.

8. A method for double-sided overlay precision alignment and back hole protection from over-etching risk control according to claim 7, characterized in that: The photolithography depth is corrected according to the photoresist thickness distribution factor and the photoresist edge roughness factor to obtain the precise depth value of each photolithography point. The formula for calculating the precise depth value of each photolithography point is: ； In the formula, is the precise depth value of the i-th feature point, is the initial overlay depth value of the i-th feature point.

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