Voltage selection circuit, multi-stage voltage selection circuit, chip and voltage stabilizer

Abstract

The embodiment of the invention provides a voltage selection circuit, a multi-stage voltage selection circuit, a chip and a voltage stabilizer. The voltage selection circuit comprises a first PMOS tube, the grid electrode of the first PMOS tube receives a first voltage, and the source electrode of the first PMOS tube receives a second voltage; the grid electrode of the second NMOS tube receives the first voltage, and the drain electrode of the second NMOS tube receives the second voltage; the drain electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube and outputs voltage VG; and the selection module is connected with the source electrode of the third NMOS transistor and the drain electrode of the first PMOS transistor to receive the voltage VG, and is configured to receive the first voltage and the second voltage, select a voltage VMAX1 from the first voltage and the second voltage and output the voltage VMAX1, and the voltage VMAX1 is further applied to the grid electrode of the third NMOS transistor.

Description

Technical Field

[0001] The present invention relates to the field of circuit control technology, and more specifically, to a voltage selection circuit, a multi-stage voltage selection circuit, a chip and a voltage stabilizer. Background Art

[0002] In the design process of, for example, a digital distributed low-dropout linear regulator (DLDO), it is necessary to select between different voltages and select a higher voltage as a driver. Considering the specific design requirements of the voltage range of the power supply of the DLDO, a selection circuit that can effectively select the voltage is needed to achieve voltage output and effectively use the selected voltage for driving.

[0003] In the current voltage selection circuit, generally speaking, it is possible to select and drive voltages among different voltages with large differences. However, if the voltages to be selected are close to each other, it is difficult for the current voltage selection circuit to achieve the voltage selection function, and even if a voltage is selected, it is difficult to make it have a strong driving capability.

[0004] Therefore, there is a need for a voltage selection circuit, a multi-level voltage selection circuit, a chip and a voltage regulator that can compare and select voltages between voltages with relatively close voltage differences and can make the selected voltage have a stronger driving capability. Summary of the invention

[0005] According to one aspect of the present invention, a voltage selection circuit is provided, comprising: a first PMOS tube, a gate of the first PMOS tube receiving a first voltage, and a source of the first PMOS tube receiving a second voltage; a second NMOS tube, a gate of the second NMOS tube receiving the first voltage, and a drain of the second NMOS tube receiving the second voltage; a third NMOS tube, a drain of the third NMOS tube connected to the source of the second NMOS tube, a source of the third NMOS tube connected to the drain of the first PMOS tube and outputting a voltage VG; a selection module, the selection module connecting the source of the third NMOS tube and the drain of the first PMOS tube to receive the voltage VG, and being configured to receive the first voltage and the second voltage, and select a voltage VMAX1 from the first voltage and the second voltage for output, and the voltage VMAX1 is also applied to the gate of the third NMOS tube.

[0006] In one example, the selection module includes: a fourth PMOS tube, the gate of the fourth PMOS tube receives the voltage VG, and the source of the fourth PMOS tube receives the first voltage; a fifth PMOS tube, the gate of the fifth PMOS tube receives the first voltage, the source of the fifth PMOS tube receives the second voltage, and the drain of the fifth PMOS tube is connected to the drain of the fourth PMOS tube and outputs the voltage VMAX1.

[0007] In an example, the voltage VG outputted by the source of the third NMOS tube and the drain of the first PMOS tube further includes a driving module, and the driving module is used to increase the leakage current at the voltage VG.

[0008] In one example, the driving module includes at least one of the following: one or more NMOS tubes; one or more resistors; one or more current sources.

[0009] In one example, when the driving module includes multiple NMOS tubes, the multiple NMOS tubes are connected in series, the source of each stage of the NMOS tube is connected to the drain of the next stage of the NMOS tube, the drain of the first stage of the NMOS tube receives the voltage VG, the last stage of the NMOS tube is grounded, and the gate of each stage of the NMOS tube receives a high level respectively.

[0010] In an example, the high level is the first voltage or the second voltage.

[0011] In one example, when the driving module includes a plurality of resistors, the plurality of resistors are connected in series, one end of the series-connected resistor is connected to the voltage VG, and the other end is grounded.

[0012] According to another aspect of the present invention, a multi-stage voltage selection circuit is provided, comprising: a plurality of cascaded voltage selection circuits as described in any one of the above items, wherein the voltage selection circuit of the first stage inputs the first voltage V1 and the second voltage V2, and outputs a selected voltage VMAX1; the subsequent n+1th stage voltage selection circuits respectively input the voltage VMAX selected by the previous stage voltage selection circuit n and the voltage V to be selected n+2 , and output from VMAX n and V n+2 The voltage VMAX selected in n+1 , where n is a positive integer greater than or equal to 1.

[0013] According to another aspect of the present invention, there is further provided a chip, comprising: the voltage selection circuit as described in any one of the above items, or the multi-stage voltage selection circuit as described in the above items.

[0014] According to another aspect of the present invention, a voltage regulator is provided, comprising the chip as described above.

[0015] According to the voltage selection circuit, multi-stage voltage selection circuit, chip and voltage regulator of the embodiment of the present invention, the third NMOS tube receiving the voltage VMAX1 through the gate in the circuit can make VG also produce a voltage drop correspondingly when the voltage VMAX1 produces a voltage drop due to driving the load circuit, thereby avoiding the problem that the selection module is difficult to select from the first voltage and the second voltage because VG cannot be linked with the voltage VMAX1 when performing voltage selection. The embodiment of the present invention can perform stable voltage comparison and selection between voltages with relatively close voltage differences, and can make the selected voltage have a strong driving capability.

[0016] In addition, through the further setting of the driving module in the embodiment of the present invention, the leakage current at the voltage VG is further increased, thereby increasing the voltage difference |Vgs| between the gate-source of the second NMOS tube and the third NMOS tube, reducing the on-resistance in the selection module, and further increasing the driving capability of the selected voltage VMAX1. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments of the present invention or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings of the embodiments of the present invention.

[0018] Figure 1 A schematic diagram of a voltage selection circuit according to an embodiment of the present invention is shown;

[0019] Figure 2 A specific structural schematic diagram of a selection module in a voltage selection circuit according to an embodiment of the present invention is shown;

[0020] Figure 3 A schematic diagram showing a voltage selection circuit including a driving module according to an embodiment of the present invention is shown;

[0021] Figure 4 A schematic diagram of a voltage selection circuit according to an embodiment of the present invention is shown, wherein a driving module of the voltage selection circuit includes a plurality of NMOS tubes connected in series;

[0022] Figure 5 A schematic diagram showing substrate voltage access of a MOS tube in a voltage selection circuit according to an example of an embodiment of the present invention is shown;

[0023] Figure 6A schematic structural diagram of a multi-stage voltage selection circuit according to another example of an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only embodiments of a part of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0025] Before proceeding to the description of the following specific embodiments, it may be advantageous to set forth the definitions of certain words and phrases used throughout this patent document. The terms "include" and "comprising" and their derivatives are meant to include but are not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean to include, be included in, be connected to, be interconnected with, contain, be contained in, be connected to or be connected with, be coupled to or be coupled with, be able to communicate with, collaborate with, be intertwined, be juxtaposed, be close to, be bound to or be bound with, have, have... attributes, have... relationships or have relationships with, etc. The term "controller" means any device, system or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or in a combination of hardware and software and / or firmware. The functions associated with any particular controller may be centralized or distributed, local or remote.

[0026] The terms used to describe the embodiments of the present invention are not intended to limit and / or define the scope of the present invention. For example, unless otherwise defined, the technical terms or scientific terms used in this disclosure should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs.

[0027] It should be understood that the words "first", "second" and the like used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Unless the context clearly indicates otherwise, the singular forms "a", "an" or "the" and the like do not indicate quantity limitation, but indicate the presence of at least one.

[0028] As used herein, any reference to "one example" or "example", "one embodiment" or "embodiment" means that a particular element, feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment. The phrases "in one embodiment" or "in an example" appearing in different places in the specification do not necessarily all refer to the same embodiment.

[0029] It will be further understood that the terms "include" or "comprises" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0030] The various embodiments discussed below used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure.

[0031] In the design process of a digital distributed low-dropout linear regulator (DLDO), due to the variation in the setting range of the power supply voltage, when some circuits in the DLDO need to select a voltage from different voltages for driving, it is difficult to meet the demand of selecting a voltage between relatively close voltages.

[0032] Therefore, a voltage selection circuit and corresponding chip and voltage regulator are needed, which can not only select a higher voltage when two power supply voltages are close, but also ensure that the selected voltage has a considerable driving capability.

[0033] In addition, a multi-stage voltage selection circuit and a corresponding chip and a voltage regulator are also needed, which can select a voltage from multiple voltages by cascading the voltage selection circuits and perform driving operations.

[0034] Figure 1 A schematic diagram of a voltage selection circuit according to an embodiment of the present invention is shown.

[0035] like Figure 1 As shown, the voltage selection circuit 1 may include at least a first PMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3 and a selection module N1. Figure 1In the embodiment, the gate of the first PMOS tube M1 can receive the first voltage V1, and the source of the first PMOS tube M1 can receive the second voltage V2. The gate of the second NMOS tube M2 can receive the first voltage V1, and the drain of the second NMOS tube can receive the second voltage V2. The drain of the third NMOS tube M3 can be connected to the source of the second NMOS tube, and the source of the third NMOS tube M3 can be connected to the drain of the first PMOS tube M1 and output the voltage VG. In addition, the selection module N1 can connect the source of the third NMOS tube M3 to the drain of the first PMOS tube M1 to receive the voltage VG, and can be configured to receive the first voltage V1 and the second voltage V2, and select the voltage VMAX1 from the first voltage V1 and the second voltage V2 for output, and the voltage VMAX1 can also be applied to the gate of the third NMOS tube M3.

[0036] Optionally, Figure 1 The selection module N1 in the circuit can be any circuit module that can select one of the first voltage V1 and the second voltage V2 as the voltage VMAX1 and output it. In one example, when the voltage difference between V1 and V2 is large, the selection module N1 can select the higher voltage from the first voltage V1 and the second voltage V2 as the voltage VMAX1 to output. In another example, when the voltage difference between V1 and V2 is small, the selection module N1 can stably select one of the first voltage V1 and the second voltage V2 (the first voltage V1 or the second voltage V2) as the voltage VMAX1 to output. Considering that the first voltage V1 and the second voltage V2 are very close at this time, the selection module N1 can meet the voltage selection requirements of the voltage selection circuit as long as it can stably select one of the voltages (the first voltage V1 or the second voltage V2) and make it have a strong load driving capability.

[0037] In an example of the present invention, the selection module N1 may be composed of two MOS transistors. Figure 2 FIG. 2 shows a schematic diagram of a specific structure of a selection module in a voltage selection circuit according to an embodiment of the present invention. Figure 2 As shown, the selection module N1 may include a fourth PMOS tube M4, a gate of the fourth PMOS tube M4 may receive the voltage VG, and a source of the fourth PMOS tube M4 may receive the first voltage V1. In addition, the selection module N1 may also include a fifth PMOS tube M5, a gate of the fifth PMOS tube M5 may receive the first voltage V1, a source of the fifth PMOS tube M5 may receive the second voltage V2, and a drain of the fifth PMOS tube M5 may be connected to the drain of the fourth PMOS tube M4 and output the voltage VMAX1.

[0038] Figure 2 The specific structure of the selection module N1 shown is only an example in the embodiment of the present invention. In addition, in another example, Figure 2 The source of the fourth PMOS tube M4 of the selection module N1 can receive the second voltage V2, and the gate of the fifth PMOS tube M5 can receive the second voltage V2, and the source can receive the first voltage V1. In practical applications, any specific structural form of the selection module capable of voltage comparison and selection can be adopted according to specific needs, and no limitation is made here. Figure 2 In the embodiment, the number of components, connection mode and input voltage value in the selection module N1 shown therein can be changed according to actual needs, and other components capable of voltage selection can also be used to implement a specific voltage selection function.

[0039] The following is for Figure 2 The structure of the voltage selection circuit shown in the figure is used to illustrate the specific voltage selection working mode of the voltage selection circuit of this example. Figure 2 In the voltage selection circuit shown, the voltage difference between V1 and V2 can be large (for example, it can be expressed as |V1-V2|>V th , where V th is the threshold voltage) or the voltage difference between V1 and V2 is close (for example, it can be expressed as |V1-V2|≤V th ), the selection function of the voltage VMAX1 in V1 and V2 is realized respectively.

[0040] In one example, when the voltage difference between V1 and V2 is large, it can be expressed as V1-V2>V th When V1 is smaller than V2, V2-V1>V th Optionally, when V1-V2>V th When the voltage VG received by the gate of the fourth PMOS tube M4 in the selection module N1 is the second voltage V2, the fourth PMOS tube M4 is turned on, and the fifth PMOS tube M5 is turned off, and the output voltage VMAX1 is the first voltage V1.

[0041] In addition, optionally, when V2-V1>V thWhen the first PMOS tube M1 is turned on, VG is the second voltage V2. Considering that the voltages across the second NMOS tube M2 and the third NMOS tube M3 connected in series are both the second voltage V2, it can be considered that the second NMOS tube M2 and the third NMOS tube M3 are both turned off, and the gate voltage of the fourth PMOS tube M4 in the input selection module N1 is the second voltage V2. At this time, the fourth PMOS tube M4 is turned off, and the fifth PMOS tube M5 is turned on, and the output voltage VMAX1 is the second voltage V2.

[0042] In another example, consider that the voltage difference between V1 and V2 is relatively close (expressed as |V1-V2|≤V th ). At this time, since the voltage difference between V1 and V2 is very small, it is less than the threshold voltage V of the first PMOS tube M1. th , then the first PMOS tube M1 is in the cut-off state. For the second NMOS tube M2, since the first PMOS tube M1 is in the cut-off state, the source of the second NMOS tube M2, namely VG, is floating, and there is only a very small leakage current. At this time, the second NMOS tube M2 is in the deep subthreshold region, and the voltage of the source of the second NMOS tube M2, namely VG, is equal to V1-|Vgs2|, where |Vgs2| is the gate-source voltage difference of the second NMOS tube M2 at this time. Since M2 is in the deep subthreshold region at this time, |Vgs2| is less than the threshold voltage V when the transistor is normally turned on. th In the case where the source of the second NMOS tube M2 is directly connected to the drain of the first PMOS tube M1 without introducing the third NMOS tube M3, for the second NMOS tube M2, due to the effect of the leakage current, the voltage VG will be equal to (V1-|Vgs2|), and since the value of |Vgs2| is less than the threshold voltage V when the transistor is normally turned on th At this time, the voltage between the gate and source of the fourth PMOS tube M4 |Vgs| is less than the threshold voltage V th , thus being in a nearly cut-off state, with poor driving capability, and the output VMAX1 can easily drop due to driving a large load.

[0043] However, by introducing the third NMOS tube M3, when the VMAX1 output by the selection module N1 drives the load circuit to generate a corresponding voltage drop, due to the effect of the leakage current, the voltage VG will become approximately equal to (VMAX1-|Vgs3|), where |Vgs3| is the gate-source voltage difference of the third NMOS tube M3 at this time. Subsequently, the voltage VG is input to the gate of the fourth PMOS tube M4, so that when the output VMAX1 voltage drops, the gate voltage of the fourth PMOS tube M4 will also drop, thereby increasing the voltage difference |Vgs| between the gate and source of the fourth PMOS tube M4, and the fourth PMOS tube M4 can be turned on, thereby increasing the driving capability.

[0044] In this case, even when the load of the output voltage VMAX1 is large, the voltage VMAX1 can stably output a voltage that is slightly smaller than the first voltage V1 and approximately equal to the first voltage V1. At this time, by stably selecting the approximate value of the first voltage V1 from the first voltage V1 and the second voltage V2, the output result of the voltage selection of the voltage selection circuit 1 can be guaranteed, and the selected voltage can be guaranteed to have a strong driving capability.

[0045] Of course, the above Figure 2 The specific structure and voltage selection method of the selection module N1 in the voltage selection circuit 1 shown in the figure are only examples. In other examples, the output result of the voltage selection of the voltage selection circuit 1 can be ensured by, for example, stably selecting the second voltage V2 from the first voltage V1 and the second voltage V2, and it can also be ensured that the selected voltage has a strong driving capability.

[0046] According to another example of the embodiment of the present invention, the voltage selection circuit 1 may further include a driving module N2. Figure 3 FIG. 2 shows a schematic diagram of a voltage selection circuit including a driving module according to an embodiment of the present invention. Figure 3 As shown, the driving module N2 can be set at the voltage VG output by the source of the third NMOS tube and the drain of the first PMOS tube. The driving module N2 can be used to increase the leakage current at the voltage VG, so that when the voltage VMAX1 drives the load circuit to generate a voltage drop, the voltage VG can be more quickly and stably reduced to (VMAX1-V th ), shortening the time interval experienced during the voltage drop realization process. The specific value of the leakage current provided by the driving module N2 can be flexibly designed by those skilled in the art according to needs. In one example, the leakage current provided by the driving module N2 can be about several hundred nA. The leakage current can further increase the voltage difference |Vgs| between the gate and source of the fourth PMOS tube M4, reduce the on-resistance of the fourth PMOS tube M4, and further increase the driving capability of the fourth PMOS tube M4, so that the output voltage VMAX1 is closer to V1.

[0047] Optionally, the driving module N2 may include at least one of the following: one or more NMOS tubes; one or more resistors; one or more current sources. The above specific composition of the driving module N2 is only an example. In practical applications, any composition that can provide leakage current can be used, and there is no limitation here.

[0048] In an example, the driving module N2 may include a plurality of NMOS transistors connected in series. Figure 4FIG. 4 is a schematic diagram of a voltage selection circuit according to an embodiment of the present invention, wherein a driving module of the voltage selection circuit includes a plurality of NMOS transistors MM1-MMn connected in series. Figure 4 As shown, the multiple NMOS tubes MM1-MMn are connected in series, the source of each stage of the NMOS tube is connected to the drain of the next stage of the NMOS tube, the drain of the first stage of the NMOS tube MM1 receives the voltage VG, and the last stage of the NMOS tube MMn is grounded V SS , the gate of each stage of NMOS tubes receives the high level V. Optionally, the high level V received by the gates of these NMOS tubes can be any one of the first voltage V1 and the second voltage V2. Of course, optionally, the high level V can also be other high levels with reasonable values, which is not limited here.

[0049] In another example, when the driving module includes a resistor, one end of the resistor can be connected to the voltage VG, and the other end can be connected to the ground V SS When the driving module includes multiple resistors, the multiple resistors can be connected in series, and one end of the series resistor can be connected to the voltage VG, and the other end can be connected to the ground V SS .

[0050] In another example, when the driving module includes one or more current sources, the current direction provided by the current source may flow out from the voltage VG, and the one or more current sources may be used to provide leakage current to facilitate the voltage VG to drop to (VMAX1-V th ).

[0051] According to an embodiment of the present invention, when the voltage selection circuit is applied to a chip, the substrate of each MOS tube in the voltage selection circuit needs to meet different voltage access modes. Figure 5 FIG. 1 is a schematic diagram showing the substrate voltage access of a MOS tube in a voltage selection circuit according to an example of an embodiment of the present invention. Figure 5 As shown, the substrate of the NMOS tube in the voltage selection circuit 1 can be grounded V SS , and the substrate of the PMOS tube can receive the highest voltage among the source, gate, and drain of the PMOS tube to avoid leakage. Therefore, the substrate of the first PMOS tube M1 in the voltage selection circuit 1 can receive the second voltage V2, and the substrates of the fourth PMOS tube M4 and the fifth PMOS tube M5 can receive the voltage VMAX1. The substrates of the second NMOS tube M2, the third NMOS tube M3, and the NMOS tubes MM1-MMn connected in series in the voltage selection circuit 1 can be grounded V SS .

[0052] According to the voltage selection circuit of the embodiment of the present invention, the third NMOS tube receiving the voltage VMAX1 via the gate in the circuit can make VG also produce a voltage drop correspondingly when the voltage VMAX1 produces a voltage drop due to driving the load circuit, thereby avoiding the problem that the selection module is difficult to select from the first voltage and the second voltage because VG cannot be linked with the voltage VMAX1 when performing voltage selection. The embodiment of the present invention can perform stable voltage comparison and selection between voltages with relatively close voltage differences, and can make the selected voltage have a strong driving capability.

[0053] In addition, through the further setting of the driving module in the embodiment of the present invention, the leakage current at the voltage VG is further increased, thereby increasing the voltage difference |Vgs| between the gate-source of the second NMOS tube and the third NMOS tube, reducing the on-resistance in the selection module, and further increasing the driving capability of the selected voltage VMAX1.

[0054] In the embodiment according to the present invention Figure 1-Figure 5 Based on the structural design of the voltage selection circuit shown, when it is desired to further perform voltage selection and stable load driving from multiple input voltages, multiple voltage selection circuits can be cascaded to obtain a multi-stage voltage selection circuit. Figure 6 FIG. 2 is a schematic diagram showing a structure of a multi-level voltage selection circuit according to another example of an embodiment of the present invention. Figure 6 As shown, the multi-stage voltage selection circuit may include a plurality of the aforementioned voltage selection circuits connected in cascade, and the specific working principle thereof is as described above and will not be described in detail here.

[0055] In the embodiment of the present invention, the voltage selection circuit of the first stage inputs the first voltage V1 and the second voltage V2, and outputs the selected voltage VMAX1; each subsequent n+1th stage voltage selection circuit can respectively input the voltage VMAX selected by the previous stage voltage selection circuit. n and the voltage V to be selected n+2 , and output from VMAX n and V n+2 The voltage VMAX selected in n+1 , where n is a positive integer greater than or equal to 1. Figure 6 In the example shown, when two voltages of a voltage selection circuit input to a certain level are close to each other, the voltage selection circuit can be stably switched from VMAX to VMAX. n and V n+2 Select a voltage (VMAX n or V n+2 ) as voltage VMAX n+1 , and not necessarily a relatively high voltage.

[0056] The multi-stage voltage selection circuit according to the embodiment of the present invention can avoid the problem of difficulty in selecting a voltage from the voltages to be selected when performing voltage selection by designing the cascaded voltage selection circuits. The embodiment of the present invention can perform stable voltage comparison and selection between voltages with relatively close voltage differences, and can make the selected voltage have a strong driving capability, which can be suitable for various subsequent application scenarios.

[0057] According to another embodiment of the present invention, a chip is provided, which includes the voltage selection circuit as described above, or the multi-stage voltage selection circuit as described above.

[0058] According to another embodiment of the present invention, a voltage regulator is provided, comprising the chip as described above. The voltage regulator in the embodiment of the present invention may be, for example, a digital distributed low dropout linear regulator (DLDO).

[0059] Although the subject matter has been described in detail for various specific example embodiments of the subject matter, each example is provided by way of explanation rather than limitation of the present disclosure. Those skilled in the art, after obtaining an understanding of the foregoing, can easily make changes, variations, and equivalents to such embodiments. Therefore, the present invention does not exclude including such modifications, variations, and / or additions to the subject matter that would be apparent to those of ordinary skill in the art. For example, a feature illustrated or described as part of one embodiment can be used together with another embodiment to produce yet another embodiment. Therefore, it is intended that the present disclosure covers such changes, variations, and equivalents.

[0060] Specifically, although the drawings of the present disclosure describe steps performed in a specific order for the purpose of illustration and discussion, the method of the present disclosure is not limited to the order or arrangement of the specific illustrations. The various steps of the above method can be omitted, rearranged, combined and / or adjusted in various ways without departing from the scope of the present disclosure.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0062] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A voltage selection circuit, comprising: A first PMOS transistor, wherein a gate of the first PMOS transistor receives a first voltage, and a source of the first PMOS transistor receives a second voltage; a second NMOS transistor, wherein a gate of the second NMOS transistor receives the first voltage, and a drain of the second NMOS transistor receives the second voltage; a third NMOS tube, wherein the drain of the third NMOS tube is connected to the source of the second NMOS tube, the source of the third NMOS tube is connected to the drain of the first PMOS tube and outputs a voltage VG; A selection module, wherein the selection module connects the source of the third NMOS tube and the drain of the first PMOS tube to receive the voltage VG, and is configured to receive the first voltage and the second voltage, and select a voltage VMAX1 from the first voltage and the second voltage to output, and the voltage VMAX1 is also applied to the gate of the third NMOS tube.

2. The voltage selection circuit according to claim 1, wherein: The selection module comprises: a fourth PMOS tube, wherein a gate of the fourth PMOS tube receives the voltage VG, and a source of the fourth PMOS tube receives the first voltage; A fifth PMOS tube, wherein a gate of the fifth PMOS tube receives the first voltage, a source of the fifth PMOS tube receives the second voltage, a drain of the fifth PMOS tube is connected to the drain of the fourth PMOS tube and outputs the voltage VMAX1.

3. The voltage selection circuit according to claim 1, wherein: A driving module is also included at the voltage VG output by the source of the third NMOS tube and the drain of the first PMOS tube, and the driving module is used to increase the leakage current at the voltage VG.

4. The voltage selection circuit as claimed in claim 3, wherein: The driving module includes at least one of the following: One or more NMOS tubes; one or more resistors; One or more current sources.

5. The voltage selection circuit as claimed in claim 4, wherein: When the driving module includes multiple NMOS tubes, the multiple NMOS tubes are connected in series, the source of each stage of the NMOS tube is connected to the drain of the next stage of the NMOS tube, the drain of the first stage of the NMOS tube receives the voltage VG, the last stage of the NMOS tube is grounded, and the gate of each stage of the NMOS tube receives a high level respectively.

6. The voltage selection circuit as claimed in claim 5, wherein: The high level is the first voltage or the second voltage.

7. The voltage selection circuit as claimed in claim 4, wherein: When the driving module includes a plurality of resistors, the plurality of resistors are connected in series, one end of the series-connected resistors is connected to the voltage VG, and the other end is grounded.

8. A multi-level voltage selection circuit, comprising: A plurality of cascaded voltage selection circuits according to any one of claims 1 to 7, wherein the voltage selection circuit of the first stage inputs the first voltage V1 and the second voltage V2, and outputs a selected voltage VMAX1; and the subsequent voltage selection circuits of the n+1th stage respectively input the voltage VMAX selected by the voltage selection circuit of the previous stage n and the voltage V to be selected n+2 , and output from VMAX n and V n+2 The voltage VMAX selected in n+1 , where n is a positive integer greater than or equal to 1.

9. A chip, comprising: The voltage selection circuit according to any one of claims 1 to 7, or the multi-stage voltage selection circuit according to claim 8.

10. A voltage regulator comprising the chip according to claim 9.

Images