Memory management method and storage device

Abstract

The present invention provides a memory management method and storage device. The method includes: obtaining a first read count corresponding to a first physical unit in a first physical management unit; obtaining an average read count corresponding to the first physical management unit; obtaining a first evaluation value corresponding to the first physical management unit based on the first read count and the average read count; if the first evaluation value is greater than a trigger threshold, performing a read verification operation on the first physical management unit; during the read verification operation, determining whether first data read from the first physical management unit meets an update condition; and if the first data does not meet the update condition, adjusting the trigger threshold from the first value to a second value. This effectively improves the management efficiency of performing read verification operations on a storage device.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] Digital cameras, mobile phones, and MP3 players have experienced rapid growth in recent years, driving a surge in consumer demand for storage media. Rewritable non-volatile memory (RNV) is ideally suited for portable electronic products such as laptops due to its non-volatile data, power efficiency, compact size, lack of mechanical structure, and fast read / write speeds. For example, a solid-state drive (SSD) is a type of memory storage device that uses a flash memory module as its storage medium. Consequently, the flash memory industry has become a highly sought-after sector within the electronics industry in recent years.

[0003] Generally speaking, a rewritable non-volatile memory module typically includes multiple physical erase units, each of which contains multiple physical programming pages. When the data stored in a physical programming cell within a physical erase unit is read multiple times (for example, hundreds of thousands to millions of times), the data stored in this physical programming cell is likely to generate bit errors or be lost due to the applied read voltage. This can even cause bit errors or loss in data stored in other physical programming cells within the same physical erase unit. This phenomenon is known as "read disturb." "Read disturb" refers to a phenomenon that can affect the integrity of memory cell data. When a memory cell is frequently read, these read operations can interfere with neighboring memory cells, potentially changing or corrupting the data in memory cells that are not directly accessed. Specifically, in the NAND Flash architecture, data is read and written in pages, while erasure is performed in blocks. Each page is connected by a word line (WL), and pages are physically close to each other. When a page is read multiple times, the floating gate voltage around it may indirectly affect the floating gate voltage state of adjacent pages, causing slight changes in the charge in those pages. If these changes accumulate to a certain extent, they may cause the originally stored data bit to flip, that is, from 1 to 0 or from 0 to 1, resulting in data errors.

[0004] To address this issue, manufacturers must develop various memory management methods to effectively suppress the probability of read disturbance. Summary of the Invention

[0005] The present invention provides a memory management method and a memory device, which can effectively improve the management efficiency of performing a read verification operation on the memory device.

[0006] An embodiment of the present invention provides a memory management method for a storage device, wherein the storage device includes a memory module, the memory module includes multiple entity management units, the multiple entity management units include a first entity management unit, the first entity management unit includes multiple entity units, and the memory management method includes: obtaining a first read count corresponding to a first entity unit among the multiple entity units, wherein the first read count reflects the total number of times the first entity unit is read; obtaining an average read count corresponding to the first entity management unit, wherein the average read count reflects the average number of times the read operation is performed on the multiple entity units; obtaining a first evaluation value corresponding to the first entity management unit based on the first read count and the average read count, wherein the first evaluation value reflects the degree of imbalance of the read operations performed on the multiple entity units; if the first evaluation value is greater than a trigger critical value, performing a read verification operation on the first entity management unit; in the read verification operation, determining whether the first data read from the first entity management unit meets the update condition; and if the first data does not meet the update condition, adjusting the trigger critical value from the first value to a second value, wherein the second value is greater than the first value.

[0007] Another embodiment of the present invention provides a storage device comprising a connection interface, a memory module, and a memory controller. The connection interface is configured to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module comprises a plurality of physical management units, the plurality of physical management units including a first physical management unit, the first physical management unit comprising a plurality of physical units, and the memory controller is configured to: obtain a first read count corresponding to a first physical unit among the plurality of physical units, wherein the first read count reflects the total number of read operations performed on the first physical unit; obtain an average read count corresponding to the first physical management unit, wherein the average read count reflects the average number of read operations performed on the plurality of physical units; obtain a first evaluation value corresponding to the first physical management unit based on the first read count and the average read count, wherein the first evaluation value reflects the degree of unevenness of the read operations performed on the plurality of physical units; if the first evaluation value is greater than a trigger threshold, perform a read-verify operation on the first physical management unit; during the read-verify operation, determine whether first data read from the first physical management unit meets an update condition; and if the first data does not meet the update condition, adjust the trigger threshold from the first value to a second value, wherein the second value is greater than the first value.

[0008] Therefore, for certain situations that cannot be effectively detected traditionally, such as only a small number of physical units in certain physical management units having serious read disturb problems, the present invention can still accurately trigger the read verification operations of these physical management units.

[0009] In addition, the present invention can also provide a long-term and automatic triggering mechanism for the read verification operation, thereby improving the technical problem that traditionally only a single verification can be performed on the physical unit, and further improving the management efficiency of executing the read verification operation on the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0011] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0012] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0013] Figure 4 is a schematic diagram showing management of entity units by an entity management unit according to an embodiment of the present invention;

[0014] Figure 5 is a flowchart of a memory management method according to an embodiment of the present invention;

[0015] Figure 6 FIG. 4 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0019] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0020] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0021] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0022] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data accuracy. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits), and the present invention is not limited thereto.

[0026] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile data storage.

[0027] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0028] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit may be adjusted according to practical needs and are not limited by the present invention. In one embodiment, a physical programming unit may be considered a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, but the present invention is not limited to this.

[0029] In one embodiment, a physical programming unit is the smallest unit to which data is written synchronously in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be programmed synchronously to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0030] In one embodiment, a physical erase unit may include multiple physical programming units. Multiple physical programming units in a physical erase unit may be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to multiple physical programming units in the physical erase unit to change the threshold voltages of at least some of the memory cells in these physical programming units. By performing an erase operation on a physical erase unit, data stored in the physical erase unit may be cleared.

[0031] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also known as user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, the physical unit may be associated with the idle area 32. Furthermore, the physical units in the idle area 32 may be erased to clear the data in the physical units. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0033] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cells, the physical cells may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. A logical unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is currently not mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data read, write, or erase based on the information in the management table (i.e., the logical-to-physical mapping table).

[0037] In one embodiment, the memory control circuit 23 may manage at least some of the physical units (e.g., physical units 301(1) to 301(B)) in the memory module 122 through a plurality of physical management units. Each physical management unit may include a plurality of physical units. In one embodiment, a physical management unit is also referred to as a virtual unit. In one embodiment, the memory control circuit 23 may manage or access a plurality of physical units in a physical management unit using a physical management unit as a basic unit. For example, a plurality of physical units included in the same physical management unit may be accessed synchronously or sequentially (e.g., to read data, write data, or erase data).

[0038] Figure 4 This is a schematic diagram showing how to manage entity units through entity management units according to an embodiment of the present invention. Figure 4 In one embodiment, the memory module 122 includes physical management units 41(1)-41(D). The total number of physical management units 41(1)-41(D) can be set or adjusted according to practical needs, and the present invention is not limited thereto.

[0039] Each of the entity management units 41(1) to 41(D) may include multiple entity units. For example, the entity management unit 41(1) includes entity units 401(1) to 401(E), and the entity management unit 41(D) includes entity units 402(1) to 402(E). For example, the entity units 401(1) to 401(E) and 402(1) to 402(E) may be included in Figure 3 In the entity units 301(1) to 301(B) in FIG. In addition, the total number of entity units included in each entity management unit can be set or adjusted according to practical needs, and the present invention does not impose any limitation thereto.

[0040] In one embodiment, the memory control circuit 23 may select a physical management unit (also referred to as a first physical management unit) from the physical management units 41 (1) to 41 (D). For example, the first physical management unit may be the physical management unit 41 (i), and i is an integer between 1 and D. Then, the memory control circuit 23 may determine (for example, select) a physical unit (also referred to as a first physical unit) from the first physical management unit. The first physical unit may be one of the multiple physical units included in the first physical management unit. For example, assuming that the first physical management unit is the physical management unit 41 (1), the first physical unit may be one of the physical units 401 (1) to 401 (E). Alternatively, assuming that the first physical management unit is the physical management unit 41 (D), the first physical unit may be one of the physical units 402 (1) to 402 (E).

[0041] In one embodiment, the memory control circuit 23 may determine one of the multiple physical units included in the first physical management unit as the first physical unit according to a preset rule. For example, the memory control circuit 23 may determine one of the multiple physical units included in the first physical management unit as the first physical unit at different time points through a rotation or other method.

[0042] In one embodiment, the memory control circuit 23 may execute a random algorithm to determine the first physical unit. For example, the memory control circuit 23 may randomly determine one of the multiple physical units included in the first physical management unit as the first physical unit based on the operation result of the random algorithm. For example, the memory control circuit 23 may input a seed into the random algorithm. The random algorithm may generate an output value in response to the seed. The memory control circuit 23 may randomly determine one of the multiple physical units included in the first physical management unit as the first physical unit based on the output value.

[0043] In one embodiment, based on different output values ​​of the random algorithm, the memory control circuit 23 may randomly determine different physical units in the first physical management unit as the first physical unit. For example, based on a certain output value of the random algorithm (also referred to as the first output value), the memory control circuit 23 may determine a certain physical unit in the first physical management unit (also referred to as the first candidate unit) as the first physical unit. Alternatively, based on another output value of the random algorithm (also referred to as the second output value), the memory control circuit 23 may determine another physical unit in the first physical management unit (also referred to as the second candidate unit) as the first physical unit. The first candidate unit and the second candidate unit are different physical units in the first physical management unit.

[0044] In one embodiment, after determining the first physical unit from the first physical management unit, the memory control circuit 23 may obtain a read count (also referred to as a first read count) corresponding to the first physical unit. The first read count may reflect the total number of read operations performed on the first physical unit. For example, the read operations performed on the first physical unit are used to read data from the first physical unit. For example, assuming that the total number of read operations performed on the first physical unit over a period of time is "40", the first read count may be "40". In one embodiment, the memory control circuit 23 only records the most recent and maximum read count corresponding to the first physical unit.

[0045] In one embodiment, the memory control circuit 23 may also obtain an average read count corresponding to the first physical management unit. This average read count reflects the average number of read operations performed on the multiple physical units in the first physical management unit. For example, assuming that this average read count is "50," it means that an average of "50" read operations have been performed on the multiple physical units in the first physical management unit over the past period of time. However, in reality, the total number of read operations performed on each physical unit in the first physical management unit over the past period of time may be higher or lower than this average number. In one embodiment, the memory control circuit 23 only records the most recent and largest average read count corresponding to the first physical management unit.

[0046] In one embodiment, the memory control circuit 23 only records the latest and largest read count corresponding to the first physical unit (e.g., the first read count) and the latest and largest read count corresponding to the first physical management unit (e.g., the average read count). Therefore, the storage space required to store the one or more read counts can be reduced.

[0047] In one embodiment, the memory control circuit 23 may first obtain a total read count corresponding to the first physical management unit. This total read count reflects the total number of times the first physical management unit has been read. For example, assuming that the total number of times the first physical management unit has been read is "1000" times over the past period of time, the total read count may be "1000". Then, the memory control circuit 23 may obtain the average read count based on the total read count and the total number of physical units included in the first physical management unit. For example, assuming that the total read count is "1000" and the total number of physical units included in the first physical management unit is "20", the memory control circuit 23 may divide the total read count (e.g., "1000") by the total number of physical units included in the first physical management unit (e.g., "20") to obtain the average read count (e.g., "50").

[0048] In one embodiment, the memory control circuit 23 may further determine (e.g., select) another physical unit (also referred to as a second physical unit) from the first physical unit management unit. Compared to the first physical unit, the second physical unit may be another one of the multiple physical units included in the first physical unit management unit. The total number of second physical units determined may be one or more. The memory control circuit 23 may obtain a read count (also referred to as a second read count) corresponding to the second physical unit. The second read count may reflect the total number of times a read operation is performed on the second physical unit. For example, the read operation performed on the second physical unit is used to read data from the second physical unit. For example, assuming that the total number of times a read operation is performed on the second physical unit in the past period of time is "20", the second read count may be "20". In one embodiment, the second read count may be less than the first read count. In one embodiment, the second read count may be equal to or greater than the first read count.

[0049] In one embodiment, the memory control circuit 23 may obtain the average read count corresponding to the first physical management unit based on the first read count and the second read count. For example, the average read count may reflect the average of the first read count and the second read count.

[0050] In one embodiment, after obtaining the average read count, if the second read count is smaller than the first read count, the memory control circuit 23 may further save the first read count and remove the second read count, thereby reducing the memory space required for storing the read counts.

[0051] In one embodiment, after obtaining the average read count, the memory control circuit 23 may compare the first read count with the second read count to obtain a comparison result. This comparison result may reflect a relative numerical relationship between the first read count and the second read count. For example, this relative numerical relationship may be that the first read count is less than, equal to, or greater than the second read count. Based on the comparison result, the memory control circuit 23 may retain the first read count with the relatively larger value and remove the second read count with the relatively smaller value.

[0052] In other words, in response to the comparison result indicating that the second read count is less than the first read count, the memory control circuit 23 may store the first read count and remove the second read count. However, if the comparison result indicates that the first read count is less than the second read count, the memory control circuit 23 may instead store the second read count and remove the first read count. This also reduces the memory space required to store the read counts.

[0053] In one embodiment, by removing (i.e., not storing) one or more read counts that are older and / or have relatively smaller values, the storage space required for storing the read counts can be reduced. However, even if the read counts stored for the first entity management unit (or one or more entity units within the first entity management unit) are reduced, the accuracy of triggering the read-verify operation for the first entity management unit (or one or more entity units within the first entity management unit) is not affected and may even be improved.

[0054] In one embodiment, the memory control circuit 23 may obtain an evaluation value (also referred to as a first evaluation value) corresponding to the first physical management unit based on the first read count and the average read count. The first evaluation value may reflect the degree of imbalance in the execution of the read operations on the multiple physical units in the first physical management unit. Alternatively, from another perspective, the first evaluation value may reflect whether the read operations were executed evenly on the multiple physical units in the first physical management unit over a period of time.

[0055] In one embodiment, the memory control circuit 23 may compare the first evaluation value with a critical value (also referred to as a trigger critical value). If the first evaluation value is greater than the trigger critical value, the memory control circuit 23 may perform a read verification operation on the first entity management unit. For example, when the first evaluation value is greater than the trigger critical value (or in response to the first evaluation value being greater than the trigger critical value), the memory control circuit 23 may perform the read verification operation on all entity units in the first entity management unit one by one. For example, the read verification operation may be used to ensure or improve the correctness of at least a portion of the data currently stored in the first entity management unit. However, if the first evaluation value is not greater than (e.g., less than or equal to) the trigger critical value, the memory control circuit 23 may not perform the read verification operation on the first entity management unit. In this way, unnecessary waste of system resources can be avoided.

[0056] In one embodiment, the memory control circuit 23 may obtain an evaluation factor (also referred to as a balance evaluation factor) based on the first read count and the average read count. This balance evaluation factor is related to the degree of imbalance in which the read operations are respectively executed on the multiple physical units in the first physical management unit. For example, this balance evaluation factor may be positively correlated with the degree of imbalance in which the read operations are respectively executed on the multiple physical units in the first physical management unit. That is, if this balance evaluation factor is larger, it means that in the past period of time, the degree of imbalance in which the read operations are respectively executed on the multiple physical units in the first physical management unit is higher (equivalent to the fact that in the past period of time, the multiple physical units in the first physical management unit are less balanced in reading). Conversely, if this balance evaluation factor is smaller, it means that in the past period of time, the degree of imbalance in which the read operations are respectively executed on the multiple physical units in the first physical management unit is lower (equivalent to the fact that in the past period of time, the multiple physical units in the first physical management unit are more balanced in reading).

[0057] In one embodiment, the memory control circuit 23 may obtain the balance evaluation factor according to the following formula (1).

[0058] t=|(B(i)-AVG) / AVG| (1)

[0059] In formula (1), B(i) represents the first read count, AVG represents the average read count, and t represents the balance assessment factor. According to formula (1), the calculated t (i.e., the balance assessment factor) is positively correlated with the difference (which can be positive or negative) between B(i) (i.e., the first read count) and AVG (i.e., the average read count). That is, the greater the difference between B(i) and AVG, the greater the calculated t. It should be noted that formula (1) can also be set or adjusted according to practical needs, and the present invention is not limited thereto.

[0060] In one embodiment, after obtaining the balance evaluation factor, the memory control circuit 23 may obtain a first evaluation value based on the average read count and the balance evaluation factor. For example, the first evaluation value may be positively correlated with the average read count and the balance evaluation factor.

[0061] In one embodiment, the memory control circuit 23 may obtain the first evaluation value according to the following formula (2).

[0062] EV=AVG×(1+t) (2)

[0063] In formula (2), EV represents the first evaluation value. According to formula (2), the larger the AVG (i.e., the average read count) and / or t (i.e., the balance evaluation factor), the larger the calculated EV (i.e., the first evaluation value). It should be noted that formula (2) can also be set or adjusted according to practical needs and is not limited by the present invention.

[0064] In one embodiment, if the first evaluation value is greater than the trigger threshold, it indicates that the degree of imbalance in read operations performed on multiple physical units in the first physical management unit over a period of time has been relatively high (i.e., the difference between the read counts corresponding to the multiple physical units in the first physical management unit is relatively large). Therefore, by comparing the first evaluation value with the trigger threshold, physical management units that are likely to cause access errors in the future due to uneven usage of multiple physical units within the physical management unit (e.g., only some physical units have severe read disturb) can be effectively detected.

[0065] On the other hand, if the first evaluation value is not greater than the trigger threshold, it indicates that the degree of imbalance in the read operations performed on the multiple physical units in the first physical management unit over the past period of time is relatively low (i.e., the difference between the read counts corresponding to the multiple physical units in the first physical management unit is small). In this case, the memory control circuit 23 may not perform the read verification operation on the first physical management unit to avoid unnecessary waste of system resources.

[0066] In one embodiment, the memory control circuit 23 may also compare the first read count with the trigger threshold. If the first read count is greater than the trigger threshold, the memory control circuit 23 may directly perform a read-verify operation on the first physical management unit. For example, if the first read count is greater than the trigger threshold (or in response to the first read count being greater than the trigger threshold), the memory control circuit 23 may perform the read-verify operation on all physical units in the first physical management unit one by one to ensure or improve the correctness of at least a portion of the data currently stored in the first physical management unit. However, if the first read count is not greater than (e.g., less than or equal to) the trigger threshold, the memory control circuit 23 may not perform the read-verify operation on the first physical management unit to avoid unnecessary waste of system resources.

[0067] In one embodiment, during the read verification operation, the memory control circuit 23 may instruct the memory module 122 to read data (also referred to as first data) from the first physical management unit. For example, the first data may include data read from at least one physical unit in the first physical management unit.

[0068] In one embodiment, the step of reading data from at least one physical unit in the first physical management unit includes first selecting a target physical unit from the first physical management unit. Specifically, the memory control circuit 23 selects the target physical unit from the first physical management unit by first selecting the physical unit with the largest number of erases as the target physical unit.

[0069] In one embodiment, after selecting a physical cell with the largest number of erase times as a target physical cell, the memory control circuit 23 may traverse all physical programming cells in the physical cell to read data.

[0070] In one embodiment, data is not read from all physical programming cells, as this is time-consuming. Instead, after selecting a target physical cell, at least two physical programming cells are randomly selected from the target physical cells, where the word lines (WL) to which these two physical programming cells belong are adjacent. For example, the first physical programming cell belongs to WL0, and the second physical programming cell belongs to WL1; WL0 and WL1 are adjacent word lines. Furthermore, the first read voltage required to read the data in the first physical programming cell and the second read voltage required to read the data in the second physical programming cell are the same. Preferably, the first read voltage and the second read voltage values ​​are stored in a reread voltage table pre-programmed into the storage device 12.

[0071] In one embodiment, at least two physical programming units are randomly selected from the target physical unit, wherein the first physical programming unit is randomly selected, and the second physical programming unit in an adjacent word line relationship is also randomly selected.

[0072] In one embodiment, the operation of selecting at least two physical programming units from the target physical unit is not random. Instead, the physical programming unit with the largest physical address value is first read. If this physical programming unit is not the target physical programming unit, the physical programming unit with a physical address value half of the maximum value is then selected to determine whether it is the target physical programming unit. If not, the next round of physical programming unit determination is performed using half of this value. For example, if a physical unit includes 100 physical programming units, the first round of searching is for the physical programming unit on page 99. If not, the second round of searching is for the physical programming unit on page 49, and so on. If the target physical programming unit is page 24, only three rounds of searching are required to find the target physical programming unit, which is faster than searching the target physical programming unit traversally.

[0073] In one embodiment, the memory control circuit 23 constructs a table of physical programming units that successfully read data in response to a data read instruction, and uses a sorting algorithm to manage this table. The physical address values ​​of the physical programming units with the largest data error bit values ​​during historical read operations are arranged at the head of the table. Subsequent selection of target physical programming units is made based on this table.

[0074] In one embodiment, the memory control circuit 23 may construct the physical programming unit table based on the data error bit value corresponding to at least one physical programming unit detected during the historical read operation. For example, the physical programming unit table may be constructed using an LRU-K algorithm or other algorithms. For example, the memory control circuit 23 may add the physical address values ​​of the physical programming units whose corresponding data error bit values ​​are greater than a threshold value to the physical programming unit table. For example, the data error bit value may be positively correlated with the bit error rate of the physical programming unit. Thereafter, the memory control circuit 23 may select a target physical programming unit from the physical programming unit table, so that the data error bit value corresponding to the selected target physical programming unit is necessarily greater than the threshold value.

[0075] In one embodiment, the memory control circuit 23 may continuously perform the read-verify operation on the physical programming cells located on a plurality of non-adjacent word lines in the first physical management unit. For example, after determining to perform the read-verify operation on the first physical management unit, the memory control circuit 23 may continuously read data from the physical programming cells located on non-adjacent word lines WL0, WL3, WL6, WL9, etc. in the first physical management unit as the first data, and perform the read-verify operation based on the first data. It should be noted that the non-adjacent word lines on which data is continuously read and verified include at least one skipped word line (i.e., data is not read and verified) between them. In addition, the number of word lines located between the non-adjacent word lines can be adjusted according to practical needs.

[0076] In one embodiment, after determining to perform the read-verify operation on the first physical management unit, the memory control circuit 23 may first sequentially perform read-verify operations (also referred to as a first read-verify operation) on the physical programmed cells located on a plurality of non-adjacent word lines in the first physical management unit based on a certain number of intervals (also referred to as a first interval number). For example, the first interval number is used to reflect (or define) the total number of skipped word lines (i.e., not subjected to data read and verification) between word lines on which data is sequentially read and verified in the first read-verify operation. For example, assuming that in the first read-verify operation, the physical programmed cells located on non-adjacent word lines WL0 and WL5 in the first physical management unit are sequentially subjected to read-verify operations, the first interval number is "4."

[0077] In one embodiment, after completing the first read-verify operation, the memory control circuit 23 may switch to continuously performing the next stage of the read-verify operation (also referred to as the second read-verify operation) on the physical programmed cells located on multiple non-adjacent word lines in the first physical management unit based on another interval number (also referred to as the second interval number). For example, the second interval number is used to reflect (or define) the total number of skipped word lines (i.e., not subjected to data read and verification) between the word lines on which data is continuously read and verified in the second read-verify operation. For example, assuming that in the second read-verify operation, the physical programmed cells located on non-adjacent word lines WL1 and WL4 in the first physical management unit are subjected to continuous read-verify operations, the second interval number is "3."

[0078] In one embodiment, the second interval number may be the same as the first interval number, thereby reducing the complexity of managing and executing the read verification operation.

[0079] In one embodiment, the second interval number can be smaller than the first interval number. Thus, in the early stages of a read-verify operation, the efficiency of scanning the entire first physical management unit can be improved by increasing the interval number (e.g., setting the interval number to the first interval number). In the later stages of the read-verify operation, the accuracy of scanning the physical programming units in the first physical management unit can be improved by reducing the interval number (e.g., switching the interval number to the second interval number), thereby improving the accuracy of subsequent decisions regarding whether data needs to be updated (or moved).

[0080] In one embodiment, after obtaining the first data, the memory control circuit 23 may determine whether the first data meets the update condition. If the first data meets the update condition, the memory control circuit 23 may restore the first data to another physical management unit (also referred to as the second physical management unit) in the memory module 122. Figure 4 For example, assuming the first physical management unit is physical management unit 41(i), the second physical management unit may be physical management unit 41(j). i and j may be integers between 1 and D, and i is different from j. However, if the first data does not meet the update condition, the memory control circuit 23 may not restore the first data to the second physical management unit.

[0081] In one embodiment, after obtaining the first data, the decoding circuit 25 may perform a decoding operation on the first data. This decoding operation may be used to detect and attempt to correct error bits in the first data. Based on the result of this decoding operation, the memory control circuit 23 may determine whether the total number of error bits in the first data exceeds a predetermined value. If the total number of error bits exceeds the predetermined value, the memory control circuit 23 may determine that the first data meets the update condition. However, if the total number of error bits does not exceed the predetermined value, the memory control circuit 23 may determine that the first data does not meet the update condition.

[0082] In one embodiment, by restoring first data that originally contained relatively many error bits to the second physical management unit, the accuracy of the restored first data can be improved. Furthermore, restoring the first data to the second physical management unit can also reduce the total number of error bits contained in the first data subsequently read from the second physical management unit.

[0083] In one embodiment, after performing a decoding operation on the first data, the memory control circuit 23 may also determine whether the first data was successfully decoded based on the result of the decoding operation. If the first data cannot be successfully decoded (e.g., the first data contains uncorrectable data or error bits), the memory control circuit 23 may determine that the first data meets the update condition. However, if the first data can be successfully decoded (e.g., all data or error bits in the first data can be corrected), the memory control circuit 23 may determine that the first data does not meet the update condition.

[0084] In one embodiment, after restoring the first data to the second physical management unit, the memory control circuit 23 may reset the read count information corresponding to the first physical management unit. For example, the read count information may include a total read count and / or an average read count corresponding to the first physical management unit. In one embodiment, the read count information may also include a read count corresponding to any physical unit in the first physical management unit (e.g., the first read count). In one embodiment, in response to restoring the first data to the second physical management unit, the memory control circuit 23 may reset the total read count corresponding to the first physical management unit, the average read count corresponding to the first physical management unit, and / or the read count corresponding to any physical unit in the first physical management unit to zero (or restore them to their initial values).

[0085] In one embodiment, after restoring the first data to the second physical management unit, the memory control circuit 23 may further re-associate the first physical management unit (including all physical units in the first physical management unit) to the second physical management unit. Figure 3In one embodiment, after restoring the first data to the second physical management unit, the memory control circuit 23 may further erase all physical units in the first physical management unit.

[0086] In one embodiment, after starting to perform a read-verify operation on the first physical management unit, if it is determined that the first data read from the first physical management unit does not meet the update condition (for example, all data read from the first physical management unit can be successfully decoded and / or the total number of error bits in all data read is not greater than a preset value), the memory control circuit 23 may further adjust the trigger threshold from the first value to a second value, where the second value is greater than the first value. For example, the second value may be two times, three times, or another multiple of the first value, or another value greater than the first value.

[0087] In one embodiment, after adjusting the trigger critical value from the first value to the second value, the memory control circuit 23 may obtain the updated first read count, the average read count and / or the first evaluation value as the storage device 12 is used. In one embodiment, when the first evaluation value and / or the first evaluation value is greater than the new trigger critical value (i.e., the second value), the memory control circuit 23 may perform a read verification operation on the first physical management unit again. The execution details of the read verification operation have been described above and will not be repeated here. In this way, it is ensured that before moving data from the first physical management unit (for example, moving it to the second physical management unit), a long-term and automated trigger mechanism for the read verification operation is maintained for the first physical management unit, thereby continuously monitoring and maintaining the usage status (for example, health) of the first physical management unit.

[0088] Figure 5 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 5In step S501, a first read count corresponding to the first entity unit in the first entity management unit is obtained, wherein the first read count reflects the total number of times the read operation is performed on the first entity unit. In step S502, an average read count corresponding to the first entity management unit is obtained, wherein the average read count reflects the average number of times the read operation is performed on multiple entity units in the first entity management unit. In step S503, a first evaluation value corresponding to the first entity management unit is obtained based on the first read count and the average read count, wherein the first evaluation value reflects the degree of imbalance of the read operations performed on the multiple entity units. In step S504, it is determined whether the first evaluation value is greater than the trigger critical value. If the first evaluation value is greater than the trigger critical value, in step S505, a read verification operation is performed on the first entity management unit. However, if the first evaluation value is not greater than the trigger critical value, in step S506, a read verification operation is not performed on the first entity management unit.

[0089] Figure 6 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 6 In step S601, a read verification operation is performed on the first entity management unit. In step S602, it is determined whether the first data read from the first entity management unit meets the update condition. If the first data meets the update condition, in step S603, the first data is restored to the second entity management unit and the read count information corresponding to the first entity management unit is reset. However, if the first data does not meet the update condition, in step S604, the trigger threshold is adjusted from the first value to the second value, wherein the second value is greater than the first value. For example, this trigger threshold is used for Figure 5 Step S504.

[0090] However, Figure 5 and Figure 6 The steps have been described in detail above and will not be repeated here. Figure 5 and Figure 6 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 5 and Figure 6 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0091] In summary, the memory management method and storage device proposed in the embodiments of the present invention can effectively improve the accuracy of triggering read-verify operations on physical management units. In particular, the present invention can accurately trigger read-verify operations for certain conditions that are traditionally difficult to detect, such as when only a small number of physical units within a physical management unit experience severe read disturb issues. This effectively improves the operational stability of the storage device.

[0092] In addition, the present invention can also provide a long-term and automatic triggering mechanism for the read verification operation, thereby improving the technical problem that traditionally only a single verification can be performed on the physical unit, and further improving the management efficiency of executing the read verification operation on the storage device.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of entity management units, the plurality of entity management units includes a first entity management unit, the first entity management unit includes a plurality of entity units, and the memory management method includes: Obtaining a first read count corresponding to a first physical unit among the plurality of physical units, wherein the first read count reflects a total number of times read operations are performed on the first physical unit; Obtaining an average read count corresponding to the first physical management unit, wherein the average read count reflects an average number of times the read operation is performed on the plurality of physical units; Obtaining a first evaluation value corresponding to the first physical management unit according to the first read count and the average read count, wherein the first evaluation value reflects a degree of imbalance in the read operations performed on the plurality of physical units; If the first evaluation value is greater than the trigger threshold, performing a read verification operation on the first physical management unit; In the read verification operation, determining whether the first data read from the first entity management unit meets an update condition; and If the first data does not meet the update condition, the trigger threshold is adjusted from a first value to a second value, wherein the second value is greater than the first value.

2. The memory management method according to claim 1, further comprising: If the first read count is greater than the trigger threshold, the read verification operation is performed on the first physical management unit.

3. The memory management method according to claim 1 , further comprising: According to the operation result of the random algorithm, one of the plurality of entity units is randomly determined as the first entity unit.

4. The memory management method according to claim 1 , wherein the step of obtaining the first evaluation value corresponding to the first physical management unit according to the first read count and the average read count comprises: Obtaining a balance evaluation factor according to the first read count and the average read count, wherein the balance evaluation factor is positively correlated with the imbalance degree; The first evaluation value is obtained according to the average read count and the balance evaluation factor.

5. The memory management method according to claim 4 , wherein the step of obtaining the balance evaluation factor according to the first read count and the average read count comprises: According to the following formula, the balance evaluation factor is obtained: t=|(B(i)-AVG) / AVG| Wherein, B(i) represents the first read count, AVG represents the average read count, and t represents the balance evaluation factor.

6. The memory management method according to claim 1 , further comprising: If the first data meets the update condition, the first data is restored to a second physical management unit among the plurality of physical management units, and the read count information corresponding to the first physical management unit is reset.

7. The memory management method according to claim 1 , wherein the step of obtaining the average read count corresponding to the first physical management unit comprises: Obtaining a second read count corresponding to a second physical unit among the plurality of physical units, wherein the second read count reflects a total number of times the read operation is performed on the second physical unit, and the second read count is less than the first read count; Obtaining the average read count according to the first read count and the second read count; as well as After obtaining the average read count, the first read count is saved and the second read count is removed.

8. The memory management method according to claim 7, wherein the steps of saving the first read count and removing the second read count comprise: comparing the first read count and the second read count to obtain a comparison result; as well as According to the comparison result, the first read count is saved, and the second read count is removed.

9. The memory management method according to claim 8, wherein the step of saving the first read count and removing the second read count according to the comparison result comprises: In response to the comparison result reflecting that the second read count is less than the first read count, the first read count is saved and the second read count is removed.

10. The memory management method according to claim 1, further comprising: The read verification operation is continuously performed on the physical programming units located on a plurality of non-adjacent word lines in the first physical management unit.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical management units, the plurality of physical management units include a first physical management unit, the first physical management unit includes a plurality of physical units, and the memory controller is configured to: Obtaining a first read count corresponding to a first physical unit among the plurality of physical units, wherein the first read count reflects a total number of times read operations are performed on the first physical unit; Obtaining an average read count corresponding to the first physical management unit, wherein the average read count reflects an average number of times the read operation is performed on the plurality of physical units; Obtaining a first evaluation value corresponding to the first physical management unit according to the first read count and the average read count, wherein the first evaluation value reflects a degree of imbalance in the read operations performed on the plurality of physical units; If the first evaluation value is greater than the trigger threshold, performing a read verification operation on the first physical management unit; In the read verification operation, determining whether the first data read from the first entity management unit meets the update condition; as well as If the first data does not meet the update condition, the trigger threshold is adjusted from a first value to a second value, wherein the second value is greater than the first value.

12. The storage device according to claim 11, wherein the memory controller is further configured to: If the first read count is greater than the trigger threshold, the read verification operation is performed on the first physical management unit.

13. The storage device according to claim 11, wherein the memory controller is further configured to: According to the operation result of the random algorithm, one of the plurality of entity units is randomly determined as the first entity unit.

14. The storage device according to claim 11 , wherein the memory controller obtains the first evaluation value corresponding to the first physical management unit according to the first read count and the average read count, comprising: Obtaining a balance evaluation factor according to the first read count and the average read count, wherein the balance evaluation factor is positively correlated with the imbalance degree; The first evaluation value is obtained according to the average read count and the balance evaluation factor.

15. The storage device according to claim 14, wherein the memory controller obtains the balance evaluation factor according to the first read count and the average read count, comprising: According to the following formula, the balance evaluation factor is obtained: t=|(B(i)-AVG) / AVG| Wherein, B(i) represents the first read count, AVG represents the average read count, and t represents the balance evaluation factor.

16. The storage device according to claim 11, wherein the memory controller is further configured to: If the first data meets the update condition, the first data is restored to a second physical management unit among the plurality of physical management units, and the read count information corresponding to the first physical management unit is reset.

17. The storage device according to claim 11, wherein the operation of the memory controller obtaining the average read count corresponding to the first physical management unit comprises: Obtaining a second read count corresponding to a second physical unit among the plurality of physical units, wherein the second read count reflects a total number of times the read operation is performed on the second physical unit, and the second read count is less than the first read count; Obtaining the average read count according to the first read count and the second read count; as well as After obtaining the average read count, the first read count is saved and the second read count is removed.

18. The memory device according to claim 17, wherein the memory controller saves the first read count and removes the second read count comprising: comparing the first read count and the second read count to obtain a comparison result; as well as According to the comparison result, the first read count is saved, and the second read count is removed.

19. The storage device according to claim 18, wherein the memory controller saves the first read count and removes the second read count according to the comparison result, comprising: In response to the comparison result reflecting that the second read count is less than the first read count, the first read count is saved and the second read count is removed.

20. The memory device according to claim 11, wherein the memory controller is further configured to: The read verification operation is continuously performed on the physical programming units located on a plurality of non-adjacent word lines in the first physical management unit.

Images