Method for operating storage device and storage device

Abstract

A nonvolatile memory device includes a multi-level cell in a memory cell array, the memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of pages. A method of operating the nonvolatile memory device includes: preprogramming multi-bit data in a preprogramming block of the memory block, dividing the multi-level cell into a plurality of state groups based on a state code indicating a state of the multi-level cell to generate summary data indicating a state group code corresponding to the state group, and programming the summary data in a summary block of the memory block.

Description

[0001] This application is a divisional application of the invention patent application with the application date of September 6, 2019, the Chinese application number 2019108408524, and the invention name “Method for operating a storage device and a storage device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] Priority is claimed on Korean Patent Application No. 10-2018-0159593 filed on December 12, 2018 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0004] The inventive concepts herein generally relate to memory devices, and more particularly, to a method of operating a nonvolatile memory device, a method of operating a memory device, and a memory device. Background Art

[0005] Semiconductor memory devices can be classified into volatile memory and non-volatile memory. When the power is off, the volatile memory may lose the content stored therein. Non-volatile memory can retain the stored content even when the power is off. The characteristics of flash memory as a non-volatile memory device include large capacity storage capacity, relatively high noise resistance, and low power operation. Flash memory devices are therefore adopted in various fields. For example, mobile systems such as smart phones, tablet PCs, etc. typically use flash memory as a storage medium.

[0006] In order to increase storage capacity, there has recently been interest in flash memories formed of multi-cell cells storing two or more bits of data per cell. Summary of the invention

[0007] Embodiments of the inventive concept provide a method of operating a nonvolatile memory device capable of enhancing programming performance and efficiency of a memory space.

[0008] Embodiments of the inventive concept provide a method of operating a memory device, which can enhance programming performance and efficiency of a memory space.

[0009] Embodiments of the inventive concept provide a nonvolatile memory device capable of enhancing programming performance and efficiency of a memory space.

[0010] An embodiment of the inventive concept provides a storage device, including: a nonvolatile memory including a plurality of memory blocks, the memory blocks including a preprogrammed block and a summary block, the preprogrammed block including a plurality of first cells, the summary block including a plurality of second cells; and a memory controller configured to preprogram data in the plurality of first cells, divide the plurality of first cells into a plurality of state groups, generate summary data indicating state group codes corresponding to the plurality of state groups, program the summary data stored in the summary block, and control the preprogrammed block and the summary block as a pair, wherein each of the plurality of first cells stores more bits than each of the plurality of second cells.

[0011] An embodiment of the inventive concept provides a method of a nonvolatile memory device, the nonvolatile memory device including a memory cell array, the memory cell array including a plurality of memory blocks, and each of the plurality of memory blocks including a plurality of pages. The method includes preprogramming multi-bit data in a multi-level cell in a preprogramming block of the plurality of memory blocks; after preprogramming the multi-bit data, dividing the multi-level cell into a plurality of state groups based on a state code indicating a state of the multi-level cell to generate digest data indicating a state group code corresponding to the plurality of state groups; and programming the digest data in a digest block of the plurality of memory blocks.

[0012] Embodiments of the inventive concept further provide a method of operating a storage device, the storage device including a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a plurality of memory blocks, and each of the memory blocks includes a plurality of pages. The method includes preprogramming multi-bit data as preprogrammed multi-bit data in a multi-level cell in a preprogrammed block of the plurality of memory blocks; after preprogramming the multi-bit data, dividing the multi-level cell into a plurality of state groups based on a state code indicating a state of the multi-level cell to generate summary data indicating a state group code corresponding to the plurality of state groups; programming the summary data in the summary blocks of the plurality of memory blocks; restoring target data by the controller based on the preprogrammed multi-bit data and the summary data; and reprogramming the restored target data in the multi-level cell in the preprogrammed block.

[0013] Embodiments of the inventive concept further provide a storage device, the storage device including a nonvolatile memory device and a controller for controlling the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of pages. The controller controls the nonvolatile memory device so that the nonvolatile memory device performs preprogramming, the preprogramming preprogramming multi-bit data in a multi-level cell in a preprogramming block of the plurality of memory blocks; after the preprogramming, based on a state code indicating a state of the multi-level cell, the multi-level cell is divided into a plurality of state groups to generate summary data indicating a state group code corresponding to the plurality of state groups; and performs summary programming, the summary programming programming summary data in a summary block of the plurality of memory blocks.

[0014] Therefore, a nonvolatile memory device or storage device preprograms multi-bit data in multi-level cells in a preprogrammed block and programs summary data generated based on a status code of the preprogrammed multi-bit data in a summary block, thereby enhancing programming performance and efficiency of a storage space. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0016] Figure 1 A block diagram of an electronic device according to an embodiment of the inventive concept is shown.

[0017] Figure 2 The embodiment according to the present invention is shown Figure 1 Block diagram of a storage device in .

[0018] Figure 3 The embodiment according to the present invention is shown Figure 2 A block diagram of a memory controller in a storage device.

[0019] Figure 4 The embodiment according to the present invention is shown Figure 2 A block diagram of a non-volatile memory device in a storage device.

[0020] Figure 5 Shows Figure 4 Block diagram of the memory cell array in FIG.

[0021] Figure 6 Shows Figure 5 Circuit diagram of one of the memory blocks in FIG.

[0022] Figure 7 Shows Figure 8 An example of the structure of a cell string in a memory block.

[0023] Figure 8 The embodiment according to the present invention is shown Figure 4 A block diagram of a control circuit in a non-volatile memory device.

[0024] Fig. 9 The embodiment according to the present invention is shown Figure 4 Block diagram of a voltage generator in a non-volatile memory device.

[0025] Fig.10 A flowchart of a method of operating a nonvolatile memory device according to an embodiment of the inventive concept is shown.

[0026] Fig.11 Shows Figure 4 A pre-programmed block and a summary block in a memory cell array of a non-volatile memory device.

[0027] Fig.12 A diagram illustrating an example of threshold voltage distribution of a multi-level cell after a pre-programming operation.

[0028] Fig.13 Shows Figure 4 A block diagram of an example of a page buffer included in a page buffer circuit in a nonvolatile memory device.

[0029] Fig.14 Shows Figure 4 A block diagram of another example of a page buffer included in a page buffer circuit in a nonvolatile memory device.

[0030] Fig.15 Shows Figure 4 A block diagram of another example of a page buffer included in a page buffer circuit in a nonvolatile memory device.

[0031] Fig.16 Shows Figure 4 A block diagram of an example of a memory cell array included in a nonvolatile memory device.

[0032] Fig.17 Shows Figure 4 A block diagram of a logic circuit included in a non-volatile memory device.

[0033] Fig.18 Shows Fig.17 A block diagram of an example of a logic circuit.

[0034] Fig.19 Shows Fig.17 A block diagram of another example of a logic circuit.

[0035] Fig. 20A flowchart of a method of operating a storage device according to an embodiment of the inventive concept is shown.

[0036] Fig.21A , Fig. 21B and Fig. 21C Shows the description Figure 2 A diagram of the operation of a storage device.

[0037] Fig. 22 A flowchart of a method of operating a nonvolatile memory device according to an embodiment of the inventive concept is shown.

[0038] Fig.23 A block diagram of a solid state disk or solid state drive (SSD) according to an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0039] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.

[0040] As traditional in the field of the present invention, the embodiment can be described and illustrated according to the block that performs the one or more functions described. These blocks (which may be referred to as units or modules, etc. herein) are physically implemented by analog and / or digital circuits, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and can be optionally driven by firmware and / or software. For example, the circuit can be specifically implemented in one or more semiconductor chips, or specifically implemented on substrate supports such as printed circuit boards, etc. The circuit constituting the block can be implemented by dedicated hardware, or implemented by a processor (for example, one or more programmed microprocessors and associated circuits), or implemented by a combination of dedicated hardware for executing some functions of the block and a processor for executing other functions of the block. Without departing from the scope of the present invention, each block of the embodiment can be physically separated into two or more interactive discrete blocks. Similarly, without departing from the scope of the present invention, the blocks of the embodiment can be physically combined into more complex blocks.

[0041] Figure 1 A block diagram of an electronic device according to an embodiment of the inventive concept is shown.

[0042] refer to Figure 1, the electronic device 10 includes a host 20 and a storage device (or storage system) 30. The storage device 30 includes a memory controller (or controller) 100 and at least one nonvolatile memory device (NVM) 200. The host 20 may control the overall operation of the storage device 30.

[0043] The nonvolatile memory device 200 may be implemented with a NAND flash memory. In an example embodiment, the nonvolatile memory device 200 may include a nonvolatile memory such as, for example, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), etc.

[0044] The memory controller 100 may exchange signals such as commands, addresses, data, etc. with the host 20 . The memory controller 100 may write and read data in and from the nonvolatile memory device 200 according to a command from the host 20 .

[0045] Figure 2 The embodiment according to the present invention is shown Figure 1 Block diagram of a storage device in .

[0046] refer to Figure 2 , the storage device 30 includes a memory controller 100 and at least one nonvolatile memory device 200 .

[0047] In example embodiments, each of the memory controller 100 and the nonvolatile memory device 200 may be provided in the form of a chip, a package, or a module. Alternatively, the memory controller 100 and the non-volatile memory device 200 may be packaged according to any of a variety of packaging technologies, such as, for example, package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flat pack (TQFP), system in package (SIP), multi chip package (MCP), etc. package, MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP), etc.

[0048] The nonvolatile memory device 200 may perform an erase operation, a program operation, or a write operation under the control of the memory controller 100. The nonvolatile memory device 200 may receive a command CMD, an address ADDR, and data DATA from the memory controller 100 through an input / output line for performing such an operation. In addition, the nonvolatile memory device 200 may receive a control signal CTRL from the memory controller 100 through a control line. In addition, the nonvolatile memory device 200 may receive power PWR from the memory controller 100 through a power line.

[0049] The memory cells of the nonvolatile memory device 200 have physical characteristics in which the threshold voltage distribution varies due to reasons such as, for example, programming elapsed time, temperature, program disturbance, and read disturbance. For example, due to the above reasons, the data stored at the nonvolatile memory device 200 may become erroneous. The memory controller 100 utilizes various error correction techniques to correct such errors. For example, the memory controller 100 includes an error correction code (ECC) engine (unit) 120 and a read manager 131. In addition, the memory controller 100 includes a program manager 133 that manages various programming operations.

[0050] During a read operation, the memory controller 100 may read data stored at a first page of the nonvolatile memory device 200 using a default read voltage set. The default read voltage set may include a predetermined read voltage. The ECC engine 120 may detect and correct errors included in data read from the nonvolatile memory device 200. In an example embodiment, the ECC engine 120 may be implemented in the form of hardware.

[0051] The data read in the read operation may include more error bits than the ECC engine 120 can correct. In such a case, the ECC engine 200 cannot correct the errors of the data, and the corresponding data may be referred to as including or having "uncorrectable error correction code (UECC) errors". Data having UECC errors may be referred to as "UECC data".

[0052] When data read with the default read voltage set includes a UECC error, the read manager 131 may, for example, adjust the read voltage set of the nonvolatile memory device 200. The memory controller 100 transmits an address ADDR, a command CMD, and a control signal CTRL so that the nonvolatile memory device 200 performs a read operation with the thus adjusted read voltage set.

[0053] The adjusted read voltage set may be included in the control signal CTRL or the command CMD. The ECC engine 120 detects and corrects errors of data read using the adjusted read voltage set.

[0054] In an example embodiment, the read manager 131 may adjust the read voltage set a predetermined number of times, and the ECC engine 120 may detect and correct errors in data read using the adjusted read voltage set. For example, the memory controller 100 may repeat a set of operations, including adjusting the read voltage set, reading data using the adjusted read voltage set, and correcting errors in the read data, a predetermined number of times.

[0055] When an error of the read data is corrected during iteration of a set of operations, the memory controller 100 outputs the corrected data to the host 20. When the read operation is iterated under the control of the read manager 131, for example, the read data or specific page data of the read data is stored in a buffer such as Figure 3 The buffer 130 may be a static random access memory (SRAM).

[0056] When an error of read data is not corrected after iteration of a set of operations (ie, when a UECC error occurs), the memory controller 100 determines a start voltage set for performing a valley search operation based on data stored in the buffer 130 .

[0057] In example embodiments of the inventive concepts, iterations of adjusting a set of read voltages and reading data using the adjusted set of read voltages may be omitted.

[0058] When an error of the read data is not corrected after a read operation based on the default read voltage set or after iteration of the set of operations, the memory controller 100 selects a programming state including a highest bit error rate from among the data stored in the buffer 130, and determines a read voltage corresponding to the selected programming state as a starting voltage set. The read manager 131 performs a valley search operation based on the determined starting voltage set to determine an optimal read level voltage, and performs a recovery read operation on the read data based on the optimal read level voltage.

[0059] In order to determine the optimal read level voltage, the read manager 131 sets a search area defined by a start read voltage and an end read voltage, determines whether the search area belongs to a reference area, changes the search area if the search area does not belong to the reference area, and searches for a new read voltage to determine the optimal read level voltage if the search area belongs to the reference area.

[0060] The program manager 133 may manage a program operation on a multi-level cell in the nonvolatile memory device 200. The program manager 133 may control the nonvolatile memory device 200 so that the nonvolatile memory device 200 performs pre-programming to pre-program multi-bit data in a multi-level cell in a pre-programming block in a memory cell array, and performs digest programming to program digest data in a digest block in the memory cell array. The digest data may be generated based on a state code indicating a state of the multi-level cell. In addition, the program manager 133 controls the nonvolatile memory device 200 to restore target data based on the pre-programmed multi-bit data and the digest data, and reprogram the restored target data in the multi-level cell in the pre-programming block.

[0061] The program manager 133 may selectively program schemes such as single level cell buffering, digest programming, and reprogramming to the nonvolatile memory device 200 based on at least one of performance of the nonvolatile memory device 200 , efficiency of storage space, and reliability.

[0062] Figure 3 The embodiment according to the present invention is shown Figure 2 A block diagram of a memory controller in a storage device.

[0063] refer to Figure 2 and Figure 3 , the memory controller 100 includes a processor 110, an ECC engine 120, a buffer 130, a randomizer 140, a host interface 150, a read only memory (ROM) 160, a migration manager 180, and a non-volatile memory interface 170 connected via a bus 105. The buffer 130 includes a read manager 131 and a program manager 133. Figure 2 The ECC engine 120 , the buffer 130 , the read manager 131 , and the program manager 133 are described, and further description thereof may be omitted hereinafter.

[0064] The processor 110 controls the overall operation of the memory controller 100. In example embodiments, the read manager 131 and the program manager 133 may be implemented in software and stored in the buffer 130. The read manager 131 and the program manager 133 stored in the buffer 130 may be driven by the processor 110. The ROM 160 stores various information required for the memory controller 100 to operate in firmware.

[0065] The randomizer 140 randomizes data to be stored in the nonvolatile memory device 200. For example, the randomizer 140 randomizes data to be stored in the nonvolatile memory device 200 by word line.

[0066] Data randomization processes data so that the programming states of memory cells connected to word lines have the same ratio. For example, if the memory cells connected to one word line are multi-level cells (MLC) each storing 4-bit data, each of the memory cells has an erased state and one of the first to fifteenth programming states. In this case, the randomizer 140 randomizes data so that, among the memory cells connected to one word line, the number of memory cells having an erased state and the number of memory cells having one of the first to fifteenth programming states are substantially the same as each other. For example, memory cells storing randomized data have programming states whose ratios are equal to each other. The randomizer 140 derandomizes the data read from the nonvolatile memory device 200.

[0067] The randomizer 140 randomizes page data. For ease of understanding, an ideal operation of the randomizer 140 has been described. However, the inventive concept is not limited thereto. For example, the randomizer 140 may randomize data so that, among memory cells connected to one word line, the number of memory cells having an erased state and the number of memory cells having one of the first to fifteenth programming states are close to the same value. For example, memory cells storing randomized data have programming states whose ratios are similar to each other.

[0068] The migration manager 180 may manage the migration of the preprogrammed data and the summary data. The migration manager 180 may migrate the preprogrammed data and the summary data corresponding to the preprogrammed data to the logic circuit 190 (refer to Fig. 21B ). If the migration of the digest data is completed, the migration manager 180 notifies the processor 110 of the completion of the migration of the digest data, and the processor 110 controls the nonvolatile memory device 200 to perform an erase operation on the digest block.

[0069] The memory controller 100 communicates with the host 20 through the host interface 150. The host interface 150 may be configured according to any of a variety of different communication protocols, such as, for example, Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnection (PCI), High-Speed ​​PCI, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industry Processor Interface (MIPI), etc. ), nonvolatile memory express (NVMe), universal flash storage (UFS), etc. The memory controller 100 communicates with the nonvolatile memory device 200 through the nonvolatile memory interface 170.

[0070] Figure 4 The embodiment according to the present invention is shown Figure 2 A block diagram of a non-volatile memory device in a storage device.

[0071] refer to Figure 4 , the nonvolatile memory device 200 includes a memory cell array 300 , an address decoder 430 , a page buffer circuit 410 , a data input / output (I / O) circuit 420 , a control circuit 500 , and a voltage generator 700 .

[0072] The memory cell array 300 is coupled to the address decoder 430 through one or more string selection lines SSL, a plurality of word lines WL, and one or more ground selection lines GSL. In addition, the memory cell array 300 is coupled to the page buffer circuit 410 through a plurality of bit lines BL.

[0073] The memory cell array 300 may include a plurality of memory cells coupled to a plurality of word lines WL and a plurality of bit lines BL.

[0074] In some example embodiments, the memory cell array 300 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 300 may include a vertical cell string vertically oriented so that at least one memory cell is located above another memory cell.

[0075] In other example embodiments, the memory cell array 300 may be a two-dimensional memory cell array formed on a substrate in a two-dimensional structure (or a horizontal structure).

[0076] Figure 5 It is shown Figure 4 Block diagram of the memory cell array in FIG.

[0077] refer to Figure 5 , the memory cell array 300 may include a plurality of memory blocks BLK1 to BLKz (z is an integer greater than 2) extending along first to third directions D1, D2, and D3. In an embodiment, the memory blocks BLK1 to BLKz are composed of Figure 4 For example, the address decoder 430 may select a memory block BLK corresponding to the block address among the memory blocks BLK1 to BLKz.

[0078] Figure 6 Shows Figure 5 Circuit diagram of one of the memory blocks in FIG.

[0079] Figure 6 The memory block BLKi may be formed on the substrate in a three-dimensional structure (or a vertical structure). For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a direction PD perpendicular to the substrate.

[0080] refer to Figure 6 , the memory block BLKi may include memory cell strings NS11 to NS33 (i.e., NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33) coupled between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the memory cell strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8 (i.e., MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8), and a ground selection transistor GST. Figure 6 , each of the memory cell strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, example embodiments are not limited thereto. In some example embodiments, each of the memory cell strings NS11 to NS33 may include any number of memory cells.

[0081] The string selection transistor SST may be connected to the corresponding string selection lines SSL1, SSL2, and SSL3. A plurality of memory cells MC1 to MC8 may be connected to the corresponding word lines WL1 to WL8 (i.e., WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8), respectively. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0082] Word lines (eg, WL1) having the same height may be commonly connected, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated. Figure 6 , the memory block BLKi is shown as being coupled to eight word lines WL1 to WL8 and three bit lines BL1 to BL3. However, example embodiments are not limited thereto. In some example embodiments, the memory cell array 300 may be coupled to any number of word lines and bit lines.

[0083] Figure 7 Shows Figure 8 An example of the structure of a cell string in a memory block.

[0084] refer to Figure 6 and Figure 7 , a pillar PL is provided on the substrate SUB such that the pillar PL extends in a direction perpendicular to the substrate SUB to contact the substrate SUB. Figure 7 Each of the ground selection line GSL, word lines WL1 to WL8, and string selection line SSL shown in FIG. 1 may be formed of a conductive material arranged in parallel with the substrate SUB. For example, the conductive material may be a metal material. The pillar PL may contact the substrate SUB through the conductive material forming the string selection line SSL, word lines WL1 to WL8, and ground selection line GSL.

[0085] Figure 7 A cross-sectional view taken along line AA' is also shown in FIG. In an embodiment, a cross-sectional view of a first memory cell MC1 corresponding to a first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be defined inside the body BD.

[0086] The cylindrical body BD may include P-type silicon and may be a region where a channel is to be formed. The column PL may further include a cylindrical tunnel insulating layer TI surrounding the cylindrical body BD, and a cylindrical charge trap layer CT surrounding the cylindrical tunnel insulating layer TI. A blocking insulating layer BI may be provided between the first word line WL and the column PL. The cylindrical body BD, the cylindrical tunnel insulating layer TI, the cylindrical charge trap layer CT, the blocking insulating layer BI, and the first word line WL may constitute a charge trap type transistor formed in a direction perpendicular to the substrate SUB or perpendicular to the upper surface of the substrate SUB. The string selection transistor SST, the ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0087] Return to reference Figure 4 , the control circuit 500 may receive a command (signal) CMD and an address (signal) ADDR from the memory controller 100 , and control an erase cycle, a program cycle, and a read operation of the nonvolatile memory device 200 based on the command signal CMD and the address signal ADDR.

[0088] A program loop may include a program operation and a program verification operation. An erase loop may include an erase operation and an erase verification operation. A read operation may include a default read operation and a recovery read operation.

[0089] For example, the control circuit 500 may generate a control signal CTL for controlling the voltage generator 700 and a control signal PCTL for controlling the page buffer circuit 410 based on the command signal CMD, and may generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 500 may provide the row address R_ADDR to the address decoder 430, and may provide the column address C_ADDR to the data input / output circuit 420.

[0090] The address decoder 430 is coupled to the memory cell array 300 through one or more string selection lines SSL, a plurality of word lines WL, and one or more ground selection lines GSL. During a program operation or a read operation, the address decoder 430 may determine one of the plurality of word lines WL as a selected word line, and determine the remaining word lines of the plurality of word lines WL except the selected word line as unselected word lines based on a row address R_ADDR.

[0091] The voltage generator 700 may generate a word line voltage VWL required for operation of the nonvolatile memory device 200 based on a control signal CTL from the control circuit 500. The voltage generator 700 may receive power PWR from the memory controller 100. The word line voltage VWL may be applied to a plurality of word lines WL through the address decoder 430.

[0092] For example, during an erase operation, the voltage generator 700 may apply an erase voltage to a well of a memory block and may apply a ground voltage to all word lines of the memory block. During an erase verification operation, the voltage generator 700 may apply an erase verification voltage to all word lines of the memory block, or may sequentially apply the erase verification voltage to the word lines on a word line basis.

[0093] For example, during a program operation, the voltage generator 700 may apply a program voltage to a selected word line and may apply a program pass voltage to unselected word lines. In addition, during a program verification operation, the voltage generator 700 may apply a program verification voltage to a selected word line and may apply a verification pass voltage to unselected word lines.

[0094] In addition, during the default read operation, the voltage generator 700 may apply a default read voltage to a selected word line and may apply a read pass voltage to unselected word lines. During the recovery read operation, the voltage generator 700 may apply an optimal read level voltage to a selected word line.

[0095] The page buffer circuit 410 is coupled to the memory cell array 300 through a plurality of bit lines BL. The page buffer circuit 410 may include a plurality of page buffers. In some example embodiments, one page buffer may be connected to one bit line. In other example embodiments, one page buffer may be connected to two or more bit lines.

[0096] The page buffer circuit 410 may temporarily store data to be programmed in a selected page or data read out from a selected page.

[0097] The data input / output circuit 420 is coupled to the page buffer circuit 410 through the data line DL. During a program operation, the data input / output circuit 420 may receive program data DATA from the memory controller 100 and provide the program data DATA to the page buffer circuit 410 based on the column address C_ADDR received from the control circuit 500. During a read operation, the data input / output circuit 420 may provide read data DATA stored in the page buffer circuit 410 to the memory controller 100 based on the column address C_ADDR received from the control circuit 500.

[0098] Figure 8 The embodiment according to the present invention is shown Figure 4 A block diagram of a control circuit in a non-volatile memory device.

[0099] refer to Figure 8 , the control circuit 500 includes a command decoder 510 , an address buffer 520 , and a control signal generator 530 .

[0100] The command decoder 510 decodes the command CMD and provides the decoded command D_CMD to the control signal generator 530. For example, when the decoded command D_CMD is a read command, the command decoder 510 provides the decoded command D_CMD to the control signal generator 530.

[0101] The address buffer 520 receives the address signal ADDR, provides a row address R_ADDR to the address decoder 430 , and provides a column address C_ADDR to the data input / output circuit 420 .

[0102] The control signal generator 530 receives the decoded command D_CMD, generates a control signal CTL based on the operation directed by the decoded command D_CMD, and provides the control signal CTL to the voltage generator 700. In addition, the control signal generator 530 generates a control signal PCTL based on the operation directed by the decoded command D_CMD, and provides the control signal PCTL to the page buffer circuit 410.

[0103] Fig. 9 The embodiment according to the present invention is shown Figure 4 Block diagram of a voltage generator in a non-volatile memory device.

[0104] refer to Fig. 9 The voltage generator 700 includes a high voltage (HV) generator 710 and a low voltage (LV) generator 730 . The voltage generator 700 may further include a negative voltage (NV) generator 750 .

[0105] The high voltage generator 710 may generate a program voltage VPGM, a program pass voltage VPPASS, a verification pass voltage VVPASS, a read pass voltage VRPASS, and an erase voltage VERS according to an operation directed by a command CMD in response to a first control signal CTL1. The program voltage VPGM is applied to a selected word line, the program pass voltage VPPASS, the verification pass voltage VVPASS, and the read pass voltage VRPASS may be applied to unselected word lines, and the erase voltage VERS may be applied to a well of a memory block. The first control signal CTL1 may include a plurality of bits indicating an operation directed by a command CMD.

[0106] The low voltage generator 730 may generate a program verification voltage VPV, a read voltage VRD, an erase verification voltage VER, and an optimal read level voltage VORD in response to the second control signal CTL2 according to an operation directed by the command CMD. The program verification voltage VPV, the read voltage VRD, the optimal read level voltage VORD, and the erase verification voltage VER may be applied to a selected word line according to an operation of the nonvolatile memory device 200. The second control signal CTL2 may include a plurality of bits indicating an operation directed by the command CMD.

[0107] Negative voltage generator 750 may generate program verification voltage VPV', read voltage VRD', and erase verification voltage VER' having negative levels according to an operation directed by command CMD in response to third control signal CTL3. Third control signal CTL3 may include a plurality of bits indicating an operation directed by command CMD.

[0108] Fig.10 A flowchart of a method of operating a nonvolatile memory device according to an embodiment of the inventive concept is shown.

[0109] Fig.11 Shows Figure 4 A pre-program block (PPG) and a digest block (DGB) in a memory cell array of a non-volatile memory device.

[0110] refer to Figures 4 to 11 , described below is a method of operating a nonvolatile memory device 200, the nonvolatile memory device 200 including a memory cell array 300, the memory cell array 300 including a plurality of memory blocks, each of the memory blocks including a plurality of pages. In operation S110, the control circuit 500 controls the voltage generator 700, the address decoder 430, and the page buffer circuit 410 to perform pre-programming PRE_PGM to pre-program multi-bit data in a multi-level cell in a pre-programming block PPB of the memory block.

[0111] In operation S130, the control circuit 500 divides the multi-level cell into a plurality of state groups GR1 and GR2 based on the state code indicating the state of the multi-level cell to generate summary data DGD indicating the state group code corresponding to the state groups GR1 and GR2. The first state group GR1 may have a state group code "0", and the second state group GR2 may have a state group code "1". Fig.11 , state group codes “0” and “1” are shown in the pre-programming block PPG below the horizontal line representing the threshold voltage Vth.

[0112] In operation S140 , the control circuit 500 controls the voltage generator 700 , the address decoder 430 , and the page buffer circuit 410 to perform the digest program DG_PGM to program the digest data DGD in the digest block DGB of the memory block.

[0113] exist Fig.11 In the embodiment, it is assumed that each of the multi-level cells can store N-bit data (N is a natural number greater than 2) and N is 4. Therefore, each of the multi-level cells may have a state code corresponding to an erase state E0 and one of the first to fifteenth program states P1 to P15. That is, each of the multi-level cells may have a state code corresponding to 2 N The status code is one of the following status codes.

[0114] The control circuit 500 divides (or groups) the multi-level cells into M state groups (M is a natural number less than or equal to N) based on the state codes of the multi-level cells. Fig.11 In , assume that M is 2.

[0115] exist Fig.11 In the embodiment, the first page PAGE1 to the fourth page PAGE4 of data can be pre-programmed sequentially or simultaneously in each of the multi-level cells. The control circuit 500 can divide the multi-level cells into state groups GR1 and GR2 corresponding to sets of non-overlapping threshold voltage distributions.

[0116] In an example embodiment, the control circuit 500 may divide the multi-level cells into state groups GR1 and GR2 based on the number of first bits in each of the state codes in each of the multi-level cells, and each of the first bits may have a first logic level. In the embodiment described below, the first logic level is "1". However, in other embodiments, the first logic level may be "0".

[0117] Therefore, the first state group GR1 may include a first set having non-overlapping threshold voltage distributions or state codes E0, P2, P4, P6, P8, P10, P12, and P14 having an even number of first bits, respectively. For example, each of the state codes E0, P2, P4, P6, P8, P10, P12, and P14 includes an even number of first bits "1". The second state group GR2 may include a second set having non-overlapping threshold voltage distributions or state codes P1, P3, P5, P7, P9, P11, P13, and P15 having an odd number of first bits, respectively. For example, each of the state codes P1, P3, P5, P7, P9, P11, P13, and P15 includes an odd number of first bits "1".

[0118] Because the sixteen state codes E0 and P1 to P15 are divided into the first state group GR1 and the second state group GR2 , the summary data DGD has two states E0 and DP1 , and thus the control circuit 500 may program the summary data DGD in a single level cell in the summary block DGB.

[0119] Therefore, data is maintained without completing reprogramming, and the storage space required to store the summary data DGD in the single-level cells is smaller than the storage space required to store the page of data in each of the single-level cells because the summary data DGD is programmed in the single-level cells. In addition, the memory controller 100 can release the buffer 130 for loading multi-bit data after completing one preprogramming.

[0120] To preprogram the multi-bit data, the control circuit 500 may load the multi-bit data to the page buffer circuit 410 coupled to the multi-level cell. The control circuit 500 may preprogram the multi-bit data loaded to the page buffer circuit 410 in the multi-level cell.

[0121] The control circuit 500 generates the summary data DGD based on the state code of the multi-bit data loaded into the page buffer circuit 410, and can temporarily store the summary data DGD in the page buffer of the page buffer circuit 410. The control circuit 500 can generate the summary data DGD by performing a logical operation on each of the bits in the multi-bit data (as will be described later for Fig.18 and Fig.19 ).

[0122] The control circuit 500 or the memory controller 100 may manage the preprogramming block PPB and the digest block DGB as a pair. That is, the preprogramming block PPB and the digest block DGB corresponding to the preprogramming block PPB may constitute a pair.

[0123] In an example embodiment, if the state code is divided into four state groups, the summary block DGB may include a multi-level cell to store summary data DGD corresponding to the four state groups.

[0124] Fig.12 A diagram illustrating an example of threshold voltage distribution of a multi-level cell after a pre-programming operation.

[0125] Fig.12 An example of storing four bits of data in a multi-level cell is shown.

[0126] refer to Fig.12 , the multi-level cell has a threshold voltage distribution E0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15 that is wider than the threshold voltage distribution shortly after the pre-programming operation. The threshold voltage distributions E0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15 overlap each other.

[0127] Threshold voltage distributions E0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14 and P15 are divided into state groups GR1, GR2, GR3 and GR4 so that each state group includes a set of non-overlapping threshold voltage distributions. For example, the first to sixteenth threshold voltage distributions E0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14 and P15 are divided into a first state group GR1, a second state group GR2, a third state group GR3, and a fourth state group GR4.

[0128] The first state group GR1 includes a non-overlapping first threshold voltage distribution (ie, erased state) E0, a fifth threshold voltage distribution (ie, fourth programming state) P4, a ninth threshold voltage distribution (ie, eighth programming state) P8, and a thirteenth threshold voltage distribution (ie, twelfth programming state) P12. The second state group GR2 includes a non-overlapping second threshold voltage distribution (ie, first programming state) P1, a sixth threshold voltage distribution (ie, fifth programming state) P5, a tenth threshold voltage distribution (ie, ninth programming state) P9, and a fourteenth threshold voltage distribution (ie, thirteenth programming state) P13.

[0129] The third state group GR3 includes a non-overlapping third threshold voltage distribution (i.e., second programming state) P2, a seventh threshold voltage distribution (i.e., sixth programming state) P6, an eleventh threshold voltage distribution (i.e., tenth programming state) P10, and a fifteenth threshold voltage distribution (i.e., fourteenth programming state) P14. The fourth state group GR4 includes a non-overlapping fourth threshold voltage distribution (i.e., third programming state) P3, an eighth threshold voltage distribution (i.e., seventh programming state) P7, a twelfth threshold voltage distribution (i.e., eleventh programming state) P11, and a sixteenth threshold voltage distribution (i.e., fifteenth programming state) P15.

[0130] The state group code can be assigned to the state groups GR1, GR2, GR3 and GR4. For example, the state group code "11" is assigned to the first state group GR1, the state group code "01" is assigned to the second state group GR2, the state group code "00" is assigned to the third state group GR3, and the state group code "10" is assigned to the fourth state group GR4.

[0131] The number of bits in each state group code is typically determined based on the number of state groups, and the number of state groups is typically determined based on the maximum number of threshold voltage distributions that overlap in any point. Fig.12 In the example of , at most four threshold voltage distributions overlap at some points, and thus the number of state groups is four, and the number of bits of each state group code is two. For example, the second threshold voltage distribution P1 overlaps the third to fifth threshold voltage distributions P2, P3, and P4, and thus four state groups are required for including non-overlapping state groups.

[0132] The control circuit 500 may program summary data DGD indicating a state group code in a summary block DGB in a memory block.

[0133] Fig.13 Shows Figure 4 A block diagram of an example of a page buffer included in a page buffer circuit in a nonvolatile memory device.

[0134] refer to Fig.13 , the page buffer 411a includes a first data latch 412a, a second data latch 413a, and a third data latch 414a.

[0135] The first data latch 412a, the second data latch 413a, and the third data latch 414a can respectively temporarily store three bits of the multi-bit data DATA. For example, the first data latch 412a can store the first bit of the multi-bit data, the second data latch 413a can store the second bit of the multi-bit data, and the third data latch 414a can store the third bit of the multi-bit data. The third data latch 414a can be used as a state group code latch that temporarily stores the state group code SGC of the multi-level cell.

[0136] Fig.14 Shows Figure 4 A block diagram of another example of a page buffer included in a page buffer circuit in a nonvolatile memory device.

[0137] refer to Fig.14 , the page buffer 411b includes a first data latch 412b, a second data latch 413b, a third data latch 414b, and a state group code latch 415b.

[0138] The first data latch 412b, the second data latch 413b, and the third data latch 414b can temporarily store three bits of the multi-bit data DATA, respectively. The state group code latch 415b can temporarily store the first state group code SGC11. The third data latch 414b can be used as a state group code latch for temporarily storing the second state group code SGC12. For example, the first state group code SGC11 can indicate the state group of the multi-level cell coupled to the currently selected word line, and the second state group code SGC12 can indicate the state group of the multi-level cell coupled to the adjacent word line.

[0139] Fig.15 Shows Figure 4 A block diagram of another example of a page buffer included in a page buffer circuit in a nonvolatile memory device.

[0140] refer to Fig.15 , the page buffer 411c includes a first data latch 412c, a second data latch 413c, a third data latch 414c, a first state group code latch 415c, and a second state group code latch 416c.

[0141] The first data latch 412c, the second data latch 413c, and the third data latch 414c can temporarily store three bits of the multi-bit data DATA, respectively. The first state group code latch 415c can temporarily store the first state group code SGC21, and the second state group code latch 416c can temporarily store the second state group code SGC22. For example, the first state group code SGC21 can indicate the state group of the multi-level cells coupled to the currently selected word line, and the second state group code SGC22 can indicate the state group of the multi-level cells coupled to the adjacent word line.

[0142] In some embodiments, a state group code may be generated based on the multi-bit data loaded into the page buffer 411c, and the first state group code latch 415c or the second state group code latch 416c may temporarily store the generated state group code. The page buffer 411c may further include a logic circuit that performs a logic operation on the bits of the multi-bit data temporarily stored in the first data latch 412c, the second data latch 413c, and the third data latch 414c.

[0143] Fig.16 Shown included in Figure 4 A block diagram of an example of a memory cell array in a nonvolatile memory device.

[0144] refer to Fig.16 , the memory cell array 300 a includes a plurality of data blocks 311 , 312 , and 313 , and a state group code (SGC) memory block 314 .

[0145] The data blocks 311 (BLOCK1), 312 (BLOCK2), and 313 (BLOCKK) may include multi-level cells storing multi-bit data. The state group code memory block 314 may store the state group code of the multi-level cells included in the data blocks 311, 312, and 313. The state group code memory block 314 may include a single-level cell. In some embodiments, the state group code memory block 314 may be based on the state group code loaded into the state group code memory block 314. Figure 4 The page buffer circuit 410 in the embodiment is used for multi-bit data of a pre-programming operation to generate a state group code, and the state group code memory block 314 may store the generated state group code.

[0146] The memory controller may perform a pre-program operation by using at least some of the data blocks 311, 312, and 313 as pre-program blocks PPB, and may perform digest programming by using the state group code memory block 314 as a digest block.

[0147] Fig.17 Shown included in Figure 4A block diagram of a logic circuit in a non-volatile memory device.

[0148] refer to Fig.17 , the logic circuit 460 generates summary data DGD indicating the state group code. In some embodiments, the logic circuit 460 may include Figure 4 In other embodiments, the logic circuit 460 may be included in the page buffer circuit 410. Figure 4 The logic circuit 460 is loaded into the control circuit 500 by Figure 4 The page buffer circuit 410 in the embodiment performs a logic operation on the bits of the multi-bit data of the pre-programming operation to generate the summary data DGD.

[0149] Fig.18 and Fig.19 Shows Fig.17 A block diagram of an example of a logic circuit.

[0150] refer to Fig.18 , the logic circuit 470 includes AND gates 471 to 478 (i.e., 471, 472, 473, 474, 475, 476, 477, and 478) and an OR gate 479. AND gate 471 outputs a logic high level when the first bit B1, the second bit B2, the third bit B3, and the fourth bit B4 of the multi-bit data are "0111". AND gate 472 outputs a logic high level when the multi-bit data is "0001". AND gate 473 outputs a logic high level when the multi-bit data is "1110". AND gate 474 outputs a logic high level when the multi-bit data is "0100". AND gate 475 outputs a logic high level when the multi-bit data is "0010". AND gate 476 outputs a logic high level when the multi-bit data is "1011". AND gate 477 outputs a logic high level when the multi-bit data is "1110". The AND gate 478 outputs a logic high level when the multi-bit data is "1101". Therefore, when the multi-bit data is "0111", "0001", "1110", "0100", "0010", "1011", "1110" or "1101", the logic circuit 470 outputs the summary data DGD corresponding to "1".

[0151] refer to Fig.19 , logic circuit 480 includes exclusive OR (XOR) gates 481 , 482 and 483 .

[0152] XOR gate 481 performs a logical XOR operation on the first bit B1 and the second bit B2 of the multi-bit data. XOR gate 482 performs a logical XOR operation on the third bit B3 of the multi-bit data and the output of XOR gate 481. XOR gate 483 performs a logical XOR operation on the fourth bit B4 of the multi-bit data and the output of XOR gate 482 to output summary data DGD. Therefore, when the multi-bit data is "0111", "0001", "1110", "0100", "0010", "1011", "1110" or "1101", logic circuit 480 can output summary data DGD corresponding to "1".

[0153] Although Fig.18 and Fig.19 An example of the logic circuit 460 is shown, but the logic circuit 460 may be implemented with various circuits. In addition, the logic circuit 460 may have various forms according to the number of bits of multi-bit data.

[0154] Fig. 20 A flowchart of a method of operating a storage device according to an embodiment of the inventive concept is shown.

[0155] refer to Figures 1 to 20 , a method of operating a memory device is provided, the memory device including a nonvolatile memory device 200 and a controller 100 controlling the nonvolatile memory device 200. The nonvolatile memory device 200 includes a memory cell array 300, the memory cell array 300 includes a plurality of memory blocks, and each of the memory blocks includes a plurality of pages. In operation S210, the control circuit 500 controls the voltage generator 700, the address decoder 430, and the page buffer circuit 410 to perform pre-programming PRE_PGM to pre-program multi-bit data in a multi-level cell in a pre-programming block PPB of the memory block.

[0156] In operation S220, the control circuit 500 divides the multi-level cells into a plurality of state groups based on state codes indicating states of the multi-level cells to generate summary data DGD indicating state group codes corresponding to the state groups.

[0157] In operation S230 , the control circuit 500 controls the voltage generator 700 , the address decoder 430 , and the page buffer circuit 410 to perform the digest program DG_PGM to program the digest data DGD in the digest block DGB of the memory block.

[0158] In operation S240, the controller (memory controller) 100 restores the target data based on the preprogrammed data and the summary data DGD. The controller 100 can restore the target data by performing a logic operation on the preprogrammed data and the summary data DGD using a logic circuit. In operation S250, the controller 250 reprograms the restored target data in the multi-level cells in the preprogrammed block PPB.

[0159] FIG. 21A to FIG. 21C Shows the description Figure 2 A diagram of the operation of a storage device.

[0160] refer to Figure 2 , Figure 3 , Figure 4 and Fig.21A , the control circuit 500 controls the voltage generator 700, the address decoder 430 and the page buffer circuit 410 to preprogram the multi-level data in the multi-level cells in the preprogramming block PPB1 and program the summary data in the summary block DGB1. When the preprogramming and the summary programming are completed, the preprogrammed multi-bit data PPD11, PPD12, PPD13 and PPD14 are stored in the preprogramming block PPB1, and the summary data DGD11, DGD12, DGD13 and DGD14 are stored in the summary block DGB1. The preprogrammed multi-bit data PPD11, PPD12, PPD13 and PPD14 correspond to the summary data DGD11, DGD12, DGD13 and DGD14, respectively. For example, the preprogramming block PPB1 and the summary block DGB1 may constitute a pair.

[0161] refer to Fig. 21B , the controller 100 provides the pre-programmed multi-bit data PPD11, PPD12, PPD13 and PPD14 to the logic circuit 190 in the controller 100 (as indicated by reference number 610), and the controller 100 migrates the summary data DGD11, DGD12, DGD13 and DGD14 to the logic circuit 190 (as indicated by reference number 620).

[0162] The logic circuit 190 recovers the target data TD by performing a logic operation on the preprogrammed multi-bit data PPD11, PPD12, PPD13, and PPD14 and the summary data DGD11, DGD12, DGD13, and DGD14. The logic circuit 190 stores the recovered target data TD in the buffer 130 in units of pages PAGE1, PAGE2, PAGE3, and PAGE4, ​​and the controller 100 reprograms the target data TD in the buffer 130 in the multi-level cells in the preprogrammed block PPB1 (as indicated by reference character RE_PGM). Therefore, some of the preprogrammed multi-bit data PPD11, PPD12, PPD13, and PPD14 are changed into multi-page data MPG11 and MPG12. Each of the multi-page data MPG11 and MPG12 includes pages of a plurality of data.

[0163] refer to Fig. 21C , if the reprogramming is completed and the migration of the summary data DGD11, DGD12, DGD13, and DGD14 in the summary block DGB1 is completed, the multi-page data MPG11, MPG12, MPG13, and MPG14 are stored in the pre-programming block PPB1. Therefore, the controller 100 changes the pre-programming block PPB1 into a multi-bit block MBB1, wherein the multi-bit block MBB1 stores the multi-page data MPG11, MPG12, MPG13, and MPG14, and each of the multi-page data MPG11, MPG12, MPG13, and MPG14 includes a plurality of pages of data. In addition, the controller 100 changes the summary block DGB1 into a free block FB1 that does not store data by performing an erase operation ERS_OP on the summary block DGB1.

[0164] Fig. 22 A flowchart of a method of operating a nonvolatile memory device according to an embodiment of the inventive concept is shown.

[0165] refer to Figures 4 to 19 and Fig. 22 , after performing a pre-programming operation and a digest programming for multi-level cells coupled to a next word line, a read operation and a reprogramming operation for multi-level cells coupled to a current word line are performed.

[0166] For example, in operation S310, multi-bit data is preprogrammed in a multi-level cell coupled to a (k+1)th word line (WL), and in operation S330, summary data is generated based on the state code of the multi-level cells in the page corresponding to the (k+1)th word line. After the pre-programming operation for the multi-level cell coupled to the (k+1)th word line, in operation S350, data is read from the multi-level cell coupled to the kth word line, and in operation S370, the multi-bit data is reprogrammed in the multi-level cell coupled to the kth word line.

[0167] As described above, since the read operation and the reprogram operation for a word line are performed after the preprogram operation for the next word line is performed, the multi-level cells coupled to the word line may be less affected by coupling due to the memory cells coupled to the next word line.

[0168] Fig.23 A block diagram of a solid state disk or solid state drive (SSD) according to an embodiment of the inventive concept is shown.

[0169] refer to Fig.23 , the SSD 1000 includes a plurality of nonvolatile memory devices 1100 and an SSD controller 1200 .

[0170] An external high voltage VPP may be optionally provided to the nonvolatile memory devices 1100. Each of the nonvolatile memory devices 1100 may include Figure 4 The nonvolatile memory device 200 of FIG. 1100. Therefore, each of the nonvolatile memory devices 1100 pre-programs multi-bit data in the multi-level cells in the pre-programming block, and programs summary data generated based on the state code of the pre-programmed multi-bit data in the summary block. Therefore, each of the nonvolatile memory devices 1100 can enhance the programming performance and efficiency of the storage space.

[0171] The SSD controller 1200 is connected to the nonvolatile memory device 1100 through a plurality of channels CH1, CH2, CH3 to Chi. The SSD controller 1200 includes one or more processors 1210, a buffer memory 1220, an ECC engine 1230, a host interface 1250, and a nonvolatile memory interface 1260.

[0172] The buffer memory 1220 stores data for driving the SSD controller 1200. The buffer memory 1220 includes a plurality of memory lines, each of which stores data or commands. The ECC engine 1230 calculates an error correction code value of data to be programmed at a write operation, and corrects errors of the read data using the error correction code value at a read operation. In a data recovery operation, the ECC engine 1230 corrects errors of data recovered from the nonvolatile memory device 1100.

[0173] Nonvolatile memory devices or storage devices according to example embodiments may be packaged using various package types or package configurations.

[0174] Embodiments of the present invention can be applied to various electronic devices including non-volatile memory devices. For example, embodiments of the present invention can be applied to systems such as mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, etc.

[0175] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications of the example embodiments are possible without materially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

Claims

1. A storage device, comprising: A nonvolatile memory comprising a plurality of memory blocks, the memory blocks comprising a preprogrammed block and a summary block, the preprogrammed block comprising a plurality of first cells, the summary block comprising a plurality of second cells; and a memory controller configured to preprogram data in the plurality of first cells, divide the plurality of first cells into a plurality of state groups, generate summary data indicating state group codes corresponding to the plurality of state groups, program the summary data stored in the summary block, and control the preprogramming block and the summary block as a pair, wherein Each first cell of the plurality of first cells stores more bits than each second cell of the plurality of second cells.

2. The storage device according to claim 1, wherein: Each first cell of the plurality of first cells stores two bits, and each second cell of the plurality of second cells stores one bit.

3. The storage device according to claim 1, wherein: Each first cell of the plurality of first cells stores four bits, and each second cell of the plurality of second cells stores two bits.

4. The storage device according to claim 1, wherein: The memory controller is configured to divide the plurality of first cells into the plurality of state groups based on state codes indicating states of the plurality of first cells after the data is preprogrammed.

5. The storage device according to claim 1, wherein: Each state group of the plurality of state groups includes a set of non-overlapping threshold voltage distributions.

Images