Chip debugging system

Abstract

The embodiment of the invention provides a chip debugging system. The chip debugging system comprises a debugging simulator, a host connected with the debugging simulator and a target chip, the host detects debugging operation of a user to generate debugging data, and packages the debugging data into a first data packet in a preset protocol format; receiving a second data packet in a preset protocol format sent by the debugging simulator; the debugging simulator receives a first data packet sent by the host, analyzes the first data packet into debugging data, sends a debugging signal to a target chip through a signal line according to the debugging data, receives the debugging signal fed back by the target chip to obtain a debugging result, packages the debugging result into a second data packet in a preset protocol format, and sends the second data packet to the host; and the target chip receives a debugging signal sent by the debugging simulator through the signal line, obtains debugging data according to the debugging signal, carries out debugging processing to obtain a debugging result, and sends a result signal to the debugging simulator through the signal line according to the result. The preset protocol designs a double-line debugging protocol and a data frame structure, and simulation, debugging and firmware upgrading can be carried out by using one signal line.

Description

Technical Field

[0001] The present invention relates to the technical field of signal transmission, and in particular to a chip debugging system. Background Art

[0002] RISC-V (reduced instruction set computer-five) is the fifth generation of free development instruction set architecture based on the principle of reduced instruction set. As an instruction set specification, RISC-V has the characteristics of complete open source, simple architecture, modular design, etc., and has broad application prospects in consumer electronics, industrial control, Internet of Things, etc. In the field of MCU (Microcontroller Unit) embedded software development, debugging emulators are usually used as necessary means for software development, debugging, code tracking, and solving software bugs (errors). With the rapid development of RSIC-V architecture in the field of semiconductor design with its advantages of simplicity, open source instruction set, and modularity, a large number of chips designed based on RISC-V architecture have appeared on the market. As an important component in the software debugging process of RISC-V chips, the existing debugger based on JTAG (Joint Test Action Group) has the problems of requiring many IO (data transmission) pins, high deployment cost, and difficulty in secondary development. Summary of the invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a chip debugging system that overcomes the above problems or at least partially solves the above problems.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a chip debugging system, comprising: a host, a debugging simulator, and a target chip; the debugging simulator is connected to the host, and is connected to the target chip through a signal line;

[0005] The host is used to detect the debugging operation of the user; generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format; and receive a second data packet in a preset protocol format sent by the debugging emulator;

[0006] The debugging simulator is configured to receive the first data packet sent by the host, parse the first data packet to obtain the debugging data, and send a debugging signal to the target chip through the signal line according to the debugging data; and receive a result signal sent by the target chip through the signal line, obtain a debugging result according to the result signal, encapsulate the debugging result into a second data packet in the preset protocol format, and send the second data packet to the host;

[0007] The target chip is used to receive the debugging signal sent by the debugging simulator through the signal line, obtain the debugging data according to the debugging signal, perform debugging processing according to the debugging data to obtain the debugging result, and send the result signal to the debugging simulator through the signal line according to the debugging result.

[0008] Optionally, the data packet in the preset protocol format includes multiple fields:

[0009] The debugging simulator is used to parse multiple fields in the first data packet to obtain the debugging data, and send a debugging signal to the target chip through the signal line according to the debugging data;

[0010] The host is used to parse multiple fields in the second data packet to obtain a debugging result.

[0011] Optionally, the data packets in the preset protocol format include a read data data packet and a write data data packet;

[0012] The read data packet includes a start field, a register selection field, a register read / write selection field, a first data signal direction reversal field, a data synchronization field, a read data field, a check field, and a second data signal direction reversal field;

[0013] The write data packet includes a start field, a register selection field, a register read / write selection field, a first data signal direction reversal field, a write data field, a check field and a second data signal direction reversal field.

[0014] Optionally, the debugging simulator is used to parse the start field and send a start signal to the target chip through the first signal line;

[0015] After sending the start signal, parsing the register selection field, and sending a register selection signal to the target chip through the signal line;

[0016] After sending the register selection signal, parsing the register read / write selection field, and sending the register read / write selection signal to the target chip through the signal line; the register read / write selection signal includes a register read signal or a register write signal;

[0017] After sending the register read / write selection signal, parsing the first data signal direction reversal field, and sending the first data signal direction reversal signal to the target chip through the signal line;

[0018] After sending the first data signal direction reversal signal, if the register read / write selection signal is a register read signal, parsing the data synchronization field, and sending a data synchronization signal to the target chip through the signal line;

[0019] After sending the data synchronization signal, parsing the read data field, and sending a target read data signal to the target chip through the first signal line;

[0020] After sending the first data signal direction reversal signal, if the register read / write selection signal is a register write signal, parsing the write data field, and sending a target write data signal to the target chip through the first signal line;

[0021] After sending the target read data signal or the target write data signal, parsing the check field, and sending a check signal to the target chip through the signal line;

[0022] After sending the verification signal, parsing the second data signal direction reversal field, and sending a second data signal direction reversal signal to the target chip through the signal line.

[0023] Optionally, the signal line includes a data signal line;

[0024] The debugging simulator is used to send a debugging signal to the target chip through the data signal line according to the debugging data; and receive a result signal sent by the target chip through the data signal line.

[0025] Optionally, the signal line further includes a clock signal line;

[0026] The debugging simulator is also used to send a clock signal to the target chip through the clock signal line.

[0027] Optionally, the target chip includes a debug transmission module, a debug module interface, a register and a processor;

[0028] The debugging transmission module is connected to the debugging client through a signal line, and is used to receive the debugging signal sent by the debugging simulator through the signal line, and send the result signal to the debugging simulator through the signal line;

[0029] The debugging module interface is connected to the debugging transmission module, and is used to obtain the debugging data according to the debugging signal, and to perform debugging processing according to the debugging data, the register and the processor to obtain the debugging result.

[0030] Optionally, the register comprises a debug module interface register;

[0031] The debugging transmission module is used to store the debugging signal and the result signal in the debugging module interface register.

[0032] Optionally, the host includes a debugging client and a debugging proxy server;

[0033] The debugging client is used to detect the debugging operation of the user;

[0034] The debugging proxy server is connected to the debugging client and the debugging simulator, and is used to generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format, and send the first data packet to the debugging simulator; and receive a second data packet in a preset protocol format sent by the debugging simulator.

[0035] Optionally, the host further includes a configuration library,

[0036] The debugging proxy server is used to obtain the chip information of the target chip from the configuration library, and send the chip information of the target chip to the debugging client;

[0037] The debugging client is used to display the chip information of the target chip to the user.

[0038] The embodiments of the present invention include the following advantages:

[0039] The present invention discloses a chip debugging system, including a host, a debugging simulator and a target chip; the debugging simulator is connected to the host and the target chip; the host detects the debugging operation of the user and generates debugging data, encapsulates it into a first data packet in a preset protocol format, and also receives a second data packet in a preset protocol format sent by the debugging simulator; the debugging simulator receives the first data packet sent by the host and parses it into debugging data, sends a debugging signal to the target chip through a signal line according to the first data packet, then receives the debugging signal fed back by the target chip to obtain a debugging result, encapsulates it into a second data packet in a preset protocol format and sends it to the host; the target chip receives the debugging signal sent by the debugging simulator through the signal line, obtains the debugging data according to the first data packet, performs debugging processing to obtain the debugging result, and sends the result signal to the debugging simulator through the signal line according to the result. The preset protocol of the present invention only uses one signal line to transmit a data packet, so as to realize the simulation, debugging and burning of the chip, solves the problem that the RISC-V CPU does not support the SWD protocol, and increases the market competitiveness of the RISC-V MCU chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram of the architecture of a chip debugging system provided by an embodiment of the present invention;

[0041] Figure 2is a schematic diagram of the architecture of another chip debugging system provided by an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of a read data packet format of a chip debugging system provided by an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of a write data packet format of a chip debugging system provided by an embodiment of the present invention;

[0044] Figure 5 It is a flow chart of a preset protocol communication state machine of a chip debugging system provided by an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of a timing sequence of a preset protocol interface reading a register of a chip debugging system provided by an embodiment of the present invention;

[0046] Figure 7 The present invention provides a timing diagram of a preset protocol interface writing register of a chip debugging system. DETAILED DESCRIPTION

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] One of the core concepts of the embodiments of the present invention is to propose a two-wire debugging scheme and protocol for debugging RISC-V processors to achieve high cohesion and low coupling. STWI (Software Two wire Debugger) uses one signal line to transmit data packets to implement debugging functions and control the RISC-V MCU, including pausing execution, single-step execution, accessing and modifying register / memory values, supporting setting breakpoints and monitoring observation points, and burning firmware.

[0049] Reference Figure 1 , shows a schematic diagram of the architecture of a chip debugging system provided by an embodiment of the present invention, the system may specifically include: a host 10, a debugging simulator 11, and a target chip 12; the debugging simulator 11 is connected to the host 10, and is connected to the target chip 12 through a signal line;

[0050] CPU (central processing unit) debugging is an integral part of software development and hardware design, helping developers identify and fix errors in code or problems in hardware design. For CPUs based on the RISC-V architecture, the debugging process usually includes hardware support, debugging tools, and related protocols.

[0051] The embodiments of the present invention are mainly directed to the simulation debugging system architecture of RISC-V MCU chips, which generally includes multiple components that work together to provide a complete development and debugging environment. The debugging system architecture of RISC-V chips aims to provide an efficient and flexible way to diagnose and debug processors based on the RISC-V architecture. This architecture generally includes hardware support, software tools, and communication protocols to ensure that developers can effectively perform code debugging, performance analysis, and troubleshooting.

[0052] The host 10 is used to detect the debugging operation of the user; generate debugging data according to the debugging operation, and encapsulate the debugging data into a first data packet in a preset protocol format; and receive a second data packet in a preset protocol format sent by the debugging simulator 11;

[0053] The host 10 includes a host computer, and the PC (personal computer) end is connected to the debugging emulator 11 through USB (serial bus) and CAN (Controller Area Network) bus, etc., and generates data from the debugging operation of the detected user, and encapsulates these data according to the STWI protocol communication state machine process to obtain a first data packet in a preset protocol format, and the preset protocol is the STWI protocol, and the first data packet is transmitted to the debugging emulator 11 through the USB and CAN bus encapsulated data. The host 10 can also receive a second data packet encapsulated by the target chip 12 and fed back to the debugging emulator 1. The second data packet is also encapsulated according to the STWI protocol communication state machine process and is in the STWI protocol format.

[0054] The debugging simulator 11 is configured to receive the first data packet sent by the host, parse the first data packet to obtain the debugging data, and send a debugging signal to the target chip through the signal line according to the debugging data; and receive a result signal sent by the target chip through the signal line, obtain a debugging result according to the result signal, encapsulate the debugging result into a second data packet in the preset protocol format, and send the second data packet to the host;

[0055] A debugging simulator generally refers to the process of testing and debugging a program using a software tool that simulates an actual hardware environment during software development. The simulator can help developers check the behavior of the code without actual hardware, and can provide additional debugging information, such as memory status, register values, etc. The debugging simulator STWI-Link in this embodiment is connected to the host through a serial bus. STWI-Link implements receiving a data packet from the host side, and after parsing the first data packet encapsulated according to the STWI protocol communication state machine process, it is sent to the target chip 12 through a signal line in the form of a debugging signal. It also implements receiving a result signal from the target chip 12, and processing the combined signal into debugging result data according to the STWI protocol communication state machine process, and then encapsulating it into a second data packet according to the STWI protocol and sending it to the host 10.

[0056] The target chip 12 is used to receive the debugging signal sent by the debugging simulator through the signal line, obtain the debugging data according to the debugging signal, perform debugging processing according to the debugging data to obtain the debugging result, and send the result signal to the debugging simulator through the signal line according to the debugging result.

[0057] MCU (Microcontroller Unit) is a small computer system that integrates a processor, memory and various peripherals on a single chip. MCU is usually used in embedded systems to perform specific control tasks. The main components of MCU are CPU (Central Processing Unit), which is responsible for executing program instructions, usually RISC architecture (such as ARMCortex-M series) or CISC architecture (such as 8051 series); memory, used to store program code and constant data; peripherals, GPIO (General Purpose Input and Output Port): used to connect external devices such as LEDs, buttons, etc., serial communication interface: such as UART, SPI, I2C, etc., used to communicate with other devices; clock and reset circuits, etc.

[0058] In the embodiment of the present invention, after the target chip 12 receives the debugging signal sent by STWI-Link through the signal line, it obtains debugging data according to the debugging signal, and the target CPU responds to the debugging data. After obtaining the debugging result, it feeds back the debugging result data or status to the host computer in the form of a debugging signal, and the status refers to whether the debugging is successful or failed.

[0059] The chip debugging system of the embodiment of the present invention includes a host, a debugging simulator and a target chip; the debugging simulator is connected to the host and the target chip; the host detects the debugging operation of the user and generates debugging data, encapsulates it into a first data packet in a preset protocol format, and also receives a second data packet in a preset protocol format sent by the debugging simulator; the debugging simulator receives the first data packet sent by the host and parses it into debugging data, sends a debugging signal to the target chip through a signal line according to it, and then receives the debugging signal fed back by the target chip to obtain a debugging result, and encapsulates it into a second data packet in a preset protocol format and sends it to the host; the target chip receives the debugging signal sent by the debugging simulator through a signal line, obtains the debugging data according to it, performs debugging processing to obtain the debugging result, and sends the result signal to the debugging simulator through the signal line according to the result. The preset protocol of the present invention can realize RISC-V MCU simulation, debugging and burning by only using one signal line of the RISC-V MCU chip to transmit the data packet, solves the problem that the RISC-V CPU does not support the SWD protocol, and increases the market competitiveness of the RISC-V MCU chip.

[0060] Reference Figure 2 , shows a schematic diagram of the architecture of another chip debugging system provided by an embodiment of the present invention, the system may specifically include: a host 20, a debugging simulator 21, and a target chip 22; the debugging simulator 21 is connected to the host 20, and is connected to the target chip 22 through a signal line;

[0061] In this embodiment, the RISC-V chip simulation and debugging system architecture consists of a host 21, a debugging emulator 21 and a target chip 22. The debugging emulator 21 can cooperate with the debugging software of the host 21 to complete basic debugging operations on the target MCU such as single step, breakpoint, full speed operation, and access monitoring points to achieve the purpose of debugging the software.

[0062] The host 20 is used to detect the debugging operation of the user; generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format; and receive a second data packet in a preset protocol format sent by the debugging emulator;

[0063] The host 20 includes: a debugging client 200 and a debugging proxy server 201;

[0064] Debugging client IDE debugger (GDB client), GDB (GNU Debugger) is a powerful open source debugging tool, widely used for debugging various programming languages ​​and platforms. GDB client usually refers to the part that communicates with the GDB server or target device. It allows developers to control and observe the execution of programs on the remote target through the command line or graphical interface on the host. The main functions of the GDB client are: connecting to the target, or directly connecting to the target hardware that supports the GDB protocol; setting breakpoints, users can set breakpoints in the source code to pause the execution of the program and check the status; single-step execution, execute the code instruction by instruction, to help understand the program flow; view and modify variables, when the program is paused, you can view and modify the variable values ​​in the memory; view the call stack, display the history of the current function call, to help track the root cause of the problem. View registers and memory, you can directly view and modify CPU registers and memory contents; conditional breakpoints, set breakpoints that will be triggered only when specific conditions are met, etc.

[0065] The debug proxy server is the debug proxy service program (STWI_OCD_Server, STWIOpen On-ChipDebugge), which is an open source debugging, memory access and flash programming tool widely used in embedded system development. It supports multiple processor architectures, including RISC-V. The OpenOCD server (openocd) can be used with the GDB debugger to provide powerful hardware debugging capabilities. The main functions of the debug proxy server are: JTAG / SWD interface, providing JTAG and SWD interfaces for connecting the target board and the debug host, supporting multiple JTAG adapters; debug interface, providing support for the GDB remote debugging protocol, allowing GDB to connect to OpenOCD for remote debugging, supporting breakpoint setting, single-step execution, register and memory reading and writing and other debugging operations; flash programming, supporting various flash chips, such as SPI Flash, QSPI Flash, eFlash, etc.; configuration file, using the configuration file to define the hardware characteristics of the target board, JTAG adapter and debugging parameters, the configuration file usually contains initialization scripts, target board definitions and debugging commands.

[0066] The debugging client 200 is used to detect the debugging operation of the user;

[0067] The debugging proxy server 201 is connected to the debugging client 200 and the debugging simulator 21, and is used to generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format, and send the first data packet to the debugging simulator 21; and receive a second data packet in a preset protocol format sent by the debugging simulator 21.

[0068] In the embodiment of the present invention, the debugging proxy server 201, i.e., the debugging software IDE and the debugging proxy service program, are remotely called, wherein STWI_OCD_Server realizes the logic implementation of operations such as burning, erasing, single-step execution, stopping, setting breakpoints, running at full speed, reading and writing peripheral registers, reading and writing storage space, setting breakpoints and monitoring observation points, and encapsulates the data according to the STWI read data packet format and the STWI write data packet format. The debugging proxy server 201 can also receive a second data packet in the STWI protocol format sent by the debugging emulator 21.

[0069] The host 20 also includes a configuration library 202. The debugging proxy server 201 is used to obtain the chip information of the target chip 22 from the configuration library 202 and send the chip information of the target chip 22 to the debugging client 200. The debugging client 200 is used to display the chip information of the target chip to the user.

[0070] In microcontroller (MCU) development, a library is a set of pre-written code that is used to perform specific functions or operate hardware peripherals. These libraries are usually provided by MCU manufacturers, but can also come from third-party developers. Using libraries can greatly simplify the development process and improve the readability and maintainability of the code.

[0071] In this embodiment, the configuration library 202, i.e., the microcontroller debugging configuration library STWI MCU Library, can implement address mapping tables, eflash (embedded Flash, flash memory technology integrated on the chip) algorithm library, configuration files, and RISC-V target chip executable driver library binary files. The microcontroller debugging configuration library STWI MCU Library adopts a high cohesion and low coupling approach to achieve compatibility with chips of different models from different manufacturers. To support chips of different models from different manufacturers, it only requires modifying the PC-side host computer software, without modifying the debugging simulator STWI-Link debugger firmware.

[0072] In another embodiment, the STWI_OCD_Server server is first started, the MCU STWI Library configuration (including the chip information to be debugged, such as RAM, flash size, chipID, etc.) and flash algorithm are called, and then the IDE debugger (such as GDB Client) is started, and the debugging (HALT CPU, read the DMIDebug HALT bit through STWI-Link, set it to 1, and write the updated value to the DMIDebug register) command is sent to the STWI_OCD_Server.

[0073] In one embodiment, the host 20 is used to parse multiple fields in the second data packet to obtain a debugging result.

[0074] In addition to the debugging signal obtained by sending the encapsulated debugging data to the debugging simulator 21, the host 20 can also parse the second data packet encapsulated in the STWI protocol format from the debugging simulator to obtain the debugging data result.

[0075] The debugging simulator 21 is configured to receive the first data packet sent by the host 20, parse the first data packet to obtain the debugging data, and send a debugging signal to the target chip 22 through the signal line according to the debugging data; and receive a result signal sent by the target chip 22 through the signal line, obtain a debugging result according to the result signal, encapsulate the debugging result into a second data packet in the preset protocol format, and send the second data packet to the host;

[0076] In this embodiment, the debugging simulator 21 is STWI-Link, and STWI_OCD_Server sends data packaged according to the STWI protocol to STWI-Link. STWI-Link parses the received data and sends it to the target CPU in the manner of the STWI protocol. The target CPU responds and feeds back data or status to STWI-Link, which is further encapsulated as a second data packet in the STWI protocol format to the host computer. After connecting to the target CPU, load the program to be debugged and set the endpoint, and use the step (set the value of the Single-step enable bit of the DMIDebug register to 1 through STWI-Link, and then the CPU will automatically enter the halt state after each instruction is executed) command for single-step debugging.

[0077] In one embodiment, the data packet in the preset protocol format includes multiple fields:

[0078] The debugging simulator 21 is used for parsing a plurality of fields in the first data packet to obtain the debugging data, and sending a debugging signal to the target chip 22 through the signal line according to the debugging data;

[0079] In one embodiment, the data packets in the preset protocol format include a read data packet and a write data packet;

[0080] In the STWI communication protocol, data is always sampled or set at the rising edge of the clock. Data is transmitted in the form of data packets, which include the start bit (START), register group selection bit (SR[1:0]), read / write selection bit (R / W), data signal direction reversal bit (Trnd, Trun Around), data synchronization bit (SYNC), data segment (DATA), and check bit (PARITY).

[0081] Reference Figure 3 , shows a schematic diagram of the format of a read data packet of a chip debugging system, wherein the read data packet includes a start field, a register selection field, a register read / write selection field, a first data signal direction reversal field, a data synchronization field, a read data field, a check field, and a second data signal direction reversal field;

[0082] The start field is a low level of one cycle on the data signal line; the register selection field indicates the register group selection, which takes two clock cycles. Selecting 00 indicates the DMIDebug register; 01 indicates the selection of the GPR general register group register group; 10 indicates the selection of the CSR control and status register; 11 indicates the bit selection of the CPU floating point unit register (FPR). The register read and write selection field is high to indicate the STWI register read operation, and low to indicate the STWI register write operation. The first data signal direction reversal field cycle is in the read / write STWI register operation, the data signal direction can be switched, which is configured by the user. The data synchronization field is a low level of one cycle, which only exists in the STWI register read operation. The user can use this bit to determine when to start reading the data returned by STWI. The read data field is 8 bits wide or 32 bits wide according to different types. The check field is the check field of the data.

[0083] Reference Figure 4 , shows a schematic diagram of the format of a write data packet of a chip debugging system, wherein the write data packet includes a start field, a register selection field, a register read / write selection field, a first data signal direction reversal field, a write data field, a check field, and a second data signal direction reversal field.

[0084] The start field is the low level of one cycle on the data signal line; the register selection field indicates the register group selection, which takes two clock cycles. Selecting 00 indicates the DMIDebug register; 01 indicates the selection of the GPR general register group register group; 10 indicates the selection of the CSR control and status register; 11 indicates the bit selection of the CPU floating point unit register (FPR). The register read and write selection field is high to indicate a read STWI register operation, and low to indicate a write STWI register operation. The first data signal direction reversal field cycle is in the read / write STWI register operation, the data signal direction can be switched, which is configured by the user. The write data field is 8 bits wide or 32 bits wide depending on the type. The check field is the check field of the data.

[0085] In order to prevent the host and the debugged target chip from competing for STWI IO, when the direction of driving STWI IO needs to change, in order to ensure that the IO direction switching is completed, a turnaround period needs to be set. During the turnaround period, neither the host nor the target chip drives STWI IO, and the state of STWI IO is undefined. The role of the two data signal direction reversal fields is to set the turnaround time period and wait for the IO state switching to stabilize. The specific value is configured by the host computer and can be set by the IDE debugger (GDB client) or STWI_OCD Server or MCU STWI Library.

[0086] Because there are only two GPIOs, one is the clock line and the other is the data line. When the data line is used as input or output, it needs to be time-division multiplexed, that is, when the direction changes, the data signal direction needs to be switched. The purpose of setting the data signal direction reversal period is to delay a certain clock cycle when the GPIO multiplexing switches the data direction to ensure that the GPIO direction switching is successful.

[0087] Reference Figure 5 , shows a flow chart of a preset protocol communication state machine of a chip debugging system, wherein the debugging simulator 21 is used to parse the start field and send a start signal to the target chip 22 through the first signal line;

[0088] After sending the start signal, parsing the register selection field, and sending a register selection signal to the target chip 22 through the signal line;

[0089] After sending the register selection signal, parsing the register read / write selection field, and sending the register read / write selection signal to the target chip 22 through the signal line; the register read / write selection signal includes a register read signal or a register write signal;

[0090] After sending the register read / write selection signal, parsing the first data signal direction reversal field, and sending the first data signal direction reversal signal to the target chip through the signal line;

[0091] After sending the first data signal direction reversal signal, if the register read / write selection signal is a register read signal, parsing the data synchronization field, and sending a data synchronization signal to the target chip through the signal line;

[0092] After sending the data synchronization signal, parsing the read data field, and sending a target read data signal to the target chip through the first signal line;

[0093] After sending the first data signal direction reversal signal, if the register read / write selection signal is a register write signal, parsing the write data field, and sending a target write data signal to the target chip through the first signal line;

[0094] After sending the target read data signal or the target write data signal, parsing the check field, and sending a check signal to the target chip through the signal line;

[0095] After sending the verification signal, parsing the second data signal direction reversal field, and sending a second data signal direction reversal signal to the target chip through the signal line.

[0096] In this embodiment, the debugging simulator STWI_Link supports drivers that comply with the PC operating system specifications (which can be Windows OS drivers or Linux OS drivers), so that the PC can normally interact with the simulator. The host communicates with STWI_Link, and any one or more of the buses such as USB, network, CAN, I2C, SPI, etc. can be selected for communication. In the debugging simulator STWI_Link, data reception and transmission of one or more transmission media of buses such as USB, network, CAN, I2C, SPI, etc. are implemented, and control logic is implemented in STWI_Link by IO operations according to the STWI communication protocol.

[0097] The target chip 22 is used to receive the debugging signal sent by the debugging simulator through the signal line, obtain the debugging data according to the debugging signal, perform debugging processing according to the debugging data to obtain the debugging result, and send the result signal to the debugging simulator through the signal line according to the debugging result.

[0098] In one embodiment, the target chip 22 includes a debug transmission module 220, a debug module interface 221, a register and a processor 222;

[0099] The debugging transmission module 220 is connected to the debugging client through a signal line, and is used to receive the debugging signal sent by the debugging simulator 21 through the signal line, and send the result signal to the debugging simulator 21 through the signal line;

[0100] The debugging module interface 221 is connected to the debugging transmission module 220 and is used to obtain the debugging data according to the debugging signal, and perform debugging processing according to the debugging data, the register and the processor 222 to obtain the debugging result.

[0101] The STWI debug interface includes the STWI communication protocol and the STWI interface controller. The STWI debug module interface implements control of the RISC-V processor, including pausing execution, single-step execution, and accessing and modifying register / memory values; supports setting breakpoints and watchpoints; and provides access to the entire system, including memory and peripherals. The STWI interface is configured with two debug pins, and the defined interface signals are clock CLOCK and STWI IO, where STWI IO is a bidirectional data signal used to transmit commands and data.

[0102] In one embodiment, the target chip also includes a system bus 223, a trigger module 224, SRAM (static random access memory), EFlash (embedded flash memory) and peripherals, and the static random access memory, embedded flash memory and peripherals are collectively component 225. During the debugging process, a watchpoint is a very useful tool that allows you to monitor changes in a specific memory address or variable while the program is running. When the content of the monitored memory location changes, the debugger will pause execution and notify you of the change. This is particularly useful for catching hard-to-track bugs, such as unexpected data modifications. The trigger module is used to monitor a certain memory address and suspend debugging when a change occurs.

[0103] In one embodiment, the registers include debug module interface registers;

[0104] The debugging transmission module 220 is used to store the debugging signal and the result signal in the debugging module interface register.

[0105] The register corresponding to the debug transmission module 220 is the DMIDebug register, which is usually a register directly related to the STWI module (located in the debug transmission module, the debug development board receives information and gives feedback to the CPU). It can control the CPU single-step operation and HALT state, set hardware breakpoints, and directly read and change the PC pointer.

[0106] In this embodiment, STWI-related registers are divided into the following parts: DMIDebug register, CPU general register (GPR), CPU control and status register (CSR), CPU floating point unit register (FPR). In addition to the DMIDebug register mentioned above, there is also GPR, which is the general register group of the processor. The processor cannot directly access the memory. The data to be processed must be moved from the memory to the GPR and then processed. After processing, the CPU writes back to the GPR and then saves it to the memory. CSR is the control status register of the CPU, which is used to store some status and control bits during the operation of the CPU, including CPU status, exception enable, exception vector address, exception instruction, and exception type.

[0107] Reference Figure 6 , shows a schematic diagram of the timing of reading registers of a preset protocol interface of a chip debugging system, indicating the timing of reading DMIDebug registers through the STWI interface. To read the DMIDebug register, you first need to send a write command and then read the data. The steps are similar to the previous data packet reading process, so they will not be repeated.

[0108] Reference Figure 7 , shows a schematic diagram of the timing of writing registers of a preset protocol interface of a chip debugging system, indicating the timing of writing DMIDebug registers through the STWI interface. To write DMIDebug registers, you first need to send a write command and then write data. The steps are similar to the previous data packet writing process and will not be repeated here.

[0109] In one embodiment, the signal line includes a data signal line 23;

[0110] The debugging simulator 21 is used to send a debugging signal to the target chip through the data signal line 23 according to the debugging data; and receive a result signal sent by the target chip through the data signal line.

[0111] In one embodiment, the signal line further includes a clock signal line 24;

[0112] The debugging simulator 21 is further configured to send a clock signal to the target chip 22 via the clock signal line 24 .

[0113] Interface signals are configured as clock (CLOCK) and data (IO) and are usually used for some specific communication protocols or hardware interfaces, such as SPI (Serial Peripheral Interface), I 2C (Inter-Integrated Circuit), single-line communication, etc. The specific configuration and use of these interface signals depends on the specific communication protocol and hardware design. The clock signal is a very important signal in the synchronous communication protocol, which provides a timing reference for data transmission. The IO data signal is usually bidirectional and can be used for data transmission. In different communication protocols, the specific names and functions of the IO data signals are different.

[0114] The chip debugging system of the embodiment of the present invention includes a host, a debugging simulator and a target chip; the debugging simulator is connected to the host and the target chip; the host detects the debugging operation of the user and generates debugging data, encapsulates it into a first data packet in a preset protocol format, and also receives a second data packet in a preset protocol format sent by the debugging simulator; the debugging simulator receives the first data packet sent by the host and parses it into debugging data, sends a debugging signal to the target chip through a signal line according to it, and then receives the debugging signal fed back by the target chip to obtain a debugging result, and encapsulates it into a second data packet in a preset protocol format and sends it to the host; the target chip receives the debugging signal sent by the debugging simulator through a signal line, obtains the debugging data according to it, performs debugging processing to obtain the debugging result, and sends the result signal to the debugging simulator through the signal line according to the result. The preset protocol of the present invention can realize RISC-V MCU simulation, debugging and burning by only using one signal line of the RISC-V MCU chip to transmit the data packet, solves the problem that the RISC-V CPU does not support the SWD protocol, and increases the market competitiveness of the RISC-V MCU chip.

[0115] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0116] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0117] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0118] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0119] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0120] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0121] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0122] The above is a detailed introduction to a chip debugging system provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A chip debugging system, characterized in that: include: Host, debugging emulator, target chip; The debugging simulator is connected to the host and is connected to the target chip via a signal line; The host is used to detect the debugging operation of the user; Generate debugging data according to the debugging operation, and encapsulate the debugging data into a first data packet in a preset protocol format; and receiving a second data packet in a preset protocol format sent by the debugging simulator; The debugging simulator is used to receive the first data packet sent by the host, parse the first data packet to obtain the debugging data, and send a debugging signal to the target chip through the signal line according to the debugging data; and receiving a result signal sent by the target chip through the signal line, obtaining a debugging result according to the result signal, encapsulating the debugging result into a second data packet in the preset protocol format and sending the second data packet to the host; The target chip is used to receive the debugging signal sent by the debugging simulator through the signal line, obtain the debugging data according to the debugging signal, perform debugging processing according to the debugging data to obtain the debugging result, and send the result signal to the debugging simulator through the signal line according to the debugging result.

2. The chip debugging system according to claim 1, characterized in that: The data packet of the preset protocol format includes multiple fields: The debugging simulator is used to parse multiple fields in the first data packet to obtain the debugging data, and send a debugging signal to the target chip through the signal line according to the debugging data; The host is used to parse multiple fields in the second data packet to obtain a debugging result.

3. The chip debugging system according to claim 2, characterized in that: The data packets in the preset protocol format include a read data packet and a write data packet; The read data packet includes a start field, a register selection field, a register read / write selection field, a first data signal direction reversal field, a data synchronization field, a read data field, a check field, and a second data signal direction reversal field; The write data packet includes a start field, a register selection field, a register read / write selection field, a first data signal direction reversal field, a write data field, a check field and a second data signal direction reversal field.

4. The chip debugging system according to claim 3, characterized in that: The debugging simulator is used to parse the start field and send a start signal to the target chip through the first signal line; After sending the start signal, parsing the register selection field, and sending a register selection signal to the target chip through the signal line; After sending the register selection signal, parsing the register read / write selection field, and sending the register read / write selection signal to the target chip through the signal line; the register read / write selection signal includes a register read signal or a register write signal; After sending the register read / write selection signal, parsing the first data signal direction reversal field, and sending the first data signal direction reversal signal to the target chip through the signal line; After sending the first data signal direction reversal signal, if the register read / write selection signal is a register read signal, parsing the data synchronization field, and sending a data synchronization signal to the target chip through the signal line; After sending the data synchronization signal, parsing the read data field, and sending a target read data signal to the target chip through the first signal line; After sending the first data signal direction reversal signal, if the register read / write selection signal is a register write signal, parsing the write data field, and sending a target write data signal to the target chip through the first signal line; After sending the target read data signal or the target write data signal, parsing the check field, and sending a check signal to the target chip through the signal line; After sending the verification signal, parsing the second data signal direction reversal field, and sending a second data signal direction reversal signal to the target chip through the signal line.

5. The chip debugging system according to claim 1, characterized in that: The signal line includes a data signal line; The debugging simulator is used to send a debugging signal to the target chip through the data signal line according to the debugging data; and receive a result signal sent by the target chip through the data signal line.

6. The chip debugging system according to claim 5, characterized in that: The signal line also includes a clock signal line; The debugging simulator is also used to send a clock signal to the target chip through the clock signal line.

7. The chip debugging system according to claim 1, characterized in that: The target chip includes a debugging transmission module, a debugging module interface, a register and a processor; The debugging transmission module is connected to the debugging client through a signal line, and is used to receive the debugging signal sent by the debugging simulator through the signal line, and send the result signal to the debugging simulator through the signal line; The debugging module interface is connected to the debugging transmission module, and is used to obtain the debugging data according to the debugging signal, and to perform debugging processing according to the debugging data, the register and the processor to obtain the debugging result.

8. The chip debugging system according to claim 7, characterized in that: The registers include debug module interface registers; The debugging transmission module is used to store the debugging signal and the result signal in the debugging module interface register.

9. The chip debugging system according to claim 1, characterized in that: The host includes a debugging client and a debugging proxy server; The debugging client is used to detect the debugging operation of the user; The debugging proxy server is connected to the debugging client and the debugging simulator, and is used to generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format, and send the first data packet to the debugging simulator; And receiving a second data packet in a preset protocol format sent by the debugging simulator.

10. The chip debugging system according to claim 1, characterized in that: The host also includes a configuration repository, The debugging proxy server is used to obtain the chip information of the target chip from the configuration library, and send the chip information of the target chip to the debugging client; The debugging client is used to display the chip information of the target chip to the user.

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