Semiconductor device physical modeling method combining material and device test analysis technology

Abstract

The invention discloses a semiconductor device physical modeling method combining a material and device test analysis technology, which comprises the following steps of: constructing an ideal simulation model in semiconductor process simulation and device simulation tool software according to a basic material and a structure of a semiconductor device to be subjected to physical modeling; obtaining typical defect model parameters of the semiconductor device based on an electrical characteristic test and material characterization analysis technology; the typical defect model parameters and the related physical process model are added to the ideal simulation model, a semiconductor device model containing the typical defect model parameters and the related physical process is constructed, the model is consistent with an actual device electrical characteristic test result in a fitting mode, and finally a model reflecting actual physical characteristics of an actual semiconductor device is constructed.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device design, and in particular relates to a semiconductor device physical modeling method combining material and device testing and analysis technology. Background Art

[0002] Constructing an accurate and self-consistent device model of (ultra) wide bandgap semiconductor devices is an important prerequisite for conducting device numerical simulation research, reliability mechanism research, and device optimization design based on the model. Common methods include physical modeling based on semiconductor physics principles, empirical modeling based on measured data, and model verification and circuit simulation using professional software such as general analog circuit simulator (SPICE), semiconductor process simulation, and device simulation tool software (TCAD). The establishment of a self-consistent device model based on semiconductor physics principles includes: 1. Material and structural modeling of basic devices, 2. Device typical defects and their characteristic models, and 3. Fitting with measured electrical characteristics. The data of step 1 can usually be obtained directly from TCAD software, but steps 2 and 3 need to be combined with actual material and device test analysis to obtain the corresponding typical defect model parameters. On this basis, the typical defect model parameters and related physical process models are added to the ideal simulation model to construct a semiconductor device model containing typical defect model parameters and their physical processes, and the model is fitted to the actual (ultra) wide bandgap semiconductor device electrical characteristic test results. The final model constructed is a model that truly reflects the physical characteristics of the actual (ultra) wide bandgap semiconductor device.

[0003] In the relevant prior art, physical modeling methods of semiconductor devices generally include: basic device modeling based on existing simulation software; device modeling based on deep learning technology and existing simulation software; and material characterization device modeling methods based on semiconductor material characterization technology to obtain defect energy levels.

[0004] Among them, the basic device modeling method based on existing simulation software analyzes and compares the device simulation results with the experimental results, calibrates the ideal physical model parameters, and makes the simulation results consistent with the experimental results to complete the establishment of the device model. However, this method mainly establishes semiconductor models based on ideal physical models, and the simulation of electrical characteristics is based on ideal physical formulas, without considering typical defects that affect the electrical characteristics of the device. Therefore, the established ideal physical model cannot truly reflect the physical characteristics of actual (ultra) wide bandgap semiconductor devices, which brings obstacles to device numerical simulation research, related physical mechanism research, and device optimization design.

[0005] The device modeling method based on deep learning technology and existing simulation software is mainly based on the measured new semiconductor device parameter library and deep neural network algorithm. By optimizing the model parameters of the existing typical basic semiconductor device model, the simulated electrical characteristics of the new semiconductor device model based on the typical semiconductor device model are fitted to the electrical characteristics test data of the new semiconductor device, thereby quickly obtaining the new semiconductor device model. The electrical characteristics of the semiconductor device may at least include IV (current voltage) characteristics, frequency characteristics, noise characteristics, temperature, process characteristics, etc., and the corresponding physical parameters may include the width and length of the device, the thickness of the gate oxide layer, the doping concentration, etc. However, the model parameters of the typical basic semiconductor device model optimized by the modeling method mainly refer to structural parameters other than physical parameters, such as the width and length of the device, the thickness of the gate oxide layer, etc. The typical semiconductor device model is essentially based on the existing TCAD simulation software related model library that is close to perfection (such as silicon material and device related models) or imperfect (such as ultra-wide bandgap semiconductor material and device related models). In particular, for ultra-wide bandgap semiconductor materials and devices, the existing TCAD simulation software related model library has incomplete model parameters and has not added typical defect model parameters that affect electrical properties. Therefore, the semiconductor device model obtained based on this method still cannot truly reflect the actual physical properties of (ultra-) wide bandgap semiconductor devices.

[0006] The device modeling method based on the semiconductor material characterization technology to obtain the defect energy level model parameters determines the internal defect energy level of the material through material characterization, and uses it as an input parameter to calibrate the ideal physical model, thereby improving the model establishment of the semiconductor device. However, this modeling method only determines the defect energy level of the semiconductor material in a one-sided way, and cannot provide a reference for the subsequent electrical characteristics fitting, such as the fitting of key electrical characteristics such as gate leakage current.

[0007] In summary, there is an urgent need for a semiconductor device physical modeling method that can reflect the true physical properties of actual (ultra) wide bandgap semiconductor devices, in order to solve the obstacles encountered in current device numerical simulation research, reliability physical mechanism research, and device optimization design. Summary of the invention

[0008] In order to solve the above problems existing in the prior art, the present invention provides a semiconductor device physical modeling method combining material and device testing and analysis technology.

[0009] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0010] A semiconductor device physical modeling method combining material and device testing and analysis technology, comprising:

[0011] According to the basic materials and structures of the semiconductor device to be physically modeled, an ideal simulation model of the semiconductor device is constructed in semiconductor process simulation and device simulation tool software; the semiconductor device includes: a wide bandgap semiconductor device or an ultra-wide bandgap semiconductor device;

[0012] The typical defect model parameters of the semiconductor device are obtained by using electrical property testing and material characterization analysis technology. The typical defect model parameters include: interface state defect energy level E it , interface state defect density D it , oxide layer defect type Type, oxide layer defect energy level E bt , oxide layer defect density N bt , the step difference between the oxide layer and the semiconductor conduction band Semiconductor material defect type Type, semiconductor material defect energy level E t And the semiconductor material defect density N t ;

[0013] According to the ideal simulation model and the typical defect model parameters, a semiconductor device model including the typical defect model parameters is constructed, and a physical process model related to the semiconductor device and its typical defects is added to the semiconductor device model to obtain a semiconductor device model including the typical defect model parameters and related physical processes; wherein the physical process model includes: a carrier statistical distribution model, a drift diffusion model, a mobility model, and a composite generation model;

[0014] A semiconductor device model including typical defect model parameters and related physical processes is fitted to the actual device electrical characteristics test results to obtain a model that reflects the real physical characteristics of the actual semiconductor device; the device electrical characteristics include: output characteristics, transfer characteristics, gate leakage current and drain leakage current.

[0015] Optionally, the interface state defect energy level E in the typical defect model parameters is obtained. it ways, including:

[0016] Obtaining a first semiconductor device sample; the first semiconductor device sample comprises, from bottom to top, a first metal layer, a semiconductor material layer, an oxide layer, and a second metal layer; the materials of the first metal layer, the semiconductor material layer, the oxide layer, and the second metal layer are the same as those of the corresponding layers of the semiconductor device;

[0017] The conductivity curve of the first semiconductor device sample from low frequency to high frequency is tested by the conductivity method, and the interface state defect energy level E is obtained according to the response frequency of the peak value in the conductivity curve. it ;

[0018] A material interface model of the semiconductor material layer and the oxide layer is constructed in a material modeling software tool, and the interface state defect energy level E is calculated based on the first principle. it ;

[0019] The interface state defect energy level E is calculated based on first principles. it The interface defect energy level E obtained by the conductivity method it Perform calibration verification.

[0020] Optionally, the interface state defect density D in the typical defect model parameters is obtained. it ways, including:

[0021] Acquire a second semiconductor device sample; the second semiconductor device sample is the same device as the semiconductor device;

[0022] Testing a transfer characteristic curve of the second semiconductor device sample;

[0023] determining a subthreshold region according to the transfer characteristic curve;

[0024] The interface state defect density D is calculated based on the subthreshold slope of the subthreshold region. it .

[0025] Optionally, the oxide layer defect type Type, the oxide layer defect energy level E in the typical defect model parameters are obtained. bt and oxide layer defect density N bt ways, including:

[0026] Obtain at least one third semiconductor material sample; the third semiconductor material sample comprises a semiconductor material layer and a single oxide layer from bottom to top; the semiconductor material layer is the same as the semiconductor layer of the semiconductor device, and the single oxide layer of the at least one third semiconductor material sample is the same as each oxide layer of the semiconductor device in one-to-one correspondence;

[0027] By performing an X-ray photoelectron spectroscopy XPS test and a photoluminescence spectrum PL test on the at least one third semiconductor material sample, the oxide layer defect type Type and the oxide layer defect energy level E are obtained. bt and oxide layer defect density N bt .

[0028] Optionally, the modeling method further includes:

[0029] Before fitting the semiconductor device model including typical defect model parameters and related physical processes to the actual device electrical characteristic test results, the oxide layer band gap width E of the semiconductor device is obtained by using electrical characteristic test and material characterization analysis technology. go ;

[0030] The oxide layer bandgap width E go Adding to the semiconductor device model including typical defect model parameters and related physical processes;

[0031] Wherein, the bandgap width E of the oxide layer is obtained go ways, including:

[0032] By testing the absorption spectrum of at least one third semiconductor material sample, the band gap width E of the oxide layer is obtained. go .

[0033] Optionally, the modeling method further includes:

[0034] When the oxide layer of the semiconductor device is a single-layer dielectric, a second semiconductor device sample is obtained; the second semiconductor device sample is the same device as the semiconductor device; the gate leakage physical mechanism thereof is determined by performing a gate leakage current test on the second semiconductor device sample; within a voltage range that conforms to the TAT gate leakage mechanism, the oxide layer defect energy level E is obtained by fitting and calculating according to the current and voltage data obtained by the test. bt , and obtain the current-voltage curve within the voltage range that conforms to the TAT gate leakage mechanism and the current-voltage curve within the voltage range that conforms to the FN gate leakage mechanism as the test basis for subsequent model fitting; the oxide layer defect energy level E obtained by fitting calculation bt The measured oxide layer defect energy level E bt Perform calibration verification;

[0035] When the oxide layer of the semiconductor device is a laminated dielectric, at least one fourth semiconductor device sample is obtained; the fourth semiconductor device sample includes a first metal layer, a semiconductor material layer, a single oxide layer and a second metal layer from bottom to top; the materials of the first metal layer, the semiconductor material layer and the second metal layer are the same as the corresponding layers of the semiconductor device, and the single oxide layer of the at least one fourth semiconductor device sample is the same as the oxide layers of the semiconductor device in a one-to-one correspondence; the leakage current physical mechanism of the at least one fourth semiconductor device sample is determined by performing a leakage current test on the at least one fourth semiconductor device sample; within the voltage range that conforms to the TAT leakage mechanism, the oxide layer defect energy level E is obtained by fitting and calculating according to the current and voltage data obtained by the test. bt ; The oxide layer defect energy level E calculated by fitting bt The measured oxide layer defect energy level E bt Verify one by one;

[0036] When the oxide layer of the semiconductor device is a laminated dielectric, a second semiconductor device sample is obtained; the second semiconductor device sample is the same device as the semiconductor device; the physical mechanism of gate leakage is determined by performing a gate leakage current test on the second semiconductor device sample; based on the current and voltage data obtained from the test, a current-voltage curve within a voltage range that conforms to the TAT gate leakage mechanism and a current-voltage curve within a voltage range that conforms to the FN gate leakage mechanism are obtained as a test basis for subsequent model fitting.

[0037] Optionally, the modeling method further includes:

[0038] Acquire at least one fourth semiconductor device sample; the fourth semiconductor device sample comprises, from bottom to top, a first metal layer, a semiconductor material layer, a single oxide layer, and a second metal layer; the materials of the first metal layer, the semiconductor material layer, and the second metal layer are the same as the corresponding layers of the semiconductor device, and the material of the single oxide layer of the at least one fourth semiconductor device sample is the same as the corresponding oxide layer of the semiconductor device;

[0039] Testing a capacitance-voltage hysteresis characteristic curve of the at least one fourth semiconductor device sample to extract a change in the flat-band voltage;

[0040] The oxide layer defect density N is calculated based on the change in the flat band voltage. bt , and use the calculated oxide layer defect density N bt The oxide layer defect density N bt Perform calibration verification.

[0041] Optionally, the step difference between the oxide layer and the semiconductor conduction band in the typical defect model parameters is obtained. ways, including:

[0042] Acquire a second semiconductor device sample; the second semiconductor device sample is the same device as the semiconductor device;

[0043] Determining the physical mechanism of gate leakage by performing a gate leakage current test on the second semiconductor device sample;

[0044] In the voltage range that conforms to the FN gate leakage mechanism, the step difference between the oxide layer and the semiconductor conduction band is calculated based on the current and voltage test data obtained by the test.

[0045] Optionally, the modeling method further includes:

[0046] Before fitting the semiconductor device model including typical defect model parameters and related physical processes to the actual device electrical characteristic test results, the semiconductor bandgap width E of the semiconductor device is obtained by using electrical characteristic test and material characterization analysis technology. gs ;

[0047] The semiconductor bandgap width E gs Adding to the semiconductor device model including typical defect model parameters and related physical processes;

[0048] Wherein, the semiconductor bandgap width E is obtained gs The methods include:

[0049] Acquire a fifth semiconductor material sample; the fifth semiconductor material sample comprises a semiconductor material layer; the semiconductor material layer is the same as the semiconductor material layer of the semiconductor device;

[0050] By testing the absorption spectrum of the fifth semiconductor material sample, the semiconductor bandgap width E is obtained. gs ;

[0051] Obtain the semiconductor material defect type Type and semiconductor material defect energy level E in the typical defect model parameters. t and semiconductor material defect density N t The methods include:

[0052] By performing an X-ray photoelectron spectroscopy XPS test and a photoluminescence spectrum PL test on the fifth semiconductor material sample, the semiconductor material defect type Type and the semiconductor material defect energy level E are obtained. t and semiconductor material defect density N t .

[0053] Optionally, the modeling method further includes:

[0054] Before fitting the semiconductor device model including typical defect model parameters and related physical processes to the actual device electrical characteristic test results, the carrier concentration N of the channel layer of the semiconductor device is obtained by using electrical characteristic test and material characterization analysis technology. d ;

[0055] The carrier concentration N d Adding to the semiconductor device model including typical defect model parameters and related physical processes;

[0056] Wherein, the carrier concentration N is obtained d ways, including:

[0057] Obtaining a sixth semiconductor device sample; the sixth semiconductor device sample is obtained by preparing a group of ohmic contact electrodes with gradually increasing adjacent spacings on the surface of the fifth semiconductor material sample;

[0058] Testing the resistance between adjacent ohmic contact electrodes in the sixth semiconductor device sample;

[0059] Fitting the sheet resistance of the semiconductor material based on the resistance and spacing between adjacent ohmic contact electrodes;

[0060] The carrier concentration N is calculated based on the sheet resistance d .

[0061] Optionally, the semiconductor device model including typical defect model parameters and related physical processes is fitted to the actual device electrical characteristic test results to obtain a model reflecting the real physical characteristics of the actual semiconductor device, including:

[0062] Simulate the electrical characteristics of a semiconductor device model that includes typical defect model parameters and related physical processes;

[0063] Fitting the device electrical characteristics output by simulation with the device electrical characteristics of actual test;

[0064] If there is a deviation between the simulation results and the actual electrical characteristics test results, adjust the parameters of the non-intrinsic and non-test analysis used in the simulation, perform the simulation again, and compare the electrical characteristics of the device with those of the actual test. Repeat this operation until the device electrical characteristics of the simulation output are consistent with the electrical characteristics of the device actually tested, and finally build a model that reflects the true physical characteristics of the actual semiconductor device.

[0065] The semiconductor device physical modeling method combined with material and device testing and analysis technology provided by the present invention comprises: constructing an ideal simulation model of the semiconductor device in semiconductor process simulation and device simulation tool software according to the basic materials and structures of the semiconductor device to be physically modeled; obtaining typical defect model parameters of the semiconductor device by using electrical characteristic testing and material characterization and analysis technology, including: interface state defect energy level E it , interface state defect density D it , oxide layer defect type Type, oxide layer defect energy level E bt , oxide layer defect density N bt , the step difference between the oxide layer and the semiconductor conduction band Semiconductor material defect type Type, semiconductor material defect energy level E t And the semiconductor material defect density N t. A semiconductor device model including typical defect model parameters is constructed based on the ideal simulation model and typical defect model parameters; a physical process model related to semiconductor devices and their typical defects is added to the semiconductor device model to construct a semiconductor device model including typical defect model parameters and related physical processes, and the model is fitted to the actual device electrical characteristics test results. The final constructed model is a model that reflects the real physical characteristics of the actual semiconductor device, which provides an important premise for conducting device numerical simulation research, reliability mechanism research, and device optimization design based on the model.

[0066] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 It is a flow chart of a semiconductor device physical modeling method combining material and device testing and analysis technology provided by an embodiment of the present invention;

[0068] FIG2(a) is a schematic diagram of the structure of a gallium oxide (Ga2O3) MOSFET having a single-layer gate dielectric layer (the gate dielectric layer is the oxide layer shown in the schematic diagram), which is a second semiconductor device sample;

[0069] FIG2( b ) is a schematic structural diagram of a gallium oxide MOSFET having a stacked gate dielectric layer, which is a second semiconductor device sample;

[0070] Figure 3 is a schematic structural diagram of a first semiconductor device sample used when performing physical modeling on the device shown in FIG. 2( a ) in an embodiment of the present invention;

[0071] Figure 4 is a schematic structural diagram of a first semiconductor device sample used when performing physical modeling on the device shown in FIG. 2( b ) in an embodiment of the present invention;

[0072] Figure 5 is a schematic structural diagram of a third semiconductor material sample used when performing physical modeling on the device shown in FIG. 2( a ) in an embodiment of the present invention;

[0073] Figure 6 is a schematic structural diagram of a third semiconductor material sample used when performing physical modeling on the device shown in FIG. 2( b ) in an embodiment of the present invention;

[0074] Figure 7 is a schematic structural diagram of a fourth semiconductor device sample used when performing physical modeling on the device shown in FIG. 2( b ) in an embodiment of the present invention;

[0075] Figure 8 It is a schematic diagram of the physical process of the gate leakage current mechanism of MOSFET;

[0076] Fig. 9 is a schematic structural diagram of a fifth semiconductor material sample used when performing physical modeling on the device shown in FIG. 2( a ) or FIG. 2( b ) in an embodiment of the present invention;

[0077] Fig.10 is a schematic structural diagram of a sixth semiconductor device sample used when performing physical modeling on the device shown in FIG. 2( a ) or FIG. 2( b ) in an embodiment of the present invention;

[0078] Fig.11 The figure shows the correspondence between the test method and the test object (semiconductor sample) used to obtain various typical defect model parameters when performing physical modeling for a single-layer gate dielectric MOSFET device;

[0079] Fig.12 The figure shows the correspondence between the test method and the test object (semiconductor sample) used to obtain various typical defect model parameters when performing physical modeling for a stacked gate dielectric MOSFET device.

[0080] Fig.13 The process of combining material and device testing and analysis technology to perform physical modeling of a conductor device in an embodiment of the present invention is exemplarily shown;

[0081] Fig.14 The actual electrical characteristics test results of the stacked-gate dielectric gallium oxide MOSFET are shown in FIG. 1 and the simulated electrical characteristics comparison of the stacked-gate dielectric gallium oxide MOSFET model including typical defect model parameters and its physical process completed by the modeling method of an embodiment of the present invention under the same conditions. DETAILED DESCRIPTION

[0082] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0083] In order to reflect the real physical properties of actual (ultra) wide bandgap semiconductor devices, thereby solving the obstacles encountered in current device numerical simulation research, reliability physical mechanism research, and device optimization design, an embodiment of the present invention provides a semiconductor device physical modeling method that combines material and device testing and analysis technology.

[0084] like Figure 1 As shown, the modeling method provided by the embodiment of the present invention includes the following steps:

[0085] S10. Construct an ideal simulation model of the semiconductor device in semiconductor process simulation and device simulation tool software according to the basic materials and structure of the semiconductor device to be physically modeled.

[0086] The semiconductor devices to be physically modeled may include wide bandgap semiconductor devices or ultra-wide bandgap semiconductor devices.

[0087] Specifically, first determine the basic materials and structure information of the real semiconductor device to be physically modeled, and then build an ideal simulation model of the semiconductor device in the semiconductor process simulation and device simulation tool software based on this information. When specifically building the ideal simulation model, the structural parameters, basic semiconductor material parameters, oxide material parameters, boundary condition settings and other parameters of the semiconductor device can be directly defined from the semiconductor process simulation and device simulation tool software (such as TCAD), so that the semiconductor device is modeled in the TCAD simulation software based on these parameters to obtain an ideal simulation model.

[0088] In the ideal simulation model, the simulation of electrical characteristics is based on ideal physical formulas, so the influence of typical defects is often not considered in the ideal simulation model. For example, for (ultra) wide bandgap semiconductor devices, taking MOSFET as an example, in the ideal simulation model, the drain current I D It is expressed as the following formula.

[0089]

[0090] Among them, V GS is the gate-source voltage, V TH is the threshold voltage, V DS is the drain-source voltage, μ n is the carrier mobility, W is the gate width, L is the channel length, C OX is the gate dielectric capacitance, I D is the drain current.

[0091] In addition, in the ideal simulation model, the threshold voltage V TH It is expressed as the following formula.

[0092]

[0093] Among them, V FB represents the flat band voltage, q represents the electron charge, N d represents the carrier concentration, W1 is the epitaxial layer channel thickness, d oxide Indicates the thickness of the gate dielectric oxide layer, ε0, ε oxide , ε s They represent the vacuum dielectric constant, the gate oxide dielectric relative dielectric constant and the semiconductor relative dielectric constant respectively.

[0094] S20, using electrical property testing and material characterization analysis technology to obtain typical defect model parameters of semiconductor devices, the typical defect model parameters include: interface state defect energy level E it , interface state defect density D it, oxide layer defect type Type, oxide layer defect energy level E bt , oxide layer defect density N bt , the step difference between the oxide layer and the semiconductor conduction band Semiconductor material defect type Type, semiconductor material defect energy level E t And the semiconductor material defect density N t .

[0095] In actual semiconductor power devices, typical defects that affect the electrical parameters of the device include: (1) point defects in semiconductor materials (such as vacancies and impurities); (2) oxide layer defects in the MOS gate dielectric layer; and (3) interface state defects between the MOS gate dielectric layer and the semiconductor.

[0096] Among them, point defects in semiconductor materials will introduce new defect / impurity energy levels. The defect energy levels can serve as the center of carrier recombination, changing parameters such as carrier concentration and mobility of semiconductor materials, thereby directly affecting the device's output current, on-resistance, switching ratio, transconductance, off-state leakage current and other electrical characteristics; oxide layer defects in the MOS gate dielectric layer will capture carriers in the channel, affecting the carrier mobility and the gate control capability of the device, thereby directly affecting the device's output current, threshold voltage, off-state leakage current, breakdown voltage, etc.; interface state defects between the MOS gate dielectric layer and the semiconductor will capture carriers in the channel, affecting parameters such as carrier concentration and mobility, thereby directly affecting the device's transfer characteristic curve hysteresis, output characteristics and other electrical characteristics.

[0097] In view of the above influences, the embodiment of the present invention obtains typical defect model parameters that affect the electrical characteristics of the device based on electrical characteristics testing and material characterization and analysis technology. The purpose is to improve the typical defect model parameters in the (ultra) wide bandgap semiconductor device model, so that the final constructed model is a model that reflects the real physical properties of the actual (ultra) wide bandgap semiconductor device.

[0098] In step S20, the specific implementation method of obtaining typical defect model parameters of semiconductor devices by using electrical property testing and material characterization analysis technology is mainly the typical defect model parameters of interface states (interface state defect energy level E it , interface state defect density D it ) and the typical defect model parameters of the oxide layer (Oxide layer defect type Type, Oxide layer defect energy level E bt , oxide layer defect density N bt , the step difference between the oxide layer and the semiconductor conduction band ) and the typical defect model parameters of semiconductor materials (semiconductor material defect type Type, semiconductor material defect energy level E t , semiconductor material defect density N t), and the specific method of obtaining each parameter will be described in detail with examples later.

[0099] S30. According to the ideal simulation model and the typical defect model parameters, a semiconductor device model including the typical defect model parameters is constructed, and a physical process model related to the semiconductor device and its typical defects is added to the semiconductor device model to obtain a semiconductor device model including the typical defect model parameters and related physical processes.

[0100] Among them, the physical process models related to semiconductor devices and their typical defects include: carrier statistical distribution model, drift diffusion model, mobility model and generation recombination model, but are not limited thereto.

[0101] Specifically, the various typical defect model parameters obtained in step S20 are added to the parameter library of the ideal simulation model constructed in step S10 to obtain a semiconductor device model containing typical defect model parameters. On this basis, the physical process model related to the semiconductor device and its typical defects is further added to the model, so that the simulation software adds a model of the coupling effect of defects on the physical process of the device according to the physical characteristics of the device to ensure that the effect of typical defects on the electrical characteristics of the semiconductor device can be accurately simulated, thereby obtaining a semiconductor device model containing typical defect model parameters and related physical processes.

[0102] S40, fitting the semiconductor device model including typical defect model parameters and related physical processes to the actual device electrical characteristic test results to obtain a model reflecting the real physical characteristics of the actual semiconductor device.

[0103] The device electrical characteristics include: output characteristics, transfer characteristics, gate leakage current and drain leakage current, but are not limited thereto. In practice, other device electrical characteristics may be added according to the modeling object and modeling requirements.

[0104] In step S40, the semiconductor device model including typical defect model parameters and related physical processes is fitted to the actual device electrical characteristics test results to obtain a model reflecting the real physical characteristics of the actual semiconductor device, including:

[0105] (1) simulating the electrical characteristics of the semiconductor device model including typical defect model parameters and related physical processes; that is, simulating the electrical characteristics of the device using the semiconductor device model including typical defect model parameters and related physical processes constructed in the previous step in the simulation software;

[0106] (2) Fitting the device electrical characteristics output by simulation with the device electrical characteristics of actual test;

[0107] (3) If there is a deviation between the simulation results and the actual electrical characteristics test results, adjust the parameters of the non-intrinsic and non-test analysis used in the simulation, perform the simulation again, and compare the results with the actual device electrical characteristics tested. Repeat this operation until the device electrical characteristics output by the simulation are consistent with the actual device electrical characteristics tested, and finally construct a model that reflects the real physical characteristics of the actual semiconductor device.

[0108] Among them, the non-intrinsic and non-test analysis parameters used in simulation include the size of the grid in the semiconductor device model, the density of the grid, the calculation step, the numerical solution method, and the number of convergence iterations. Here, the grid is a small unit for solving the device model built in the simulation. For example, in TCAD software, the semiconductor parameters in each grid are solved. By optimizing the grid, the best compromise between solution speed and accuracy can be achieved.

[0109] In step S40, the model calculation results are compared and verified in detail with the actual test data through electrical characteristic fitting to ensure that the constructed model can accurately reflect the electrical performance of the semiconductor device under different working conditions, thereby ensuring the accuracy of the device model. The final constructed model is a model that reflects the real physical characteristics of the actual (ultra) wide bandgap semiconductor device.

[0110] It should be noted that the existing device modeling methods are usually based on existing ideal physical models, without considering the impact of typical defects, and the consideration of typical defect model parameters that affect device electrical parameters is also incomplete, so it cannot reflect the real physical characteristics of actual semiconductor devices. For example, in the existing material characterization device modeling method based on semiconductor material characterization technology to obtain defect energy levels, only the semiconductor material defect energy level E is considered. t , the defect density N of semiconductor materials in the typical defect model parameters cannot be determined t and defect type Type, interface state defect energy level E at the gate oxide layer and semiconductor interface in the MOS structure it , interface state defect density D it 、Oxide layer defect type in MOS structure Type、Oxide layer defect energy level E bt , oxide layer defect density N bt And the step difference between the oxide layer and the semiconductor conduction band At the same time, the specific physical mechanism of gate leakage is not analyzed in combination with the gate leakage current-voltage characteristics of the actual device, and it is impossible to provide a reference for the fitting of subsequent electrical characteristics, such as the fitting of key electrical characteristics such as gate leakage current.

[0111] In contrast to the prior art, the semiconductor device physical modeling method provided by the embodiment of the present invention, which combines material and device testing and analysis technology, comprehensively considers the impact of typical device defects. Specifically, according to the basic materials and structures of the semiconductor device to be physically modeled, an ideal simulation model of the semiconductor device is constructed in the semiconductor process simulation and device simulation tool software; the typical defect model parameters of the semiconductor device are obtained by using electrical property testing and material characterization and analysis technology, including: interface state defect energy level E it , interface state defect density D it , oxide layer defect type Type, oxide layer defect energy level E bt , oxide layer defect density N bt , the step difference between the oxide layer and the semiconductor conduction band Semiconductor material defect type Type, semiconductor material defect energy level E t And the semiconductor material defect density N t A semiconductor device model including typical defect model parameters is constructed based on the ideal simulation model and the typical defect model parameters; a physical process model related to the semiconductor device and its typical defects is added to the semiconductor device model to construct a semiconductor device model including typical defect model parameters and related physical processes, and the model is fitted to the actual device electrical characteristics test results to be consistent, and the final constructed model is a model that reflects the real physical characteristics of the actual (ultra) wide bandgap semiconductor device.

[0112] The specific implementation method of obtaining typical defect model parameters of semiconductor devices by using electrical characteristic testing and material characterization and analysis technology in step S20 is described in detail below by way of example.

[0113] First, an example is given to illustrate how to obtain the interface state defect model parameters.

[0114] It can be understood that, for a MOSFET device, the interface state defect model parameters are typical defect model parameters at the interface between the MOS gate dielectric layer and the semiconductor.

[0115] In one embodiment, the interface state defect energy level E in the typical defect model parameters is obtained. it ways, including:

[0116] (a1) obtaining a first semiconductor device sample; the first semiconductor device sample comprises, from bottom to top, a first metal layer, a semiconductor material layer, an oxide layer, and a second metal layer; wherein the materials of the first metal layer, the semiconductor material layer, the oxide layer, and the second metal layer are the same as those of the corresponding layers of the semiconductor device;

[0117] (a2) Using the conductivity method to measure the conductivity curve of the first semiconductor device sample from low frequency to high frequency, and obtaining the interface state defect energy level E according to the response frequency of the peak value in the conductivity curveit ;

[0118] (a3) Construct a material interface model of the semiconductor material layer and the oxide layer in a material modeling software tool (e.g., VESTA), and calculate the interface state defect energy level E based on first principles. it ;

[0119] (a4) The interface state defect energy level E calculated based on first principles it The interface defect energy level E obtained by the conductivity method it Perform calibration verification.

[0120] Taking the semiconductor device shown in FIG2 as an example, the device is a gallium oxide MOSFET. First, consider the case of a single-layer gate dielectric MOSFET: a Ga2O3 material sheet with the same material parameters as the MOSFET is used to prepare a first semiconductor device sample with the same oxide layer type and oxide layer thickness as the MOSFET, such as Figure 3 As shown, the top Ni / Au metal layer, the oxide oxide layer and the bottom Ti / Au metal layer are all consistent with the gallium oxide MOSFET. The first semiconductor device sample is tested by the conductivity method. By changing the test frequency of the conductivity curve, carriers will be captured and emitted by interface defects with different time constants. When the inverse of the defect response time is within the detection frequency range, the defect will generate a conductivity peak, and then the interface state defect energy level E is calculated according to the frequency corresponding to the conductivity peak. it Specifically, by testing the conductivity curve from low frequency (1kHz) to high frequency (10MHz), the electrical characteristic data of the response at different frequencies is analyzed and processed, so as to obtain the interface state defect energy level E at the peak response frequency. it :

[0121]

[0122] Among them, τ T is the interface state defect time constant corresponding to the peak response frequency f, σ is the interface defect capture cross section, N C is the conduction band electron effective density of states, v T is the average thermal velocity of carriers, k is the Boltzmann constant, and T is the Kelvin temperature in the test of the first semiconductor device sample.

[0123] Subsequently, a material interface model of the semiconductor material layer and the oxide layer is constructed in a material modeling software tool (such as VESTA), and the interface state defect energy level E is calculated based on the first principles. itFirst principles calculations can calculate the properties of materials. In the material modeling software tool, a material interface model of the semiconductor material layer and the oxide layer is constructed, and then the properties are calculated by first principles. By deducting some atomic points at the interface in the simulation software, the interface state defect energy level E can be calculated. it Then, the interface state defect energy level E is calculated based on first principles. it The interface defect energy level E obtained by the conductivity method it Calibration verification is performed to accurately obtain the interface state defect energy level E it .

[0124] Then consider the case of stacked gate dielectric MOSFET: a Ga2O3 material sheet with the same material parameters as MOSFET is used to prepare a first semiconductor device sample with the same oxide layer type and oxide layer thickness as MOSFET, such as Figure 4 As shown in Figure 1, the materials of the top Ni / Au metal layer, oxide oxide layer and bottom Ti / Au metal layer are consistent with those of the gallium oxide device. Figure 4 The samples shown were tested by conductivity method, and the interface state defect energy level E was obtained on this basis. it Subsequently, a material interface model of the semiconductor material layer and the oxide layer in contact with it was constructed in the material modeling software tool, and the interface state defect energy level E was calculated based on the first principles. it Then, the interface state defect energy level E is calculated based on first principles. it The interface defect energy level E obtained by the conductivity method it Calibration verification is performed to accurately obtain the interface state defect energy level E it .

[0125] In one embodiment, the interface state defect density D in the typical defect model parameters is obtained. it ways, including:

[0126] (b1) obtaining a second semiconductor device sample; the second semiconductor device sample is the same device as the semiconductor device;

[0127] (b2) testing a transfer characteristic curve of a second semiconductor device sample;

[0128] (b3) determining the subthreshold region according to the transfer characteristic curve;

[0129] (b4) Calculate the interface state defect density D based on the subthreshold slope of the subthreshold region it .

[0130] Taking the gallium oxide MOSFET shown in Figure 2 as an example, we first consider the case of a single-layer gate dielectric MOSFET: for the second semiconductor device sample that is the same as the MOSFET shown in Figure 2(a), the drain voltage is fixed, different gate voltages are applied, and the drain current is measured to obtain the transfer characteristic curve. Generally, in the subthreshold region, the drain current increases by an order of magnitude with the gate voltage, and the interface state defect density D it The following relationship exists with the subthreshold slope of the subthreshold region:

[0131]

[0132] Where SS is the slope of the subthreshold curve, V t is the thermal voltage, q is the electron charge, C OX is the gate dielectric capacitance.

[0133] By analyzing the transfer characteristic curve, the curve in the subthreshold region is selected for calculation, so that the interface state defect density D between the MOS gate dielectric layer and the semiconductor can be calculated from the measured data. it .

[0134] For the case of a stacked-gate dielectric MOSFET, as shown in FIG2( b ), the test and calculation process is basically the same as that of a single-layer gate dielectric MOSFET and will not be described in detail.

[0135] The above is an example of how to obtain the interface state defect model parameters.

[0136] Then, an example is given to illustrate the method of obtaining the parameters of the oxide layer defect model.

[0137] It can be understood that, for a MOSFET device, the oxide layer defect model parameters are typical defect model parameters of a MOS gate dielectric layer.

[0138] In one embodiment, the oxide layer defect type Type and the oxide layer defect energy level E are obtained. bt and oxide layer defect density N bt ways, including:

[0139] (c1) obtaining at least one third semiconductor material sample; wherein the third semiconductor material sample comprises a semiconductor material layer and a single oxide layer from bottom to top; the semiconductor material layer is the same as the semiconductor layer of the semiconductor device, and the single oxide layer of the at least one third semiconductor material sample is the same as each oxide layer of the semiconductor device in a one-to-one correspondence;

[0140] (c2) performing an X-ray photoelectron spectroscopy (XPS) test and a photoluminescence spectroscopy (PL) test on the at least one third semiconductor material sample to obtain an oxide layer defect type Type, an oxide layer defect energy level E btand oxide layer defect density N bt .

[0141] Taking the gallium oxide MOSFET shown in FIG2 as an example, the case of a single-layer gate dielectric MOSFET is first considered: First, referring to the semiconductor material layer and oxide layer of the gallium oxide MOSFET, a preparation method is prepared as follows: Figure 5 The third semiconductor material sample shown in FIG. 1 is used to obtain the partial defect energy level E of the oxide layer by testing the photoluminescence spectrum of the sample. bt and defect type Type.

[0142] Specifically, a photoluminescence spectrum test is performed using an excitation light source with a wavelength greater than the bandgap width of the oxide layer, and E is obtained from the spectrum. C -E bt , thereby obtaining the energy level E of the defect distance conduction band bt , that is, the oxide layer defect level:

[0143] E C -E bt =hv / λ;

[0144] Among them, E C is the bottom energy level of the conduction band, h is Planck's constant, v is the frequency of light, hv is the photon energy, and λ is the wavelength of the light source.

[0145] In addition, X-ray photoelectron spectroscopy (XPS) can be used to deeply analyze the chemical state information of elements in semiconductor oxides. It can not only analyze the defect type, but also quantitatively evaluate the content of defects such as oxygen vacancies to obtain the defect molar concentration, thereby performing a semi-quantitative analysis of the defect concentration and realizing the oxide layer defect density N. bt to obtain.

[0146] Then consider the case of stacked gate dielectric MOSFET: Here, it is necessary to prepare corresponding third semiconductor material samples for each oxide layer (such as Figure 6 ), and then perform XPS test and PL test on them respectively to obtain the oxide layer defect type Type, oxide layer defect energy level E of each oxide layer bt1 、E bt2 and oxide layer defect density N bt1 、N bt2 .

[0147] In one embodiment, before the semiconductor device model including typical defect model parameters and related physical processes is matched with the actual device electrical characteristic test results, the modeling method further includes: obtaining the oxide layer band gap width E of the semiconductor device by using electrical characteristic test and material characterization analysis technology. go ; The bandgap width of the oxide layer E goAdd to the semiconductor device model including typical defect model parameters and related physical processes. Therefore, when the semiconductor device model including typical defect model parameters and related physical processes is used to simulate the device electrical characteristics in step S40, the oxide layer bandgap width E is also added. go The impact of is also taken into account.

[0148] Among them, the bandgap width E of the oxide layer is obtained go The method comprises: obtaining the oxide layer band gap width E by testing the absorption spectrum of at least one third semiconductor material sample go .

[0149] Specifically, the bandgap width can be determined by the absorption spectrum by testing the relationship between the absorption coefficient and the photon energy hv using the Tauc plot method, and the bandgap width E can be calculated using the following formula: go :

[0150] (αhv) 1 / n =B(hv-E go );

[0151] Among them, α is the absorption coefficient, hv is the photon energy, B is a constant, and the value of n is related to the type of material. When the material band gap is a direct band gap, n=1 / 2; when the material band gap is an indirect band gap, n=2.

[0152] Thus, the band gap width E of the oxide layer is determined by the absorption spectrum. go , and use it as one of the oxide model parameters.

[0153] For the case of a single-layer gate dielectric MOSFET, the object of the absorption spectrum test is Figure 5 The third semiconductor material sample shown in FIG. 1 is used to obtain the oxide layer band gap width E corresponding to the oxide layer. go For the stacked gate dielectric MOSFET, it is necessary to prepare the corresponding third semiconductor material sample for each oxide layer (such as Figure 6 ), so as to obtain the oxide layer bandgap width E corresponding to each oxide layer. go1 、E go2 .

[0154] In one embodiment, the modeling method provided by the embodiment of the present invention may further include:

[0155] (c3-1) When the oxide layer of the semiconductor device is a single-layer dielectric, a second semiconductor device sample is obtained; the second semiconductor device sample is the same device as the semiconductor device; the physical mechanism of gate leakage is determined by performing a gate leakage current test on the second semiconductor device sample; within a voltage range that conforms to the TAT gate leakage mechanism, the oxide layer defect energy level E is obtained by fitting and calculating based on the current and voltage data obtained by the test. bt, and obtain the current-voltage curve within the voltage range that conforms to the TAT (Trap Assisted Tunneling) gate leakage mechanism and the current-voltage curve within the voltage range that conforms to the FN (Fowler-Nordheim) gate leakage mechanism as the test basis for the subsequent model fitting (step S40); the oxide layer defect energy level E obtained by fitting calculation bt The oxide layer defect energy level E measured in step (c2) bt Perform calibration verification.

[0156] (c3-2) When the oxide layer of the semiconductor device is a laminated dielectric, obtaining at least one fourth semiconductor device sample; the fourth semiconductor device sample includes, from bottom to top, a first metal layer, a semiconductor material layer, a single oxide layer, and a second metal layer; wherein the materials of the first metal layer, the semiconductor material layer, and the second metal layer are the same as the corresponding layers of the semiconductor device, and the single oxide layer of at least one fourth semiconductor device sample is the same as the oxide layers of the semiconductor device in a one-to-one correspondence, such as Figure 7 ; Determine the physical leakage mechanism of at least one fourth semiconductor device sample by performing a leakage current test; and obtain the oxide layer defect energy level E by fitting and calculating according to the current and voltage data obtained from the test within a voltage range that conforms to the TAT leakage mechanism. bt1 、E bt2 ; The oxide layer defect energy level E calculated by fitting bt1 、E bt2 The oxide layer defect energy level E measured in step (c2) bt1 、E bt2 Verify one by one.

[0157] (c3-3) When the oxide layer of the semiconductor device is a laminated dielectric, a second semiconductor device sample is obtained; the second semiconductor device sample is the same device as the semiconductor device; the physical mechanism of gate leakage is determined by performing a gate leakage current test on the second semiconductor device sample; based on the current and voltage data obtained from the test, a current-voltage curve within a voltage range that conforms to the TAT gate leakage mechanism and a current-voltage curve within a voltage range that conforms to the FN gate leakage mechanism are obtained as a test basis for subsequent model fitting (step S40).

[0158] In the above step (c3-2), for the case of a single-layer gate dielectric MOSFET, the gate leakage current test object is a second semiconductor device sample that is the same as the MOSFET shown in FIG. 2(a), and the defect energy level E corresponding to the oxide layer is calculated. bt For the stacked gate dielectric MOSFET, it is necessary to prepare a corresponding fourth semiconductor device sample for each oxide layer (eg Figure 7), respectively, leakage current tests are performed to calculate the defect energy level E corresponding to each oxide layer. bt1 、E bt2 .

[0159] Specifically, the physical mechanism of gate leakage is analyzed as follows: The main leakage mechanisms of MOSFET gate dielectrics are Poole-Frenkel (PF) emission, Trap assisted tunneling (TAT) tunneling and Fowler-Nordheim (FN) emission. The first leakage mechanism is PF emission. Usually under low field (1kV / cm), electrons in oxide layer defects gain enough energy, jump over the potential barrier upward to the oxide layer conduction band, and then enter the semiconductor to form a leakage current; the second leakage mechanism is TAT ​​tunneling. There are defects in the oxide layer, and electrons enter the semiconductor conduction band through defect-assisted tunneling to form a leakage current; the third leakage mechanism is FN emission. Under high electric field, the energy bands on both sides of the oxide layer form a triangular potential barrier, and electrons in the metal directly tunnel through the potential barrier into the semiconductor conduction band to form a tunneling current. The physical process of gate leakage current mechanism can be found in. Figure 8 .

[0160] The relationship between the current density and electric field dominated by the PF, TAT and FN leakage mechanisms is as follows:

[0161]

[0162] Where J is the current density, E is the electric field, q is the unit charge, represents the oxide defect energy level E related to the PF mechanism bt , N C is the conduction band defect density, μ is the electron mobility in the oxide, E bt represents the oxide defect energy level E related to the TAT mechanism bt , C t is the rate constant related to the defect energy, N bt represents the oxide defect density N related to the TAT mechanism bt , m is the electron effective mass of the semiconductor material, m OX is the electron effective mass of the oxide layer material, is the step difference between the oxide layer and the semiconductor conduction band, ε r is the relative dielectric constant and h is Planck's constant.

[0163] In the above steps (c3-1) and (c3-2), the oxide layer defect energy level E is obtained by fitting and calculating the current and voltage data obtained by the test. btThe specific method includes: determining the voltage range that meets the TAT gate leakage mechanism, drawing a curve with 1 / E as the horizontal axis and ln(JE) as the vertical axis based on the (gate) leakage current test, if there is a linear region in the curve, the corresponding electric field is the TAT leakage mechanism, and performing a linear fit of the data in the linear region in the form of y=ax+b, and calculating the oxide layer defect energy level E according to the slope a. bt . Thus, the calculated oxide layer defect energy level E bt The oxide layer defect energy level E obtained in the calibration verification step (c2) bt .

[0164] In one embodiment, the modeling method provided by the embodiment of the present invention further includes:

[0165] (c4-1) obtaining at least one fourth semiconductor device sample; the structure of the fourth semiconductor device sample has been described above and will not be repeated here;

[0166] (c4-2) testing a capacitance-voltage (CV) hysteresis characteristic curve of at least one fourth semiconductor device sample to extract a change in a flat-band voltage;

[0167] (c4-3) The oxide layer defect density N is calculated based on the change in flat band voltage bt The calculated oxide layer defect density N bt The oxide layer defect density N obtained in step (c2) is bt Perform calibration verification.

[0168] It is understandable that when the gate oxide layer of the semiconductor device is a single-layer dielectric, it is only necessary to obtain a fourth semiconductor device sample (the structure of which can be seen in FIG. 1 ) whose oxide layer is the same as that of the semiconductor device. Figure 3 ), the capacitance-voltage hysteresis characteristic curve is tested, and the defect density N corresponding to the oxide layer is calculated. bt When the gate oxide layer of the semiconductor device is a laminated dielectric, it is necessary to refer to Figure 7 The fourth semiconductor device samples with different oxide layers are prepared respectively, and then the capacitance-voltage hysteresis characteristic curve of each fourth semiconductor device sample is tested respectively, so as to calculate the defect density N corresponding to each oxide layer respectively. bt1 、N bt2 At the same time, the oxide layer defect density N obtained by electrical properties test bt The oxide layer defect density N measured in step (c2) bt Perform calibration verification.

[0169] Specifically, by testing the capacitance-voltage hysteresis characteristic curve of the fourth semiconductor device sample, the flat-band voltage variation ΔV can be extracted. FB, combined with the gate area A of the fourth semiconductor device sample, the defect density N of the oxide layer is further calculated. bt , see the following formula:

[0170]

[0171] Among them, C OX is the gate dielectric capacitance, and q represents the electron charge.

[0172] In one embodiment, the step difference between the oxide layer and the semiconductor conduction band in the typical defect model parameters is obtained. ways, including:

[0173] (d1) obtaining a second semiconductor device sample; the second semiconductor device sample is a device made of the same material as the semiconductor device, as shown in FIG. 2( a ) and FIG. 2( b );

[0174] (d2) determining the physical mechanism of gate leakage by performing a gate leakage current test on the second semiconductor device sample;

[0175] (d3) In the voltage range that conforms to the FN gate leakage mechanism, the conduction band step difference between the oxide layer and the semiconductor is calculated based on the current and voltage test data obtained by the test.

[0176] Specifically, determine the voltage range that meets the FN gate leakage mechanism, and plot 1 / E as the horizontal axis and ln(1 / E 2 ) is the curve with the ordinate as the vertical axis. If there is a linear region in the curve, the FN leakage mechanism is in this voltage range. At the same time, a linear fit of the data in the linear region in the form of y=ax+b is performed. The conduction band step difference between the oxide layer and the semiconductor can be calculated based on the slope a.

[0177] It should be noted that in actual analysis of the physical mechanism of gate leakage of devices at room temperature, usually only TAT and FN mechanisms are involved. Since the PF mechanism requires high temperature excitation and there is almost no PF mechanism at room temperature, this mechanism is usually not considered.

[0178] The above is an example of how to obtain the oxide layer defect model parameters.

[0179] Then, an example is given to illustrate how to obtain the semiconductor material defect model parameters.

[0180] In one embodiment, the semiconductor material defect type Type and the semiconductor material defect energy level E are obtained. t and semiconductor material defect density N tThe method includes: obtaining a fifth semiconductor material sample; the fifth semiconductor material sample includes a semiconductor material layer; the semiconductor material layer is the same as the semiconductor material layer of the semiconductor device; performing XPS test and PL test on the fifth semiconductor material sample to obtain the semiconductor material defect type Type, the semiconductor material defect energy level E t and semiconductor material defect density N t .

[0181] Taking the semiconductor device shown in FIG. 2 as an example, the device is a gallium oxide MOSFET. A Ga2O3 material sheet with the same material parameters as the MOSFET is used for material characterization analysis to obtain a fifth semiconductor material sample, such as Fig. 9 As shown. Similar to step (c2), the fifth semiconductor material sample is subjected to XPS test and PL test. Among them, with the help of XPS, the chemical state information of the elements in the semiconductor can be deeply analyzed. Not only can the defect types, such as oxygen vacancies and gallium defects, be analyzed, but also the content of defects such as oxygen vacancies can be quantitatively evaluated to complete the acquisition of defect molar concentration, thereby performing quantitative analysis of defect concentration. For example, the XPS full spectrum can detect the sample element information and relative content, and the XPS fine spectrum O1s spectrum can fit the relative content of Ga-O bonds and oxygen vacancies by peak separation. The oxygen vacancy content is obtained by the following relationship: oxygen vacancy content = 100% × [(oxygen vacancy ratio) / (oxygen vacancy ratio + other element atomic number ratio)]. The oxygen vacancy defect concentration N can be quantitatively calculated by the content. t In addition, PL spectroscopy can obtain some defect energy levels E t and its type Type, revealing the position and relative content of defects such as oxygen vacancies and gallium vacancies in the band structure, and combining the above characterization to semi-quantitatively deduce the material defect density N t Through the above steps, the semiconductor material defect type Type and semiconductor material defect energy level E are obtained. t and semiconductor material defect density N t .

[0182] In one embodiment, before the semiconductor device model including typical defect model parameters and related physical processes is matched with the actual device electrical characteristic test results, the modeling method further includes: obtaining the semiconductor bandgap width E of the semiconductor device by using electrical characteristic test and material characterization analysis technology. gs ; The semiconductor bandgap width E gs Add to the semiconductor device model including typical defect model parameters and related physical processes. Therefore, when the semiconductor device model including typical defect model parameters and related physical processes is used to simulate the device electrical characteristics in step S40, the semiconductor bandgap width E is also added. gs The impact of is also taken into account.

[0183] Among them, the semiconductor bandgap width E is obtained gs The method comprises: obtaining the semiconductor bandgap width E by testing the absorption spectrum of the fifth semiconductor material sample gs .

[0184] Here, the semiconductor bandgap width E is obtained by testing the absorption spectrum of the fifth semiconductor material sample. gs The specific implementation method is similar to the method of obtaining the band gap width of the oxide layer by testing the absorption spectrum of the third semiconductor material sample in step (c2), and will not be repeated here.

[0185] In one embodiment, before fitting the semiconductor device model including typical defect model parameters and related physical processes to the actual device electrical characteristic test results, the modeling method further includes: obtaining the carrier concentration N of the channel layer of the semiconductor device d ; Get the carrier concentration N d ways, including:

[0186] (f1) obtaining a sixth semiconductor device sample; the sixth semiconductor device sample is obtained by preparing a group of ohmic contact electrodes with gradually increasing adjacent spacings on the surface of the fifth semiconductor material sample;

[0187] (f2) measuring the resistance between adjacent ohmic contact electrodes in the sixth semiconductor device sample;

[0188] (f3) fitting and calculating the sheet resistance of the semiconductor material according to the resistance and spacing between adjacent ohmic contact electrodes;

[0189] (f4) The carrier concentration N is calculated based on the sheet resistance d .

[0190] Specifically, taking gallium oxide MOSFET as an example, a transmission line model (TLM) structure sample is prepared using a Ga2O3 material sheet with the same material parameters as MOSFET. Specifically, a group of ohmic contact electrodes with gradually increasing adjacent spacing are prepared on the Ga2O3 material sheet to form a structure such as Fig.10 The sixth semiconductor device sample shown in the figure is tested by testing the resistance between adjacent metal electrodes with different spacings. The adjacent electrode spacing L is used as the horizontal coordinate and the corresponding resistance R is used as the vertical coordinate for linear fitting. The square resistance R of the semiconductor material can be obtained according to the fitting slope. sh , and then according to the block resistance R sh The carrier concentration N is calculated using the following formula: d Calculation:

[0191]

[0192] Wherein, W is the width of the ohmic contact electrode, q is the unit charge, μ is the carrier mobility, and t is the thickness of the semiconductor channel layer.

[0193] The above is an example of how to obtain semiconductor material defect model parameters.

[0194] Fig.11 The figure shows by way of example the correspondence between the test method used to obtain various characteristic model parameters and the test objects (semiconductor devices and material samples) when performing physical modeling for a single-layer gate dielectric MOSFET device. Fig.12 The figure shows by way of example the correspondence between the test methods used to obtain various model parameters and their test objects (semiconductor devices and material samples) when performing physical modeling for stacked-gate dielectric MOSFET devices.

[0195] In addition, the acquisition of typical defect model parameters required for accurate device modeling in the embodiments of the present invention is not limited to the calculation and acquisition methods involved in the text, and other equivalent testing methods that can obtain corresponding parameters can also be used to achieve the purpose of improving the typical defect model parameters of semiconductor materials. it The acquisition of E is not limited to the conductivity method, and the charge pump method can also be used to obtain the interface state defect energy level E it Parameter test and analysis method; interface state defect density D between oxide layer and semiconductor it The acquisition of interface state defect density D can be obtained not only through the subthreshold slope method, but also through the Terman method, high and low frequency capacitance-voltage method, etc. it Parameter test and analysis method. Oxide layer defect density N bt The acquisition of is not limited to CV hysteresis test, 1 / f noise test can also be used to obtain the oxide layer defect density N bt Parameter test analysis method. Similarly, the carrier concentration N d The acquisition is not necessarily limited to the TLM method, but electrical CV method, Hall test method, etc. can also be used; the characterization and analysis method for obtaining typical defect parameters of materials is not only limited to XPS and PL tests, but also positron annihilation spectroscopy and other testing methods can be used to further improve the typical defect model parameters of semiconductor materials.

[0196] In a specific example, you can follow Fig.13 The process shown in the figure combines material and device test analysis technology to perform semiconductor device physical modeling. Among them, MOSCAP represents Figure 3 The semiconductor device sample shown, Sentaurus TCAD is a semiconductor simulation software, and the SDE module is the module for building the device structure in the software.

[0197] Fig.14The actual electrical characteristics test results of the stacked-gate dielectric gallium oxide MOSFET and the electrical characteristics comparison of the stacked-gate dielectric gallium oxide MOSFET model including typical defect model parameters and its physical process completed by the modeling method of the embodiment of the present invention under the same conditions are shown. It can be seen that the modeling method of the embodiment of the present invention can achieve accurate modeling of the stacked gallium oxide MOSFET.

[0198] It should be noted that the modeling method of the embodiment of the present invention is not only applicable to the precise modeling of devices based on (ultra) wide bandgap semiconductor materials, but is also applicable to the precise modeling of devices with other basic materials and incomplete device model libraries (such as molybdenum disulfide, graphene, diamond, silicon carbide, gallium nitride, etc.).

[0199] The modeling method of the embodiment of the present invention is not limited to the MOSFET structure, but is also applicable to other semiconductor device structures (such as SBD, BJT, IGBT, etc.).

[0200] The semiconductor device precise modeling related software involved in the embodiments of the present invention is not limited to Sentaurus TCAD simulation software, but can also be applied to other semiconductor device modeling and multi-physics field modeling simulation platforms such as Silvaco TCAD and COMSOL.

[0201] In summary, the embodiment of the present invention combines electrical characteristic testing and material characterization and analysis technology to complete the establishment of an accurate self-consistent device model of (ultra) wide bandgap semiconductor devices. Specifically, the basic materials and structures of the actual (ultra) wide bandgap semiconductor device model are obtained, and its ideal simulation model is constructed in the TCAD software; based on the electrical characteristic testing and material characterization and analysis technology, the typical defect model parameters of the actual (ultra) wide bandgap semiconductor device are obtained; the typical defect model parameters and related physical process models are added to the ideal simulation model, and a semiconductor device model including typical defect model parameters and their physical processes is constructed, and the model is fitted to the electrical characteristic test results of the actual (ultra) wide bandgap semiconductor device to be consistent, and the final constructed model is a model that reflects the real physical characteristics of the actual (ultra) wide bandgap semiconductor device. This provides an effective reference for device numerical simulation research, reliability mechanism research, and device optimization design.

[0202] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0203] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0204] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0205] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A semiconductor device physical modeling method combining material and device testing and analysis technology, characterized in that: include: According to the basic materials and structures of the semiconductor device to be physically modeled, an ideal simulation model of the semiconductor device is constructed in semiconductor process simulation and device simulation tool software; the semiconductor device includes: a wide bandgap semiconductor device or an ultra-wide bandgap semiconductor device; The typical defect model parameters of the semiconductor device are obtained by using electrical property testing and material characterization analysis technology. The typical defect model parameters include: interface state defect energy level E it , interface state defect density D it , oxide layer defect type Type, oxide layer defect energy level E bt , oxide layer defect density N bt , the step difference between the oxide layer and the semiconductor conduction band φ b , semiconductor material defect type Type, semiconductor material defect energy level E t And the semiconductor material defect density N t ; According to the ideal simulation model and the typical defect model parameters, a semiconductor device model including the typical defect model parameters is constructed, and a physical process model related to the semiconductor device and its typical defects is added to the semiconductor device model to obtain a semiconductor device model including the typical defect model parameters and related physical processes; wherein the physical process model includes: a carrier statistical distribution model, a drift diffusion model, a mobility model, and a composite generation model; A semiconductor device model including typical defect model parameters and related physical processes is fitted to the actual device electrical characteristics test results to obtain a model that reflects the real physical characteristics of the actual semiconductor device; the device electrical characteristics include: output characteristics, transfer characteristics, gate leakage current and drain leakage current.

2. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 1, characterized in that: Obtain the interface state defect energy level E in the typical defect model parameters it ways, including: Obtaining a first semiconductor device sample; the first semiconductor device sample comprises, from bottom to top, a first metal layer, a semiconductor material layer, an oxide layer, and a second metal layer; the materials of the first metal layer, the semiconductor material layer, the oxide layer, and the second metal layer are the same as those of the corresponding layers of the semiconductor device; The conductivity curve of the first semiconductor device sample from low frequency to high frequency is tested by the conductivity method, and the interface state defect energy level E is obtained according to the response frequency of the peak value in the conductivity curve. it ; A material interface model of the semiconductor material layer and the oxide layer is constructed in a material modeling software tool, and the interface state defect energy level E is calculated based on the first principles. it ; The interface state defect energy level E is calculated based on first principles. it The interface defect energy level E obtained by the conductivity method it Perform calibration verification.

3. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 1, characterized in that: Obtain the interface state defect density D in the typical defect model parameters it ways, including: Acquire a second semiconductor device sample; the second semiconductor device sample is the same device as the semiconductor device; Testing a transfer characteristic curve of the second semiconductor device sample; determining a subthreshold region according to the transfer characteristic curve; The interface state defect density D is calculated based on the subthreshold slope of the subthreshold region. it .

4. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 1, characterized in that: Obtain the oxide layer defect type Type and oxide layer defect energy level E in the typical defect model parameters bt and oxide layer defect density N bt ways, including: Obtain at least one third semiconductor material sample; the third semiconductor material sample comprises a semiconductor material layer and a single oxide layer from bottom to top; the semiconductor material layer is the same as the semiconductor layer of the semiconductor device, and the single oxide layer of the at least one third semiconductor material sample is the same as each oxide layer of the semiconductor device in one-to-one correspondence; By performing an X-ray photoelectron spectroscopy XPS test and a photoluminescence spectrum PL test on the at least one third semiconductor material sample, the oxide layer defect type Type and the oxide layer defect energy level E are obtained. bt and oxide layer defect density N bt .

5. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 4, characterized in that: The modeling method also includes: Before fitting the semiconductor device model including typical defect model parameters and related physical processes to the actual device electrical characteristic test results, the oxide layer band gap width E of the semiconductor device is obtained by using electrical characteristic test and material characterization analysis technology. go ; The oxide layer bandgap width E go Adding to the semiconductor device model including typical defect model parameters and related physical processes; Wherein, the bandgap width E of the oxide layer is obtained go ways, including: By testing the absorption spectrum of at least one third semiconductor material sample, the band gap width E of the oxide layer is obtained. go .

6. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 4, characterized in that: The modeling method also includes: When the oxide layer of the semiconductor device is a single-layer dielectric, a second semiconductor device sample is obtained; the second semiconductor device sample is the same device as the semiconductor device; the gate leakage physical mechanism thereof is determined by performing a gate leakage current test on the second semiconductor device sample; within a voltage range that conforms to the TAT gate leakage mechanism, the oxide layer defect energy level E is obtained by fitting and calculating according to the current and voltage data obtained by the test. bt , and obtain the current-voltage curve within the voltage range that conforms to the TAT gate leakage mechanism and the current-voltage curve within the voltage range that conforms to the FN gate leakage mechanism as the test basis for subsequent model fitting; the oxide layer defect energy level E obtained by fitting calculation bt The measured oxide layer defect energy level E bt Perform calibration verification; When the oxide layer of the semiconductor device is a laminated dielectric, at least one fourth semiconductor device sample is obtained; the fourth semiconductor device sample includes a first metal layer, a semiconductor material layer, a single oxide layer and a second metal layer from bottom to top; the materials of the first metal layer, the semiconductor material layer and the second metal layer are the same as the corresponding layers of the semiconductor device, and the single oxide layer of the at least one fourth semiconductor device sample is the same as the oxide layers of the semiconductor device in a one-to-one correspondence; the leakage current physical mechanism of the at least one fourth semiconductor device sample is determined by performing a leakage current test on the at least one fourth semiconductor device sample; within the voltage range that conforms to the TAT leakage mechanism, the oxide layer defect energy level E is obtained by fitting and calculating according to the current and voltage data obtained by the test. bt ; The oxide layer defect energy level E calculated by fitting bt The measured oxide layer defect energy level E bt Verify one by one; When the oxide layer of the semiconductor device is a laminated dielectric, a second semiconductor device sample is obtained; the second semiconductor device sample is the same device as the semiconductor device; the physical mechanism of gate leakage is determined by performing a gate leakage current test on the second semiconductor device sample; based on the current and voltage data obtained from the test, a current-voltage curve within a voltage range that conforms to the TAT gate leakage mechanism and a current-voltage curve within a voltage range that conforms to the FN gate leakage mechanism are obtained as a test basis for subsequent model fitting.

7. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 4, characterized in that: The modeling method also includes: Acquire at least one fourth semiconductor device sample; the fourth semiconductor device sample comprises, from bottom to top, a first metal layer, a semiconductor material layer, a single oxide layer, and a second metal layer; the materials of the first metal layer, the semiconductor material layer, and the second metal layer are the same as the corresponding layers of the semiconductor device, and the material of the single oxide layer of the at least one fourth semiconductor device sample is the same as the corresponding oxide layer of the semiconductor device; Testing a capacitance-voltage hysteresis characteristic curve of the at least one fourth semiconductor device sample to extract a change in a flat-band voltage; The oxide layer defect density N is calculated based on the change in the flat band voltage. bt , and use the calculated oxide layer defect density N bt The oxide layer defect density N bt Perform calibration verification.

8. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 1, characterized in that: Obtain the step difference φ between the oxide layer and the semiconductor conduction band in the typical defect model parameters b ways, including: Acquire a second semiconductor device sample; the second semiconductor device sample is the same device as the semiconductor device; Determining the physical mechanism of gate leakage by performing a gate leakage current test on the second semiconductor device sample; In the voltage range that conforms to the FN gate leakage mechanism, the step difference φ between the oxide layer and the semiconductor conduction band is obtained by fitting and calculating the current and voltage test data obtained by the test. b .

9. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 1, characterized in that: The modeling method also includes: Before fitting the semiconductor device model including typical defect model parameters and related physical processes to the actual device electrical characteristic test results, the semiconductor bandgap width E of the semiconductor device is obtained by using electrical characteristic test and material characterization analysis technology. gs ; The semiconductor bandgap width E gs Adding to the semiconductor device model including typical defect model parameters and related physical processes; Wherein, the semiconductor bandgap width E is obtained gs The methods include: Acquire a fifth semiconductor material sample; the fifth semiconductor material sample comprises a semiconductor material layer; the semiconductor material layer is the same as the semiconductor material layer of the semiconductor device; By testing the absorption spectrum of the fifth semiconductor material sample, the semiconductor bandgap width E is obtained. gs ; Obtain the semiconductor material defect type Type and semiconductor material defect energy level E in the typical defect model parameters. t and semiconductor material defect density N t The methods include: By performing an X-ray photoelectron spectroscopy XPS test and a photoluminescence spectrum PL test on the fifth semiconductor material sample, the semiconductor material defect type Type and the semiconductor material defect energy level E are obtained. t and semiconductor material defect density N t .

10. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 9, characterized in that: The modeling method also includes: Before fitting the semiconductor device model including typical defect model parameters and related physical processes to the actual device electrical characteristic test results, the carrier concentration N of the channel layer of the semiconductor device is obtained by using electrical characteristic test and material characterization analysis technology. d ; The carrier concentration N d Adding to the semiconductor device model including typical defect model parameters and related physical processes; Wherein, the carrier concentration N is obtained d ways, including: Obtaining a sixth semiconductor device sample; the sixth semiconductor device sample is obtained by preparing a group of ohmic contact electrodes with gradually increasing adjacent spacings on the surface of the fifth semiconductor material sample; Testing the resistance between adjacent ohmic contact electrodes in the sixth semiconductor device sample; Fitting the sheet resistance of the semiconductor material based on the resistance and spacing between adjacent ohmic contact electrodes; The carrier concentration N is calculated based on the sheet resistance d .

11. The semiconductor device physical modeling method combining material and device testing and analysis technology according to claim 1, characterized in that: The semiconductor device model including typical defect model parameters and related physical processes is fitted to the actual device electrical characteristic test results to obtain a model reflecting the real physical characteristics of the actual semiconductor device, including: Simulate the electrical characteristics of a semiconductor device model that includes typical defect model parameters and related physical processes; Fitting the device electrical characteristics output by simulation with the device electrical characteristics of actual test; If there is a deviation between the simulation results and the actual electrical characteristics test results, adjust the parameters of the non-intrinsic and non-test analysis used in the simulation, perform the simulation again, and compare the electrical characteristics of the device with those of the actual test. Repeat this operation until the device electrical characteristics of the simulation output are consistent with the electrical characteristics of the device actually tested, and finally build a model that reflects the true physical characteristics of the actual semiconductor device.

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