Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises: a substrate; at least one pixel circuit located on one side of the substrate and configured to generate a light-emitting signal by using a driving transistor of the pixel circuit to perform light-emitting control; and at least one shielding unit located between the substrate and the pixel circuit, arranged opposite to the at least one pixel circuit, and configured to be controlled by a reset signal of the at least one pixel circuit to form a voltage difference between the at least one shielding unit and the driving transistor.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of OLED (Organic Light-Emitting Diode) display technology, the market has increasingly higher requirements for display image quality.

[0003] However, based on the current design of pixel circuits in display panels, the driving transistors may be subject to electronic interference, resulting in image retention issues that affect product image quality and yield. Summary of the Invention

[0004] In view of this, this application proposes a display panel and display device to solve or partially solve the above-mentioned problems.

[0005] In view of the above objectives, firstly, this application provides a display panel, comprising:

[0006] Substrate;

[0007] At least one pixel circuit, located on one side of the substrate, is configured to generate a light-emitting signal using a driving transistor of the pixel circuit for light-emitting control.

[0008] At least one shielding unit is located between the substrate and the pixel circuit, and is disposed opposite to the at least one pixel circuit. It is configured to be controlled by a reset signal of the at least one pixel circuit to create a voltage difference between the at least one shielding unit and the driving transistor.

[0009] In some exemplary embodiments, the reset signal includes: a source reset signal;

[0010] The at least one shielding unit is configured to receive the source reset signal.

[0011] In some exemplary embodiments, the at least one pixel circuit is arranged in an array, and the at least one shielding unit is arranged in an array corresponding to the at least one pixel circuit; at least one row or at least one column of shielding units is configured to receive the reset signal in series.

[0012] In some exemplary embodiments, the at least one shielding unit and the driving transistor in the at least one pixel circuit have at least partial orthogonal projections onto the substrate.

[0013] In some exemplary embodiments, the reset signal is generated by a reset signal control circuit;

[0014] Each pixel circuit and its opposite shielding unit are connected to the reset signal control circuit connected to the pixel circuit.

[0015] In some exemplary embodiments, the reset signal is generated by a reset signal control circuit; the reset signal control circuit includes: a first reset signal control circuit and a second reset signal control circuit;

[0016] The at least one pixel circuit is connected to the first reset signal control circuit;

[0017] The at least one shielding unit is connected to the second reset signal control circuit.

[0018] In some exemplary embodiments, the reset signal is generated by a reset signal control circuit; the reset signal control circuit includes a first output terminal and a second output terminal.

[0019] The at least one pixel circuit is connected to the first output terminal;

[0020] The at least one shielding unit is connected to the second output terminal.

[0021] In some exemplary embodiments, the first output terminal and the second output terminal are configured to be formed by at least one pair of common-gate output transistors.

[0022] In some exemplary embodiments, it includes: a display area and a non-display area surrounding the display area;

[0023] The reset signal control circuit is located in the non-display area on at least one side of the display area.

[0024] In some exemplary embodiments, the reset signal control circuit is located in the non-display areas on opposite sides of the display area.

[0025] Based on the same concept, in a second aspect, this application also provides a display device, including the display panel as described in the first aspect above.

[0026] As can be seen from the above description, this application provides a display panel and a display device. The display panel includes: a substrate; at least one pixel circuit located on one side of the substrate, configured to generate a light-emitting signal using a driving transistor of the pixel circuit for light emission control; and at least one shielding unit located between the substrate and the pixel circuit, disposed opposite to the at least one pixel circuit, configured to be controlled by a reset signal of the at least one pixel circuit to form a voltage difference between the at least one shielding unit and the driving transistor. This application achieves electronic shielding by setting a shielding unit between the substrate and the pixel circuit. The shielding unit is correspondingly disposed to the pixel circuit and can itself be a conductive structure, thereby stabilizing the pixel circuit through the shielding unit and improving the image retention problem. Subsequently, the reset signal is used as the control signal for the shielding unit, enabling the shielding unit to form a certain voltage difference with the driving transistor during the reset process of the pixel circuit. This voltage difference further increases the speed at which different brightness gray levels reach the set brightness gray level during the recovery process, further reducing the hysteresis of image retention, improving the image retention recovery effect, and ultimately improving the product image quality and product yield. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a partial hierarchical structure of an exemplary display panel provided in an embodiment of this application.

[0029] Figure 2 This is a schematic diagram of the arrangement structure of a shielding unit provided in an embodiment of this application.

[0030] Figure 3 A schematic diagram illustrating the hysteresis principle analysis of the driving transistor provided in the embodiments of this application.

[0031] Figure 4 This is a schematic diagram of the equivalent circuit structure of the pixel circuit provided in the embodiments of this application.

[0032] Figure 5 This is a timing diagram of some signals of an exemplary display panel provided in an embodiment of this application.

[0033] Figure 6 This is a schematic diagram of another shielding unit arrangement structure provided in an embodiment of this application.

[0034] Figure 7This is a schematic diagram of the equivalent circuit structure of a reset signal control circuit GOA provided in an embodiment of this application.

[0035] Figure 8 A schematic diagram of the equivalent circuit structure of another reset signal control circuit GOA provided in an embodiment of this application.

[0036] Figure 9 This is a schematic diagram illustrating the connection effect of the reset signal control circuit GOA provided in the embodiments of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this specification clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0038] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element, object, or method step preceding the term covers the element, object, or method step listed after the term and its equivalents, without excluding other elements, objects, or method steps. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0039] As described in the background section, thin-film transistors (TFTs) are currently the mainstream product in displays. OLEDs can be controlled through pixel circuits formed by TFTs to achieve image output. However, image retention issues may occur during product use. Analysis has revealed that the causes of image retention in OLED displays may include differences in the reliability of organic light-emitting materials, the stability of the TFT, and the influence of the substrate on the TFT.

[0040] It's important to note that the specific process of image retention is as follows: After one frame is output, the pixel circuitry or OLED needs to return to its initial state before outputting the next frame. This return process may be referred to as a reset or resetting stage in different scenarios. If the return process is not completed correctly, the OLED will still have signal input, resulting in a macroscopic remnant of the previous frame, thus causing image retention. It can be seen that the main stage in the occurrence of image retention is the return or resetting stage of the pixel circuitry or OLED.

[0041] Therefore, it can be seen that the image retention is mainly caused by the failure of the corresponding transistors in the pixel circuit, which serves as the control terminal, to quickly recover their state. This results in residual electrons or charges, preventing the OLED from quickly returning to its initial state. Furthermore, in some embodiments, the impact of image retention can be mitigated by setting an isolation structure. A shielding unit can be placed between the substrate and the pixel circuit. A constant voltage can then be applied to the shielding unit, or a constant voltage can be applied during the reset or resetting phase. This allows the pixel circuit, especially the driving transistor DTFT, to achieve electronic shielding through the shielding unit. This stabilizes the DTFT characteristics during the reset phase, thereby controlling image retention and improving the image retention problem to some extent.

[0042] In some embodiments, such as Figure 1 As shown, the pixel circuit 120 of the display panel 100 is disposed on one side of the substrate 110, while the shielding unit 130 can be disposed between the two. Of course, in some specific scenarios, an insulating layer and a buffer layer can be disposed between the shielding unit 130 and the pixel circuit 120 to achieve a certain degree of insulation and buffering. In more specific scenarios... Figure 1 The diagram mainly shows the driving transistor (DTFT, or T1) in the pixel circuit 120. Then, a fixed voltage is applied to the shielding unit 130 to electronically shield the pixel circuit 120, particularly the driving transistor T1, during the reset process, thereby stabilizing the characteristics of the driving transistor T1. Finally, to power the shielding unit 130, as... Figure 2 As shown, it can generally be designed as a mesh structure, where the horizontal direction can be positive and the vertical direction can be negative, etc.

[0043] Subsequently, during the implementation of the aforementioned embodiments, the applicant discovered that although the above method could solve the image retention problem to a certain extent, the improvement effect on the image retention problem was not ideal in some scenarios. Through research, the applicant found that, as... Figure 3 As shown, combined with the attached Figure 3(a) Due to the hysteresis characteristic of TFTs, the initial brightness when switching from a white screen L255 to the reference grayscale L48 is inconsistent with that when switching from a black screen L0 to the reference grayscale L48. This, combined with the attached... Figure 3 (b) The greater the deviation between the white image L255 and the black image L0 and the threshold voltage (Vth) of the driving transistor T1, the longer the brightness recovery time to the reference grayscale L48. This difference ultimately leads to an unsatisfactory improvement in image retention.

[0044] Therefore, in light of the above-mentioned practical situation, this application provides another display panel. This display panel achieves electronic shielding by setting a shielding unit between the substrate and the pixel circuit. The shielding unit is correspondingly arranged with the pixel circuit and can itself be a conductive structure. This allows the shielding unit to stabilize the pixel circuit and improve the image retention problem. Subsequently, a reset signal is used as the control signal for the shielding unit, enabling the shielding unit to form a certain voltage difference with the driving transistor during the pixel circuit reset process. This voltage difference further increases the speed at which different brightness gray levels reach the set brightness gray level during the recovery process, further reducing image retention hysteresis, improving image retention recovery effect, and ultimately improving product image quality and product yield.

[0045] Figure 4 This diagram illustrates the equivalent circuit structure of a pixel circuit in an exemplary display panel according to an embodiment of this application. The vertical line on one side of the driving transistor T1 represents the shielding unit 130.

[0046] Combination Figure 1 and Figure 4 As shown, a display panel 100 according to an embodiment of this application includes: a substrate 110; at least one pixel circuit 120 located on one side of the substrate 110, configured to generate a light-emitting signal using a driving transistor T1 of the pixel circuit 110 for light-emitting control; and at least one shielding unit 130 located between the substrate 110 and the pixel circuit 120, disposed opposite to the at least one pixel circuit 120, configured to be controlled by a reset signal reset of the at least one pixel circuit 120 to form a voltage difference between the at least one shielding unit 130 and the driving transistor T1.

[0047] In this embodiment, the substrate 110 can be used to support other components in the display panel 100; the pixel circuit 120 can be used to generate corresponding light-emitting signals to control the light-emitting transistors; the shielding unit 130 can be used to provide corresponding electronic shielding during the reset process of the pixel circuit 120, so as to stabilize the characteristics of the pixel circuit 120, especially the driving transistor T1 therein.

[0048] After that, as Figure 4The diagram shown is an exemplary 8T1C pixel circuit. Of course, in different application scenarios, the pixel circuit can also be other types of control circuits, such as 2T1C, 3T1C, 4T1C, 7T1C, 10T1C, etc. In the exemplary 8T1C pixel circuit, the driving transistor T1 is mainly used to generate the light-emitting signal for driving; the T2 transistor is mainly used to receive the control Data signal for data writing, controlled by the first scan signal P_gate; the T3 transistor is a compensation transistor, controlled by the second scan signal N_gate; the T4 and T5 transistors are two light-emitting control transistors, controlled by the light-emitting control signal EM. The source of the T4 transistor can be connected to the first power supply signal VDD (generally a high-level signal), and the drain of the T5 transistor can be connected to the light-emitting pixel and the first power supply signal VDD. SS (generally a low-level signal); T6, T7, and T8 transistors are three reset transistors, controlled by two reset signals Reset1 and Reset2 respectively. T6 transistor can be used to reset the gate of driving transistor T1, and T7 reset transistor can be used to reset the anode of the light-emitting pixel. Therefore, the inputs Vinit1 and Vinit2 of transistors T6 and T7 are generally low voltage or negative voltage. T8 transistor can be used to reset the source of driving transistor T1. Therefore, the input Vinit3 of transistor T8 is generally high voltage or positive voltage.

[0049] It should be noted that in the transistor structures appearing in this embodiment and subsequent embodiments, the control electrode generally corresponds to the gate (G) of the transistor, while the first and second electrodes correspond to the source (S) and drain (D) of the transistor. Furthermore, the transistors used in the embodiments of this application can all be thin-film transistors, field-effect transistors, or other devices with similar characteristics; thin-film transistors can be oxide semiconductor transistors. Based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of a switching transistor are symmetrical, they are interchangeable. Therefore, in this scheme, one of the source and drain is called the first electrode, the other is called the second electrode, and the gate is called the control electrode.

[0050] Subsequently, the shielding unit 130, indicated by the vertical line on one side of the driving transistor T1, can be connected to either Reset1 or Reset2. Thus, during the reset process of the pixel circuit 120, the shielding unit 130 can form a certain voltage difference with the pixel circuit 120. Specifically, as shown in the attached diagram... Figure 3Taking the connection between the shielding unit 130 and Reset2 as an example, after the driving transistor T1 is fully charged, Reset2 outputs VGL (a level signal, generally low or negative) to write Vinit3 (positive voltage) to the source (S) of the driving transistor T1, and VGL (negative voltage) to the shielding unit 130 corresponding to the driving transistor T1, thereby forming a gate-source voltage difference (Vgs). Combined with... Figure 3 As shown, when the shielding unit 130 is connected to the reset signal Reset, an additional bias voltage is added to shift L255 and L0 to the same negative bias position, thereby improving the afterimage effect.

[0051] Furthermore, the applicant discovered that a stronger electric field and a larger current during the bias phase result in less hysteresis and a better effect on improving image retention. As mentioned above, if the shielding unit 130 is connected to the reset signal Reset1, combined with... Figure 5 The partial signal timing diagram shown indicates that when the Reset1 signal is active, the driving transistor T1 receives the gate input Vinit1 signal. Both are negative voltage signals, and the electric field between them may be small, resulting in a potentially insignificant effect. Therefore, the shielding unit 130 can be connected to the reset signal Reset2, i.e., it can be connected to the source reset signal Reset2. In some embodiments, the reset signal includes the source reset signal Reset2; the at least one shielding unit 130 is configured to receive the source reset signal Reset2.

[0052] In some embodiments, the pixel circuits 120 can be arranged in an array, and consequently, the corresponding shielding units 130 can also be arranged in an array. Furthermore, as can be seen from the foregoing embodiments, the shielding unit 130 only needs to receive a reset signal, and therefore, as... Figure 6 As shown, it can be connected in series in each row or column direction to receive signals row by row or column by column, thereby realizing signal scanning row by row or column by column. That is, in some embodiments, the at least one pixel circuit 120 is arranged in an array, and the at least one shielding unit 130 is arranged in an array corresponding to the at least one pixel circuit 120; at least one row or at least one column of shielding units 130 is configured to receive the reset signal in series.

[0053] In some embodiments, the shielding unit 130 can correspond entirely to the pixel circuit 120, meaning one shielding unit 130 can cover one pixel circuit 120. Furthermore, as described above, the shielding unit 130 primarily targets the driving transistor T1 in the pixel circuit 120. Therefore, in other embodiments, each shielding unit 130 can correspond only to the driving transistor T1 in the pixel circuit 120. That is, the projected area of ​​the shielding unit 130 on the pixel circuit 120 can only cover the driving transistor T1 in the pixel circuit 120. This arrangement saves material costs without affecting the performance. Of course, the degree of coverage can vary in different specific scenarios. In some embodiments, the shielding unit 130 can completely cover the driving transistor T1; in other embodiments, the shielding unit 130 may only cover a portion of the driving transistor T1, etc. That is, in some embodiments, the orthogonal projections of the at least one shielding unit 130 and the at least one driving transistor T1 in the pixel circuit 120 on the substrate at least partially overlap.

[0054] In some embodiments, the reset signal Reset can be generated by the reset signal control circuit GOA. For example... Figure 7 The diagram shows a 10T3C reset signal control circuit GOA, comprising 10 transistors T9 to T18 and 3 storage capacitors C2 to C4. It receives clock signal line CK, inverted clock signal line CB, level signal lines VGL and VGH (VGL is typically low and VGH is typically high), and frame start signal line STV to ultimately generate a corresponding reset signal Reset, which is output from the OUT terminal. Furthermore, any pixel circuit 120 and its corresponding shielding unit 130 can be connected to the reset signal control circuit GOA in parallel. Taking Reset2 as an example, the OUT terminal of the reset signal control circuit GOA is connected to the gate of transistor T8 and simultaneously connected to the corresponding shielding unit 130. In some embodiments, the reset signal is generated by the reset signal control circuit GOA; any pixel circuit 120 and its opposite shielding unit 130 are both connected to the reset signal control circuit GOA connected to the pixel circuit 120.

[0055] In other embodiments, the reset signal control circuit GOA can be configured as multiple sets, so that one set is used to control the pixel circuit 120, while another set is used to control the shielding unit 130. In this way, the level signal lines VGL and VGH in the reset signal control circuit GOA controlling the shielding unit 130 can be fine-tuned, thereby adjusting the voltage of the shielding unit 130 during the bias and display phases by adjusting the voltages of VGH and VGL. That is, in some embodiments, the reset signal is generated by the reset signal control circuit GOA; the reset signal control circuit GOA includes: a first reset signal control circuit and a second reset signal control circuit; the at least one pixel circuit 120 is connected to the first reset signal control circuit; the at least one shielding unit 130 is connected to the second reset signal control circuit. The first reset signal control circuit and the second reset signal control circuit can be two sets of reset signal control circuits, and the signals of these two sets of reset signal control circuits can be completely identical, differing only in the structure of their output connections: one connected to the pixel circuit 120, and the other connected to the shielding unit 130.

[0056] In other embodiments, in addition to multiple sets of reset signal control circuits GOA, multiple output terminals OUT can also be configured, such as... Figure 8As shown, taking the original reset signal control circuit GOA as an example of a 10T3C circuit, since the 10T3C circuit has two output transistors acting on the output terminal OUT, namely transistors T17 and T18, a common-gate transistor can be set for each, namely transistors T19 and T20. T17 and T19 are a pair of common-gate transistors, and T18 and T20 are another pair. Thus, transistors T17 and T18 jointly control output terminal OUT1, and transistors T19 and T20 jointly control output terminal OUT2. In the same way, output terminal OUT2 connected to the shielding unit 130 can also be controlled. Specifically, the voltage of the shielding unit 130 during the bias and display phases can be adjusted by regulating the voltages VGH* and VGL*, which also minimizes the space required for the reset signal control circuit GOA. Of course, since the output terminal of the illustrated 10T3C circuit is controlled by two output transistors, it also forms two pairs of common-gate transistors. If the reset signal control circuit GOA is another type of circuit, its output transistors may be one or more, and thus the number of common-gate transistors will also vary, as will the number of common-gate transistor pairs. That is, in some embodiments, the reset signal is generated by a reset signal control circuit; the reset signal control circuit GOA includes a first output terminal OUT1 and a second output terminal OUT2; the at least one pixel circuit 120 is connected to the first output terminal OUT1; and the at least one shielding unit 130 is connected to the second output terminal OUT2. In some embodiments, the first output terminal and the second output terminal are configured to be formed by at least one pair of common-gate output transistors.

[0057] In some embodiments, combined with Figure 6 and Figure 9 As shown, a display panel typically includes a display area 140 and a non-display area 150, with the non-display area 150 surrounding the display area. Furthermore, a reset signal control circuit GOA can be located in the non-display area 150 on one side of the display area 140; for example, the reset signal control circuit GOA can be located in the non-display area 150 to the left or right of the display area 140. This saves space on the frame of the reset signal control circuit GOA and the display panel 100. That is, in some embodiments, the display panel 100 includes: a display area 140 and a non-display area 150 surrounding the display area 140; the reset signal control circuit GOA is located within the non-display area 150 on at least one side of the display area 140.

[0058] Furthermore, such as Figure 6 and Figure 9As shown, to provide better signal performance, the reset signal control circuit GOA can provide signals from both sides. For example, the reset signal control circuit GOA can be located in the non-display areas 150 on the left and right sides opposite to the display area 140. That is, in some embodiments, the reset signal control circuit GOA is located in the non-display areas 150 on both sides opposite to the display area 140.

[0059] Finally, it should be noted that transistors can be classified into N-type and P-type based on their characteristics. A P-type transistor conducts when the gate is low and is cut off when the gate is high; an N-type transistor conducts when the gate is high and is cut off when the gate is low. For example... Figure 4 and Figure 7 As shown, in this embodiment, P-type transistors are mostly used as examples, with only transistor T3 being an N-type transistor. This is merely a preferred embodiment for ease of implementation and does not limit the technical solution of this invention. Those skilled in the art should understand that simply changing the type of each transistor (N-type or P-type) and the polarity of the output voltage of each power supply terminal and control signal line to achieve the same conduction or cutoff operation as in this embodiment is also within the scope of protection of this application. Specific examples are not provided here.

[0060] As can be seen from the above, this application provides a display panel comprising: a substrate; at least one pixel circuit located on one side of the substrate, configured to generate a light-emitting signal using a driving transistor of the pixel circuit for light emission control; and at least one shielding unit located between the substrate and the pixel circuit, corresponding to the at least one pixel circuit, configured to be controlled by a reset signal of the at least one pixel circuit to form a voltage difference between the at least one shielding unit and the driving transistor. This application achieves electronic shielding by setting a shielding unit between the substrate and the pixel circuit. The shielding unit is correspondingly positioned to the pixel circuit and can itself be a conductive structure, thereby stabilizing the pixel circuit and improving image retention. Subsequently, the reset signal is used as the control signal for the shielding unit, enabling the shielding unit to form a certain voltage difference with the driving transistor during the pixel circuit's reset process. This voltage difference further increases the speed at which different brightness gray levels reach a set brightness gray level during the recovery process, further reducing image retention hysteresis, improving image retention recovery effect, and ultimately improving product image quality and yield.

[0061] Based on the same concept, this application also provides a display device, including a display panel as described in any of the foregoing embodiments.

[0062] The display device described above is used to apply the corresponding display panel in the foregoing embodiments and has the beneficial effects of the corresponding display panel embodiments, which will not be repeated here.

[0063] It is understandable that the display device is a product with image display function, and it is generally driven by multiple driving circuits. For example, it can be: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large wall area, home appliance, information query equipment (such as business query equipment of e-government, bank, hospital, power and other departments, monitor, etc.).

[0064] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0065] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0066] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0067] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; at least one pixel circuit located on one side of the substrate and configured to generate a light-emitting signal by using a driving transistor of the pixel circuit to perform light-emitting control; at least one shielding unit located between the substrate and the pixel circuit and arranged opposite to the at least one pixel circuit, and configured to be controlled by a reset signal of the at least one pixel circuit to form a voltage difference between the at least one shielding unit and the driving transistor; the reset signal is generated by a reset signal control circuit; any pixel circuit and the shielding unit arranged opposite to the pixel circuit are connected to the reset signal control circuit connected to the any pixel circuit, and the reset signal control circuit is configured to adjust the voltage of the at least one shielding unit in a bias stage and a display stage by using a control level signal.

2. The display panel of claim 1, wherein, The reset signal comprises a source reset signal. The at least one shielding unit is configured to receive the source reset signal.

3. The display panel of claim 1, wherein, The at least one pixel circuit is arranged in an array, and the at least one shielding unit is arranged in an array corresponding to the at least one pixel circuit; at least one row or at least one column of shielding units is configured to receive the reset signal in a series mode.

4. The display panel of claim 1, wherein, The at least one shielding unit and the driving transistor in the at least one pixel circuit at least partially overlap in orthographic projection on the substrate.

5. The display panel of claim 1, wherein, The reset signal control circuit comprises a first reset signal control circuit and a second reset signal control circuit. The at least one pixel circuit is connected to the first reset signal control circuit. The at least one shielding unit is connected to the second reset signal control circuit.

6. The display panel of claim 1, wherein, The reset signal control circuit comprises a first output end and a second output end. The at least one pixel circuit is connected to the first output end. The at least one shielding unit is connected to the second output end.

7. The display panel of claim 6, wherein, The first output end and the second output end are configured to be formed by at least one pair of output transistors sharing a gate. 8.The display panel of any one of claims 5-6, wherein, The display panel comprises: a display area and a non-display area surrounding the display area; The reset signal control circuit is arranged in the non-display area on at least one side of the display area.

9. The display panel of claim 8, wherein, The reset signal control circuit is arranged in the non-display area on opposite sides of the display area.

10. A display device, characterized by comprising: The display panel comprises: The display panel according to any one of claims 1 to 9.

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