Control circuit of resistive memory array and resistive memory

Abstract

The present application relates to a control circuit of a resistive memory array and a resistive memory, wherein the control circuit comprises a gating module, a controller and a readout circuit; the gating module comprises a logic control circuit and a multi-stage transmission gate circuit connected to each other, wherein the logic control circuit sends a corresponding secondary switch signal pair to the multi-stage transmission gate circuit based on a plurality of read-write control signals and an address signal output by the controller, and controls a target memory cell corresponding to the address signal to be connected or disconnected with the readout circuit; the multi-stage transmission gate circuit applies a corresponding input voltage to the target memory cell based on the secondary switch signal pair and a plurality of read-write control signals, wherein the input voltage is determined from a plurality of preset voltages received by the multi-stage transmission gate circuit; and the readout circuit reads a current value output by the target memory cell when connected to the target memory cell, thereby solving the problem of a large area occupied by the peripheral circuit.

Description

Technical Field

[0001] The present application relates to the field of microelectronic technology, and in particular to a control circuit of a resistive memory array and a resistive memory. Background Art

[0002] As a new type of storage and computing device, Resistive Random Access Memory (RRAM) has the advantages of low power consumption, high speed, and compatibility with complementary metal oxide semiconductor (CMOS) processes. Its resistance value can be programmed by voltage, and its resistance value is still preserved for a long time after the excitation voltage is removed, which has the characteristics of non-volatility. RRAM also has the advantages of small size and high integration density, which has significant advantages over other new storage and computing devices. The peripheral circuit of resistive random access memory is relatively complex. For a 1T1R type storage array, it is necessary to control the reading and writing of each storage cell in the storage array through word lines, bit lines and source lines respectively. As the scale of the storage array expands, its peripheral circuit occupies a larger area, which reduces the storage density per unit area.

[0003] With regard to the problem in the prior art that the peripheral circuit occupies a large area, no effective solution has been proposed yet. Summary of the invention

[0004] In this embodiment, a control circuit of a resistive memory array and a resistive memory are provided to solve the problem of a large area occupied by peripheral circuits in the related art.

[0005] In a first aspect, a control circuit of a resistive memory array is provided in this embodiment, wherein the control circuit comprises a gating module connected to the resistive memory array, and a controller and a readout circuit connected to the gating module; the resistive memory array comprises a plurality of memory cells, the gating module comprises a logic control circuit and a multi-stage transmission gate circuit connected to each other, The logic control circuit sends a corresponding pair of secondary switch signals to the multi-stage transmission gate circuit based on a plurality of read / write control signals and address signals output by the controller, and controls the target storage unit corresponding to the address signal to be connected or disconnected from the readout circuit; The multi-stage transmission gate circuit applies a corresponding input voltage to the target memory cell based on the secondary switch signal pair and the plurality of read / write control signals, wherein the input voltage is determined from a plurality of preset voltages received by the multi-stage transmission gate circuit; The read circuit reads a current value outputted from the target memory cell when connected to the target memory cell.

[0006] In some embodiments, the multi-stage transmission gate circuit includes a word line primary transmission gate circuit and a word line secondary transmission gate circuit, the multiple read and write control signals include a read control signal and a write control signal, the word line primary transmission gate circuit includes a first transmission gate and a second transmission gate, The word line primary transmission gate circuit generates a primary switch signal pair of the first transmission gate based on the write control signal to control a preset word line write voltage signal to connect or disconnect with the word line secondary transmission gate circuit; and The word line primary transmission gate circuit generates a primary switch signal pair of the second transmission gate based on the read control signal to control a preset word line read voltage signal to be connected or disconnected with the word line secondary transmission gate circuit.

[0007] In some embodiments, the logic control circuit includes a word line logic control circuit, the plurality of read and write control signals include an enable signal, When the enable signal is at a low level, the word line secondary transmission gate circuit disconnects the word line terminal of the target memory cell based on the secondary switch signal pair; the word line logic control circuit controls the word line terminal of the target memory cell to be grounded based on the secondary switch signal pair; In the case that both the enable signal and the address signal are at a high level, the word line secondary transmission gate circuit restores the connection with the word line terminal of the target memory cell based on the secondary switch signal pair.

[0008] In some embodiments, the multi-stage transmission gate circuit includes a bit line primary transmission gate circuit and a bit line secondary transmission gate circuit, the multiple read and write control signals include a set control signal and a reset control signal, the bit line primary transmission gate circuit includes a fourth transmission gate and a fifth transmission gate, The bit line primary transmission gate circuit generates a primary switch signal pair of the fourth transmission gate based on the setting control signal to control the connection or disconnection of a preset bit line setting voltage signal with the bit line secondary transmission gate circuit; and The bit line primary transmission gate circuit generates a primary switch signal pair of the fifth transmission gate based on the reset control signal to control the bit line secondary transmission gate circuit to be grounded or disconnected.

[0009] In some embodiments, the logic control circuit includes a bit line logic control circuit, the plurality of read and write control signals include an enable signal and a read control signal, The bit line logic control circuit controls a preset bit line read voltage signal to be connected or disconnected with a bit line terminal of the target memory cell based on the read control signal, the enable signal and the address signal; The bit line logic control circuit generates the secondary switch signal pair based on the enable signal and the address signal.

[0010] In some embodiments, the multi-stage transmission gate circuit includes a source line primary transmission gate circuit and a source line secondary transmission gate circuit, the multiple read and write control signals include a set control signal and a reset control signal, the source line primary transmission gate circuit includes a seventh transmission gate and an eighth transmission gate, The source line primary transmission gate circuit generates a primary switch signal pair of the seventh transmission gate based on the set control signal to control the source line secondary transmission gate circuit to be grounded or disconnected; and The source line primary transmission gate circuit generates a primary switch signal pair of the eighth transmission gate based on the reset control signal to control the connection or disconnection of a preset source line reset voltage signal with the source line secondary transmission gate circuit.

[0011] In some embodiments, the logic control circuit includes a source line logic control circuit, the plurality of read and write control signals include an enable signal, a read control signal, a set signal, and a reset signal, The source line logic control circuit controls the readout circuit to connect or disconnect with the source line terminal of the target memory cell based on the read control signal, the enable signal and the address signal; The source line logic control circuit generates the secondary switch signal pair based on the set signal, the reset signal, the enable signal and the address signal.

[0012] In some embodiments, the control circuit further includes a digital-to-analog conversion circuit. The digital-to-analog conversion circuit is used to convert the voltage value output by the controller into a corresponding word line write voltage signal, and output it to the multi-stage transmission gate circuit.

[0013] In some embodiments, the readout circuit includes a current-to-voltage conversion circuit and an analog-to-digital conversion circuit. The current-to-voltage circuit converts the current value output by the target storage unit into a corresponding voltage signal, and the analog-to-digital conversion circuit converts the voltage signal into a voltage value and sends it to the controller.

[0014] In a second aspect, a resistive memory is provided in this embodiment. The resistive memory includes a resistive memory array and a control circuit of the resistive memory array as described in the first aspect.

[0015] Compared with the related art, the control circuit of the resistive memory array provided in the present embodiment sends a corresponding secondary switch signal pair to a multi-stage transmission gate circuit based on a plurality of read-write control signals and address signals output by a controller through a logic control circuit, applies a corresponding input voltage to a target memory cell based on the secondary switch signal pair and the plurality of read-write control signals through the multi-stage transmission gate circuit, and implements a read-write operation corresponding to the input voltage; controls the corresponding target memory cell to be connected or disconnected with a read-out circuit based on a plurality of read-write control signals and address signals through a logic control circuit, and reads a current value output by the target memory cell when the read-out circuit is connected to the target memory cell, and implements a read operation by reading the current value of the target memory cell through the read-out circuit, and obtains a data read result through the current value; the control circuit implements the gating of word lines, bit lines and source lines and the corresponding voltage input and current reading through a gating module, reduces the occupied area of ​​the peripheral circuit, and solves the problem of a large occupied area of ​​the peripheral circuit.

[0016] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 is a schematic diagram of a control circuit of a resistive memory array according to some embodiments of the present application; Figure 2 is a connection diagram of a resistive memory array in some embodiments of the present application; Figure 3 is a connection diagram of a word line multi-stage transmission gate circuit in some embodiments of the present application; Figure 4 is a connection diagram of a word line multi-stage transmission gate circuit and a word line logic control circuit in some embodiments of the present application; Figure 5 is a connection diagram of a bit line multi-stage transmission gate circuit in some embodiments of the present application; Figure 6 is a schematic diagram of the connection between a bit line multi-stage transmission gate circuit and a bit line logic control circuit in some embodiments of the present application; Figure 7 is a connection diagram of a source line multi-stage transmission gate circuit of some embodiments of the present application; Figure 8 is a schematic diagram of the connection between a source line multi-stage transmission gate circuit and a source line logic control circuit in some embodiments of the present application; Fig. 9is a circuit connection diagram of a digital-to-analog conversion circuit in some embodiments of the present application; Fig.10 It is a connection diagram of the readout circuit of some embodiments of the present application. DETAILED DESCRIPTION

[0018] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0020] Figure 1 1 is a schematic diagram of the structure of the control circuit of the resistive memory array in some embodiments of the present application. Figure 1 As shown, the control circuit of the resistive memory array includes a gating module 20 connected to the resistive memory array 40, and a controller 10 and a readout circuit 30 connected to the gating module 20; the resistive memory array 40 includes a plurality of memory cells, and the gating module 20 includes a logic control circuit 22 and a multi-stage transmission gate circuit 24 connected to each other. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the control circuit of the resistive memory array. Figure 1More or fewer components as shown, or with Figure 1 Different configurations shown.

[0021] The logic control circuit 22 sends a corresponding secondary switch signal pair to the multi-stage transmission gate circuit 24 based on the multiple read / write control signals and the address signal output by the controller 10, and controls the target storage unit 401 corresponding to the address signal to be connected or disconnected from the readout circuit 30. The multi-stage transmission gate circuit 24 applies a corresponding input voltage to the target storage unit 401 based on the secondary switch signal pair and the multiple read / write control signals, and the input voltage is determined from the multiple preset voltages received by the multi-stage transmission gate circuit 24; the readout circuit 30 reads the current value output by the target storage unit 401 when connected to the target storage unit 401.

[0022] The resistive memory array in this embodiment may be a single transistor single resistor (1T1R) array. Figure 2 Schematic diagram of the connection of the resistive memory array in some embodiments of the present application. Figure 2 As shown, the 1T1R array includes a total of (m+1)×(n+1) memory cells, each of which includes a transistor and a resistor. The transistor can isolate the selected memory cell from other unselected memory cells. The word line WL[0:m] is connected to the gate of the transistor, and adjusting the voltage of WL[0:m] can control the limit current transmitted to the memory cell. The drain of the transistor is connected to the bit line BL[0:n] through the resistor, and the source of the transistor is connected to the source line SL[0:n]. Operations on the 1T1R array generally include write operations and read operations, wherein the write operation includes set Set and reset Reset. Set is to set "1", and reset is to set "0".

[0023] In some embodiments, when a set operation is performed, the corresponding row is selected through the word line WL[0:m] to turn on the corresponding transistor, and the corresponding set voltage is applied to the bit line BL[0:n] of the corresponding column while SL[0:n] is grounded; when a reset operation is performed, the corresponding row is selected through the word line WL[0:m] to turn on the corresponding transistor, the bit line BL[0:n] of the corresponding column is grounded, and the corresponding reset voltage is applied to the SL[0:n] of the corresponding column. For unselected rows and columns, the corresponding WL, BL, and SL can all be grounded. The WL voltages corresponding to the reset and set operations can be the same. When a read operation is performed, the corresponding row is selected through the word line WL[0:m] to turn on the corresponding transistor, and the corresponding read voltage is applied to the BL[0:n] of the corresponding column, while the SL[0:n] of the corresponding column is grounded, and the current value is read by connecting the readout circuit to the SL[0:n] of the corresponding column, which may correspond to a high impedance state or a low impedance state.

[0024] The read / write control signal in this embodiment may include an enable signal, a read control signal when performing a read operation, and a write control signal, a set control signal, and a reset control signal when performing a write operation. The address signal may include a row address signal and a column address signal. Specifically, the read / write control signal and the address signal may be set to be high level valid. The secondary switch signal pair is a pair of control signals, one of which is high level and the other is low level.

[0025] When performing a read operation or a write operation, the controller 10 sends corresponding read / write control signals and address signals to the logic control circuit 22 and the multi-stage transmission gate circuit 24. The logic control circuit 22 determines the target storage unit 401 according to the read / write control signal and the address signal, and outputs the corresponding secondary switch signal pair to the multi-stage transmission gate circuit 24. The multi-stage transmission gate circuit 24 determines the input voltages of WL, BL, and SL corresponding to the target storage unit 401 from the received multiple preset voltages according to the secondary switch signal pair and the read / write control signal, and applies the input voltages to the WL, BL, and SL corresponding to the target storage unit 401, respectively, thereby completing the read operation or the write operation.

[0026] When performing a read operation, the logic control circuit 22 also controls the target storage unit 401 to be connected to the read circuit 30 according to the read / write control signal and the address signal. The read circuit 30 reads the current value of SL to obtain a data read result when connected to the target storage unit 401. When not performing a read operation, the read circuit 30 is disconnected from the target storage unit 401.

[0027] The control circuit of the resistive memory array of the present embodiment sends a corresponding secondary switch signal pair to a multi-stage transmission gate circuit based on a plurality of read / write control signals and address signals output by a controller through a logic control circuit, applies a corresponding input voltage to a target memory cell through the multi-stage transmission gate circuit based on the secondary switch signal pair and the plurality of read / write control signals, and implements a read / write operation corresponding to the input voltage; controls the corresponding target memory cell to be connected or disconnected with a readout circuit based on a plurality of read / write control signals and address signals through a logic control circuit, and reads a current value output by the target memory cell when the readout circuit is connected to the target memory cell, implements a read operation, and obtains a data read result through the current value; the control circuit implements the gating of word lines, bit lines, and source lines and the corresponding voltage input and current reading through a gating module, reduces the occupied area of ​​the peripheral circuit, and solves the problem of a large occupied area of ​​the peripheral circuit.

[0028] In some embodiments, Figure 3 Schematic diagram of the connection of word line multi-stage transmission gate circuits in some embodiments of the present application. Figure 3As shown, the multi-stage transmission gate circuit includes a word line first-level transmission gate circuit 2411 and a word line second-level transmission gate circuit 2412, multiple read and write control signals include a read control signal READ and a write control signal WRITE, and the word line first-level transmission gate circuit 2411 includes a first transmission gate T1 and a second transmission gate T2.

[0029] The word line first-level transmission gate circuit 2411 generates a first-level switch signal pair of the first transmission gate T1 based on the write control signal WRITE to control the connection or disconnection of the preset word line write voltage signal VWLDAC with the word line second-level transmission gate circuit 2412; the word line first-level transmission gate circuit 2411 generates a first-level switch signal pair of the second transmission gate T2 based on the read control signal READ to control the connection or disconnection of the preset word line read voltage signal VWLREAD with the word line second-level transmission gate circuit 2412.

[0030] Further, the word line multi-stage transmission gate circuit may also include a level shift circuit, which is used to convert the voltage of the input high-level signal or low-level signal to drive the first transmission gate T1 and the second transmission gate T2, but will not change the relative high and low levels of the signal. The word line secondary transmission gate circuit 2412 may include a transmission gate T3. Specifically, T1, T2, and T3 may be CMOS transmission gates. Specifically, when the first control terminal (positive phase terminal) of the CMOS transmission gate is at a high level and the second control terminal (inverting terminal) is at a low level, the input terminal and the output terminal are connected; when the first control terminal (positive phase terminal) of the transmission gate is at a low level and the second control terminal (inverting terminal) is at a high level, the input terminal and the output terminal are disconnected.

[0031] The write control signal WRITE and the read control signal READ cannot be valid at the same time. When performing a write operation, the write control signal WRITE is at a high level. After the write control signal WRITE and the corresponding inverted signal are level-shifted, they are used as the control signal of T1. The input and output of T1 are connected, and the word line write voltage signal VWLDAC is sent to the input of the word line secondary transmission gate circuit 2412. At this time, the input and output of T2 are disconnected.

[0032] Similarly, when performing a read operation, the read control signal READ is at a high level, the T2 input terminal and the output terminal are connected, and the word line read voltage signal VWLREAD is sent to the input terminal of the word line secondary transmission gate circuit 2412. At this time, the T1 input terminal and the output terminal are disconnected.

[0033] Furthermore, the transmission gate T3 controls the input and output ends of T3 to be turned on or off according to the secondary switch signal pair sent by the word line logic control circuit, thereby controlling the word line read voltage signal VWLREAD or the word line write voltage signal VWLDAC to be applied to the word line end of the target memory cell, thereby realizing the selection of the target memory cell for the read operation or the write operation; and disconnecting the connection with the word line end of the memory cell when the memory cell is not selected.

[0034] The control circuit of the resistive memory array of the present embodiment sends the corresponding word line read voltage signal or word line write voltage signal to the word line secondary transmission gate circuit through the word line primary transmission gate circuit during the read operation and the write operation respectively; applies the word line read voltage signal or the word line write voltage signal to the word line end of the target memory cell through the word line secondary transmission gate circuit, thereby selecting the target memory cell for the read operation or the write operation, and realizing the selection and output of the word line voltages corresponding to different operations.

[0035] In some embodiments, Figure 4 Schematic diagram of the connection between the word line multi-stage transmission gate circuit and the word line logic control circuit in some embodiments of the present application. Figure 4 As shown, the multiple read-write control signals also include an enable signal BANK_EN. When the enable signal BANK_EN is at a low level, the word line secondary transmission gate circuit 2412 disconnects the word line end of the target storage unit based on the secondary switch signal pair S1 / S2; the word line logic control circuit 221 controls the word line end of the target storage unit to be grounded based on the secondary switch signal pair S1 / S2.

[0036] The enable signal BANK_EN and the word line address signal LW_WL <m:1>When both are at high level, the word line secondary transmission gate circuit 2412 restores the connection with the word line end of the target memory cell based on the secondary switch signal pair S1 / S2.

[0037] Specifically, the enable signal BANK_EN and the word line address signal LW_WL <m:1>When the enable signal BANK_EN or the word line address signal LW_WL <m:1>When it is low level, S1 is low level, S2 is high level, the input end and output end of T3 are disconnected, the switch tube Q1 is turned on, and the word line end of the target storage unit is grounded.

[0038] When the enable signal BANK_EN and the word line address signal LW_WL <m:1>When the word line address signal LW_WL is high, S1 is high, S2 is low, the input and output ends of T3 are connected, and the switch tube Q1 is turned off. <m:1>There are m address signals, the address signal of the row where the target storage unit is located is high level, and the others are low level.

[0039] The control circuit of the resistive memory array of this embodiment implements voltage input control of the word line end of the target memory cell through the word line logic control circuit, outputs corresponding word line voltages under different operating conditions, and ensures the correctness of the word line voltages.

[0040] In some embodiments, Figure 5 Schematic diagram of the connection of the bit line multi-stage transmission gate circuit in some embodiments of the present application. Figure 5 As shown, the multi-stage transmission gate circuit includes a bit line first-level transmission gate circuit 2421 and a bit line second-level transmission gate circuit 2422, multiple read and write control signals include a set control signal SET and a reset control signal RESET, and the bit line first-level transmission gate circuit 2421 includes a fourth transmission gate T4 and a fifth transmission gate T5.

[0041] The bit line primary transmission gate circuit 2421 generates a primary switch signal pair of the fourth transmission gate T4 based on the set control signal SET to control the preset bit line set voltage signal VBLSET to connect or disconnect with the bit line secondary transmission gate circuit 2422; the bit line primary transmission gate circuit 2421 generates a primary switch signal pair of the fifth transmission gate T5 based on the reset control signal RESET to control the bit line secondary transmission gate circuit 2422 to be grounded or disconnected. The bit line set voltage signal VBLSET can provide a set voltage SET and a forming voltage FORMING.

[0042] Similar to the word line multi-stage transmission gate circuit in the above embodiment, the bit line multi-stage transmission gate circuit may also include a level shift circuit, which is used to convert the input high level signal or low level signal into a voltage to drive the fourth transmission gate T4 and the fifth transmission gate T5, but will not change the relative high and low levels of the signal. The bit line secondary transmission gate circuit 2422 may include a transmission gate T6. Specifically, T4, T5, and T6 may be CMOS transmission gates. The level and on-off relationship of the first control terminal and the second control terminal will not be repeated.

[0043] Among them, the set control signal SET and the reset control signal RESET cannot be valid at the same time. When the set operation is performed, the set control signal SET is at a high level. After the level shift of the set control signal SET and the corresponding inverted signal, they are used as the control signal of T4. The input terminal and the output terminal of T4 are connected, and the bit line set voltage signal VBLSET is sent to the input terminal of the bit line secondary transmission gate circuit 2422. At this time, the input terminal and the output terminal of T5 are disconnected.

[0044] Similarly, when a reset operation is performed, the reset control signal RESET is at a high level, the input terminal of T5 is connected to the output terminal, and the input terminal of the bit line secondary transmission gate circuit 2422 is grounded. At this time, the input terminal of T4 is disconnected from the output terminal.

[0045] Furthermore, the transmission gate T6 controls the input and output ends of T6 to be turned on or off according to the secondary switch signal pair sent by the bit line logic control circuit, thereby controlling the bit line set voltage signal VBLSET or 0V ground to be applied to the bit line end of the target storage unit to implement a set operation or a reset operation.

[0046] The control circuit of the resistive memory array of the present embodiment connects the corresponding bit line set voltage signal or ground signal to the bit line secondary transmission gate circuit through the bit line primary transmission gate circuit during the set operation and the reset operation respectively; applies the bit line set voltage or the ground voltage to the bit line end of the target memory cell through the bit line secondary transmission gate circuit to implement the set operation or the reset operation, thereby realizing the selection and output of the bit line voltage corresponding to different operations.

[0047] In some embodiments, Figure 6 Schematic diagram of the connection between the bit line transmission gate circuit and the bit line logic control circuit in some embodiments of the present application. Figure 6 As shown, the logic control circuit includes a bit line logic control circuit 222, and a plurality of read and write control signals include an enable signal BANK_EN and a read control signal READ. The bit line logic control circuit 222 is based on the read control signal READ, the enable signal BANK_EN and the bit line address signal LW_BL. <n:1>, controls the preset bit line read voltage signal VBLREAD to be connected or disconnected with the bit line terminal of the target memory cell; the bit line logic control circuit 222 is based on the enable signal BANK_EN and the bit line address signal LW_BL <n:1>, generating a secondary switch signal pair S3 / S4.

[0048] In this embodiment, any two of the read control signal READ, the set control signal SET, and the reset control signal RESET cannot be valid at the same time. <n:1>High level is valid.

[0049] When the enable signal BANK_EN and the bit line address signal LW_BL <n:1>When the read control signal READ is high, the transmission gate T6 is turned on. Further, when the read control signal READ is high, the switch tube Q2 is turned on, the transmission gates T4 and T5 are turned off, and the bit line end of the target memory cell is applied with the bit line read voltage signal VBLREAD. Similarly, when the enable signal BANK_EN and the bit line address signal LW_BL <n:1>When the bit line voltage VBLSET is applied to the bit line of the target memory cell, the switch Q2 is turned off, the transmission gates T4 and T6 are turned on, the transmission gate T5 is turned off, and the bit line set voltage signal VBLSET is applied to the bit line of the target memory cell. <n:1>is at a high level and the reset control signal RESET is at a high level, the bit line terminal of the target memory cell is grounded.

[0050] When the enable signal BANK_EN or the bit line address signal LW_BL <n:1>When it is at a low level, the transmission gate T6 is turned off, the switch tube Q2 is turned off, and the bit line end of the target storage unit is disconnected from the gating module.

[0051] The control circuit of the resistive memory array of this embodiment controls the connection or disconnection between the target memory cell and the selection module through the bit line logic control circuit; through the bit line logic control circuit and the bit line transmission gate circuit, the input voltage of the bit line end of the target memory cell is controlled when the target memory cell is connected to the selection module, and the corresponding bit line voltage is output under different operating conditions, thereby ensuring the correctness of the bit line voltage.

[0052] In some embodiments, Figure 7 Schematic diagram of the connection of source line multi-stage transmission gate circuits in some embodiments of the present application. Figure 7 As shown, the multi-stage transmission gate circuit includes a source line first-level transmission gate circuit 2431 and a source line second-level transmission gate circuit 2432, and multiple read-write control signals include a set control signal SET and a reset control signal RESET. The source line first-level transmission gate circuit 2431 includes a seventh transmission gate T7 and an eighth transmission gate T8. The source line first-level transmission gate circuit 2431 generates a first-level switch signal pair of the seventh transmission gate T7 based on the set control signal SET to control the source line second-level transmission gate circuit 2432 to be grounded or disconnected; the source line first-level transmission gate circuit 2431 generates a first-level switch signal pair of the eighth transmission gate T8 based on the reset control signal RESET to control the preset source line reset voltage signal VSLRESET to be connected or disconnected from the source line second-level transmission gate circuit 2432.

[0053] Similar to the word line multi-stage transmission gate circuit in the above embodiment, the source line multi-stage transmission gate circuit may further include a level shift circuit, which is used to convert the input high level signal or low level signal into a voltage to drive the seventh transmission gate T7 and the eighth transmission gate T8, but will not change the relative high and low levels of the signal. The source line secondary transmission gate circuit 2432 may include a transmission gate T9. Specifically, T7, T8, and T9 may be CMOS transmission gates. The level and on-off relationship of the first control terminal and the second control terminal will not be repeated.

[0054] Among them, the set control signal SET and the reset control signal RESET cannot be valid at the same time. When the set operation is performed, the set control signal SET is at a high level. After the level shift of the set control signal SET and the corresponding inverted signal, they are used as the control signal of T7. The input terminal of T7 is connected to the output terminal, and the input terminal of the source line secondary transmission gate circuit 2432 is grounded. At this time, the input terminal of T8 is disconnected from the output terminal.

[0055] Similarly, when a reset operation is performed, the reset control signal RESET is at a high level, the input terminal of T8 is connected to the output terminal, and the source line reset voltage signal VSLRESET is sent to the input terminal of the source line secondary transmission gate circuit 2432. At this time, the input terminal of T7 is disconnected from the output terminal.

[0056] Furthermore, the transmission gate T9 controls the input and output ends of T9 to be turned on or off according to the secondary switch signal pair sent by the source line logic control circuit, thereby controlling the source line end of the target storage unit to be grounded or applying the source line reset voltage signal VSLRESET to implement a set operation or a reset operation.

[0057] The control circuit of the resistive memory array of the present embodiment connects the corresponding ground signal or source line reset voltage signal to the source line secondary transmission gate circuit through the source line primary transmission gate circuit during the set operation and the reset operation respectively; applies the ground voltage or the source line reset voltage to the source line terminal of the target memory cell through the source line secondary transmission gate circuit to implement the set operation or the reset operation, thereby realizing the selection and output of the source line voltage corresponding to different operations.

[0058] In some embodiments, Figure 8 Schematic diagram of the connection between the source line multi-stage transmission gate circuit and the source line logic control circuit in some embodiments of the present application. Figure 8 As shown, the logic control circuit includes a source line logic control circuit 223, and a plurality of read and write control signals include an enable signal BANK_EN, a read control signal READ, a set signal SET, and a reset signal RESET. The source line logic control circuit 223 is based on the read control signal READ, the enable signal BANK_EN, and the source line address signal LW_SL <n:1>, control the read circuit to connect or disconnect the source line terminal of the target memory cell; the source line logic control circuit 223 is based on the set signal SET, the reset signal RESET, the enable signal BANK_EN and the source line address signal LW_SL <n:1>, generating a secondary switch signal pair S5 / S6.

[0059] As in the above embodiment, any two of the read control signal READ, the set control signal SET, and the reset control signal RESET cannot be valid at the same time. <n:1>High level is valid.

[0060] When the enable signal BANK_EN and the source line address signal LW_SL <n:1>When the enable signal BANK_EN and the source line address signal LW_SL are high, the switch tube Q3 is turned on, and the source line terminal of the target storage unit is connected to the read circuit. <n:1>When the enable signal BANK_EN and the set control signal SET are high, the switch tube Q3 is turned off, the transmission gates T7 and T9 are turned on, the transmission gate T8 is turned off, and the source line terminal of the target storage unit is grounded. Similarly, when the enable signal BANK_EN and the source line address signal LW_SL <n:1>When the reset control signal RESET is high, the switch tube Q3 is turned off, the transmission gates T8 and T9 are turned on, the transmission gate T7 is turned off, and the source line end of the target storage unit is connected to the source line reset voltage signal VSLRESET.

[0061] When the enable signal BANK_EN or the bit line address signal LW_BL <n:1>When it is at a low level, the transmission gate T9 is turned off, the switch tube Q3 is turned off, and the source line end of the target storage unit is disconnected from the selection module.

[0062] The control circuit of the resistive memory array of the present embodiment controls the connection or disconnection between the target memory cell and the selection module through the source line logic control circuit; controls the input voltage of the source line terminal of the target memory cell when the target memory cell is connected to the selection module through the source line logic control circuit and the source line transmission gate circuit, outputs the corresponding source line voltage under different operation conditions, and ensures the correctness of the bit line voltage; and controls the source line terminal of the target memory cell to connect to the read-out circuit when the read control signal is valid, and obtains the data reading result by reading the current value of the source line terminal.

[0063] In some embodiments, the control circuit further includes a digital-to-analog conversion circuit, which is used to convert the voltage value output by the controller into a corresponding word line write voltage signal and output it to the multi-stage transmission gate circuit. Fig. 9 Schematic diagram of the circuit connection of the digital-to-analog conversion circuit of some embodiments of the present application. Fig. 9 As shown, the digital-to-analog conversion circuit includes a capacitor array 41 and a rail-to-rail input-output operational amplifier 42. The capacitor array includes 9 capacitors and 9 switches (6 capacitors and 6 switches are shown in the figure), and the capacitance values ​​of the 9 capacitors are C, C / 2, C / 4, C / 8, C / 16, C / 32, C / 64, C / 128, and C / 128 respectively. The upper plates of the 9 capacitors are connected to the non-inverting input terminal of the rail-to-rail input-output operational amplifier 42, the lower plate of a capacitor with a capacitance value of C / 128 is connected to GND, the lower plates of the other 8 capacitors are connected to the reference voltage VREF through switches, and the upper plates of all capacitors are connected to GND through the clock switch DAC_CLK. According to the input digital voltage value and the reference voltage VREF, an analog voltage is generated as the word line write voltage signal VWLDAC.

[0064] When using the digital-to-analog conversion circuit, firstly, the clock switch DAC_CLK is grounded, and switches D0 to D7 are grounded, so that both ends of all capacitors are grounded, and then DAC_CLK is disconnected, and the capacitor array connects the lower plate of each capacitor to the reference voltage VREF. According to the law of conservation of charge, its output voltage satisfies:

[0065] In some embodiments, Fig.10 Schematic diagram of the connection of the readout circuit in some embodiments of the present application. Fig.10 As shown, the read circuit includes a current-to-voltage conversion circuit 51 and an analog-to-digital conversion circuit 52. The current-to-voltage conversion circuit 51 converts the current value I output by the target storage unit to IN The analog-to-digital conversion circuit 52 converts the voltage signal into a corresponding voltage signal, and the analog-to-digital conversion circuit 52 converts the voltage signal into a digital voltage value D<7:0> and sends it to the controller. Specifically, the analog-to-digital conversion circuit 52 can be an 8-bit successive approximation analog-to-digital converter.

[0066] The input end of the current-to-voltage circuit 51 is connected to the source line logic control circuit, and the output end is connected to the input end of the analog-to-digital conversion circuit 52. The function of the current-to-voltage circuit 51 is to convert the source line current I IN The analog-to-digital conversion circuit 52 performs analog-to-digital conversion on the voltage generated by the current-to-voltage circuit 51 .

[0067] The current-to-voltage circuit 51 may include an operational amplifier clamping circuit and a current scaling circuit. The operational amplifier clamping circuit is used to clamp the source line SL of the resistive memory array to a fixed voltage, namely, the source line read voltage VSLREAD, and the current scaling circuit is used to convert the current I IN Scaling is performed and a voltage is generated at the input end of the analog-to-digital conversion circuit 52. The direction of the SL current is controlled by the digital control signal COMPUTE_OC. When COMPUTE_OC is high, the current flows out of the chip for chip testing; when COMPUTE_OC is low, the current flows to the op amp clamp circuit.

[0068] The analog-to-digital conversion circuit 52 includes a sample-and-hold circuit SH, a comparator COMP, two P-DAC capacitor arrays, and a successive approximation register SAR module. When its enable signal ENA is at a high level, the analog-to-digital conversion circuit 52 works normally. When ENA is at a low level, the input of the comparator COMP is pulled to GND, and the output of the analog-to-digital conversion circuit 52 is 0.

[0069] In some embodiments, the present application further provides a resistive memory, which includes a resistive memory array and a control circuit of the resistive memory array as described in the above embodiments.

[0070] The resistive memory of the present embodiment applies a corresponding input voltage to a target memory cell in the resistive memory array through a control circuit of the resistive memory array, thereby realizing a read and write operation corresponding to the input voltage; controls the target memory cell to be connected or disconnected with a read circuit, and when the read circuit is connected with the target memory cell, reads a current value output by the target memory cell, thereby realizing that during a read operation, the current value of the target memory cell is read through the read circuit, and a data reading result is obtained through the current value; realizes the selection of word lines, bit lines and source lines and the corresponding voltage input and current reading, thereby reducing the occupied area of ​​the peripheral circuit and solving the problem of a large occupied area of ​​the peripheral circuit.

[0071] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0072] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0073] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0074] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0075] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A control circuit of a resistive memory array, the control circuit comprising a gating module connected to the resistive memory array, and a controller and a readout circuit connected to the gating module; the resistive memory array comprises a plurality of memory cells, characterized in that: The gating module includes a logic control circuit and a multi-stage transmission gate circuit connected to each other. The logic control circuit sends a corresponding pair of secondary switch signals to the multi-stage transmission gate circuit based on a plurality of read / write control signals and address signals output by the controller, and controls the target storage unit corresponding to the address signal to be connected or disconnected from the readout circuit; The multi-stage transmission gate circuit applies a corresponding input voltage to the target memory cell based on the secondary switch signal pair and the plurality of read / write control signals, wherein the input voltage is determined from a plurality of preset voltages received by the multi-stage transmission gate circuit; The read circuit reads a current value outputted from the target memory cell when connected to the target memory cell.

2. The circuit according to claim 1, characterized in that The multi-stage transmission gate circuit includes a word line primary transmission gate circuit and a word line secondary transmission gate circuit, the multiple read and write control signals include a read control signal and a write control signal, and the word line primary transmission gate circuit includes a first transmission gate and a second transmission gate. The word line primary transmission gate circuit generates a primary switch signal pair of the first transmission gate based on the write control signal to control a preset word line write voltage signal to be connected or disconnected with the word line secondary transmission gate circuit; and The word line primary transmission gate circuit generates a primary switch signal pair of the second transmission gate based on the read control signal to control a preset word line read voltage signal to be connected or disconnected with the word line secondary transmission gate circuit.

3. The circuit according to claim 2, characterized in that The logic control circuit includes a word line logic control circuit, the multiple read and write control signals include an enable signal, When the enable signal is at a low level, the word line secondary transmission gate circuit disconnects the word line terminal of the target memory cell based on the secondary switch signal pair; the word line logic control circuit controls the word line terminal of the target memory cell to be grounded based on the secondary switch signal pair; In the case that both the enable signal and the address signal are at a high level, the word line secondary transmission gate circuit restores the connection with the word line terminal of the target memory cell based on the secondary switch signal pair.

4. The circuit according to claim 1, characterized in that The multi-stage transmission gate circuit includes a bit line primary transmission gate circuit and a bit line secondary transmission gate circuit, the multiple read and write control signals include a set control signal and a reset control signal, and the bit line primary transmission gate circuit includes a fourth transmission gate and a fifth transmission gate, The bit line primary transmission gate circuit generates a primary switch signal pair of the fourth transmission gate based on the setting control signal to control the connection or disconnection of a preset bit line setting voltage signal with the bit line secondary transmission gate circuit; and The bit line primary transmission gate circuit generates a primary switch signal pair of the fifth transmission gate based on the reset control signal to control the bit line secondary transmission gate circuit to be grounded or disconnected.

5. The circuit according to claim 4, characterized in that The logic control circuit includes a bit line logic control circuit, the multiple read and write control signals include an enable signal and a read control signal, The bit line logic control circuit controls a preset bit line read voltage signal to be connected or disconnected with a bit line terminal of the target memory cell based on the read control signal, the enable signal and the address signal; The bit line logic control circuit generates the secondary switch signal pair based on the enable signal and the address signal.

6. The circuit according to claim 1, characterized in that The multi-stage transmission gate circuit includes a source line primary transmission gate circuit and a source line secondary transmission gate circuit, the multiple read and write control signals include a set control signal and a reset control signal, the source line primary transmission gate circuit includes a seventh transmission gate and an eighth transmission gate, The source line primary transmission gate circuit generates a primary switch signal pair of the seventh transmission gate based on the set control signal to control the source line secondary transmission gate circuit to be grounded or disconnected; and The source line primary transmission gate circuit generates a primary switch signal pair of the eighth transmission gate based on the reset control signal to control the connection or disconnection of a preset source line reset voltage signal with the source line secondary transmission gate circuit.

7. The circuit according to claim 6, characterized in that The logic control circuit includes a source line logic control circuit, the multiple read and write control signals include an enable signal, a read control signal, a set signal and a reset signal, The source line logic control circuit controls the readout circuit to connect or disconnect with the source line terminal of the target memory cell based on the read control signal, the enable signal and the address signal; The source line logic control circuit generates the secondary switch signal pair based on the set signal, the reset signal, the enable signal and the address signal.

8. The circuit according to claim 1, characterized in that The control circuit also includes a digital-to-analog conversion circuit, The digital-to-analog conversion circuit is used to convert the voltage value output by the controller into a corresponding word line write voltage signal, and output it to the multi-stage transmission gate circuit.

9. The circuit according to claim 1, characterized in that The readout circuit includes a current-to-voltage conversion circuit and an analog-to-digital conversion circuit. The current-to-voltage circuit converts the current value output by the target storage unit into a corresponding voltage signal, and the analog-to-digital conversion circuit converts the voltage signal into a voltage value and sends it to the controller.

10. A resistive random access memory, characterized in that: The resistive memory comprises a resistive memory array and a control circuit of the resistive memory array as claimed in any one of claims 1 to 9.

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