Non-volatile memory and erasing method and system thereof

Abstract

The present disclosure provides a non-volatile memory and an erasing method and system thereof. The non-volatile memory includes a target physical block, the target physical block includes a basic memory cell array and a target memory cell array, wherein the memory cells in the target memory cell array are memory cells with special functions other than the basic memory cells, and the basic memory cell array and the target memory cell array share bit lines and well areas; the erasing method includes: in response to receiving an erase instruction, determining the first physical block corresponding to the area to be erased according to the erase instruction; in response to the first physical block being the target physical block, performing an erase operation of the area to be erased according to the erase instruction, and performing a refresh programming operation of the target physical block to correct the threshold voltage of the memory cells in the target physical block. The present disclosure effectively reduces the influence of well interference and program interference, ensures the accuracy of data storage, improves the reliability, service life and overall performance of the non-volatile memory, and meets the needs of users.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a non-volatile memory and an erasing method and system thereof. Background Art

[0002] Informatization is the general trend of the current era. Data storage and management are becoming more and more important. Various storage technologies have emerged, and flash memory technology has been widely used in various fields. Among them, Nor Flash (non-volatile flash memory technology) is a major non-volatile flash memory technology, which is characterized by fast reading speed and allows the system to directly execute the stored code.

[0003] For Nor Flash with more functions, in addition to operating the array of basic storage cells, it is also necessary to have advanced security functions, that is, it is necessary to provide a one-time programming (OTP) bit and a storage area outside the basic storage cell array (for example, a security register) for users to use, so as to store sensitive or important data more securely. However, when adding Security Register related functions to the existing Nor Flash, the area of ​​the entire chip will increase, which significantly increases the cost of Nor Flash, and data errors are prone to occur when operating the Security Register, which cannot meet the user's security storage needs. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defects of the prior art that the implementation of advanced security functions by Nor Flash leads to an increase in chip area and the inability to ensure data accuracy, and to provide a non-volatile memory and an erasing method and system thereof.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] According to a first aspect of the present disclosure, a method for erasing a nonvolatile memory is provided, wherein the nonvolatile memory includes a target physical block, the target physical block includes a basic memory cell array and a target memory cell array, wherein the memory cells in the target memory cell array are memory cells with special functions other than the basic memory cells, and the basic memory cell array and the target memory cell array share a bit line and a well region;

[0007] The erasing method comprises:

[0008] In response to receiving an erase instruction, determining a first physical block corresponding to the area to be erased according to the erase instruction;

[0009] In response to the first physical block being the target physical block, an erase operation of the to-be-erased area is performed according to the erase instruction, and a refresh program operation of the target physical block is performed to correct the threshold voltage of the storage cells in the target physical block.

[0010] Preferably, the step of performing an erase operation on the to-be-erased area according to the erase instruction and performing a refresh programming operation on the target physical block comprises:

[0011] Execute an erasing operation of the area to be erased according to the erasing instruction;

[0012] A refresh program operation of the target memory cell array is performed to correct the threshold voltages of the memory cells corresponding to the target memory cell array.

[0013] Preferably, the regions in the basic memory cell array correspond to a plurality of preset division rules, and the regions in the basic memory cell array determine the corresponding target division rules based on the interference degree of the target physical block, so as to obtain a plurality of first sub-regions of the same size, wherein the interference degree represents the maximum limit at which the threshold voltage of the basic memory cell array remains stable during the erasing operation of the target physical block;

[0014] The step of performing an erase operation on the to-be-erased area according to the erase instruction and performing a refresh programming operation on the target physical block comprises:

[0015] In response to the area to be erased being located in the basic memory cell array, performing an erase operation on the area to be erased;

[0016] Acquire a current first sub-region in the basic memory cell array; wherein the current first sub-region represents the first sub-region where a refresh programming operation is to be performed;

[0017] Execute a refresh programming operation of the current first sub-region;

[0018] Executing a refresh programming operation of the target memory cell array;

[0019] The next first sub-region of the current first sub-region is used as the new current first sub-region, and the step of determining the first physical block corresponding to the area to be erased according to the erase instruction in response to receiving the erase instruction is returned to be executed.

[0020] Preferably, the regions in the basic memory cell array correspond to a plurality of preset division rules, and the regions in the basic memory cell array determine the corresponding target division rules based on the interference degree of the target physical block, so as to obtain a plurality of first sub-regions of the same size, wherein the interference degree represents the maximum limit at which the threshold voltage of the basic memory cell array remains stable during the erasing operation of the target physical block;

[0021] The step of performing an erase operation on the to-be-erased area according to the erase instruction and performing a refresh programming operation on the target physical block comprises:

[0022] In response to the area to be erased being located in the target memory cell array, performing an erase operation on the area to be erased;

[0023] Executing a refresh programming operation of the target memory cell array;

[0024] Acquire a current first sub-region in the basic memory cell array; wherein the current first sub-region represents the first sub-region where a refresh programming operation is to be performed;

[0025] Execute a refresh programming operation of the current first sub-region;

[0026] The next first sub-region of the current first sub-region is used as the new current first sub-region, and the step of determining the first physical block corresponding to the area to be erased according to the erase instruction in response to receiving the erase instruction is returned to be executed.

[0027] Preferably, the erasing method further comprises:

[0028] In response to powering on again, the current first sub-region in the basic memory cell array is determined based on a preset determination method.

[0029] Preferably, the target storage cell array includes at least one of a serial flash memory discoverable parameter storage array, a status register storage array, a unique identification number storage array, and a security register storage array;

[0030] and / or,

[0031] The step of performing a refresh programming operation on the target memory cell array comprises:

[0032] The refresh programming operation is performed on at least one of the serial flash memory discoverable parameter storage array, the status register storage array, the unique identification number storage array, and the security register storage array.

[0033] Preferably, the non-volatile memory further includes a plurality of initial physical blocks; the initial physical blocks are physical blocks in the non-volatile memory except the target physical blocks;

[0034] The erasing method further comprises:

[0035] In response to the first physical block being the initial physical block, an erase operation of the to-be-erased area is performed according to the erase instruction, and a refresh program operation of the initial physical block is performed.

[0036] According to a second aspect of the present disclosure, there is provided an erasing system for a nonvolatile memory, wherein the nonvolatile memory includes a target physical block, the target physical block includes a basic memory cell array and a target memory cell array, wherein the memory cells in the target memory cell array are memory cells with special functions other than the basic memory cells, and the basic memory cell area and the target memory cell array share a bit line and a well area;

[0037] The erasure system includes a determination module and an execution module;

[0038] The determination module is used for determining the first physical block corresponding to the area to be erased according to the erase instruction in response to receiving the erase instruction;

[0039] The execution module is used for executing an erase operation of the to-be-erased area according to the erase instruction in response to the first physical block being the target physical block, and executing a refresh programming operation of the target physical block to correct the threshold voltage of the storage unit in the target physical block.

[0040] According to a third aspect of the present disclosure, a nonvolatile memory is provided, wherein the nonvolatile memory comprises the erasing system described in the second aspect of the present disclosure.

[0041] Preferably, the non-volatile memory includes Nor Flash.

[0042] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0043] The positive and progressive effect of the present disclosure is that the target memory cell array composed of memory cells with special functions and the basic memory cell array are planned in the same physical block, and the bit lines and well areas are shared, so that the area and cost of the peripheral circuit can be reduced, and a refresh programming operation is performed when an erase command is executed to correct the threshold voltage of the memory cell, thereby ensuring the accuracy of the data stored in the target memory cell array, correcting the tiny charge errors caused by interference, and reducing the cumulative effect of interference, so that the non-volatile memory has an advanced security function capable of storing important data without increasing the size of the non-volatile memory, and at the same time can effectively reduce the influence of phenomena such as well interference and program interference, thereby ensuring the accuracy of data storage, improving the reliability and service life of the non-volatile memory, and improving the overall performance of the non-volatile memory to meet the needs of users. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A storage cell array diagram of a target physical block disclosed herein;

[0045] Figure 2 A first flow chart of the method for erasing a non-volatile memory disclosed in the present invention;

[0046] Figure 3 A first flow chart of step S2 of the method for erasing a non-volatile memory disclosed in the present invention;

[0047] Figure 4 A second flow chart of step S2 of the method for erasing a non-volatile memory disclosed in the present invention;

[0048] Figure 5 A second flow chart of the method for erasing a non-volatile memory disclosed in the present invention;

[0049] Figure 6 The module diagram of the erasing system of the non-volatile memory disclosed in the present invention is shown in FIG. DETAILED DESCRIPTION

[0050] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0051] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0052] The current mainstream floating gate technology plans Nor Flash into a storage array, and performs independent read and write operations on each storage unit through bit lines (BL), word lines (WL) and decoder circuits. Taking 8Mb Nor Flash as an example, there are 256 blocks, Each block has 16 sectors. The sector has 16 pages, each page e has 256 bytes, that is, a sector is 4K bytes, a block is 64Kbytes, in the page buffer, a word line generally corresponds to a page, a bit line generally corresponds to a byte. In order to reduce costs, reduce the size of external circuits and share the array well area, storage cells are organized together in the form of physical blocks (PB).

[0053] For Nor Flash, some operations on storage cells may cause data errors. For example, when performing a write operation, other storage cells on the current bit line that are not being operated may change, resulting in program disturb or drain disturb. When performing high-voltage operations, the operation of a storage cell may interfere with the charge distribution in the floating gate of an adjacent storage cell, resulting in well disturb and causing data errors.

[0054] In the denser PB, program disturb and well disturb are both very serious disturbances. Well disturb can affect all storage cells in the entire well area, and program disturb affects the data cells on an entire BL. Too much interference will cause unforeseen error accumulation during the erase operation, affecting the accuracy of the storage cell data.

[0055] The purpose of Security Register is to enable users to store sensitive or important data more securely, so it has very high requirements for fault tolerance and does not allow data errors. Therefore, the existing method of adding Security Register related functions to Nor Flash usually separates the Security Register from other PBs and performs read and write control separately. However, this method adds WL transmission tubes and BL transmission tubes, which not only creates idle WL transmission tubes, but also increases a large area due to the added BL transmission tubes, significantly increasing the cost of Nor Flash.

[0056] Based on this, in order to solve the problem that the existing Nor Flash implements the advanced security function of the security register, which leads to an increase in chip area and an inability to ensure data accuracy, a non-volatile memory and an erasing method and system thereof are provided to effectively reduce well interference and ensure data accuracy without increasing the size of the non-volatile memory.

[0057] Example 1

[0058] In a specific embodiment of the present disclosure, a method for erasing a non-volatile memory is provided. The method is applied to a non-volatile memory including a target physical block, such as Figure 1 As shown, the target physical block includes a basic memory cell array 1 and a target memory cell array 2, wherein the memory cells in the target memory cell array 2 are memory cells with special functions other than the basic memory cells, and the basic memory cell array 1 and the target memory cell array 2 share bit lines and well regions.

[0059] In order to reduce the area of ​​the peripheral circuit, the target memory cell array 2 and the basic memory cell array 1 are planned in one PB to form a target physical block. Taking the target memory cell array including three 1024-byte security register memory arrays as an example, the basic memory cell array 1 is located on the normal WL and is composed of the basic memory cells between bit line 0-bit line m and normal word line0-normal word line n. The target memory cell array 2 is located on the security WL and is composed of the special function memory cells between bit line 0-bit line m and security word line0-security word line2. The transistors of the special function memory cells in the target memory cell array 2 are embedded in the well. In each well, multiple basic memory cells and special function memory cells share the same substrate and voltage source. The security register memory array can be configured by controlling the relevant status register by the OTP bit.

[0060] Of course, the target storage cell array 2 may include storage cells with special functions such as a serial flash discoverable parameter (SFDP) storage array, a state register storage array, a unique identification number (Unique Identification) storage array, and a security register storage array. During the non-volatile memory design stage, the storage array type and composition of the target storage cell array 2 may be set according to specific actual needs.

[0061] Considering that the target memory cell array and the basic memory cell array are jointly controlled, although the BL transmission tube can be shared to reduce the area of ​​the peripheral circuit, too many interference operations are introduced between different memory cells, which makes it easy for data errors to occur when operating the target memory cell array, and cannot meet the user's demand for secure storage. Therefore, this embodiment also provides a corresponding non-volatile memory erasing method.

[0062] like Figure 2 As shown, the erasing method includes:

[0063] S1, in response to receiving an erase instruction, determining a first physical block corresponding to the area to be erased according to the erase instruction;

[0064] S2. In response to the first physical block being a target physical block, performing an erase operation on the area to be erased according to an erase instruction, and performing a refresh program operation on the target physical block to correct the threshold voltage of a storage cell in the target physical block.

[0065] Specifically, when receiving an erase instruction, step S1 determines the first physical block where the area to be erased is located through the erase instruction. If the area to be erased is a basic storage cell array or a target storage cell array on a target physical block, then after executing the erase operation of the area to be erased corresponding to the erase instruction, step S2 performs a refresh programming operation on the target physical block to correct the threshold voltages of the basic storage cell array in the target physical block and the storage cells in the target storage cell array, effectively reducing the influence of phenomena such as well interference and program interference, reducing the probability of data errors in the storage cells, and ensuring the effectiveness of data storage and the accuracy of operations.

[0066] Among them, the erase instruction can be a block erase (BE) instruction, a sector erase (SE) instruction, and a chip erase (CE) instruction. A complete erase instruction generally includes an instruction type, an address, and data. In non-volatile memory, different erase instructions correspond to different erase operations of the entire storage area, that is, BE, SE, and CE will erase the entire block, sector, and chip respectively. The more storage units covered by the erase instruction, the larger the operation scale.

[0067] In a specific implementation, step S2 includes:

[0068] S211, performing an erase operation on the area to be erased according to the erase instruction;

[0069] S212, performing a refresh programming operation on the target memory cell array to correct the threshold voltages of the memory cells corresponding to the target memory cell array.

[0070] Specifically, since the fault tolerance of the target memory cell array is higher than that of the basic memory cell array, when the area to be erased corresponding to the erase instruction is located on the target physical block, after performing the erase operation on the area to be erased, a refresh programming operation must be performed on the target memory cell array to correct the threshold voltage of the memory cell corresponding to the target memory cell array, ensure the accuracy of the data in the target memory cell array, correct the tiny charge errors caused by interference, reduce the cumulative effect of interference, increase the reliability and service life of the non-volatile memory, and improve the overall performance of the non-volatile memory.

[0071] In a specific implementation, the regions in the basic memory cell array correspond to a plurality of preset division rules, and the regions in the basic memory cell array determine the corresponding target division rules based on the interference degree of the target physical block, so as to obtain a plurality of first sub-regions of the same region size, wherein the interference degree represents the maximum limit to which the threshold voltage of the basic memory cell array remains stable during the erasing operation of the target physical block;

[0072] The erasing method further includes: in response to powering on again, determining a current first sub-region in the basic memory cell array based on a preset determination method.

[0073] like Figure 3 As shown, step S2 includes:

[0074] S221, in response to the area to be erased being located in the basic storage cell array, performing an erase operation on the area to be erased;

[0075] S222, obtaining a current first sub-region in the basic memory cell array; wherein the current first sub-region represents a first sub-region where a refresh programming operation is to be performed;

[0076] S223, executing a refresh programming operation of the current first sub-region;

[0077] S224, executing a refresh programming operation of the target memory cell array;

[0078] S225: Take the next first sub-region of the current first sub-region as the new current first sub-region, and return to step S1.

[0079] Specifically, since the basic memory cell array has relatively low requirements for data accuracy, but it is also necessary to avoid storage data errors as much as possible, in order to balance the elimination of interference and execution time, each time an erase operation is performed on the target physical block, in addition to performing a refresh programming operation on the target memory cell array, a refresh programming operation is also performed on a portion of the area in the basic memory cell array.

[0080] Among them, through pre-setting a plurality of basic memory cell array division rules, for example, the division rule can be to divide the basic memory cell array into two first sub-areas, or into four first sub-areas, or into eight first sub-areas, etc., and then by performing an erase operation test on the target physical block, the interference degree of the basic memory cell array resulting in data errors caused by changes in threshold voltage in multiple erase operation tests of the target physical block is determined, and the division rule of the basic memory cell array is determined according to the size of the interference degree to divide the basic memory cell array into a plurality of first sub-areas, and each time an erase operation is performed, a refresh programming operation is performed on a first sub-area in the basic memory cell array.

[0081] In order to improve the execution efficiency of the entire erasing process, when the area to be erased is located in the basic storage cell array in the target physical block, after performing the erase operation on the area to be erased, first perform a refresh programming operation on the current first sub-area, then perform a refresh programming operation on the target storage cell array, and use the next first sub-area of ​​the current first sub-area as the current first sub-area, waiting for the next erase operation to perform the refresh programming operation, thereby ensuring that each first sub-area in the basic storage cell array can be refreshed and programmed, reducing the cumulative effect of interference and ensuring the overall performance of the non-volatile memory.

[0082] Among them, since the first sub-region where the refresh programming operation was performed last time cannot be known after power failure, a preset determination method (for example, a random selection method) can be used to determine a random first sub-region in the basic storage cell array as the current first sub-region, and starting with the current first sub-region, each time an erase operation is performed, a refresh programming operation is performed on a first sub-region in turn.

[0083] For example, after multiple erasing operation tests on the target physical block, it is determined that performing a refresh programming operation on one quarter of the basic storage cell array during each erasing operation can effectively reduce the cumulative effect of interference, so the division rule of the basic storage cell can be determined as dividing the basic storage cell into four first sub-areas A1, A2, A3, and A4. When the power is turned on again, the current first sub-area is randomly determined to be A3, and then when an erase instruction is received that the area to be erased is located in the basic storage cell array, after performing an erase operation on the area to be erased, a refresh programming operation is performed on the first sub-area A3, and then a refresh programming operation is performed on the target storage cell array, and A4 is taken as the current first sub-area. When the erase instruction is received next time, a refresh programming operation is performed on A4, thereby performing refresh programming operations in sequence of A3→A4→A1→A2→A3, so as to effectively reduce the cumulative effect of interference and avoid the situation where data errors in the basic storage cell array occur.

[0084] In a specific embodiment, Figure 4 As shown, step S2 includes:

[0085] S231, in response to the area to be erased being located in the target memory cell array, performing an erase operation on the area to be erased;

[0086] S232, executing a refresh programming operation of the target memory cell array;

[0087] S233, obtaining a current first sub-region in the basic storage cell array; wherein the current first sub-region represents a first sub-region where a refresh programming operation is to be performed;

[0088] S234, executing a refresh programming operation of the current first sub-region;

[0089] S235: Take the next first sub-region of the current first sub-region as the new current first sub-region, and return to step S1.

[0090] Specifically, in order to improve the execution efficiency of the entire erasing process, when the area to be erased is located in the target memory cell array in the target physical block, after performing the erase operation on the area to be erased, first perform a refresh programming operation on the target memory cell array, then perform a refresh programming operation on the current first sub-area, and use the next first sub-area of ​​the current first sub-area as the current first sub-area, waiting for the next erase operation to perform the refresh programming operation, thereby ensuring that each first sub-area in the basic memory cell array can be refreshed and programmed, reducing the cumulative effect of interference, and ensuring the overall performance of the non-volatile memory. The specific implementation principle can be found in the relevant description of the aforementioned embodiment, which will not be repeated here.

[0091] If the target memory cell array includes multiple different memory arrays, each time the refresh programming operation of the target memory cell array is performed, the refresh programming operation may be performed on each memory array, or the refresh programming operation may be performed on only one type of memory array each time. Of course, considering that the target memory cell array has a very high requirement for fault tolerance, and the time required for the target memory cell array to perform refresh programming is very short, it is safest to perform the refresh programming operation on each memory array each time.

[0092] For example, the target memory cell array includes a serial flash memory discoverable parameter storage array and a security register storage array. When the refresh programming operation of the target memory cell array is currently executed, the refresh programming operation can be performed only on the serial flash memory discoverable parameter storage array. When the refresh programming operation of the target memory cell array is executed next time, the refresh programming operation can be performed only on the security register storage array, and the cycle is repeated. Alternatively, the refresh programming operation can be performed on the serial flash memory discoverable parameter storage array and the security register storage array each time the refresh programming operation of the target memory cell array is executed.

[0093] In a specific implementation, the non-volatile memory further includes a plurality of initial physical blocks; the initial physical blocks are physical blocks in the non-volatile memory other than the target physical blocks;

[0094] The erase method also includes:

[0095] S3. In response to the first physical block being an initial physical block, performing an erase operation on the area to be erased according to an erase instruction, and performing a refresh program operation on the initial physical block.

[0096] Specifically, the target memory cell array is usually only set on one physical block in the non-volatile memory, and the other physical blocks are still the initial physical blocks that only include the basic memory cell array. In order to ensure the accuracy of the data stored in the basic memory cell array on the initial physical block, after the initial physical block is erased, a refresh programming operation is also performed on the initial physical block to correct the threshold voltage of the basic memory cell array on the initial physical block, effectively reduce the influence of phenomena such as well interference and program interference, and ensure the effectiveness of data storage and the accuracy of operation.

[0097] Among them, each time a refresh programming operation is performed on the initial physical block, the refresh programming operation can be performed only on the current second sub-region in the initial physical block, and the next second sub-region can be used as the current second sub-region. The division method of the second sub-region can be determined by performing multiple erase operation tests on the initial physical block. The specific implementation principle can be found in the relevant description of the first sub-region in the aforementioned embodiment, and will not be repeated here.

[0098] In a specific example, if Figure 5As shown, after receiving the erase instruction, it is determined whether the area to be erased in the erase instruction is located on the target physical block. If not, the erase operation is performed on the area to be erased on the initial physical block, and the refresh programming operation of the initial physical block is performed. If so, it is determined whether the area to be erased is located on the target storage cell array of the target physical block. If so, the erase operation is performed on the area to be erased on the target storage cell array, and the refresh programming operation of the target storage cell array is performed, and then the refresh programming operation is performed on the basic storage cell array. If not, the erase operation is performed on the area to be erased on the basic storage cell array, and the refresh programming operation of the basic storage cell array is performed, and then the refresh programming operation is performed on the target storage cell array.

[0099] In this embodiment, a target memory cell array composed of memory cells with special functions and a basic memory cell array are planned in the same physical block, and the bit lines and well areas are shared, so as to reduce the area and cost of the peripheral circuits. A refresh programming operation is performed when an erase command is executed to correct the threshold voltage of the memory cell, thereby ensuring the accuracy of the data stored in the target memory cell array, correcting the tiny charge errors caused by interference, and reducing the cumulative effect of interference, so that the non-volatile memory has an advanced security function of being able to store important data without increasing the size of the non-volatile memory. At the same time, the influence of well interference and program interference and the like can be effectively reduced, thereby ensuring the accuracy of data storage, improving the reliability and service life of the non-volatile memory, and enhancing the overall performance of the non-volatile memory to meet the needs of users.

[0100] Example 2

[0101] In a specific embodiment of the present disclosure, a non-volatile memory erasing system is provided, wherein the non-volatile memory includes a target physical block, the target physical block includes a basic memory cell array and a target memory cell array, wherein the memory cells in the target memory cell array are memory cells with special functions other than the basic memory cells, and the basic memory cell area and the target memory cell array share a bit line and a well area;

[0102] like Figure 6 As shown, the erasure system includes a determination module 100 and an execution module 200;

[0103] The determination module 100 is used to determine the first physical block corresponding to the area to be erased according to the erase instruction in response to receiving the erase instruction;

[0104] The execution module 200 is used for executing an erase operation of the to-be-erased area according to an erase instruction in response to the first physical block being a target physical block, and executing a refresh programming operation of the target physical block to correct the threshold voltage of the storage cells in the target physical block.

[0105] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0106] In this embodiment, a target memory cell array composed of memory cells with special functions and a basic memory cell array are planned in the same physical block, and the bit lines and well areas are shared, so as to reduce the area and cost of the peripheral circuits. A refresh programming operation is performed when an erase command is executed to correct the threshold voltage of the memory cell, thereby ensuring the accuracy of the data stored in the target memory cell array, correcting the tiny charge errors caused by interference, and reducing the cumulative effect of interference, so that the non-volatile memory has an advanced security function of being able to store important data without increasing the size of the non-volatile memory. At the same time, the influence of well interference and program interference and the like can be effectively reduced, thereby ensuring the accuracy of data storage, improving the reliability and service life of the non-volatile memory, and enhancing the overall performance of the non-volatile memory to meet the needs of users.

[0107] Example 3

[0108] In a specific embodiment of the present disclosure, a non-volatile memory is provided. The non-volatile memory includes the erasing system described in any of the above embodiments.

[0109] Among them, the non-volatile memory includes Nor Flash.

[0110] In this embodiment, a target memory cell array composed of memory cells with special functions and a basic memory cell array are planned in the same physical block, and the bit lines and well areas are shared, so as to reduce the area and cost of the peripheral circuits. A refresh programming operation is performed when an erase command is executed to correct the threshold voltage of the memory cell, thereby ensuring the accuracy of the data stored in the target memory cell array, correcting the tiny charge errors caused by interference, and reducing the cumulative effect of interference, so that the non-volatile memory has an advanced security function of being able to store important data without increasing the size of the non-volatile memory. At the same time, the influence of well interference and program interference and the like can be effectively reduced, thereby ensuring the accuracy of data storage, improving the reliability and service life of the non-volatile memory, and enhancing the overall performance of the non-volatile memory to meet the needs of users.

[0111] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A method for erasing a non-volatile memory, characterized in that: The nonvolatile memory includes a target physical block, the target physical block includes a basic memory cell array and a target memory cell array, wherein the memory cells in the target memory cell array are memory cells with special functions other than the basic memory cells, and the basic memory cell array and the target memory cell array share a bit line and a well area; The erasing method comprises: In response to receiving an erase instruction, determining a first physical block corresponding to the area to be erased according to the erase instruction; In response to the first physical block being the target physical block, an erase operation of the to-be-erased area is performed according to the erase instruction, and a refresh program operation of the target physical block is performed to correct the threshold voltage of the storage cells in the target physical block.

2. The erasing method according to claim 1, characterized in that: The step of performing an erase operation on the to-be-erased area according to the erase instruction and performing a refresh programming operation on the target physical block comprises: Execute an erasing operation of the area to be erased according to the erasing instruction; A refresh program operation of the target memory cell array is performed to correct the threshold voltages of the memory cells corresponding to the target memory cell array.

3. The erasing method according to claim 1, characterized in that: The regions in the basic memory cell array correspond to a plurality of preset division rules, and the regions in the basic memory cell array determine the corresponding target division rules based on the interference degree of the target physical block, so as to obtain a plurality of first sub-regions of the same region size, wherein the interference degree represents a maximum limit at which the threshold voltage of the basic memory cell array remains stable during the erasing operation of the target physical block; The step of performing an erase operation on the to-be-erased area according to the erase instruction and performing a refresh programming operation on the target physical block comprises: In response to the area to be erased being located in the basic memory cell array, performing an erase operation on the area to be erased; Acquire a current first sub-region in the basic memory cell array; wherein the current first sub-region represents the first sub-region where a refresh programming operation is to be performed; Execute a refresh programming operation of the current first sub-region; Executing a refresh programming operation of the target memory cell array; The next first sub-region of the current first sub-region is used as the new current first sub-region, and the step of determining the first physical block corresponding to the area to be erased according to the erase instruction in response to receiving the erase instruction is returned to be executed.

4. The erasing method according to claim 1, characterized in that: The regions in the basic memory cell array correspond to a plurality of preset division rules, and the regions in the basic memory cell array determine the corresponding target division rules based on the interference degree of the target physical block, so as to obtain a plurality of first sub-regions of the same region size, wherein the interference degree represents a maximum limit at which the threshold voltage of the basic memory cell array remains stable during the erasing operation of the target physical block; The step of performing an erase operation on the to-be-erased area according to the erase instruction and performing a refresh programming operation on the target physical block comprises: In response to the area to be erased being located in the target memory cell array, performing an erase operation on the area to be erased; Executing a refresh programming operation of the target memory cell array; Acquire a current first sub-region in the basic memory cell array; wherein the current first sub-region represents the first sub-region where a refresh programming operation is to be performed; Execute a refresh programming operation of the current first sub-region; The next first sub-region of the current first sub-region is used as the new current first sub-region, and the step of determining the first physical block corresponding to the area to be erased according to the erase instruction in response to receiving the erase instruction is returned to be executed.

5. The erasing method according to claim 3 or 4, characterized in that: The erasing method further comprises: In response to powering on again, the current first sub-region in the basic memory cell array is determined based on a preset determination method.

6. The erasing method according to any one of claims 2 to 4, characterized in that: The target storage cell array includes at least one of a serial flash memory discoverable parameter storage array, a status register storage array, a unique identification number storage array, and a security register storage array; and / or, The step of performing a refresh programming operation on the target memory cell array comprises: The refresh programming operation is performed on at least one of the serial flash memory discoverable parameter storage array, the status register storage array, the unique identification number storage array, and the security register storage array.

7. The erasing method according to claim 1, characterized in that: The non-volatile memory further includes a plurality of initial physical blocks; the initial physical blocks are physical blocks in the non-volatile memory other than the target physical blocks; The erasing method further comprises: In response to the first physical block being the initial physical block, an erase operation of the to-be-erased area is performed according to the erase instruction, and a refresh program operation of the initial physical block is performed.

8. A non-volatile memory erasing system, characterized in that: The nonvolatile memory includes a target physical block, the target physical block includes a basic memory cell array and a target memory cell array, wherein the memory cells in the target memory cell array are memory cells with special functions other than the basic memory cells, and the basic memory cell area and the target memory cell array share a bit line and a well area; The erasure system includes a determination module and an execution module; The determination module is used for determining the first physical block corresponding to the area to be erased according to the erase instruction in response to receiving the erase instruction; The execution module is used for executing an erase operation of the to-be-erased area according to the erase instruction in response to the first physical block being the target physical block, and executing a refresh programming operation of the target physical block to correct the threshold voltage of the storage unit in the target physical block.

9. A non-volatile memory, characterized in that: The non-volatile memory comprises an erasure system as claimed in claim 8.

10. The nonvolatile memory according to claim 9, characterized in that: The non-volatile memory includes NorFlash.

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