Repair analysis method, device and computer equipment for chip failure storage unit

Abstract

The present application relates to a method, device, computer equipment, computer-readable storage medium and computer program product for repairing and analyzing failed memory cells of a chip. The method comprises: obtaining the number of row spares of row memory cells and the number of column spares of column memory cells of a memory matrix; for each failed memory cell in the memory matrix, counting the number of failed memory cells in the left area and the upper area in the same row as the failed memory cell, and determining the first target cell among all failed memory cells; for each failed memory cell in the memory matrix, counting the number of failed memory cells in the right area and the lower area in the same row as the failed memory cell, and determining the second target cell among all failed memory cells; according to the first target cell, the second target cell, the number of row spares and the number of column spares, determining the judgment result of whether to run the repair analysis algorithm on the memory matrix. The use of this method can reduce computational redundancy and improve the efficiency of repair analysis.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a method, device, computer equipment, computer-readable storage medium and computer program product for repairing and analyzing a failed chip storage unit. Background Art

[0002] In the chip production process, ATE equipment is used to perform quality inspection on the produced IC chips to distinguish qualified from unqualified chips and ensure product quality and reliability. Modern DDR memory circuits contain redundant spare row and column cells. Through repair operations, these spare memory cells replace the rows or columns of failed memory cells to achieve the goal of zero failure. The Repair Analysis function reads the information of failed memory cells in the memory from the AFM and finds a way to replace the failed row or column with spare row and column cells through analysis algorithms. If no replacement method is found, it is concluded that it cannot be repaired.

[0003] Traditional repair algorithms, such as the Fault Driven algorithm, need to traverse all failed storage units, which may result in huge computational complexity and time consumption. Existing early termination judgment methods in the industry, such as simple judgment based on spare row and column resources, although the amount of calculation is small, the judgment range is wide and cannot accurately predict the scene that cannot be repaired.

[0004] Therefore, there is an urgent need for a more sophisticated chip failed storage unit repair analysis method, device, computer equipment, computer readable storage medium and computer program product that can reduce computational redundancy and improve repair analysis efficiency. Summary of the invention

[0005] Based on this, it is necessary to provide a chip failure storage unit repair analysis method, device, computer equipment, computer readable storage medium and computer program product that can reduce computational redundancy and improve repair analysis efficiency in response to the above technical problems.

[0006] In a first aspect, the present application provides a method for repairing and analyzing a failed memory cell of a chip, comprising:

[0007] Obtaining the row spare number of the row storage unit and the column spare number of the column storage unit of the memory matrix;

[0008] For each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell are counted to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, a first target cell among all failed storage cells is determined;

[0009] For each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage cell, a second target cell among all failed storage cells is determined;

[0010] A determination result of whether to execute a repair analysis algorithm on the memory matrix is ​​determined according to the first target unit, the second target unit, the row spare number, and the column spare number.

[0011] In one embodiment, the determining of the first target unit among all failed storage units based on the first statistical result corresponding to each failed storage unit includes:

[0012] For each failed storage unit, when the first statistical result corresponding to the failed storage unit indicates that the number of failed storage units in the left area of ​​the same row as the failed storage unit is 0, and the number of failed storage units in the upper area of ​​the same column as the failed storage unit is 0, the failed storage unit is determined as the first target unit.

[0013] In one embodiment, the determining the second target unit among all failed storage units based on the second statistical result corresponding to each failed storage unit includes:

[0014] For each failed storage cell, when the second statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the right area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the lower area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the second target cell.

[0015] In one embodiment, the determining of whether to run a repair analysis algorithm on the memory matrix according to the first target unit, the second target unit, the row spare number, and the column spare number includes:

[0016] Taking the intersection of a first set consisting of all first target units and a second set consisting of all second target units to obtain a third set;

[0017] A determination result of whether to execute a repair analysis algorithm on the memory matrix is ​​determined according to the third set, the row spare quantity, and the column spare quantity.

[0018] In one embodiment, the determining of whether to run a repair analysis algorithm on the memory matrix according to the third set, the row spare number, and the column spare number includes:

[0019] Remove the failed storage units included in the third set from the first set, and determine a first number of failed storage units in the first set;

[0020] removing the failed storage units included in the third set from the second set, and determining a second number of failed storage units in the second set;

[0021] Determine a minimum value between the first number and the second number, and when the minimum value is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix;

[0022] When the minimum value is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0023] In one embodiment, the determining of whether to run a repair analysis algorithm on the memory matrix according to the third set, the row spare number, and the column spare number includes:

[0024] Determine a third number of failed storage units in the third set, and when the third number is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix;

[0025] When the third number is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0026] In a second aspect, the present application also provides a chip failure storage unit repair analysis device, comprising:

[0027] A data acquisition module, used for acquiring the row spare quantity of the row storage unit and the column spare quantity of the column storage unit of the memory matrix;

[0028] A statistical module, for counting, for each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell, to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, determine a first target cell among all failed storage cells;

[0029] The statistical module is further used to count the number of failed storage cells in the right area of ​​the same row as the failed storage cell and the number of failed storage cells in the lower area of ​​the same column as the failed storage cell for each failed storage cell in the memory matrix to obtain a second statistical result, and determine a second target cell among all failed storage cells based on the second statistical result corresponding to each failed storage cell;

[0030] The analysis module is used to determine whether to run a repair analysis algorithm on the memory matrix according to the first target unit, the second target unit, the row spare number and the column spare number.

[0031] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0032] Obtaining the row spare number of the row storage unit and the column spare number of the column storage unit of the memory matrix;

[0033] For each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell are counted to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, a first target cell among all failed storage cells is determined;

[0034] For each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage cell, a second target cell among all failed storage cells is determined;

[0035] A determination result of whether to execute a repair analysis algorithm on the memory matrix is ​​determined according to the first target unit, the second target unit, the row spare number, and the column spare number.

[0036] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0037] Obtaining the row spare number of the row storage unit and the column spare number of the column storage unit of the memory matrix;

[0038] For each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell are counted to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, a first target cell among all failed storage cells is determined;

[0039] For each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage cell, a second target cell among all failed storage cells is determined;

[0040] A determination result of whether to execute a repair analysis algorithm on the memory matrix is ​​determined according to the first target unit, the second target unit, the row spare number, and the column spare number.

[0041] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0042] Obtaining the row spare number of the row storage unit and the column spare number of the column storage unit of the memory matrix;

[0043] For each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell are counted to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, a first target cell among all failed storage cells is determined;

[0044] For each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage cell, a second target cell among all failed storage cells is determined;

[0045] A determination result of whether to execute a repair analysis algorithm on the memory matrix is ​​determined according to the first target unit, the second target unit, the row spare number, and the column spare number.

[0046] The above-mentioned chip failed storage unit repair analysis method, device, computer equipment, computer readable storage medium and computer program product can quickly identify the unrepairable scenario by counting the number of failed storage units in a specific area (upper left and lower right) of the failed storage unit, thereby avoiding running the complete repair analysis algorithm and saving time and computing resources. The traditional repair algorithm needs to traverse all failed storage units, which will lead to a huge amount of calculation in a large-scale memory matrix. The early termination strategy reduces unnecessary calculations, especially when facing a large number of failed storage units. This method can significantly reduce the amount of calculation. This method can quickly determine whether the memory matrix is ​​repairable without sacrificing too much accuracy, thereby avoiding invalid calculations. By accurately identifying which failed storage units cannot be repaired by spare resources, spare row storage units and column storage units can be more effectively allocated to improve resource utilization. By improving the efficiency and accuracy of repair analysis, qualified and unqualified chips can be identified more quickly, thereby improving the overall product quality and reliability. Reducing invalid calculations and improving the efficiency of repair analysis can reduce the time cost and computing cost in the production process, thereby reducing the overall production cost. To sum up, the technical effect of the present invention is that a new repair analysis method is used to improve the repair analysis efficiency in the chip production process, reduce calculation redundancy, and maintain a high judgment accuracy, which is of great significance for improving product quality and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 This is an application environment diagram of a chip failure storage unit repair analysis method in one embodiment;

[0049] Figure 2 A schematic diagram of a process flow of a chip failure storage unit repair and analysis method in one embodiment;

[0050] Figure 3 A schematic diagram of a flow chart of a method for repairing and analyzing a failed chip storage unit in another embodiment;

[0051] Figure 4 It is a flowchart of a method for repairing and analyzing a failed memory unit of a chip in another embodiment;

[0052] Figure 5A schematic diagram of each failed storage unit in the memory matrix in the most detailed embodiment;

[0053] Figure 6 It is a structural block diagram of a chip failure storage unit repair analysis device in one embodiment;

[0054] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0055] In the modern electronic manufacturing industry, chip automated test equipment (ATE) plays a vital role. The main function of ATE is to perform quality inspection on the produced integrated circuit (IC) chips to ensure product quality and reliability. Through ATE, qualified chips can be distinguished from unqualified chips, thereby ensuring the performance and stability of the final product. With the development of technology, modern DDR memory circuit design contains a certain number of redundant spare storage row and column units. The existence of these spare resources enables the spare storage cells to replace the rows or columns of the faulty cells through repair operations when a faulty cell appears in the memory, achieving the so-called "0 fault" goal. The repair analysis function in ATE is to read the information of the failed storage cells in the memory from the automatic failure memory (AFM) and try to find a way to replace the faulty row or column with the spare storage row and column cells through the analysis algorithm. If the analysis program cannot find a suitable alternative, it will conclude that it cannot be repaired. This process plays a decisive role in determining whether the memory chip is repairable and how to repair it.

[0056] Typical repair algorithms in the industry, such as the Fault Driven algorithm, need to traverse all failed storage units, which will result in huge computational workload and time consumption when the memory matrix is ​​large or the number of failed storage units is large. The efficiency problem of this algorithm is particularly prominent in large-scale production because it directly affects production efficiency and cost. In order to solve the efficiency problem of traditional repair algorithms, the industry has proposed early termination strategies. These strategies aim to avoid running the full repair algorithm by quickly judging whether the current distribution of failed storage units is unrepairable, saving time and computing resources. However, this early termination judgment method has the problem of insufficient accuracy. Although they have a small amount of calculation, the judgment range is too broad and cannot accurately predict the unrepairable scenario. Existing early termination methods, such as simple judgments based on spare row and column resources, can quickly draw conclusions, but the accuracy of such judgments is low. This means that even if it is judged to be repairable, after actually running the repair analysis algorithm, it may still be concluded that it is unrepairable, resulting in a waste of resources. In order to improve the accuracy of early termination judgment, methods based on fault grouping are proposed. These methods group single or multiple faults that share the same row address or column address into fault groups, and then judge whether it is repairable based on the number of fault groups and the number of allocated slots of spare resources. However, these methods are inefficient in practice because they involve complex binary tree traversal and merging operations, resulting in long computation time.

[0057] In view of the limitations of existing traditional technologies, this application proposes a new early termination strategy, aiming to provide a more sophisticated and low-computation fast judgment method. This method significantly reduces the amount of calculation while maintaining high judgment accuracy, thus improving the efficiency of repair analysis.

[0058] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0059] The chip failure storage unit repair analysis method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, the server 102 communicates with the server 104 via a network. The data storage system can store data that the server 104 needs to process. The data storage system can be integrated on the server 104, or placed on the cloud or other network servers.

[0060] The server 104 obtains the row spare number of the row storage units and the column spare number of the column storage units of the memory matrix; using the server 102, for each failed storage unit in the memory matrix, counts the number of failed storage units in the left area of ​​the same row as the failed storage unit and the number of failed storage units in the upper area of ​​the same column as the failed storage unit to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage unit, determines the first target unit among all failed storage units; for each failed storage unit in the memory matrix, counts the number of failed storage units in the right area of ​​the same row as the failed storage unit and the number of failed storage units in the lower area of ​​the same column as the failed storage unit to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage unit, determines the second target unit among all failed storage units; the server 104 determines the judgment result of whether to run the repair analysis algorithm on the memory matrix according to the first target unit, the second target unit, the row spare number and the column spare number.

[0061] Among them, server 102 / server 104 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services.

[0062] In an exemplary embodiment, Figure 2 As shown, a method for repairing and analyzing a failed memory cell of a chip is provided, and the method is applied to Figure 1 The server 104 in the example is used as an example to illustrate the method, which includes the following steps S202 to S206. Among them:

[0063] Step S202, obtaining the row spare quantity of the row storage units and the column spare quantity of the column storage units of the memory matrix.

[0064] Specifically, in chip automated test equipment (ATE), before starting the repair analysis process for the memory matrix, it is necessary to clearly know the specific configuration of the spare resources in the memory matrix. Spare resources refer to the row storage cells and column storage cells preset in the DDR memory circuit that can be used to replace the faulty cells. This step is the basis for effective repair analysis because it is directly related to whether the faulty cells in the memory matrix can be repaired through spare resources.

[0065] It is necessary to know the number of spare cells in each row and column of the memory matrix to replace the failed cells when they are detected to ensure the integrity and functionality of the memory. The memory matrix is ​​a two-dimensional structure composed of rows and columns, where each cell has the potential to become a failure point. Knowing the number of spare cells in rows and columns helps to analyze and plan how to use these spare resources to repair the failure.

[0066] During the repair analysis process, it is necessary to decide how to allocate row and column storage units based on the location of the failed storage unit and the distribution of spare resources. This step requires a clear understanding of the spare resources of the memory matrix in order to make reasonable decisions in the subsequent repair analysis.

[0067] Step S204, for each failed memory cell in the memory matrix, count the number of failed memory cells in the left area of ​​the same row as the failed memory cell, and the number of failed memory cells in the upper area of ​​the same column as the failed memory cell, to obtain a first statistical result, and based on the first statistical result corresponding to each failed memory cell, determine the first target cell among all the failed memory cells.

[0068] For each failed memory cell in the memory matrix, the number of failed memory cells in the right area of ​​the same row as the failed memory cell and the number of failed memory cells in the lower area of ​​the same column as the failed memory cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed memory cell, a second target cell among all failed memory cells is determined.

[0069] Specifically, assuming that the intersection point at the upper left corner of the memory matrix is ​​used as the origin of the coordinate system, for each failed storage cell, check the number of all failed storage cells on the left side (i.e., with a smaller X value) of its same row. This statistical result reflects the fault density on the left side of each failed storage cell. Similarly, for each failed storage cell, check the number of all failed storage cells above (i.e., with a smaller Y value) of its same column. This statistical result reflects the fault density above each failed storage cell. Based on these two statistical results, determine the first target cells, which are cells that do not have other failed storage cells on their left and above areas.

[0070] For each failed memory cell, check the number of all failed memory cells to the right of its same row (i.e., with a larger X value). This statistical result reflects the fault density to the right of each failed memory cell. For each failed memory cell, check the number of all failed memory cells below its same column (i.e., with a larger Y value). This statistical result reflects the fault density below each failed memory cell. Based on these two statistical results, determine the second target cells. These cells are those that do not have other failed memory cells to their right and in the area below them.

[0071] Step S206, determining whether to run a repair analysis algorithm on the memory matrix according to the first target unit, the second target unit, the number of spare rows, and the number of spare columns.

[0072] Specifically, based on the first target unit, the second target unit, the number of row spares, and the number of column spares, the repairability of the memory matrix can be judged. If the number of the first target unit and the second target unit exceeds the number of spare resources, the memory matrix is ​​likely to be unable to be fully repaired. This is because the spare resources are not enough to replace all the faulty units.

[0073] By accurately identifying which failed storage cells are most likely to require spare resources, limited row and column storage cells can be allocated more efficiently. Combining the statistics of failed storage cells with the number of spare resources, more accurate repair decisions can be made to avoid ineffective repair attempts.

[0074] In the above-mentioned chip failed memory cell repair analysis method, by counting the number of failed memory cells in a specific area (upper left and lower right) of the failed memory cells, the unrepairable scenario can be quickly identified, thereby avoiding running the complete repair analysis algorithm and saving time and computing resources. The traditional repair algorithm needs to traverse all failed memory cells, which will result in a huge amount of calculation in a large-scale memory matrix. The early termination strategy reduces unnecessary calculations, especially when facing a large number of failed memory cells. This method can significantly reduce the amount of calculation. This method can quickly determine whether the memory matrix is ​​repairable without sacrificing too much accuracy, thereby avoiding invalid calculations. By accurately identifying which failed memory cells cannot be repaired by spare resources, spare row memory cells and column memory cells can be more effectively allocated to improve resource utilization. By improving the efficiency and accuracy of repair analysis, qualified and unqualified chips can be identified more quickly, thereby improving the overall product quality and reliability. Reducing invalid calculations and improving the efficiency of repair analysis can reduce the time cost and computing cost in the production process, thereby reducing the overall production cost.

[0075] In an exemplary embodiment, determining a first target unit among all failed storage units based on a first statistical result corresponding to each failed storage unit includes:

[0076] For each failed storage cell, when the first statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the left area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the upper area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the first target cell.

[0077] Specifically, if the number of failed storage cells in the left area of ​​the same row is 0, it means that there are no other failed storage cells in the same row of the currently considered failed storage cell and in the area to its left. If the number of failed storage cells in the upper area of ​​the same column is 0, it means that there are no other failed storage cells in the same column of the currently considered failed storage cell and in the area above it.

[0078] When a failed storage cell meets the above two conditions, it is determined as the first target cell. Such a cell has no other failed storage cells in the left side of its same row and in the upper area of ​​the same column. The first target cell represents the cells that may be easier to repair during the repair process because there are no other failed storage cells around them, so there is no need to consider complex repair strategies to solve the mutual influence between multiple failed storage cells. On the other hand, these cells are also critical because if they cannot be repaired, it may affect the repair status of the entire memory matrix because they have no adjacent failed storage cells to form a fault group, thus requiring more spare resources to be processed separately.

[0079] In summary, the process of determining the first target unit is a screening process, which helps to identify those units that may need special attention during the repair process based on the geographical location of the failed storage unit and the distribution of surrounding failed storage units, thereby improving the repair efficiency and success rate.

[0080] In an exemplary embodiment, determining the second target unit among all failed storage units based on the second statistical result corresponding to each failed storage unit includes:

[0081] For each failed storage cell, when the second statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the right area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the lower area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the second target cell.

[0082] Specifically, the second target cell refers to a specific failed storage cell in the memory matrix that has no other failed storage cells in the right area of ​​the same row and the lower area of ​​the same column. Specifically:

[0083] The number of failed memory cells in the right region of the same row being 0 means that there are no other failed memory cells in the same row as the failed memory cell currently being considered and in the region to its right.

[0084] The number of failed memory cells in the region below the same column being 0 means that there are no other failed memory cells in the same column as the failed memory cell currently considered and in the region below it.

[0085] These cells have no other failed memory cells in the area to their right and below, which may indicate that they are relatively isolated in the memory matrix and such cells may be easier to handle individually. By identifying these isolated failed memory cells, their repair strategies can be prioritized because they may not require complex spare resource allocation strategies.

[0086] In terms of technical implementation, the process of determining the second target cell involves counting the number of failed storage cells around each failed storage cell in the memory matrix. This process can be achieved through the following steps:

[0087] Traverse each failed storage unit: Traverse each failed storage unit in the memory matrix. For each failed storage unit, count the number of failed storage units in the right area of ​​the same row and the area below the same column. If there are no other failed storage units in the right area and the area below a failed storage unit, it meets the conditions for becoming the second target unit. Mark the failed storage unit that meets the conditions as the second target unit to facilitate subsequent repair analysis and processing.

[0088] In this embodiment, through the above steps, the second target cell can be effectively identified from all failed storage cells, providing important reference information for the repair analysis of the memory matrix. This method helps to improve the efficiency and success rate of memory repair, especially when facing complex failure modes.

[0089] In an exemplary embodiment, determining whether to run a repair analysis algorithm on a memory matrix according to the first target unit, the second target unit, the number of spare rows, and the number of spare columns includes:

[0090] Taking the intersection of a first set consisting of all first target units and a second set consisting of all second target units to obtain a third set;

[0091] A determination result of whether to run a repair analysis algorithm on the memory matrix is ​​determined based on the third set, the number of spare rows, and the number of spare columns.

[0092] The first set refers to all first target units. The second set refers to all second target units. The third set refers to the intersection of the first set and the second set, that is, the set of failed storage units that belong to both the first target unit and the second target unit.

[0093] Specifically, the failed memory cells in the third set are those that have no other failed memory cells in the surrounding (left, right, top, bottom) areas. These cells are relatively isolated in the memory matrix and may be easier to repair because they do not require complex spare resource allocation strategies.

[0094] In this embodiment, the possibility of repair is evaluated by identifying relatively isolated failed storage cells in the memory matrix. By calculating the intersection of the first target cell and the second target cell and combining the number of spare resources, it can be effectively determined whether the memory matrix is ​​repairable. This method not only improves the efficiency of repair analysis, but also optimizes the allocation of resources, which is a key step in achieving efficient memory repair.

[0095] In an exemplary embodiment, Figure 3 As shown, according to the third set, the number of spare rows and the number of spare columns, the judgment result of determining whether to run the repair analysis algorithm on the memory matrix includes:

[0096] Step S302, removing the failed storage units included in the third set from the first set, and determining a first number of failed storage units in the first set;

[0097] Step S304, removing the failed storage units included in the third set from the second set, and determining a second number of failed storage units in the second set;

[0098] Step S306, determining the minimum value between the first number and the second number, and when the minimum value is greater than the sum of the row spare number and the column spare number, determining that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; and there is no need to continue running the repair analysis algorithm on the memory matrix;

[0099] Step S308: When the minimum value is not greater than the sum of the number of spare rows and the number of spare columns, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0100] Specifically, since the third set is the intersection of the first set (all first target units) and the second set (all second target units), it includes failed storage units that meet the conditions of both the first target unit and the second target unit.

[0101] Therefore, after removing the failed storage units included in the third set from the first set, the number of remaining failed storage units is used as the first number and is counted by the first counter.

[0102] After removing the failed storage units included in the third set from the second set, the number of remaining failed storage units is used as the second number and is counted by the second counter.

[0103] The minimum value of the first number and the second number is determined, and the minimum value is compared with the sum of the row spare number and the column spare number. If the minimum value is greater than the sum of the row spare number and the column spare number, it means that even if all spare resources are used, all remaining failed storage cells cannot be covered. Therefore, the memory matrix is ​​determined to be unrepairable.

[0104] If the minimum value is not greater than the sum of the row spare number and the column spare number, it means that the existing spare resources are sufficient to cover all the remaining failed memory cells. Therefore, the memory matrix is ​​determined to be repairable.

[0105] In this embodiment, by accurately calculating the number of remaining failed storage units and comparing them with the spare resources, a clear basis for judgment is provided, thereby avoiding unnecessary repair attempts. By identifying which failed storage units must be repaired, limited spare resources can be allocated more effectively.

[0106] By calculating the number of remaining failed storage cells in the first and second sets after removing the third set, and comparing them with the spare resources, it is determined whether the memory matrix can be repaired. This method not only improves the efficiency and accuracy of repair analysis, but also optimizes the allocation of resources, which is a key step in achieving efficient memory repair. In this way, it can ensure that as many memory matrices as possible can be repaired under limited spare resources, thereby improving overall production efficiency and product quality.

[0107] In an exemplary embodiment, Figure 4 As shown, according to the third set, the number of spare rows and the number of spare columns, the judgment result of determining whether to run the repair analysis algorithm on the memory matrix includes:

[0108] Step S402, determining a third number of failed storage units in a third set, and when the third number is greater than the sum of the row spare number and the column spare number, determining that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; and there is no need to continue running the repair analysis algorithm on the memory matrix;

[0109] Step S404: when the third number is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0110] Specifically, first, it is necessary to determine the third number of failed storage units in the third set. The third number can be determined by using the intersection of the first set and the second set, or by directly counting using a third counter.

[0111] If the third number (i.e., the number of failed memory cells in the third set) is greater than the sum of the row spare number and the column spare number, this means that the existing spare resources are insufficient to cover all of these failed memory cells. In this case, the memory matrix is ​​determined to be unrepairable. This is because even if all spare rows and columns are used, all failed cells cannot be replaced.

[0112] If the third number is not greater than the sum of the row spare number and the column spare number, this means that the existing spare resources are sufficient to cover all these failed memory cells. In this case, the memory matrix is ​​determined to be repairable. This is because there are enough spare rows and columns to replace all failed cells.

[0113] In this embodiment, whether the memory matrix is ​​repairable is determined by directly comparing the number of failed storage cells (the third number) in the third set with the sum of the number of spare rows and the number of spare columns. This method is simple and direct, and can quickly make a repair decision, which helps to improve the efficiency and effect of memory repair. In this way, it is possible to reasonably decide which memory matrices are worth repairing and which are not worth repairing under limited spare resources, thereby improving overall production efficiency and reducing costs.

[0114] In one of the most detailed embodiments of this application, Figure 5 As shown, a schematic diagram of each failed storage unit in the memory matrix is ​​shown.

[0115] For the memory matrix shown in the figure, the two sides of the matrix are called X sides (rows) or Y sides (columns), assuming that the values ​​of the X side start from 0 and increase from top to bottom, and the values ​​of the Y side start from 0 and increase from left to right.

[0116] 1. The variable SpareRowN is the number of spare row resources of this memory matrix, and SpareColumnN is the number of spare column resources of this memory matrix.

[0117] 2. NnluCounter (No-No-Left-UpCounter) is the first counter, NnrdCounter (No-No-Right-DownCounter) is the second counter, and SingleCounter is the third counter. The variables of these three counters are initialized to 0. NnluCounter is used to count the number of failed storage cells in the memory matrix where there are no other failed storage cells in the left and upper regions only (i.e., the first number); NnrdCounter is used to count the number of failed storage cells in the memory matrix where there are no other failed storage cells in the right and lower regions only (i.e., the second number); SingleCounter is used to count the number of failed storage cells in the memory matrix where there are no other failed storage cells in the left, upper, right, and lower regions (i.e., the third number).

[0118] After determining the distribution of all failed storage cells in the memory matrix, traverse each failed storage cell and make the following judgments:

[0119] 1. Initialize the variables Nnlu (i.e., all the first target units in the first set above) and Nnrd (i.e., all the second target units in the second set above) to 0.

[0120] 2. Traverse the X and Y directions of each failed storage unit to see if there are other failed storage units with X or Y values ​​lower than the unit. If there are no such units, the unit belongs to the first target unit, and Nnlu is set to 1.

[0121] 3. Traverse the X and Y directions of each failed storage unit to see if there are other failed storage units with X or Y values ​​higher than the unit. If there are no such units, the unit belongs to the second target unit, and Nnrd is set to 1.

[0122] 4. If Nnlu is equal to 1 and Nnrd is equal to 0, NnluCounter is incremented by 1. The failed storage unit corresponding to NnluCounter is detailed in Figure 5 The circular logo shown;

[0123] If Nnlu is equal to 0 and Nnrd is equal to 1, NnrdCounter is incremented by 1. The failed storage unit corresponding to NnrdCounter is detailed in Figure 5 The hexagon logo shown;

[0124] If Nnlu is equal to 1 and Nnrd is equal to 1, SingleCounter increases by 1.

[0125] 5. After completing the traversal of all defective cells, determine when "Min (NnluCounter, NnrdCounter)" > "SpareRowN + SpareColumnN", that is, the minimum value between the two counters NnluCounter and NnrdCounter. If it is greater than the number of spare rows and columns of this memory matrix, it means that the spare resources are not enough to repair these defective cells, so it can be concluded that "the memory matrix cannot be repaired", and there is no need to run the repair analysis algorithm subsequently.

[0126] 6. When "SingleCounter" > "SpareRowN + SpareColumnN", that is, when the number of isolated points is greater than the number of spare rows and columns of the memory matrix, it is known that the spare resources are not enough to repair these defective units, so it can be concluded that "the memory matrix cannot be repaired", and there is no need to run the repair analysis algorithm subsequently.

[0127] 7. If the above steps cannot lead to the conclusion that "the memory matrix cannot be repaired", run the repair analysis algorithm to analyze.

[0128] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0129] Based on the same inventive concept, the embodiment of the present application also provides a chip failure storage unit repair analysis device for implementing the chip failure storage unit repair analysis method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the one or more chip failure storage unit repair analysis devices provided below can refer to the limitations of the chip failure storage unit repair analysis method above, and will not be repeated here.

[0130] In an exemplary embodiment, Figure 6 As shown, a repair analysis device for a chip failure storage unit is provided, comprising:

[0131] The data acquisition module 602 is used to acquire the number of spare rows of the row storage units and the number of spare columns of the column storage units of the memory matrix;

[0132] The statistical module 604 is used to count the number of failed storage cells in the left area of ​​the same row as the failed storage cell and the number of failed storage cells in the upper area of ​​the same column as the failed storage cell for each failed storage cell in the memory matrix, obtain a first statistical result, and determine a first target cell among all failed storage cells based on the first statistical result corresponding to each failed storage cell;

[0133] The statistical module 604 is further used to count the number of failed storage cells in the right area of ​​the same row as the failed storage cell and the number of failed storage cells in the lower area of ​​the same column as the failed storage cell for each failed storage cell in the memory matrix to obtain a second statistical result, and determine a second target cell among all failed storage cells based on the second statistical result corresponding to each failed storage cell;

[0134] The analysis module 606 is used to determine whether to run a repair analysis algorithm on the memory matrix according to the first target unit, the second target unit, the number of spare rows, and the number of spare columns.

[0135] In an exemplary embodiment, the statistical module 604 is also used to determine, for each failed storage unit, the failed storage unit as the first target unit when the first statistical result corresponding to the failed storage unit indicates that the number of failed storage units in the left area in the same row as the failed storage unit is 0, and the number of failed storage units in the upper area in the same column as the failed storage unit is 0.

[0136] In an exemplary embodiment, the statistical module 604 is also used to determine, for each failed storage unit, the failed storage unit as the second target unit when the second statistical result corresponding to the failed storage unit indicates that the number of failed storage units in the right area in the same row as the failed storage unit is 0, and the number of failed storage units in the lower area in the same column as the failed storage unit is 0.

[0137] In an exemplary embodiment, the analysis module 606 is also used to take the intersection of a first set consisting of all first target units and a second set consisting of all second target units to obtain a third set; based on the third set, the number of spare rows and the number of spare columns, determine whether to run the repair analysis algorithm on the memory matrix.

[0138] In an exemplary embodiment, the analysis module 606 is further used to remove the failed storage cells included in the third set from the first set, and determine the first number of failed storage cells in the first set; remove the failed storage cells included in the third set from the second set, and determine the second number of failed storage cells in the second set; determine the minimum value between the first number and the second number, and when the minimum value is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; when the minimum value is not greater than the sum of the row spare number and the column spare number, determine that the memory matrix may be repaired, and it is necessary to run the repair analysis algorithm on the memory matrix for repair analysis.

[0139] In an exemplary embodiment, the analysis module 606 is also used to determine a third number of failed storage cells in a third set. When the third number is greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix. When the third number is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repaired, and it is necessary to run the repair analysis algorithm on the memory matrix for repair analysis.

[0140] Each module in the above chip failure storage unit repair analysis device can be implemented in whole or in part by software, hardware and their combination. Each module can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0141] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the row spare number of the row storage unit of the memory matrix and the column spare number of the column storage unit. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a repair analysis method for a chip failure storage unit is implemented.

[0142] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0143] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0144] Obtaining the row spare number of the row storage unit and the column spare number of the column storage unit of the memory matrix;

[0145] For each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell are counted to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, a first target cell among all failed storage cells is determined;

[0146] For each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage cell, a second target cell among all failed storage cells is determined;

[0147] A determination result of whether to run a repair analysis algorithm on the memory matrix is ​​determined according to the first target unit, the second target unit, the number of spare rows, and the number of spare columns.

[0148] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0149] For each failed storage cell, when the first statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the left area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the upper area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the first target cell.

[0150] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0151] For each failed storage cell, when the second statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the right area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the lower area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the second target cell.

[0152] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0153] Taking the intersection of a first set consisting of all first target units and a second set consisting of all second target units to obtain a third set;

[0154] A determination result of whether to run a repair analysis algorithm on the memory matrix is ​​determined based on the third set, the number of spare rows, and the number of spare columns.

[0155] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0156] Remove the failed storage units included in the third set from the first set to determine a first number of failed storage units in the first set;

[0157] Remove the failed storage units included in the third set from the second set to determine a second number of failed storage units in the second set;

[0158] Determine a minimum value between the first number and the second number, and when the minimum value is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; there is no need to continue running the repair analysis algorithm on the memory matrix;

[0159] When the minimum value is not greater than the sum of the number of spare rows and the number of spare columns, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0160] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0161] Determine a third number of failed storage units in the third set, and when the third number is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; there is no need to continue running the repair analysis algorithm on the memory matrix;

[0162] When the third number is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0163] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0164] Obtaining the row spare number of the row storage unit and the column spare number of the column storage unit of the memory matrix;

[0165] For each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell are counted to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, a first target cell among all failed storage cells is determined;

[0166] For each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage cell, a second target cell among all failed storage cells is determined;

[0167] A determination result of whether to run a repair analysis algorithm on the memory matrix is ​​determined according to the first target unit, the second target unit, the number of spare rows, and the number of spare columns.

[0168] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0169] For each failed storage cell, when the first statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the left area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the upper area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the first target cell.

[0170] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0171] For each failed storage cell, when the second statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the right area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the lower area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the second target cell.

[0172] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0173] Taking the intersection of a first set consisting of all first target units and a second set consisting of all second target units to obtain a third set;

[0174] A determination result of whether to run a repair analysis algorithm on the memory matrix is ​​determined based on the third set, the number of spare rows, and the number of spare columns.

[0175] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0176] Remove the failed storage units included in the third set from the first set to determine a first number of failed storage units in the first set;

[0177] Remove the failed storage units included in the third set from the second set to determine a second number of failed storage units in the second set;

[0178] Determine a minimum value between the first number and the second number, and when the minimum value is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; there is no need to continue running the repair analysis algorithm on the memory matrix;

[0179] When the minimum value is not greater than the sum of the number of spare rows and the number of spare columns, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0180] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0181] Determine a third number of failed storage units in the third set, and when the third number is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; there is no need to continue running the repair analysis algorithm on the memory matrix;

[0182] When the third number is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0183] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0184] Obtaining the row spare number of the row storage unit and the column spare number of the column storage unit of the memory matrix;

[0185] For each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell are counted to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, a first target cell among all failed storage cells is determined;

[0186] For each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage cell, a second target cell among all failed storage cells is determined;

[0187] A determination result of whether to run a repair analysis algorithm on the memory matrix is ​​determined according to the first target unit, the second target unit, the number of spare rows, and the number of spare columns.

[0188] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0189] For each failed storage cell, when the first statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the left area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the upper area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the first target cell.

[0190] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0191] For each failed storage cell, when the second statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the right area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the lower area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the second target cell.

[0192] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0193] Taking the intersection of a first set consisting of all first target units and a second set consisting of all second target units to obtain a third set;

[0194] A determination result of whether to run a repair analysis algorithm on the memory matrix is ​​determined based on the third set, the number of spare rows, and the number of spare columns.

[0195] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0196] Remove the failed storage units included in the third set from the first set to determine a first number of failed storage units in the first set;

[0197] Remove the failed storage units included in the third set from the second set to determine a second number of failed storage units in the second set;

[0198] Determine a minimum value between the first number and the second number, and when the minimum value is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; there is no need to continue running the repair analysis algorithm on the memory matrix;

[0199] When the minimum value is not greater than the sum of the number of spare rows and the number of spare columns, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0200] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0201] Determine a third number of failed storage units in the third set, and when the third number is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; there is no need to continue running the repair analysis algorithm on the memory matrix;

[0202] When the third number is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

[0203] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0204] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0205] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0206] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for repairing and analyzing a failed memory cell of a chip, characterized in that: The method comprises: Obtaining the row spare number of the row storage unit and the column spare number of the column storage unit of the memory matrix; For each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell are counted to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, a first target cell among all failed storage cells is determined; For each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell are counted to obtain a second statistical result, and based on the second statistical result corresponding to each failed storage cell, a second target cell among all failed storage cells is determined; A determination result of whether to execute a repair analysis algorithm on the memory matrix is ​​determined according to the first target unit, the second target unit, the row spare number, and the column spare number.

2. The method according to claim 1, characterized in that The determining of a first target unit among all failed storage units based on a first statistical result corresponding to each failed storage unit includes: For each failed storage unit, when the first statistical result corresponding to the failed storage unit indicates that the number of failed storage units in the left area of ​​the same row as the failed storage unit is 0, and the number of failed storage units in the upper area of ​​the same column as the failed storage unit is 0, the failed storage unit is determined as the first target unit.

3. The method according to claim 1, characterized in that The determining of the second target unit among all failed storage units based on the second statistical result corresponding to each failed storage unit includes: For each failed storage cell, when the second statistical result corresponding to the failed storage cell indicates that the number of failed storage cells in the right area of ​​the same row as the failed storage cell is 0, and the number of failed storage cells in the lower area of ​​the same column as the failed storage cell is 0, the failed storage cell is determined as the second target cell.

4. The method according to claim 1, characterized in that: The determining, based on the first target unit, the second target unit, the row spare number, and the column spare number, whether to run a repair analysis algorithm on the memory matrix comprises: Taking the intersection of a first set consisting of all first target units and a second set consisting of all second target units to obtain a third set; A determination result of whether to execute a repair analysis algorithm on the memory matrix is ​​determined according to the third set, the row spare quantity, and the column spare quantity.

5. The method according to claim 4, characterized in that The determining, based on the third set, the number of spare rows and the number of spare columns, whether to run a repair analysis algorithm on the memory matrix comprises: Remove the failed storage units included in the third set from the first set, and determine a first number of failed storage units in the first set; removing the failed storage units included in the third set from the second set, and determining a second number of failed storage units in the second set; Determine a minimum value between the first number and the second number, and when the minimum value is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; When the minimum value is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

6. The method according to claim 4, characterized in that The determining, based on the third set, the number of spare rows and the number of spare columns, whether to run a repair analysis algorithm on the memory matrix comprises: Determine a third number of failed storage units in the third set, and when the third number is greater than the sum of the row spare number and the column spare number, determine that the memory matrix cannot be repaired, and there is no need to continue running the repair analysis algorithm on the memory matrix; When the third number is not greater than the sum of the row spare number and the column spare number, it is determined that the memory matrix may be repairable, and a repair analysis algorithm needs to be run on the memory matrix to perform repair analysis.

7. A chip failure storage unit repair analysis device, characterized in that: The device comprises: A data acquisition module, used for acquiring the row spare quantity of the row storage unit and the column spare quantity of the column storage unit of the memory matrix; A statistical module, for counting, for each failed storage cell in the memory matrix, the number of failed storage cells in the left region in the same row as the failed storage cell and the number of failed storage cells in the upper region in the same column as the failed storage cell, to obtain a first statistical result, and based on the first statistical result corresponding to each failed storage cell, determine a first target cell among all failed storage cells; The statistical module is further used to count, for each failed storage cell in the memory matrix, the number of failed storage cells in the right region of the same row as the failed storage cell and the number of failed storage cells in the lower region of the same column as the failed storage cell to obtain a second statistical result, and determine a second target cell among all failed storage cells based on the second statistical result corresponding to each failed storage cell; The analysis module is used to determine whether to run a repair analysis algorithm on the memory matrix according to the first target unit, the second target unit, the row spare number and the column spare number.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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