A dynamic patching method based on SRAM and a SRAM testing and quality verification platform

Abstract

The present invention discloses a dynamic patching method based on SRAM and an SRAM test and quality verification platform, the dynamic patching method is applied to SRAM TQV, and virtual redundant resources are set on the SRAM TQV, the dynamic patching method includes performing a functional test and a minimum voltage test on a wafer that passes a DC test, and recording all failure addresses of all failure areas in the wafer, all failure areas include a functional test failure area and / or a minimum voltage test failure area; all failure addresses are divided into corresponding failure modes according to a preset algorithm, and the failure modes include block failure, word line failure and bit line failure; a patching algorithm is obtained, and according to the patching algorithm and the failure mode, all failure addresses are patched using virtual redundant resources. The present invention implements dynamic patching of SRAM TQV in the wafer verification and analysis process, and solves the problem that the existing SRAM TQV cannot dynamically patch the failed part of SRAM, which makes it difficult to continue testing the peripheral circuit of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of memory dynamic patching, and in particular to a dynamic patching method based on SRAM and an SRAM testing and quality verification platform. Background Art

[0002] Static Random-Access Memory (SRAM) is a type of random access memory. SRAM can save the data stored inside it without a refresh circuit, but it needs to be powered on for read and write operations. Powering off will cause data loss.

[0003] In the prior art, when using SRAM TQV (SRAM Test and Quality Verification Platform) to test SRAM, due to cost constraints, SRAM TQV often does not plan redundant space. Therefore, when using SRAM TQV to perform yield analysis and verification on SRAM, when encountering process or circuit problems with SRAM, it is unable to solve the problems or failed parts of SRAM in a short period of time, which undoubtedly interferes with the yield analysis.

[0004] Currently, no effective solution has been proposed for the problem that the existing SRAM TQV cannot dynamically repair the failed part of the SRAM, making it difficult to continue testing the peripheral circuits of the chip. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a dynamic repair method based on SRAM and an SRAM testing and quality verification platform to at least solve the problem that the existing SRAM TQV cannot dynamically repair the failed part of the SRAM, making it difficult to continue testing the chip peripheral circuits.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a dynamic patching method based on SRAM, which is applied to SRAM TQV, and the SRAM TQV is provided with virtual redundant resources, the virtual redundant resources include redundant blocks, redundant word lines and redundant bit lines, and the dynamic patching method includes:

[0008] Performing a functional test and a minimum voltage test on the wafer that passes the DC test, and recording all failure addresses of all failure areas in the wafer, wherein all failure areas include a functional test failure area and / or a minimum voltage test failure area;

[0009] Dividing all the failed addresses into corresponding failure modes according to a preset algorithm, wherein the failure modes include block failure, word line failure and bit line failure;

[0010] A repair algorithm is obtained, and according to the repair algorithm and the failure mode, the virtual redundant resources are used to perform address repair on all the failed addresses.

[0011] Furthermore, the one functional test includes a functional write-read test, a functional read-after-write test, and a functional March C test.

[0012] Furthermore, the one minimum voltage test includes redundancy test, peripheral circuit test and storage array test at 20% lower than normal voltage.

[0013] Furthermore, a repair algorithm is obtained, and according to the repair algorithm and the failure mode, the virtual redundant resources are used multiple times to perform address repair on all the failed addresses to obtain an optimal repair solution.

[0014] Furthermore, after using the virtual redundant resources to perform address repair on all the failed addresses, the method further includes:

[0015] The wafer is subjected to secondary functional testing, wherein the secondary functional testing includes a basic function write-read test, a basic function read-after-write test, a basic checkboard test, and a basic function March 6N test.

[0016] Furthermore, a secondary minimum voltage test is performed on the wafer to determine the reliability of the wafer at the lowest operating voltage.

[0017] Furthermore, a retention test is performed on the wafer, wherein the retention test is performed under a condition of 30% lower voltage than a normal voltage, and the waiting time is 100 ms.

[0018] Furthermore, when the wafer passes the DC test, the wafer is classified into a failure classification area.

[0019] Furthermore, the DC test includes one or more of an open circuit or short circuit test of a VSS pin, an open circuit or short circuit test of a power pin, a low leakage current test, a high leakage current test, a current test during a power short circuit, a standby current test, and a current test in an active mode.

[0020] A second aspect of the present invention provides a SRAM testing and quality verification platform for implementing any of the dynamic patching methods described above.

[0021] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0022] The present invention discloses a dynamic patching method based on SRAM, which presets virtual redundant resources on SRAM TQV, and then divides the wafer into corresponding failure modes according to all the failure addresses after the SRAM TQV obtains all the failure addresses of all the failure areas on the wafer, and finally uses a patching algorithm and a failure mode to perform address patching on all the failure areas corresponding to all the failure addresses, so as to realize dynamic patching of SRAM TQV in the wafer verification and analysis process, thereby facilitating the continued peripheral circuit testing of the chip, and solving the problem that the existing SRAM TQV cannot dynamically patch the failed part of the SRAM, resulting in difficulty in continuing the peripheral circuit testing of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A flow chart of a dynamic patching method based on SRAM according to an embodiment of the present invention;

[0025] Figure 2 The working process of the SRAM TQV platform of the embodiment of the present invention;

[0026] Figure 3 Schematic diagram of different failure modes of an embodiment of the present invention;

[0027] Figure 4 The flowchart is a specific implementation method of an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0029] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0030] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0031] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0032] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0033] The conventional repair scheme in the industry is to make some redundant designs near the array area of ​​the wafer, and use a repair algorithm to calculate the best repair scheme for the fail address of the array area, which helps to improve product yield. However, due to cost considerations, the SRAM TQV in the FAB factory (wafer length) often does not plan redundancy space. As a result, after detecting a wafer failure, it is difficult to continue testing the peripheral circuits of the wafer chip, which will interfere with the SRAM yield analysis.

[0034] Based on this, this specification embodiment proposes a processing solution: Figures 1-2 As shown, a dynamic patching solution based on SRAM of the present invention presets virtual redundant resources on SRAM TQV, so that when SRAM TQV verifies and analyzes the wafer, if it is found that the wafer fails, the virtual redundant resources can be used to replace the failed area to achieve dynamic patching of SRAM, so that SRAM TQV can continue to perform peripheral circuit testing or other tests on the wafer chip, so as to achieve more efficient problem analysis and improve wafer yield.

[0035] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0036] Example 1

[0037] The invention discloses a dynamic patching method based on SRAM, which is applied to SRAM TQV, and the SRAM TQV is preset with virtual redundant resources, which include redundant blocks, redundant word lines and redundant bit lines.

[0038] The virtual redundant resource of the present application does not have an actual physical entity, but adopts a virtual preset algorithm and is integrated into the SRAM TQV.

[0039] Among them, SRAM TQV is a testing and quality verification platform for testing and quality verification of static random access memory, which usually includes functional testing function, electrical parameter testing function, fault detection and repair function, data analysis and reporting function to ensure that SRAM chips meet the expected standards in terms of function, performance and reliability.

[0040] When the dynamic repair method of the present invention is applied to SRAM TQV, it can improve the dynamic repair of the SRAM TQV on the failed area of ​​the wafer, so as to continue testing the wafer after dynamic repair, and solve the problem in the prior art that the SRAM TQV encounters process or circuit problems during yield analysis and cannot be solved in the short term.

[0041] like Figure 1 As shown, the dynamic patching method includes:

[0042] Step S102, performing a functional test and a minimum voltage test on the wafer that passes the DC test, and recording all failure addresses of all failure areas in the wafer, where all failure areas include a functional test failure area and / or a minimum voltage test failure area.

[0043] Among them, before performing a functional test and a minimum voltage test, it is necessary to use SRAM TQV to perform a DC test on the wafer to detect whether there is a problem with the wafer circuit. When the DC test detects that there is a problem with the wafer circuit, the wafer is classified into a failure classification area.

[0044] Specifically, Figure 2 As shown, the DC test includes one or more of an open or short circuit test of the VSS pin, an open or short circuit test of the power pin, a low leakage current test, a high leakage current test, a current test when the power supply is short-circuited, a standby current test, and a current test in active mode.

[0045] Preferably, if Figure 2 As shown, the DC test includes Figure 2 Follow steps 1 to 8 in the test to determine whether the wafer circuit is correct.

[0046] Specifically, the open or short condition of the VSS pin is used to identify potential open or short failures; the open or short condition of the power pin is used to detect abnormal current of the power pin to identify open or short failures; the low leakage current test is used to detect small leakage failures by measuring low leakage current; high leakage current is used to indicate serious failures, such as conduction failures; the current test when the power supply is short-circuited is used to measure the leakage current of the power pin when the circuit is in shutdown mode; the standby current test is used to detect leakage failures in standby mode; the current test in active mode is used to detect failures in the working state.

[0047] In some of the embodiments, the DC test also includes a Write through test for detecting failure of the IO circuit.

[0048] Specifically, the Write through test is used to directly connect DIN and DOUT, bypassing the storage unit area, and detect whether the IO circuit is normal.

[0049] After the SRAM TQV passes the DC test on the wafer, the SRAM TQV performs a functional test and a minimum voltage test on the wafer to determine whether there are functional failures in various areas on the wafer or whether the minimum voltage test fails.

[0050] Among them, a functional test includes a functional write-read test, a functional read-after-write test, a functional March C test, etc.; a minimum voltage test includes a redundancy test, a peripheral circuit test and a storage array test at 20% below the normal voltage.

[0051] Specifically, Figure 2 In steps 9 to 11, when performing a functional write-read test, the wafer is at a normal voltage, and immediately reads data after writing data to an address bit to obtain a read failure bitmap. By collecting the failure bitmap, it is possible to identify which areas on the wafer have functional failures; in a functional write-after-read test, at a normal voltage, data is written to all address bits in a block in a low-to-high order, and then the first address bit is returned to read in a low-to-high order to collect the corresponding failure bitmap for more comprehensive detection of functional failures of storage cells; in a functional March C test, at a normal voltage, a March C test is performed and a failure bitmap is collected. The March C test is a complex storage unit test method for detecting more hidden failures. The failure bitmap includes the failure address of the failure area.

[0052] More specifically, Figure 2In steps 12 to 13, in a redundant test at 20% below normal voltage, redundant failure addresses are collected to detect failures under non-ideal working conditions; under conditions of 20% below normal voltage, by collecting failure addresses of peripheral circuits and storage arrays, all parts of the chip can be fully tested.

[0053] Among them, the area that fails the functional test in a functional test is a functional test failure area. At this time, the FCM module in the SRAM TQV changes the address of the functional test failure area from pass to fail; and if it fails during the minimum voltage test, it is recorded as fail at this address.

[0054] If an address corresponding to a wafer region fails both the functional test and the minimum voltage test, the address is recorded as a fail. If a wafer region corresponding to an address fails several times, it is recorded as a fail. If a wafer region corresponding to an address fails once, the address is recorded as a fail, that is, it is recorded as a failed address.

[0055] Through step S102, the SRAM TQV can record all the failure addresses on the wafer, so that the SRAM TQV can subsequently classify the failure of the wafer into different failure modes according to the failure addresses, and adopt corresponding repair solutions.

[0056] Step S104: classify all failed addresses into corresponding failure modes according to a preset algorithm, where the failure modes include block failure, word line failure and bit line failure.

[0057] like Figure 3 As shown, the failure modes can be divided into block failure, word line failure and bit line failure according to the arrangement mode and arrangement quantity of the failure addresses.

[0058] Specifically, Figure 3 Seven failure modes are shown in the data, including block failure, clustered word line failure, clustered bit line failure, double word line failure, double bit line failure, word line failure and bit line failure. Block failure means more than 30% of the complete storage block fails; clustered word line failure means more than 3 consecutive adjacent word lines fail at the same time, and the failure rate of each complete word line exceeds 30%; clustered bit line failure means more than 3 consecutive adjacent bit lines fail at the same time, and the failure rate of each complete bit line exceeds 30%; double word line failure means two adjacent word lines fail at the same time, and the failure rate of each complete word line exceeds 30%; double bit line failure means two adjacent bit lines fail at the same time, and the failure rate of each complete bit line exceeds 30%; word line failure means more than 30% of one complete word line fails; bit line failure means more than 30% of one complete bit line fails.

[0059] After all the failed addresses are divided according to the preset rules and the corresponding failure modes are generated in step S104, it is convenient for the SRAM TQV to execute the corresponding repair scheme according to the failure mode and the repair algorithm.

[0060] Step S106: Obtain a repair algorithm, and use virtual redundant resources to perform address repair on all failed addresses according to the repair algorithm and the failure mode.

[0061] Specifically, when the failure mode of the wafer is block failure, the redundant block in the SRAM TQV is used to replace the corresponding failed block; when the failure mode of the wafer is word line failure, the redundant word line in the SRAM TQV is used to replace the corresponding failed word line; when the failure mode of the wafer is bit line failure, the redundant bit line in the SRAM TQV is used to replace the corresponding failed bit line.

[0062] The address repair includes updating the internal address mapping table to redirect the address originally pointing to the failed area to the virtual redundant resource, thereby ensuring that subsequent access requests to the failed address can be automatically transferred to the virtual redundant resource to repair the failed area.

[0063] Through step S106, the virtual redundant resources in the SRAM TQV are used to repair the failed area according to the failure mode, so that when the SRAM TQV analyzes the wafer, it can redirect the access request to the virtual redundant resources to implement the repair of the failed area, thereby solving the problem that the existing SRAM TQV cannot solve the failed area in a short period of time, thereby interfering with the yield analysis.

[0064] In some of the embodiments, a repair algorithm is obtained, and according to the repair algorithm and the failure mode, virtual redundant resources can be used multiple times to perform address repair on all failed addresses to obtain an optimal repair solution.

[0065] In some of the embodiments, after the wafer is dynamically repaired, it can also be subjected to a secondary functional test, a secondary minimum voltage test, and a retention test to eliminate yield problems caused by peripheral circuits, improve the test yield value, and facilitate the analysis of design, R&D, and process-related issues.

[0066] After all failed addresses are repaired using the virtual redundant resources, the method further includes:

[0067] Step S108, performing secondary functional test on the wafer, the secondary functional test includes basic function write-read test, basic function read-after-write test, basic function checkboard test, and basic function March 6N test.

[0068] like Figure 2 As shown, Figure 2 Steps 15 to 18 in the figure are respectively basic function write-read test, basic function write-after-read test, basic checkboard test, and basic function March 6N test.

[0069] Among them, the basic function checkboard test is to write checkerboard format data in the memory cell array under normal voltage. Checkerboard format data means that different data are written to adjacent memory cells. After writing the data, all memory cells are read to check the failure positions in the memory cells. The basic function March 6N test is to perform MarchC 6N test under normal voltage to check the timing and sequential failures in the memory cells.

[0070] Furthermore, after the secondary functional test of the wafer, it also includes:

[0071] Step S110 , performing a secondary minimum voltage test on the wafer to determine the reliability of the wafer at the minimum operating voltage.

[0072] Furthermore, after performing the secondary minimum voltage test on the wafer, it also includes:

[0073] Step S112: performing a retention test on the wafer. The retention test is performed under a condition of 30% lower voltage than the normal voltage, and the waiting time is 100 ms.

[0074] Among them, the retention test is used to detect the ability of data to be retained in the storage unit. Under the conditions of low voltage and waiting time, if data retention failure is found, repair processing can be carried out in time.

[0075] The embodiment of the present invention can effectively improve product yield, quickly locate problems, greatly improve test efficiency, and greatly help design, research and development, and process problem solving capabilities by applying simulated redundancy and efuse repair technology to the SRAM platform.

[0076] The present invention also provides a SRAM testing and quality verification platform for implementing any of the above-mentioned dynamic patching methods.

[0077] Among them, the SRAM testing and quality verification platform includes testing equipment, testing software, hardware equipment, etc.

[0078] Specifically, the test equipment includes automatic test equipment and probe cards. The automatic test equipment is used to execute various automated test procedures to improve test efficiency and accuracy; the probe card is used to connect the test equipment and the chip to guide the test signal to be accurately measured.

[0079] The test software includes a test program and a data management system. The test program includes a preset algorithm, a patching algorithm, etc.;

[0080] The hardware device includes a control circuit and a virtual redundant resource management system, which is responsible for allocating and mapping spare resources during the dynamic patching process.

[0081] The SRAM TQV platform of the present invention can comprehensively detect the performance and failure of the chip under different working conditions. The dynamic repair method realizes effective repair of failures through the following key steps:

[0082] Comprehensive testing: Identify failure modes and failure addresses through multiple testing methods.

[0083] Classification and analysis: Classify the failed addresses into block failures, word line failures, and bit line failures.

[0084] Redundancy repair: Based on the classification results, dynamic repair is performed using reserved redundant blocks, word lines, and bit lines.

[0085] Verify and optimize: Verify the patching effect through further testing and optimize as needed.

[0086] This systematic dynamic repair process can effectively eliminate some yield problems caused by peripheral circuits, improve test yield values, and also facilitate the analysis of design, R&D and process-related issues.

[0087] Example 2

[0088] This embodiment is a specific implementation method of a dynamic patching method based on SRAM of the present invention.

[0089] like Figure 4 As shown, the dynamic patching method comprises the following steps:

[0090] 10. Design some redundancy Block / WL / BL circuits in the Memory array area. When failure occurs, the algorithm can be used to use redundancy to repair the failure location and improve the CP test yield;

[0091] 20. SRAM test program flow: Screen out the dies with circuit problems through DC test (1~8) and output failbin. Function test (9~11) and Vmin test (12~13) can be performed on DC pass dies, and the FCM function of T5830 machine can be used to record the fail address under normal voltage and -20% voltage;

[0092] 30. Analyze the failure mode. The fail address recorded in FCM can be classified into different failure modes according to the algorithm, such as Block / WL / BL fail;

[0093] 40. Develop a patching algorithm (14), calculate different failure modes in FCM, perform address patching for Block / WL / BLfail respectively, and obtain the optimal redundancy patching solution through the algorithm;

[0094] 50. Adding a repair solution to the subsequent functional test (15-20) can effectively eliminate some yield problems caused by peripheral circuits, improve the test yield value, and also help analyze design, R&D and process-related problems

[0095] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0096] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A dynamic patching method based on SRAM, characterized in that: Applied to SRAM TQV, and the SRAM TQV is provided with virtual redundant resources, the virtual redundant resources include redundant blocks, redundant word lines and redundant bit lines, the dynamic patching method includes: Performing a functional test and a minimum voltage test on the wafer that passes the DC test, and recording all failure addresses of all failure areas in the wafer, wherein all failure areas include a functional test failure area and / or a minimum voltage test failure area; Dividing all the failed addresses into corresponding failure modes according to a preset algorithm, wherein the failure modes include block failure, word line failure and bit line failure; A repair algorithm is obtained, and according to the repair algorithm and the failure mode, the virtual redundant resources are used to perform address repair on all the failed addresses.

2. The dynamic patching method according to claim 1, characterized in that: The one-time functional test includes a functional write-read test, a functional read-after-write test, and a functional March C test.

3. The dynamic patching method according to claim 2, characterized in that: The one-time minimum voltage test includes redundancy test, peripheral circuit test and memory array test at 20% lower than the normal voltage.

4. The dynamic patching method according to claim 1, characterized in that: A repair algorithm is obtained, and according to the repair algorithm and the failure mode, the virtual redundant resources are used multiple times to perform address repair on all the failed addresses, so as to obtain an optimal repair solution.

5. The dynamic repair method according to any one of claims 1 to 4, characterized in that: After using the virtual redundant resources to perform address repair on all the failed addresses, the method further includes: The wafer is subjected to secondary functional testing, wherein the secondary functional testing includes a basic function write-read test, a basic function read-after-write test, a basic checkboard test, and a basic function March 6N test.

6. The dynamic patching method according to claim 5, characterized in that: A secondary minimum voltage test is performed on the wafer to determine the reliability of the wafer at the minimum operating voltage.

7. The dynamic patching method according to claim 6, characterized in that: A retention test is performed on the wafer, wherein the retention test is performed under a condition of 30% lower voltage than a normal voltage, and the waiting time is 100 ms.

8. The dynamic patching method according to claim 1, characterized in that: When the wafer fails the DC test, the wafer is classified into a failure classification area.

9. The dynamic patching method according to claim 8, characterized in that: The DC test includes one or more of an open or short circuit test of a VSS pin, an open or short circuit test of a power pin, a low leakage current test, a high leakage current test, a current test during a power short circuit, a standby current test, and a current test in an active mode.

10. A SRAM testing and quality verification platform, characterized in that: Used to implement the dynamic repair method described in any one of claims 1 to 9.

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