Silicon wafer double gettering method and preparation method of heterojunction battery piece
By chemical corrosion and heat treatment on the silicon wafer, defects are formed to attract impurities, and impurities are captured using the phosphorus diffusion and impurities absorption process, the problem of inefficiency of existing impurities absorption methods is solved, and the impurities are fully removed and the life of lesser children in the silicon wafer is improved.
Patent Information
- Application Number
- CN202411928551.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-04-01
AI Technical Summary
The existing miscellaneous absorption methods are cumbersome and inefficient in large-scale industrial production, resulting in a high content of metal impurities remaining in the silicon wafer, and the life of minority carriers is not significantly improved.
The dual impurity absorption method of silicon wafers is adopted, including chemical corrosion to form surface defects, heat treatment causes impurities to diffuse to the defects, and impurities are captured through the phosphorus diffusion absorption process.
The full diffusion and absorption of metal impurities in the silicon wafer are achieved, which improves the lifespan of 25-40%, and significantly improves the conversion efficiency of the battery.
Smart Images
Figure CN119742230A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of heterojunction batteries, and in particular to a silicon wafer double gettering method and a method for preparing a heterojunction battery cell. Background Art
[0002] Heterojunction cells have the characteristics of short manufacturing process, low process temperature, high open circuit voltage and high photoelectric conversion efficiency. As a high-efficiency solar cell, they have been developed and applied on a large scale. In order to obtain high-efficiency heterojunction solar cells, minority carriers must have a long life and a low recombination rate. Therefore, the performance of silicon wafers directly affects the final conversion efficiency of the cell. However, metal impurities doped into silicon wafers, such as iron (Fe), nickel (Ni), copper (Cu) and chromium (Cr), have high mobility, can diffuse over long distances, and act as recombination centers, which will affect the collection efficiency of carriers.
[0003] In order to reduce the adverse effects of impurities on material properties, people have widely studied methods to remove impurities. Among them, impurity removal technology is an effective method, which artificially creates defect centers inside or on the back of silicon wafers. These defect centers can attract and fix harmful defects and metal impurities in silicon wafers, which can not only reduce the impurity content inside the silicon wafer, but also extend the life of minority carriers, thereby improving the overall efficiency of the battery.
[0004] At present, the phosphorus diffusion gettering technology is mainly tubular gettering. During the tubular gettering process, the silicon wafer is placed in a quartz boat, and the quartz boat is manually pushed in and out of the tubular diffusion furnace. This method is cumbersome and inefficient in large-scale industrial production, limiting the overall efficiency of gettering. In addition, the efficiency of existing gettering methods is slow, resulting in the inability of slow-diffusing metals such as iron (Fe) and chromium (Cr) to fully diffuse into the gettering layer, resulting in a high content of metal impurities remaining in the silicon wafer, and the minority carrier lifetime is not significantly improved. Summary of the invention
[0005] One of the purposes of the present invention is to provide a double impurity gettering method for silicon wafers, which can fully diffuse and capture impurities in the silicon wafer, effectively remove impurities and increase the minority carrier lifetime of the silicon wafer, while having good process stability.
[0006] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are particularly adopted:
[0007] A silicon wafer double gettering method comprises the following steps:
[0008] Providing a raw silicon wafer, performing surface etching on the raw silicon wafer to form defects as gettering centers, and sequentially performing heat treatment and phosphorus diffusion gettering to obtain a substrate silicon wafer;
[0009] The surface etching method includes chemical etching;
[0010] The chemical etching solution includes at least one of HF, KOH and NaOH.
[0011] Further, the concentration of the corrosive solution is 10-25%;
[0012] Preferably, the chemical etching method is etching by a gas phase process;
[0013] Preferably, the gas phase process includes using corrosive liquid vapor to perform reactive corrosion.
[0014] Furthermore, the reaction time between the etching solution and the silicon wafer is 60-400s.
[0015] Furthermore, after the etching, the step of cleaning the silicon wafer is also included;
[0016] The method for cleaning the silicon wafer comprises first cleaning the surface of the silicon wafer with deionized water, and then blowing the surface of the silicon wafer with gas.
[0017] Furthermore, the temperature of the heat treatment is 500-900° C., and the time of the heat treatment is 30-200 seconds.
[0018] Furthermore, the phosphorus diffusion gettering includes chain phosphorus diffusion gettering.
[0019] Furthermore, the temperature of the chain phosphorus diffusion gettering is 650-950° C., and the time of the chain phosphorus diffusion gettering is 100-1000 s.
[0020] Furthermore, the diffusion source of the chain phosphorus diffusion gettering includes H3PO4.
[0021] Furthermore, the H3PO4 is coated on the surface of the heat-treated silicon wafer by smearing and / or ultrasonic spraying.
[0022] Compared with the prior art, the present invention has at least the following beneficial effects:
[0023] The double gettering method for silicon wafers provided by the present invention has the advantages of firstly being able to remove impurities efficiently: chemical corrosion forms artificial defects on the surface of the silicon wafer, increasing the contactable area of the silicon wafer, which not only improves the covering effect of the phosphorus slurry, but also enables the silicon wafer to better contact with the electrolyte in the subsequent battery preparation process, which is beneficial to improving the conversion efficiency of the battery. At the same time, the metal impurities inside the silicon wafer can diffuse and migrate to the defects during the heat treatment process, and then through the phosphorus diffusion gettering process, the capture effect of the phosphorus silicon glass layer is utilized to further reduce the concentration of metal impurities in the silicon wafer. Therefore, the double gettering strategy can fully diffuse and getter the metal impurities inside the silicon wafer, especially for metal impurities with low diffusion coefficients. The double gettering method can fully diffuse and getter the metal impurities (such as Fe, Cr and other metals with slow diffusion), thereby effectively reducing their content in the silicon wafer; secondly, it can improve the minority carrier lifetime of the silicon wafer: by adopting the "chemical corrosion + phosphorus diffusion gettering" double gettering strategy, the minority carrier lifetime of the silicon wafer can be improved by 25%-40%, which greatly reduces the recombination of minority carriers and is beneficial to improving the final conversion efficiency of the battery.
[0024] At the same time, on the surface of the raw silicon wafer, the present invention forms defects by etching through a gas phase process, that is, using etching liquid vapor to perform chemical etching to form defects. On the one hand, the etching liquid vapor can more effectively contact and react with the solid matter, thereby achieving a higher reaction rate; on the other hand, the defects formed by steam corrosion are more uniform, so that the consistency of the impurity gettering effect at various locations on the silicon wafer is good; in addition, the reaction of steam corrosion is easier to control and operate, and the steam concentration can also be adjusted more simply and accurately.
[0025] A second object of the present invention is to provide a method for preparing a heterojunction cell, comprising the following steps:
[0026] Prepare a substrate silicon wafer using any of the double gettering methods described above;
[0027] Performing texturing treatment on at least one side of the substrate silicon wafer using a texturing agent;
[0028] Sequentially depositing an intrinsic passivation layer and a doping layer on both sides of the substrate silicon wafer;
[0029] Conductive film deposition is performed on both sides of the substrate silicon wafer and electrodes are prepared.
[0030] The method for preparing the heterojunction solar cell provided by the present invention is conducive to preparing a solar cell with high conversion efficiency and can improve the conversion efficiency by 0.2%-1.0%. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0032] Figure 1 This is a process flow chart of the silicon wafer double gettering method provided in Example 1 of the present invention. DETAILED DESCRIPTION
[0033] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0034] According to a first aspect of the present invention, a silicon wafer double gettering method is provided, comprising the following steps:
[0035] Providing a raw silicon wafer, etching the surface of the raw silicon wafer to form defects as gettering centers, and sequentially performing heat treatment and phosphorus diffusion gettering to obtain a substrate silicon wafer;
[0036] Surface etching methods include chemical etching;
[0037] The chemical etching solution includes but is not limited to at least one of HF, KOH and NaOH.
[0038] The double impurity gettering method for silicon wafers provided by the present invention has the advantages of firstly being able to efficiently remove impurities: chemical corrosion forms artificial defects on the surface of the silicon wafer, increasing the contactable area of the silicon wafer, which not only improves the covering effect of the phosphorus slurry, but also enables the silicon wafer to better contact with the electrolyte in the subsequent battery preparation process, which is beneficial to improving the conversion efficiency of the battery. At the same time, the metal impurities inside the silicon wafer can diffuse and migrate to the defects during the heat treatment process, and then through the phosphorus diffusion gettering process, the capture effect of the phosphorus silicon glass layer is utilized to further reduce the concentration of metal impurities in the silicon wafer. Therefore, the double impurity gettering strategy can fully diffuse and getter the metal impurities inside the silicon wafer, especially for metal impurities with low diffusion coefficients. The double impurity gettering method can fully diffuse and getter the metal impurities (such as Fe, Cr and other metals with slow diffusion), thereby effectively reducing their content in the silicon wafer; secondly, it can improve the minority carrier lifetime of the silicon wafer: by adopting the "chemical corrosion + phosphorus diffusion gettering" double impurity gettering strategy, the minority carrier lifetime of the silicon wafer can be improved by 25-40%, which greatly reduces the recombination of minority carriers, which is beneficial to improving the final conversion efficiency of the battery.
[0039] In a preferred embodiment, the concentration of the etching solution can be 10-25%, and its typical but non-limiting concentration is, for example, 10%, 15%, 20%, and 25%; the reaction time of the etching solution and the silicon wafer can be 60-400s, and its typical but non-limiting reaction time is, for example, 60s, 70s, 80s, 90s, 100s, 150s, 200s, 250s, 300s, 350s, and 400s.
[0040] The appropriate concentration of the etching solution and its reaction time with the silicon wafer are more conducive to further improving the effect of forming artificial defects on the silicon wafer surface and further increasing the contact area of the silicon wafer. If the concentration of the etching solution is too high, it will cause excessive corrosion on the silicon wafer surface to form defects, resulting in an increase in the fragmentation rate; if the concentration of the etching solution is too low, the artificial defects formed will be shallow, which is not conducive to the removal of impurities.
[0041] In the present invention, the chemical etching method preferably adopts a gas phase process, that is, a 10-25% etching liquid vapor is introduced under a nitrogen atmosphere, and the reaction time is 60-400 seconds. The etching liquid can be an acidic or alkaline solution such as HF, KOH, and NaOH. By adopting the gas phase process, the steam can more effectively contact and react with the solid material, achieving a higher reaction rate, and at the same time, the defects formed by the corrosion are more uniform, so that the consistency of the impurity gettering effect at various places of the silicon wafer is good; in addition, the steam concentration can be flexibly adjusted according to the reaction requirements, which not only makes the adjustment process simpler, making the steam phase reaction easier to control and operate, but also can adjust the concentration more accurately.
[0042] In addition, chemical etching can also adopt a tank process, with a concentration of 10-25% of the etching solution, the reaction is carried out at room temperature, and the reaction time is 60-400s. The etching solution can be an acidic or alkaline solution such as HF, KOH, NaOH, etc. The above steps can form artificial defect sites on the surface of the silicon wafer, which effectively increases the contactable area of the silicon wafer surface.
[0043] At the same time, after chemical etching, the surface of the silicon wafer can be cleaned with deionized water at room temperature for 60-300 seconds, and then the silicon wafer can be purged with clean air at 60-80°C to dehydrate and dry the silicon wafer for 60-300 seconds.
[0044] In a preferred embodiment, the heat treatment temperature can be 500-900°C, and typical but non-limiting temperatures are, for example, 500°C, 600°C, 700°C, 800°C, and 900°C. The heat treatment time can be 30-200s, and typical but non-limiting times are, for example, 30s, 50s, 100s, 120s, 140s, 160s, 180s, and 200s.
[0045] The appropriate temperature and time of heat treatment are more conducive to further improving the effect of diffusion and migration of metal impurities inside the silicon wafer to the defects. If the temperature of heat treatment is too high, it will lead to the generation of internal defects such as oxygen precipitation, resulting in the generation of deeper composite energy levels; if the temperature of heat treatment is too low, it will make it difficult for impurities to fully diffuse to the defects.
[0046] In the present invention, the silicon wafer after chemical etching can be transported by a ceramic roller into a high-temperature furnace for heat treatment. Nitrogen can be introduced into the high-temperature furnace as a protective gas. The temperature of the high-temperature furnace is 500-900°C and the heat treatment time is 30-200s. This can effectively promote the diffusion and migration of metal impurities inside the silicon wafer to the artificial defects, so that some impurities are captured by the defects.
[0047] In a preferred embodiment, the phosphorus diffusion gettering may be a chain phosphorus diffusion gettering; wherein the temperature of the chain phosphorus diffusion gettering may be 650-950°C, and its typical but non-limiting temperatures are, for example, 650°C, 700°C, 750°C, 800°C, 850°C, 900°C, 950°C, and the time of the chain phosphorus diffusion gettering may be 100-1000s, and its typical but non-limiting time is, for example, 100s, 200s, 300s, 400s, 500s, 600s, 700s, 800s, 900s, 1000s.
[0048] The appropriate temperature and time of chain phosphorus diffusion gettering are more conducive to sufficient gettering, which can make the impurities fully diffuse and be captured, thereby effectively reducing the content of metal impurities. If the temperature of chain phosphorus diffusion gettering is too high, it will lead to the generation of internal defects such as oxygen precipitation, resulting in the generation of deeper composite energy levels; if the temperature of chain phosphorus diffusion gettering is too low, it will make it difficult for impurities to fully diffuse to the defects.
[0049] In the present invention, after the heat-treated silicon wafer is cooled by cold clean air blowing, a layer of phosphorus slurry can be evenly covered on the surface of the silicon wafer by soft roller coating or ultrasonic spraying, wherein the main components of the phosphorus slurry are phosphoric acid (H3PO4), water and surfactant, etc.; then, the silicon wafer with the surface evenly covered with phosphorus slurry is sent to a diffusion furnace through a ceramic roller conveyor for chain diffusion and impurity gettering, and nitrogen can be introduced into the diffusion furnace as a protective gas. The capture effect of the phosphorus silicon glass layer generated at high temperature can further reduce the concentration of metal impurities in the silicon wafer; and the artificial defects generated on the surface of the silicon wafer by chemical corrosion can increase the coverage surface area of the phosphorus slurry, which can effectively improve the phosphorus diffusion and impurity gettering effect.
[0050] In summary, the present invention adopts a dual impurity gettering strategy of "chemical corrosion + phosphorus diffusion gettering". First, chemical corrosion is used to form an artificial impurity gettering center on the surface of the silicon wafer; then, through heat treatment, the metal impurities in the silicon wafer diffuse to the surface defects and are removed by the defects; then, chain phosphorus diffusion gettering is used to further reduce the metal impurity content, thereby achieving full diffusion and capture of impurities. In addition, both chemical corrosion and phosphorus diffusion gettering processes are relatively stable processes that can be stably implemented in industrial production. At the same time, the stability and efficiency of the process can be further improved by optimizing the process parameters.
[0051] In summary, the double impurity gettering method of the present invention, with the coordinated cooperation of each step and its process parameters, can fully diffuse and remove the metal impurities inside the silicon wafer, effectively improving the minority carrier lifetime of the silicon wafer by 25-40%, and improving the efficiency of the battery cell by 0.2-1.0%.
[0052] According to a second aspect of the present invention, there is provided a method for preparing a heterojunction cell, comprising the following steps:
[0053] Prepare a substrate silicon wafer using any of the double gettering methods described above;
[0054] Performing texturing treatment on at least one side of the substrate silicon wafer using a texturing agent;
[0055] Depositing an intrinsic passivation layer and a doping layer on both sides of the substrate silicon wafer in sequence;
[0056] Conductive film deposition and electrode preparation are performed on both sides of the substrate silicon wafer.
[0057] The method for preparing the heterojunction solar cell provided by the present invention is conducive to preparing a solar cell with high conversion efficiency.
[0058] The present invention is further described below by way of examples. Unless otherwise specified, the materials in the examples are prepared according to existing methods or directly purchased from the market.
[0059] Example 1
[0060] A silicon wafer double gettering method, the process flow chart of which is shown in Figure 1 , including the following steps:
[0061] (1) performing pre-cleaning and drying treatment on the single crystal silicon wafer after diamond wire cutting to obtain a pre-cleaned single crystal silicon wafer;
[0062] (2) using chemical etching to clean the surface of the single crystal silicon wafer before step (1) and then etching it to form artificial defects, thereby obtaining a chemically etched silicon wafer;
[0063] The chemical etching method is a gas phase process, which includes the following steps:
[0064] In a nitrogen atmosphere, the etching liquid vapor is introduced, and the reaction time with the silicon wafer is 200 seconds; wherein the etching liquid is HF solution, and the mass concentration is 20%;
[0065] Then, the surface of the silicon wafer was cleaned with deionized water at room temperature for 120 seconds, and then the silicon wafer was purged with clean air at 65°C to dehydrate and dry the silicon wafer for 150 seconds.
[0066] (3) The silicon wafer after chemical etching in step (2) is transported into a high-temperature furnace via a ceramic roller for high-temperature heat treatment to promote the diffusion of impurities into defects. Nitrogen is introduced into the high-temperature furnace as a protective gas. The heat treatment temperature is 600° C. and the heat treatment time is 120 s to obtain a heat-treated silicon wafer;
[0067] (4) After the heat treatment in step (3), the silicon wafer is cooled by cold clean air blowing, and then phosphorus slurry is evenly coated on the surface of the silicon wafer by a soft roller coating method. The main components of the phosphorus slurry are phosphoric acid (H3PO4), water and a surfactant, so as to obtain a silicon wafer with a surface evenly covered with phosphorus slurry;
[0068] (5) The silicon wafer with the surface uniformly covered with phosphorus paste in step (4) is transported into a diffusion furnace via a ceramic roller for chain diffusion doping, wherein the metal impurities are further captured and removed. Nitrogen is introduced into the diffusion furnace as a protective gas, the doping temperature is 800° C., and the doping time is 180 s, thereby obtaining a doped silicon wafer.
[0069] Example 2
[0070] A silicon wafer double gettering method comprises the following steps:
[0071] (1) performing pre-cleaning and drying treatment on the single crystal silicon wafer after diamond wire cutting to obtain a pre-cleaned single crystal silicon wafer;
[0072] (2) using chemical etching to clean the surface of the single crystal silicon wafer before step (1) and then etching it to form artificial defects, thereby obtaining a chemically etched silicon wafer;
[0073] The chemical etching method is a tank process, which includes the following steps:
[0074] At room temperature, the surface of the silicon wafer was etched using a 20% mass concentration etching solution (HF solution) for a reaction time of 200 seconds.
[0075] Then, the surface of the silicon wafer was cleaned with deionized water at room temperature for 120 seconds, and then the silicon wafer was purged with clean air at 70°C to dehydrate and dry the silicon wafer for 120 seconds.
[0076] (3) The silicon wafer after chemical etching in step (2) is transported into a high-temperature furnace via a ceramic roller for high-temperature heat treatment to promote the diffusion of impurities into defects. Nitrogen is introduced into the high-temperature furnace as a protective gas. The heat treatment temperature is 700° C. and the heat treatment time is 90 seconds to obtain a heat-treated silicon wafer;
[0077] (4) After the heat treatment in step (3), the silicon wafer is cooled by cold clean air blowing, and then phosphorus slurry is evenly coated on the surface of the silicon wafer by a soft roller coating method. The main components of the phosphorus slurry are phosphoric acid (H3PO4), water and a surfactant, so as to obtain a silicon wafer with a surface evenly covered with phosphorus slurry;
[0078] (5) The silicon wafer with the surface uniformly covered with phosphorus paste in step (4) is transported into a diffusion furnace via a ceramic roller to perform chain diffusion doping, wherein the metal impurities are further captured and removed. Nitrogen is introduced into the diffusion furnace as a protective gas, the doping temperature is 750° C., and the doping time is 240 s, thereby obtaining a doped silicon wafer.
[0079] Example 3
[0080] A silicon wafer double gettering method comprises the following steps:
[0081] (1) performing pre-cleaning and drying treatment on the single crystal silicon wafer after diamond wire cutting to obtain a pre-cleaned single crystal silicon wafer;
[0082] (2) using chemical etching to clean the surface of the single crystal silicon wafer before step (1) and then etching it to form artificial defects, thereby obtaining a chemically etched silicon wafer;
[0083] The chemical etching method is a gas phase process, which includes the following steps:
[0084] In a nitrogen atmosphere, the etching liquid vapor is introduced, and the reaction time with the silicon wafer is 100 seconds; wherein the etching liquid is a KOH solution with a mass concentration of 25%;
[0085] Then, the surface of the silicon wafer was cleaned with deionized water at room temperature for 180 seconds, and then the silicon wafer was purged with clean air at 70°C to dehydrate and dry the silicon wafer for 120 seconds.
[0086] (3) The silicon wafer after chemical etching in step (2) is transported into a high-temperature furnace via a ceramic roller for high-temperature heat treatment to promote the diffusion of impurities into defects. Nitrogen is introduced into the high-temperature furnace as a protective gas. The heat treatment temperature is 800° C. and the heat treatment time is 60 s to obtain a heat-treated silicon wafer;
[0087] (4) After the heat treatment in step (3), the silicon wafer is cooled by cold clean air blowing, and then a phosphorus slurry is evenly coated on the surface of the silicon wafer by ultrasonic spraying. The main components of the phosphorus slurry are phosphoric acid (H3PO4), water and a surfactant, so as to obtain a silicon wafer with a surface evenly covered with the phosphorus slurry;
[0088] (5) The silicon wafer with the surface uniformly covered with phosphorus paste in step (4) is transported into a diffusion furnace via a ceramic roller to perform chain diffusion doping, wherein the metal impurities are further captured and removed. Nitrogen is introduced into the diffusion furnace as a protective gas, the doping temperature is 900° C., and the doping time is 120 s, thereby obtaining a doped silicon wafer.
[0089] Example 4
[0090] The difference between this embodiment and embodiment 1 is that the mass concentration of the etching solution (HF solution) used in step (2) of this embodiment is 10%, and the remaining steps and process parameters are the same as those of embodiment 1 to obtain a silicon wafer after doping.
[0091] Example 5
[0092] The difference between this embodiment and embodiment 1 is that the etching solution used in step (2) of this embodiment is NaOH solution, and the remaining steps and process parameters are the same as those of embodiment 1 to obtain a silicon wafer after doping.
[0093] Example 6
[0094] The difference between this embodiment and embodiment 1 is that the heat treatment temperature in step (3) of this embodiment is 500° C., and the remaining steps and process parameters are the same as those of embodiment 1, to obtain a doped silicon wafer.
[0095] Example 7
[0096] The difference between this embodiment and embodiment 1 is that the heat treatment temperature in step (3) of this embodiment is 900° C., and the remaining steps and process parameters are the same as those of embodiment 1, to obtain a doped silicon wafer.
[0097] Example 8
[0098] The difference between this embodiment and embodiment 1 is that the gettering temperature in step (5) of this embodiment is 650° C., and the remaining steps and process parameters are the same as those of embodiment 1, to obtain a gettered silicon wafer.
[0099] Example 9
[0100] The difference between this embodiment and embodiment 1 is that the gettering temperature in step (5) of this embodiment is 950° C., and the remaining steps and process parameters are the same as those of embodiment 1, to obtain a gettered silicon wafer.
[0101] Comparative Example 1
[0102] The difference between this comparative example and Example 1 is that the chemical etching in step (2) and the heat treatment in step (3) are not performed in this comparative example 1, and the remaining steps and their process parameters are the same as those in Example 1 to obtain a silicon wafer.
[0103] Compared with Example 1, the defect of this comparative example is that only phosphorus diffusion and doping are performed, impurities need to diffuse from a deeper position to the surface, and the coating surface area of the phosphorus paste is small, resulting in a low doping efficiency.
[0104] Comparative Example 2
[0105] The difference between this comparative example and Example 1 is that the chemical etching in step (2) is not performed in this comparative example, and the remaining steps and process parameters are the same as those in Example 1 to obtain a silicon wafer.
[0106] Compared with Example 1, the defect of this comparative example is that high-temperature heat treatment is directly performed without chemical corrosion, which results in impurities being unable to be captured in defects and may even lead to the formation of internal defects, resulting in a decrease in the minority carrier lifetime.
[0107] Comparative Example 3
[0108] The difference between this comparative example and Example 1 is that the heat treatment in step (3) is not performed in this comparative example, and the remaining steps and process parameters are the same as those in Example 1 to obtain a silicon wafer.
[0109] Compared with Example 1, the defect of this comparative example is that no heat treatment is performed, resulting in the impurities being unable to diffuse to the artificial defects; during the phosphorus diffusion and doping process, the diffusion time of the impurities is prolonged or the diffusion is insufficient, resulting in a decrease in the minority carrier lifetime.
[0110] Comparative Example 4
[0111] The difference between this comparative example and Example 1 is that the diffusion gettering in step (5) is not performed in this comparative example, and the remaining steps and process parameters are the same as those in Example 1 to obtain a silicon wafer.
[0112] Compared with Example 1, the defect of this comparative example is that no diffusion gettering is performed, resulting in impurities being concentrated at the artificial defects and unable to be removed, the impurity concentration in the silicon wafer is not reduced, and the minority carrier lifetime is not improved.
[0113] Test example
[0114] The metal impurity contents in the silicon wafers obtained after gettering in Examples 1-9 and the silicon wafers obtained in Comparative Examples 1-4 are shown in Table 1.
[0115] Table 1
[0116]
[0117] As can be seen from Table 1, by adopting the dual impurity gettering strategy of "chemical corrosion + phosphorus diffusion gettering", the metal impurity content in the silicon wafer is effectively reduced, especially the metals with slower diffusion such as Fe and Cr can be fully diffused and gettered, while the minority carrier lifetime of the silicon wafer is increased by 25%-40%, which greatly reduces the recombination of minority carriers and is beneficial to improving the final conversion efficiency of the battery.
[0118] The performance of the silicon wafers obtained after gettering in Examples 1-9 and the silicon wafers obtained in Comparative Examples 1-4 were tested respectively, and the results are shown in Table 2.
[0119] Performance testing method: Test the minority carrier lifetime of silicon wafers and the battery conversion efficiency after being made into battery cells.
[0120] Table 2
[0121]
[0122] It can be seen that the present invention adopts a double impurity gettering strategy of "chemical corrosion + phosphorus diffusion gettering". First, the surface of the silicon wafer is artificially etched with chemical reagents such as acid and alkali to form defects, and then heat-treated in a high-temperature furnace to diffuse and migrate some metal impurities in the silicon wafer into the defect layer; afterwards, in order to further remove impurities, phosphorus diffusion gettering is performed on the heat-treated silicon wafer, and a chain gettering process with H3PO4 as the diffusion source is used. A phosphorus silicon glass gettering layer is formed by high-temperature dehydration and reaction in the gettering furnace to achieve the purpose of gettering. In short, the double impurity gettering method of the present invention, under the coordinated cooperation of each step and its process parameters, can increase the minority carrier lifetime of the silicon wafer after gettering by 25%-40%, greatly reduce the recombination of minority carriers, and effectively improve the final conversion efficiency of the battery, and the conversion efficiency can be increased by 0.2%-1.0%.
[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A silicon wafer double gettering method, characterized in that: The following steps are involved: Providing a raw silicon wafer, performing surface etching on the raw silicon wafer to form defects as gettering centers, and sequentially performing heat treatment and phosphorus diffusion gettering to obtain a substrate silicon wafer; The surface etching method includes chemical etching; The chemical etching solution includes at least one of HF, KOH and NaOH.
2. The double gettering method according to claim 1, characterized in that: The mass concentration of the corrosive liquid is 10-25%; Preferably, the chemical etching method is etching by a gas phase process; Preferably, the gas phase process includes using corrosive liquid vapor to perform reactive corrosion.
3. The double gettering method according to claim 2, characterized in that: The reaction time between the etching solution and the silicon wafer is 60-400s.
4. The double gettering method according to any one of claims 1 to 3, characterized in that: After the etching, the step of cleaning the silicon wafer is also included; The method for cleaning the silicon wafer comprises first cleaning the surface of the silicon wafer with deionized water, and then blowing the surface of the silicon wafer with gas.
5. The double gettering method according to any one of claims 1 to 3, characterized in that: The temperature of the heat treatment is 500-900° C., and the time of the heat treatment is 30-200 seconds.
6. The double gettering method according to any one of claims 1 to 3, characterized in that: The phosphorus diffusion gettering includes chain phosphorus diffusion gettering.
7. The double gettering method according to claim 6, characterized in that: The temperature of the chain phosphorus diffusion gettering is 650-950° C., and the time of the chain phosphorus diffusion gettering is 100-1000 s.
8. The double gettering method according to claim 7, characterized in that: The diffusion source of the chain phosphorus diffusion gettering includes H3PO4.
9. The double gettering method according to claim 8, characterized in that: The H3PO4 is covered on the surface of the heat-treated silicon wafer by smearing and / or ultrasonic spraying.
10. A method for preparing a heterojunction battery cell, characterized in that: The method comprises preparing a substrate silicon wafer using the double gettering method according to any one of claims 1 to 9; Performing texturing treatment on at least one side of the substrate silicon wafer using a texturing agent; Sequentially depositing an intrinsic passivation layer and a doping layer on both sides of the substrate silicon wafer; Conductive film deposition is performed on both sides of the substrate silicon wafer and electrodes are prepared.