MEMS filtering isolation coupler and processing method

By using MEMS filter isolation coupler in RF devices and using silicon-based band lines and multi-layer substrate integrated waveguide structure, the problem of signal crosstalk after assembly of traditional RF devices is solved, and the miniaturization of RF systems, high power capacity and full electromagnetic shielding effect is achieved.

CN119742558AActive Publication Date: 2025-04-01MT MICROSYST
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Patent Information

Application Number
CN202510183082.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-02-19
Publication Date
2025-04-01
Estimated Expiration
2045-02-19

AI Technical Summary

Technical Problem

After the assembly of traditional RF devices, the devices are prone to crosstalk between signals, interfering with the quality of signal transmission.

Method used

Using MEMS filter isolation coupler, the integrated waveguide structure of silicon-based band lines and multi-layer substrates is used to integrate the waveguide structure. The designed RF device has a fully electromagnetic shielding effect. Through the three-dimensional multi-layer silicon-based process of the silicon-based MEMS filter isolation coupler, the circuit cascade optimization between devices is achieved.

Benefits of technology

It realizes the miniaturization of the RF system, high power capacity, and fully electromagnetic shielded anti-interference ability, improves electrical performance, reduces overall loss, and reduces the overall size.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention provides an MEMS filtering isolation coupler and a processing method, and belongs to the technical field of radio frequency MEMS passive devices. The MEMS filtering isolation coupler comprises a metal carrier, a silicon chip and magnetic steel; the silicon chip comprises a lower-layer silicon wafer and an upper-layer silicon wafer which are superposed, the lower surface of the lower-layer silicon wafer is connected with the metal carrier, the lower end of the lower-layer silicon wafer is provided with a mounting groove with a downward opening, and the mounting groove is used for accommodating the gyromagnetic ferrite; the lower-layer silicon wafer and the upper-layer silicon wafer are longitudinally connected, and a metal circuit is formed between the lower-layer silicon wafer and the upper-layer silicon wafer; the metal circuit comprises a filter function circuit, an isolator function circuit and a coupler function circuit; and the magnetic steel is adhered to the upper end surface of the upper silicon wafer. According to the MEMS filtering isolation coupler provided by the invention, a silicon-based strip line and multi-layer substrate integrated waveguide structure is adopted, a designed radio frequency device has higher power capacity and a full-electromagnetic shielding effect, and the problems that current communication equipment is complex and electromagnetic environment interference is serious are effectively solved.
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Description

Technical Field

[0001] The invention belongs to the technical field of radio frequency MEMS passive devices, and more specifically, relates to a MEMS filtering isolation coupler and a processing method thereof. Background Art

[0002] At present, communication equipment is developing in the direction of miniaturization, high efficiency, anti-interference, energy saving and efficiency improvement, which puts forward an urgent demand for integrated, high-power, high-performance and full electromagnetic shielding of RF devices in transceiver components. The miniaturization and integration of RF devices can effectively reduce the complexity and volume of communication equipment, improve the integration and portability of equipment; the high power and high performance of RF devices directly improve the power and efficiency of transceiver components, which is conducive to the coverage and communication quality of communication equipment; the full electromagnetic shielding of RF devices can reduce signal leakage and the intervention of external noise interference, protect communication equipment from external interference, ensure the stability of RF signal transmission, and thus improve the reliability of the entire RF system.

[0003] The isolator is a transmitting component used in communication equipment. It plays the role of one-way transmission, absorbing reflections to protect the power amplifier, and improving the output characteristics of the subsequent stage. The coupler couples the transmitting power in the transmitting component and plays the role of power monitoring and signal analysis. The filter retains the signals within a specific frequency band and filters out unnecessary signals outside the specific frequency, thereby improving the signal-to-noise ratio of the communication system.

[0004] Traditionally, the transceiver assembly uses micro-assembly processes such as gold wire bonding, chip bonding, and welding to assemble the above-mentioned RF devices together. The advantage is the simple process, but the disadvantage is low assembly efficiency, easy assembly errors, poor consistency, especially without special electromagnetic shielding between devices, which is very easy to cause signal crosstalk during high-power operation, interfere with signal transmission quality, and even seriously deteriorate the electrical performance of the components. Summary of the invention

[0005] The purpose of the present invention is to provide a MEMS filter isolation coupler and a processing method, aiming to solve the problem that after traditional radio frequency devices are assembled, signals are easily crosstalked between devices, which interferes with the signal transmission quality.

[0006] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: to provide a MEMS filter isolation coupler, including a metal carrier, a silicon chip and a magnetic steel; the silicon chip includes a stacked lower silicon wafer and an upper silicon wafer, the lower surface of the lower silicon wafer is connected to the metal carrier, and the lower end of the lower silicon wafer is provided with a mounting groove with an opening facing downward, and the mounting groove is used to accommodate a rotating magnetic ferrite; the lower silicon wafer and the upper silicon wafer are longitudinally connected and a metal circuit is formed therebetween, and the metal circuit includes a filter function circuit, an isolator function circuit and a coupler function circuit; the lower silicon wafer and the upper silicon wafer both have metallized vias along the thickness direction, and the metallized vias are used to connect the metal circuit; the magnetic steel is bonded to the upper end surface of the upper silicon wafer.

[0007] As another embodiment of the present application, the lower surface of the lower silicon wafer has a lower metal ground pattern, and the metal ground pattern is used to connect the metal carrier; The upper surface of the lower silicon wafer has a lower circuit metal pattern, the lower surface of the upper silicon wafer has an upper circuit metal pattern, and the lower circuit metal pattern and the upper circuit metal pattern are bonded to form the metal circuit; The upper surface of the upper silicon wafer has an upper metal ground pattern.

[0008] As another embodiment of the present application, the metal circuit is connected to a thin film resistor, and the thin film resistor is located between the lower silicon wafer and the upper silicon wafer.

[0009] As another embodiment of the present application, the metallized via includes a lower through hole passing through the lower silicon wafer and an upper through hole passing through the upper silicon wafer, the lower through hole connecting the lower metal ground pattern and the metal circuit, and the upper through hole connecting the upper metal ground pattern and the metal circuit.

[0010] As another embodiment of the present application, the lower through hole includes a first lower through hole and a second lower through hole, the upper end of the first lower through hole is connected to the upper through hole, and the upper end of the second lower through hole is connected to the metal circuit.

[0011] As another embodiment of the present application, the cross-section of the metallized via is circular, and the inner diameter of the metallized via gradually decreases toward the metal circuit.

[0012] As another embodiment of the present application, the depth of the mounting groove is 0.6-0.85 times the thickness of the underlying silicon wafer.

[0013] The beneficial effects of the MEMS filter isolation coupler provided by the present invention are as follows: compared with the prior art, the MEMS filter isolation coupler of the present invention utilizes the unique three-dimensional multi-layer silicon-based process of MEMS, adopts silicon-based strip lines and multi-layer substrate integrated waveguide structures, and the designed radio frequency devices have higher power capacity and full electromagnetic shielding effect, which effectively solves the problems of complex current communication equipment and serious electromagnetic environment interference; and improves the miniaturization, high power capacity, and full electromagnetic shielding anti-interference ability of the radio frequency system; achieves circuit cascade optimization between devices, improves electrical performance, reduces overall loss, and reduces overall size, thereby achieving the goal of miniaturization of the MEMS filter isolation coupler.

[0014] A method for processing a MEMS filter isolation coupler is also provided, comprising the following steps: S1. Prepare the lower silicon wafer: Etching mounting grooves and lower through holes on the lower silicon wafer, preparing lower circuit metal patterns, metal ground, and thin film resistors for filter function / isolator function / coupler function on the upper surface of the lower silicon wafer, and preparing lower metal ground patterns on the lower surface; S2. Prepare the upper silicon wafer: Etching an upper through hole on the upper silicon wafer, preparing an upper circuit metal pattern and a metal ground for a filter function / isolator function / coupler function on the lower surface of the upper silicon wafer, and preparing an upper metal ground pattern on the upper surface; S3. Preparation of silicon chip: The upper silicon wafer is stacked on the upper end of the lower silicon wafer and wafer-level bonding is performed; S4. Assembling silicon chip: The rotating magnetic ferrite is installed in the above-mentioned installation groove, the lower surface of the lower silicon wafer is connected to the metal carrier, and the upper surface of the upper silicon wafer is adhered to the magnetic steel.

[0015] As another embodiment of the present application, the side walls of the lower through hole and the upper through hole are both metallized to form metallized vias.

[0016] As another embodiment of the present application, in step S3, the bonded double-layer silicon wafer needs to be diced to obtain a single filter isolation coupling chip.

[0017] The beneficial effect of the MEMS filter isolation coupler processing method provided by the present invention is that: compared with the prior art, the MEMS filter isolation coupler processing method of the present invention can very conveniently prepare strip line and multi-layer substrate integrated waveguide structures through the cooperation of the lower silicon wafer and the upper silicon wafer. The process is mature, simple and stable, which is conducive to the mass production of MEMS filter isolation couplers. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the internal circuit principle of a MEMS filtering isolation coupler provided in an embodiment of the present invention; Figure 2 A schematic cross-sectional structure diagram of a MEMS filter isolation coupler provided in an embodiment of the present invention; Figure 3 A schematic diagram of the production process flow of a MEMS filter isolation coupler provided in an embodiment of the present invention; Figure 4 A schematic diagram of the assembly process of a MEMS filtering isolation coupler provided in an embodiment of the present invention.

[0020] In the figure: 1. upper silicon wafer; 2. lower silicon wafer; 3. metal carrier; 4. gyromagnetic ferrite; 5. magnetic steel; 6. first lower through hole; 7. second lower through hole; 8. upper through hole; 9. metal circuit; 10. upper metal ground pattern; 11. lower metal ground pattern; 12. mounting groove; 13. lower circuit metal pattern; 14. upper circuit metal pattern; 15. filter functional circuit; 16. thin film resistor; 17. isolator functional circuit; 18. coupler functional circuit. DETAILED DESCRIPTION

[0021] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0022] See also Figures 1 to 4, the MEMS filter isolation coupler and processing method provided by the present invention are now described. The MEMS filter isolation coupler includes a metal carrier 3, a silicon chip and a magnetic steel 5; the silicon chip includes a stacked lower silicon wafer 2 and an upper silicon wafer 1, the lower surface of the lower silicon wafer 2 is connected to the metal carrier 3, and the lower end of the lower silicon wafer 2 is provided with a mounting groove 12 with an opening facing downward, and the mounting groove 12 is used to accommodate a rotating magnetic ferrite 4; the lower silicon wafer 2 and the upper silicon wafer 1 are longitudinally connected and a metal circuit 9 is formed between the two, and the metal circuit 9 includes a filter function circuit 15, an isolator function circuit 17 and a coupler function circuit 18; the lower silicon wafer 2 and the upper silicon wafer 1 both have metallized vias along the thickness direction, and the metallized vias are used to connect the metal circuit 9; the magnetic steel 5 is bonded to the upper end surface of the upper silicon wafer 1.

[0023] Compared with the prior art, the MEMS filtering isolation coupler provided by the present invention utilizes the unique three-dimensional multi-layer silicon-based process of MEMS, adopts silicon-based strip lines and multi-layer substrate integrated waveguide structures, and the designed radio frequency device has higher power capacity and full electromagnetic shielding effect, which effectively solves the problems of complex current communication equipment and serious electromagnetic environment interference; and improves the miniaturization, high power capacity, and full electromagnetic shielding anti-interference ability of the radio frequency system; achieves circuit cascade optimization between devices, improves electrical performance, reduces overall loss, and reduces overall size, thereby realizing the goal of miniaturization of MEMS filtering isolation couplers.

[0024] Optionally, the metal carrier 3 is made of iron-nickel alloy, which serves as a ground carrier for the magnetic matching and filtering of the gyromagnetic ferrite 4 and the thermal stress matching of the coupled silicon chip. The magnetic steel 5 is made of samarium cobalt permanent magnet, which serves to provide a steady DC magnetic field for the isolator. The metallized via is a silicon-based metallized through hole, which serves as an equivalent metal sidewall and a connection to the RF ground.

[0025] The lower surface of the lower silicon wafer 2 has a lower metal ground pattern 11, and the metal ground pattern is used to connect the metal carrier 3; the upper surface of the lower silicon wafer 2 has a lower circuit metal pattern 13, and the lower surface of the upper silicon wafer 1 has an upper circuit metal pattern 14, and the lower circuit metal pattern 13 and the upper circuit metal pattern 14 are bonded to form a metal circuit 9; the upper surface of the upper silicon wafer 1 has an upper metal ground pattern 10.

[0026] Circuit metal patterns are arranged on the upper surface of the lower silicon wafer 2 and the lower surface of the upper silicon wafer 1, and the two circuit metal patterns are connected by longitudinal gold-gold bonding to form a metal circuit 9. The metal circuit 9 includes a filter function circuit 15, an isolator function circuit 17, a coupler function circuit 18, etc.

[0027] The traditional RF device installation method is a micro-assembly process, including welding, bonding, and gold wire bonding of multiple chips. The assembly efficiency is low, and there are assembly errors of more than millimeter level, resulting in poor index consistency. The MEMS filter isolation coupling chip, that is, the above-mentioned silicon chip, compactly cascades the three RF function circuits through the connection of the lower silicon wafer 2 and the upper silicon wafer 1, and matches and optimizes the electrical performance inside the silicon chip. There is no need for later use and debugging, and it has high performance while reducing the size. The MEMS three-dimensional process used has the characteristics of micron-level high precision, good index consistency, and easy mass production.

[0028] The MEMS filter isolation coupling chip is based on a double-layer silicon wafer, and the thermal conductivity of the silicon wafer is 140W / (m*K). Common filters and couplers are based on ceramics or gallium arsenide, and the thermal conductivity is usually in the range of 20 to 50W / (m*K). Compared with common ceramic or gallium arsenide RF devices, the heat dissipation effect of silicon wafers is better under power heat consumption. In addition, the RF device uses a silicon-based stripline and a multi-layer substrate integrated waveguide structure, which has a smaller electric field and magnetic field density than the microstrip structure. In particular, the maximum magnetic field strength of the multi-layer substrate integrated waveguide structure decreases by more than 50%, significantly improving the power handling capacity of the RF device. Therefore, the MEMS filter isolation coupling chip has a high power capacity.

[0029] In addition, the outermost surface of the MEMS filter isolation coupling chip is all metal, which has the characteristics of full electromagnetic shielding, and can significantly reduce signal leakage and external noise interference. The MEMS three-dimensional silicon process can be used to easily prepare stripline and multi-layer substrate integrated waveguide structures, and the process is mature, simple and stable.

[0030] Optionally, the MEMS filter isolation coupling chip is composed of a lower silicon wafer 2 and an upper silicon wafer 1 stacked together, wherein the thickness of the lower silicon wafer 2 and the upper silicon wafer 1 are both 0.4mm-0.65mm, and the resistivity of the two silicon wafers is required to be greater than 3000Ω•cm.

[0031] In some possible embodiments, see Figure 1 The metal circuit 9 is connected to a thin film resistor 16, and the thin film resistor 16 is located between the lower silicon wafer 2 and the upper silicon wafer 1. The thin film resistor 16 is a NiCr thin film or a TaN thin film.

[0032] The above-mentioned metal circuit 9 plays the function of an isolator, adopts a multi-layer substrate integrated waveguide structure, utilizes an external magnetic steel 5 to magnetize the gyromagnetic ferrite 4, and performs non-reciprocal unidirectional transmission between the input port and the output port to output the working signal. The third port is cascaded with a thin film resistor 16 to absorb the reverse signal.

[0033] The input port of the isolator structure is cascaded with a filter circuit. The filter circuit uses a silicon-based stripline transmission line, and can select λ / 4 or λ / 2 resonators. The bandpass filter function is realized through an interdigital or comb-line topology structure. The in-band working signal is transmitted normally, and the out-band noise signal is suppressed.

[0034] The output port of the isolator structure is cascaded with a coupler circuit. The coupler circuit adopts a silicon-based stripline transmission line and realizes the coupler function through a narrow-edge coupled transmission line topology. The through port transmits the working signal, and the coupled port outputs the coupled signal. The coupled signal is used to monitor the working signal power and signal analysis.

[0035] The three RF devices are tightly cascaded, and the internal direct matching optimizes telecommunications indicators, reducing the size while maintaining high performance, reducing the use of micro-assembly and debugging in the later stage, and achieving the full electromagnetic shielding effect and high power capacity effect of the MEMS filter isolation coupler.

[0036] In some possible embodiments, see Figure 2 The metallized vias include a lower through hole penetrating the lower silicon wafer 2 and an upper through hole 8 penetrating the upper silicon wafer 1, the lower through hole connecting the lower metal ground pattern 11 and the metal circuit 9, and the upper through hole 8 connecting the upper metal ground pattern 10 and the metal circuit 9. The shape of the metallized via is not limited, and can be a circular hole, a square hole, or a polygonal hole.

[0037] The lower through hole penetrating the lower silicon wafer 2 is used to connect the metal circuit 9 on the lower surface and the upper surface of the lower silicon wafer 2; the upper through hole 8 penetrating the upper silicon wafer 1 is used to connect the metal circuit 9 on the lower surface and the upper surface of the upper silicon wafer 1.

[0038] The lower through hole includes a first lower through hole 6 and a second lower through hole 7 . The upper end of the first lower through hole 6 is connected to the upper through hole 8 , and the upper end of the second lower through hole 7 is connected to the metal circuit 9 .

[0039] The upper through hole 8 in the stripline structure region of the upper silicon wafer 1 is aligned with and connected to the first lower through hole 6 .

[0040] When the cross section of the metallized via is circular, the inner diameter of the metallized via gradually decreases toward the direction of the metal circuit 9. The change in the inner diameter of the metallized via not only facilitates the manufacturing process, but also helps to adapt to the wiring density of the metal circuit 9. Since the wiring density of the metal circuit 9 is greater than the wiring density of the upper surface of the upper silicon wafer 1 and the wiring density of the lower surface of the lower silicon wafer 2, setting the metallized via as a variable diameter hole can further adapt to the wiring of the two connected circuits, thereby improving the connection stability.

[0041] The depth of the mounting groove 12 is 0.6-0.85 times the thickness of the lower silicon wafer 2. The depth of the mounting groove 12 can be adjusted according to the design, and the range is generally between 0.6-0.85 times the thickness of the silicon wafer. The shape of the mounting groove 12 can be circular, square or polygonal. The sidewalls of the mounting groove 12 are not metallized.

[0042] A method for processing a MEMS filter isolation coupler is also provided, comprising the following steps: S1. Prepare the lower silicon wafer 2: Etching mounting grooves 12 and metalized vias on the lower silicon wafer 2, preparing lower circuit metal patterns 13, metal ground, and thin film resistors 16 for filter functions / isolator functions on the upper surface of the lower silicon wafer 2, and preparing lower metal ground patterns 11 on the lower surface; S2. Preparation of upper silicon wafer 1: Etching metalized vias on the upper silicon wafer 1, preparing an upper circuit metal pattern 14 and a metal ground for a filter function / isolator function / coupler function on the lower surface of the upper silicon wafer 1, and preparing an upper metal ground pattern 10 on the upper surface; S3. Preparation of silicon chip: The upper silicon wafer 1 is stacked on the upper end of the lower silicon wafer 2 and wafer-level bonding is performed; S4. Assembling silicon chip: The rotating magnetic ferrite 4 is installed in the above-mentioned installation groove 12, the lower surface of the lower silicon wafer 2 is connected to the metal carrier 3, and the upper surface of the upper silicon wafer 1 is adhered to the magnetic steel 5.

[0043] First, a lower silicon wafer 2 and an upper silicon wafer 1 are prepared, and a metal circuit 9 is formed between the lower silicon wafer 2 and the upper silicon wafer 1 using the circuit metal patterns thereon. The metal circuit 9 includes a filter function circuit 15, an isolator function circuit 17 and a coupler function circuit 18 connected in sequence; and metallized vias are used to connect the metal circuit 9 to the circuits on the outside of the upper silicon wafer 1 and the lower silicon wafer 2 to form a silicon chip; and the assembly of the filter isolation coupler is then realized by assembling the silicon chip.

[0044] Compared with the prior art, the MEMS filter isolation coupler processing method provided by the present invention can very conveniently prepare stripline and multi-layer substrate integrated waveguide structures through the cooperation of the lower silicon wafer 2 and the upper silicon wafer 1. The process is mature, simple and stable, which is conducive to the mass production of MEMS filter isolation couplers.

[0045] In steps S1 and S2 , the side walls of the lower through hole and the upper through hole 8 are both metallized to form metallized vias.

[0046] With respect to step S1, the preparation steps of the lower silicon wafer 2 are as follows: First, a mounting groove 12 of a specific depth is deeply etched on the lower surface of the lower silicon wafer 2, with the groove opening of the mounting groove 12 facing downward. A plurality of through silicon vias are etched in the thickness direction of the lower silicon wafer 2, and the through silicon vias are generally circular holes or square holes.

[0047] Then, metal circuits 9 , metal ground, thin film resistors 16 and other patterns of filter function / isolator function / coupler function are prepared on the upper surface of the lower silicon wafer 2 ; and metal ground patterns are prepared on the lower surface of the lower silicon wafer 2 .

[0048] Then, the sidewalls of the lower through hole of the lower silicon wafer 2 are metallized, and the lower through hole electrically connects the upper and lower metal circuits 9 of the lower silicon wafer 2. The inner sidewalls of the mounting groove 12 do not need to be processed during the metallization process.

[0049] For step S2, the upper silicon wafer 1 is prepared as follows: First, a plurality of through silicon vias (TSVs) are etched in the thickness direction of the upper silicon wafer 1. The TSVs in the stripline structure area are aligned with the first lower end through hole 6 of the lower silicon wafer 2.

[0050] Then, metal circuits 9 with filter functions / isolator functions / coupler functions, metal ground and other metal patterns are prepared on the lower surface of the upper silicon wafer 1; and metal ground patterns are prepared on the upper surface of the upper silicon wafer 1.

[0051] Next, the sidewalls of the upper through hole 8 of the upper silicon wafer 1 are metallized, and the upper through hole 8 electrically connects the upper and lower surfaces of the upper silicon wafer 1 with the metal circuits 9 .

[0052] In step S3, the bonded double-layer silicon wafer needs to be diced to obtain a single filter isolation coupling chip.

[0053] For step S3, the upper silicon wafer 1 and the lower silicon wafer 2 are wafer-level bonded to form a silicon-based MEMS filter isolation coupling chip structure wafer. The double-layer silicon wafer is diced to obtain a single silicon-based MEMS filter isolation coupling chip.

[0054] For step S4, the single silicon-based MEMS filter isolation coupling chip obtained in step S3 is assembled. The gyromagnetic ferrite 4 is placed in the mounting groove 12 and heterogeneously integrated with the lower silicon wafer 2. The magnetic steel 5 is bonded to the upper surface of the upper silicon wafer 1 above the isolator functional circuit 17 to complete the assembly of the silicon-based MEMS filter isolation coupler.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. MEMS filter isolation coupler, characterized in that: The invention comprises a metal carrier (3), a silicon chip and a magnetic steel (5); the silicon chip comprises a stacked lower silicon wafer (2) and an upper silicon wafer (1); the lower surface of the lower silicon wafer (2) is connected to the metal carrier (3); the lower end of the lower silicon wafer (2) is provided with a mounting groove (12) with an opening facing downwards; the mounting groove (12) is used to accommodate a gyromagnetic ferrite (4); the lower silicon wafer (2) and the upper silicon wafer (1) are longitudinally connected and a metal circuit (9) is formed therebetween; the metal circuit (9) comprises a filter function circuit (15), an isolator function circuit (17) and a coupler function circuit (18); the lower silicon wafer (2) and the upper silicon wafer (1) both have metallized vias along the thickness direction; the metallized vias are used to connect the metal circuit (9); the magnetic steel (5) is bonded to the upper end surface of the upper silicon wafer (1).

2. The MEMS filter isolation coupler according to claim 1, characterized in that: The lower surface of the lower silicon wafer (2) has a lower metal ground pattern (11), and the metal ground pattern is used to connect the metal carrier (3); The upper surface of the lower silicon wafer (2) has a lower circuit metal pattern (13), the lower surface of the upper silicon wafer (1) has an upper circuit metal pattern (14), and the lower circuit metal pattern (13) and the upper circuit metal pattern (14) are bonded and connected to form the metal circuit (9); The upper surface of the upper silicon wafer (1) has an upper metal ground pattern (10).

3. The MEMS filter isolation coupler according to claim 2, characterized in that: The metal circuit (9) is connected to a thin film resistor (16), and the thin film resistor (16) is located between the lower silicon wafer (2) and the upper silicon wafer (1).

4. The MEMS filter isolation coupler according to claim 2, characterized in that: The metallized via comprises a lower through hole penetrating the lower silicon wafer (2) and an upper through hole (8) penetrating the upper silicon wafer (1), the lower through hole connecting the lower metal ground pattern (11) and the metal circuit (9), and the upper through hole (8) connecting the upper metal ground pattern (10) and the metal circuit (9).

5. The MEMS filter isolation coupler according to claim 4, characterized in that: The lower end through hole comprises a first lower end through hole (6) and a second lower end through hole (7), the upper end of the first lower end through hole (6) is connected to the upper end through hole (8), and the upper end of the second lower end through hole (7) is connected to the metal circuit (9).

6. The MEMS filter isolation coupler according to claim 4, characterized in that: The cross section of the metallized via hole is circular, and the inner diameter of the metallized via hole gradually decreases towards the metal circuit (9).

7. The MEMS filter isolation coupler according to claim 1, characterized in that: The depth of the mounting groove (12) is 0.6-0.85 times the thickness of the lower silicon wafer (2).

8. A method for processing a MEMS filter isolation coupler, characterized in that: The following steps are involved: S1. Preparing a lower silicon wafer (2): Etching a mounting groove (12) and a lower through hole on the lower silicon wafer (2), preparing a lower circuit metal pattern (13), a metal ground, and a thin film resistor (16) for a filter function / an isolator function / a coupler function on the upper surface of the lower silicon wafer (2), and preparing a lower metal ground pattern (11) on the lower surface; S2. Preparing an upper silicon wafer (1): Etching an upper through hole (8) on the upper silicon wafer (1), preparing an upper circuit metal pattern (14) and a metal ground for a filter function / isolator function / coupler function on the lower surface of the upper silicon wafer (1), and preparing an upper metal ground pattern (10) on the upper surface; S3. Preparation of silicon chip: The upper silicon wafer (1) is stacked on the upper end of the lower silicon wafer (2) and wafer-level bonding is performed; S4. Assembling silicon chip: The rotating magnetic ferrite (4) is installed in the above-mentioned installation groove (12), the lower surface of the lower silicon wafer (2) is connected to the metal carrier (3), and the upper surface of the upper silicon wafer (1) is adhered to the magnetic steel (5).

9. The method for manufacturing a MEMS filter isolation coupler according to claim 8, wherein: The side walls of the lower through hole and the upper through hole (8) are both metallized to form metallized vias.

10. The method for manufacturing a MEMS filter isolation coupler according to claim 8, wherein: In step S3, the bonded double-layer silicon wafer needs to be diced to obtain a single filter isolation coupling chip.

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