High-efficiency synchronous rectification speed regulation circuit of brushless direct current motor

Abstract

The invention discloses a high-efficiency synchronous rectification speed regulation circuit of a brushless direct current motor, which comprises a synchronous rectification speed regulation controller, a trapezoidal controller, a grid controller and a bridge driver which are integrated on the same chip, the synchronous rectification speed regulation controller comprises a synchronous rectification comparator, a rectification time regulator, a dead time insertion module, an interlocking protection module, an anti-misjudgment module, a detection signal gating unit, a state machine, a digital-to-analog converter and a dead time generator. The built-in synchronous rectification speed regulation controller module is adopted to control the current flowing through the motor, the rectification ripple is adjustable, the dead time influencing the rectification efficiency is optimized, the motor driving efficiency is improved, the speed regulation of the brushless motor can be realized by adopting simple external devices, and the use threshold is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits and motor control, and in particular relates to a high-efficiency synchronous rectification speed regulation circuit for a brushless DC motor. Background Art

[0002] A DC motor is a device that uses a DC power supply to convert electrical energy into mechanical energy. As an important type of DC motor, brushless DC motors are gradually replacing brushed DC motors due to their advantages such as quietness, high efficiency, and long life. They have a wide range of applications, such as industrial control, automotive industry, consumer electronics, and many other fields. The operation of brushless DC motors requires corresponding motor driver chips. Generally speaking, the mainstream electrical structure of brushless DC motors is a Y-type inductive structure, and the common driver structure is a three-phase bridge driver. The main components of the motor driver chip are the motor controller and the bridge driver. The bridge driver is directly connected to the brushless DC motor to drive the motor, and the motor controller is responsible for controlling the bridge driver to realize the electronic commutation and speed control of the brushless motor.

[0003] The motor controller needs to implement electronic commutation. Since the back electromotive force waveform of the brushless DC motor is trapezoidal, the commonly used commutation method is trapezoidal control; however, basic trapezoidal control can only make the brushless DC motor run normally, and cannot achieve motor speed regulation. Speed ​​control depends on the number of motor poles and load current, and is generally achieved by changing the motor power supply frequency.

[0004] The traditional brushless DC motor speed control scheme is as follows [JA Prakosa, DV Samokhvalov, GRV Ponce and F. Sh. Al-Mahturi, "Speed ​​Control of Brushless DC Motor for QuadCopter Drone Ground Test," 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), Saint Petersburg and Moscow, Russia, 2019, pp. 644-648] and [NR Raipure, RTUgale and BN Chaudhari, "Solar Powered BLDC Motor Drive for Wide Speed ​​Range Electric Vehicle Application," 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Chennai, India, 2018, pp. 1-6]. This control system structure is as follows Figure 1 As shown, an external programmable device such as MCU is used to realize trapezoidal control of the motor, and an internal pulse width modulation (PWM) controller is used to control the motor current, thereby realizing speed regulation; the advantage of using an external programmable controller is that it is easy to develop and implement, and the PWM controller integrated in these programmable devices is easy to realize speed control. However, it is difficult for an external controller to obtain the working state of the bridge drive. In order to prevent the high and low sides of the bridge drive from being turned on at the same time, a fixed dead time must be inserted at the moment when the high and low side power tubes are alternately turned on, but this will bring additional efficiency loss; at the same time, the development of an external controller requires a deep understanding of the control principle and implementation scheme of the brushless DC motor, and the threshold for users is relatively high. Summary of the invention

[0005] In view of the above, the present invention provides a high-efficiency brushless DC motor synchronous rectification speed control circuit, which adopts a built-in high-efficiency synchronous rectification controller to provide an optimized dead time, improve the motor drive efficiency, and use simple external devices to achieve speed regulation of the brushless motor, thereby lowering the usage threshold.

[0006] A high-efficiency synchronous rectification speed regulation circuit for a brushless DC motor includes a synchronous rectification speed regulation controller, a trapezoidal controller, a gate controller, and a bridge driver integrated on the same chip, wherein:

[0007] The trapezoidal controller provides a three-phase switch control signal and a three-phase enable signal to the gate controller, controls the bridge driver through the gate controller to realize six-step trapezoidal control of the brushless DC motor, and provides a three-phase enable signal to the synchronous rectification speed control controller to select the phase to be controlled;

[0008] The synchronous rectification controller obtains the three-phase switch state signal of the bridge driver from the chip, provides a synchronous rectification control signal to the gate controller, controls the bridge driver to switch between the freewheeling state and the rectification state through the gate controller, and adjusts the driving current of the bridge driver;

[0009] The gate controller selects the three-phase switch control signal and the synchronous rectification control signal according to the three-phase enable signal, thereby providing the three-phase switch drive signal to the bridge driver;

[0010] The bridge driver amplifies the power of the three-phase switch driving signal to control the on and off of the internal power switch device, thereby driving the brushless DC motor to achieve electronic commutation and speed regulation.

[0011] Furthermore, the synchronous rectification speed control controller comprises:

[0012] A detection signal gating unit selects a switch state signal of one phase from the three-phase switch state signals according to the three-phase enable signal, including the high-side tube state signal HO and the low-side tube state signal LO of the phase;

[0013] The synchronous rectifier comparator acquires the DC feedback voltage of the bridge driver through an off-chip sampling resistor, compares it with the reference voltage, and generates a comparison signal;

[0014] The rectifier time regulator outputs a control signal SR_Ctrl with a fixed pulse width when detecting the rising edge of the comparison signal. The pulse width is adjusted by the timing capacitor outside the chip.

[0015] The dead time insertion module detects the rising edge of the control signal SR_Ctrl in two ways and inserts the dead time through delay to generate the synchronous rectification high side control signal HI and the synchronous rectification low side control signal LI;

[0016] The state machine determines the optimal dead time by judging the signals SR_Ctrl, LO, HO, LI, and HI, thereby outputting the corresponding data signal;

[0017] A digital-to-analog converter, which converts the data signal into analog levels;

[0018] The dead time generator generates the corresponding dead time according to the analog level and provides it to the dead time insertion module.

[0019] Furthermore, when the trapezoidal controller controls the low-side tube of a phase in the bridge driver to turn on, the enable signal of the phase outputted by the trapezoidal controller is high level, and the detection signal gating unit selects the switch state signal of the phase according to the enable signal.

[0020] Furthermore, the synchronous rectification speed control controller also includes an anti-misjudgment module, which is used to detect the rising edge of the low-side tube state signal LO and generate a shielding pulse signal of a fixed duration to provide it to the rectification time regulator. When the corresponding low-side tube is turned on, the rectification time regulator will be briefly shielded to prevent erroneous operation caused by misjudgment of the synchronous rectification comparator.

[0021] Furthermore, the rectifier time regulator includes an RS latch RS1, a three-input AND gate AND4, two-input AND gates AND1 to AND3, an OR gate OR1, buffers BUF1 and BUF2, inverters INV1 and INV2, comparators CMP1 and CMP2, PMOS tubes PM1 and PM2, NMOS tube NM1 and a resistor R C , wherein the first input terminal of AND1 is connected to the comparison signal, the second input terminal of AND1 is connected to the output terminal of INV2 and the first input terminal of AND3, the input terminal of INV2 is connected to the shielding pulse signal, the output terminal of AND1 is connected to the S input terminal of RS1 and the first input terminal of AND4, the R input terminal of RS1 is connected to the third input terminal of AND4 and the output terminal of INV1, the Q output terminal of RS1 is connected to the second input terminal of AND4, the output terminal of AND4 is connected to the first input terminal of OR1, the second input terminal of OR1 is connected to the output terminal of AND2, the output terminal of OR1 is connected to the input terminal of BUF1, the output terminal of BUF1 is connected to the gate of PM1, the gate of PM2 and the gate of NM1, and the source of PM1 is connected to the power supply voltage V CC , the drain of PM1 is connected to the drain of NM1, the positive input terminal of CMP1 and one end of the timing capacitor, the source of NM1 is grounded, and the other end of the timing capacitor is connected to R C One end of PM2 is connected to the drain of PM2 and the inverting input of CMP2. C The other end is connected to the source of PM2 and connected to the power supply voltage V CC , the positive input of CMP2 and the negative input of CMP1 are connected to the threshold voltage V THThe output end of CMP1 is connected to the first input end of AND2 and the input end of INV1, the output end of CMP2 is connected to the second input end of AND2 and the second input end of AND3, the output end of AND3 is connected to the input end of BUF2, and the output end of BUF2 generates a control signal SR_Ctrl.

[0022] Furthermore, the dead time insertion module includes a buffer BUF3, an inverter INV3, rising edge detection modules S1 and S2, delay modules D1 and D2, and two-input AND gates AND5 and AND6, wherein the input end of BUF3 and the input end of INV3 are connected to the control signal SR_Ctrl, the output end of BUF3 is connected to the input end of S1 and the second input end of AND5, the output end of S1 is connected to the input end of D1, the output end of D1 is connected to the first input end of AND5, the output end of AND5 generates a synchronous rectification high-side control signal HI, the output end of INV3 is connected to the input end of S2 and the second input end of AND6, the output end of S2 is connected to the input end of D2, the output end of D2 is connected to the first input end of AND6, and the output end of AND6 generates a synchronous rectification low-side control signal LI.

[0023] Furthermore, the judgment logic of the state machine is: firstly, a fixed data signal DATA is set to indicate the dead time, and then the control signal SR_Ctrl is detected:

[0024] If the rising edge of SR_CTRL is detected, it means that the bridge driver switches from the freewheeling state to the rectification state. The state machine then detects the sequence of the LO falling edge and the HI rising edge: if the HI rising edge is detected first, it means that the dead time is small, and the data signal DATA is increased by 1 bit; if the LO falling edge is detected first, it means that the dead time is large, and the data signal DATA is reduced by 1 bit;

[0025] If the falling edge of SR_CTRL is detected, it means that the bridge driver switches from the rectification state to the freewheeling state. The state machine then detects the sequence of the HO falling edge and the LI rising edge: if the LI rising edge is detected first, it means that the dead time is small, and the data signal DATA is increased by 1 bit; if the HO falling edge is detected first, it means that the dead time is large, and the data signal DATA is reduced by 1 bit;

[0026] In the next control cycle, the control signal SR_Ctrl is detected again and the dead time is adjusted according to the above method, so as to continuously optimize it.

[0027] Furthermore, the synchronous rectification speed control controller also includes an interlock protection module for preventing the dead time insertion from being too small, resulting in the high-side tube and the low-side tube in the bridge driver being turned on at the same time; the interlock protection module includes inverters INV4 and INV5 and NOR gates NOR1 and NOR2, wherein the input end of INV4 is connected to the synchronous rectification high-side control signal HI, the output end of INV4 is connected to the first input end of NOR1, the second input end of NOR1 is connected to the low-side tube state signal LO, the output end of NOR1 generates the synchronous rectification high-side control signal HC, the input end of INV5 is connected to the synchronous rectification low-side control signal LI, the output end of INV5 is connected to the second input end of NOR2, the first input end of NOR2 is connected to the high-side tube state signal HO, and the output end of NOR2 generates the synchronous rectification low-side control signal LC, and then provides HC and LC to the gate controller.

[0028] Based on the above technical solution, the present invention has the following beneficial technical effects:

[0029] 1. High efficiency: The present invention adopts a built-in synchronous rectification speed control controller module to control the current flowing through the motor. The rectification ripple is adjustable, and the dead time that affects the rectification efficiency is optimized. Compared with the traditional PWM modulation technology, the current control efficiency is higher and the speed regulation capability is better.

[0030] 2. The speed regulation method is simple; the present invention only requires an external sampling resistor and a voltage source to adjust the motor speed. Compared with speed regulation using PWM control of an MCU, it is easier to use and more convenient to develop. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is the system structure block diagram of the traditional brushless DC motor speed control solution.

[0032] Figure 2 1 is a structural block diagram of a synchronous rectification speed regulation circuit of a brushless DC motor in an embodiment of the present invention.

[0033] Figure 3 Schematic diagram of the circuit structure of a synchronous rectification speed control controller in an embodiment of the present invention.

[0034] Figure 4 Schematic diagram of the circuit structure of the rectification time regulator in an embodiment of the present invention.

[0035] Figure 5 Schematic diagram of the judgment process of the state machine in the embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0037] Trapezoidal control is the most commonly used control scheme for brushless DC motor control. There are six working states in total. In each working state, only one phase of the high-side tube and the other phase of the low-side tube of the bridge driver are turned on, and connected to the motor winding to form a loop. Basic trapezoidal control cannot achieve motor speed control. To achieve motor speed regulation, the current flowing through the stator (that is, the output current of the bridge driver) must be controlled. Traditional DC brushless motor speed regulation schemes such as Figure 1 As shown, the MCU internal PWM controller is used to control the motor current. The traditional PWM speed regulation scheme controlled by MCU cannot detect the working status of the bridge drive at all times due to the use of discrete device solutions. The switching of rectification and freewheeling needs to insert a fixed dead time, which causes efficiency loss.

[0038] The synchronous rectification speed control controller, trapezoidal controller, gate controller and bridge driver of the synchronous rectification speed control circuit of the brushless DC motor of the present invention are all integrated on the same chip. The synchronous rectification speed control controller circuit can always detect the high-side tube gate state signal of the high-side gate drive and the low-side tube gate state signal of the low-side gate drive in the bridge driver, optimize the dead time, and have higher rectification efficiency.

[0039] like Figure 2 As shown, the synchronous rectification speed regulation circuit of the brushless DC motor of the present invention includes a synchronous rectification speed regulation controller, a trapezoidal controller, a gate controller and a bridge driver. The input port VSW of the synchronous rectification speed regulation controller and the driving ground port PGND of the bridge driver are connected to the sampling resistor R S One side, R S The other side is grounded, and the input port VREF of the synchronous rectifier speed controller is connected to the reference power supply V REF , V REF The other side is grounded, ports CP and CN of the synchronous rectification speed control controller are respectively connected to two ends of the timing capacitor C1, and output signals HC and LC of the synchronous rectification speed control controller are connected to the gate controller input.

[0040] The trapezoidal controller outputs EN1, EN2, EN3, H1, L1, H2, L2, H3, and L3 signals, which are all input to the gate controller, and EN1, EN2, and EN3 are input to the synchronous rectification speed control controller.

[0041] The gate controller has three phases in total, of which the first phase includes two two-to-one multiplexing gates MUX1 and MUX2 and two buffers BUF1 and BUF2. HC is used as input 1 of MUX1, H1 is used as input 0 of MUX1, LC is used as input 1 of MUX2, and L1 is used as input 0 of MUX2. The selection signals of the two multiplexing gates are both EN1. The output of MUX1 is connected to the input of BUF1, and BUF1 outputs the HC1 signal. The output of MUX2 is connected to the input of BUF2, and BUF2 outputs the LC1 signal. The structure of the other two phases is the same as that of the first phase. The input signals of the second phase are H2, HC, L2, LC, and EN2, and the output signals are HC2 and LC2. The input signals of the third phase are H3, HC, L3, LC, and EN3, and the output signals are HC3 and LC3.

[0042] The bridge driver has three phases in total, of which the first phase includes a high-side gate driver module, a low-side gate driver module, and two N-type LDMOS tubes ND1 and ND2. The HC1 signal is input to the high-side gate driver module, and the LC1 signal is input to the low-side gate driver module. The high-side gate driver module outputs the high-side tube gate state signal HO1. When HO1 is high, it means that the corresponding high-side MOS tube is turned on, otherwise it means it is turned off. At the same time, it is connected to the gate of ND1 to control its conduction and shutdown; the low-side gate driver module outputs the low-side tube gate state signal LO1. When LO1 is high, it means that the corresponding low-side MOS tube is turned on, otherwise it means it is turned off. At the same time, it is connected to the gate of ND2 to control its conduction and shutdown. The source of ND1 and the drain of ND2 are connected to the output port OUT1, the drain of ND1 is connected to the driving power port VM, and the source of ND2 is connected to the driving ground port PGND; the other two phases have the same structure as the first phase, the inputs of the second phase are HC2 and LC2 respectively, the outputs are HO2, LO2 and OUT2 respectively, the driving power port is VM, and the driving ground port is PGND; the inputs of the third phase are HC3 and LC3 respectively, the outputs are HO3, LO3 and OUT3 respectively, the driving power port is VM, and the driving ground port is PGND; the outputs OUT1, OUT2 and OUT3 of the bridge driver are directly connected to the brushless DC motor.

[0043] When the trapezoidal controller controls the bridge driver to be in one of the six working states, the trapezoidal controller enables the gate driver of this phase to be turned on at the low side, so that the synchronous rectification speed controller controls this phase, and the other two phases are still controlled by the trapezoidal controller.

[0044] like Figure 2As shown, taking the trapezoidal controller controlling the second phase high-side tube conduction and the first phase low-side tube conduction as an example, at this time, the gate controller input signal of the first phase selects the HC and LC signals through MUX1 and MUX2, that is, the first phase of the bridge drive is controlled by the synchronous rectification speed controller. When the motor is in the freewheeling state, the motor current will increase. At this time, the external sampling resistor R S The bridge drive current is sampled and when the current exceeds the VREF port voltage V ref When the synchronous rectification speed controller controls the bridge driver from the freewheeling state to the synchronous rectification for a certain period of time, and then returns to the freewheeling state after the time is up. In this way, the motor current will be limited to V ref / R S , to control the motor current, so only need to change V ref The value of can change the motor current and achieve the speed regulation effect of the brushless DC motor.

[0045] In order to realize the above rectification process, the synchronous rectification speed control controller in this embodiment is as follows: Figure 3 As shown, it includes a synchronous rectification comparator, a rectification time regulator, an anti-misjudgment module, a dead time insertion module, an interlock protection module, a detection signal gating unit, a state machine, a digital-to-analog converter and a dead time generator.

[0046] The output signals EN1, EN2, EN3, HO1, LO1, HO2, LO2, HO3, and LO3 of the trapezoidal controller are input to the detection signal selection unit to control its output HO and LO signals; taking the trapezoidal controller controlling the conduction of the second-phase high-side tube and the conduction of the first-phase low-side tube as an example, at this time, the HO and LO signals respectively select the HO1 and LO1 signals to detect the switching states of the first-phase ND1 and ND2.

[0047] The positive input of the synchronous rectifier comparator is connected to the sampling resistor R through the VSW port. S The negative input is connected to the reference voltage V through the VREF port. ref , when the VSW port level is lower than V ref When the motor is in the freewheeling state, the motor current increases and the voltage of the VSW port rises. When the VSW port level is greater than Vref, the synchronous rectification comparator output signal CMP changes from low to high. At this time, the rectification time regulator output signal SR_Ctrl outputs a time of T SD High level, T SD It is the rectification time of the synchronous rectification comparator, which can be adjusted. When the signal is high, HI is high, LI is low, the high-side tube of the first phase in the bridge driver is turned on, and the synchronous rectification state is entered. When the signal is low, HI is low, LI is high, the low-side tube of the first phase in the bridge driver is turned on, and the freewheeling state is entered.

[0048] TSD The size of is realized by the rectifier time regulator and the off-chip timing capacitor C1, such as Figure 4 The rectifier time regulator includes an RS latch RS1, a three-input AND gate AND4, three two-input AND gates AND1, AND2 and AND3, a two-input OR gate OR1, two buffers BUF1 and BUF2, two inverters INV1 and INV2, two comparators CMP1 and CMP2, two PMOS tubes PM1 and PM2, an NMOS tube NM1, and a resistor R C , the power supply of the circuit is V CC , ground level is GND, threshold level is V TH When the input IN signal is low, PM1 and PM2 are turned on, NM1 is turned off, and the voltage of CN and CP ports is V CC , the output signal OUT is low level; when the rising edge of the input signal is detected, PM1 and PM2 are turned off, NM1 is turned on, and the voltage at the CN terminal is pulled to GND. Since the voltage across the capacitor C1 cannot suddenly change, the voltage at the CP terminal follows the voltage at the CN terminal, and then C1 is connected by the power supply V CC Through the resistor R C Charging, OUT becomes high. When the time is T SD After the time, CP level is charged to V TH When T is on, PM1 and PM2 are turned on again, clamping the voltages of CN and CP to VCC, and the OUT level becomes low again; T SD The expression is:

[0049]

[0050] By adjusting the capacitance of C1, the rectification time T SD Through adjustment, you can choose the appropriate capacitor value and rectification time according to different types of brushless DC motors.

[0051] The SR_Ctrl signal needs to enter the dead time insertion module to generate the corresponding HI and LI signals. The dead time insertion module includes a buffer BUF3, an inverter INV3, two rising edge detection modules, two delay modules, and two two-input AND gates AND5 and AND6. This module will perform a fixed delay on the opening of the two signals, generate dead time, and generate the corresponding HI and LI signals; the delay module determines the size of the dead time, and the size of the delay is determined by the dead time generator.

[0052] Affected by temperature, process, and voltage, the optimal dead time is variable. Inserting a fixed dead time will result in a loss of efficiency. Therefore, the state machine provides the optimal dead time by judging the SR_Ctrl, LO, HO, LI, and HI signals, outputs the corresponding data signal DATA, and converts it into a level V through a digital-to-analog converter. DT The dead time generator generates the corresponding dead time T according to the level D Provided to the delay module in the dead time insertion module.

[0053] The judgment process of the state machine is as follows Figure 5 As shown in the figure: When the synchronous rectification speed controller is powered on, the state machine first sets a fixed dead time through the digital-to-analog converter, and then the state machine detects the SR_CTRL control signal. If the state machine detects the rising edge of SR_CTRL, it means that the bridge drive switches from the freewheeling state to the rectification state. Figure 2 In the middle, ND2 is closed and ND1 is opened. The state machine detects the falling edge of LO and the rising edge of HI in the following order: if the rising edge of HI is detected first, it means that the dead time is small, and the state machine output DATA will increase by 1 bit; if the falling edge of LO is detected first, it means that the dead time is large, and the state machine output DATA will decrease by 1 bit. If the state machine detects the falling edge of SR_CTRL, it means that the bridge driver switches from rectification to freewheeling state. Figure 2 In the process, ND1 is closed and ND2 is opened, and the state machine detects the falling edge of HO and the rising edge of LI in sequence: if the rising edge of LI is detected first, it means that the dead time is small, and the state machine output DATA will increase by 1 bit; if the falling edge of HO is detected first, it means that the dead time is large, and the state machine output DATA will decrease by 1 bit; and then the next round of judgment is carried out. In this way, through continuous feedback judgment, the state machine dynamically adjusts the output DATA, and then adjusts the dead time, so as to obtain the optimized dead time and reduce efficiency loss.

[0054] In order to prevent damage caused by too small dead time, the synchronous rectification speed controller has an interlock protection module to achieve anti-feedthrough function. When the HO signal is high, the low-side control signal is not allowed to send a pilot signal. Similarly, when the LO signal is high, the high-side signal is also restricted.

[0055] The LI and HI signals are input to the interlock protection module, and the interlock protection module receives LO and HO from the detection signal selection unit. The interlock protection module includes two inverters INV4 and INV5, two two-input NOR gates NOR1 and NOR2. When the HO signal is high, it means that the high-side tube is turned on, and the LI signal is not allowed to pass at this time; when the LO signal is high, it means that the low-side tube is turned on, and the HI signal is not allowed to pass at this time, which is used to prevent the high-side and low-side tubes of the bridge drive from being turned on at the same time; the interlock protection module outputs control signals HC and LC to the gate controller to realize the control of the bridge drive.

[0056] In summary, the brushless DC motor synchronous rectification speed regulation circuit of the present invention can provide flexible rectification time according to dynamically optimized dead time, and can flexibly adjust the motor speed through an external reference voltage, and the speed regulation method is simple and has high efficiency.

[0057] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments. Improvements and modifications made by those skilled in the art to the present invention based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A high-efficiency brushless DC motor synchronous rectification speed regulation circuit, characterized in that: It includes a synchronous rectification speed control controller, a trapezoidal controller, a gate controller and a bridge driver integrated on the same chip, wherein: The trapezoidal controller provides a three-phase switch control signal and a three-phase enable signal to the gate controller, controls the bridge driver through the gate controller to realize six-step trapezoidal control of the brushless DC motor, and provides a three-phase enable signal to the synchronous rectification speed control controller to select the phase to be controlled; The synchronous rectification controller obtains the three-phase switch state signal of the bridge driver from the chip, provides a synchronous rectification control signal to the gate controller, controls the bridge driver to switch between the freewheeling state and the rectification state through the gate controller, and adjusts the driving current of the bridge driver; The gate controller selects the three-phase switch control signal and the synchronous rectification control signal according to the three-phase enable signal, thereby providing the three-phase switch drive signal to the bridge driver; The bridge driver amplifies the power of the three-phase switch driving signal to control the on and off of the internal power switch device, thereby driving the brushless DC motor to achieve electronic commutation and speed regulation.

2. The synchronous rectification speed regulation circuit of a brushless DC motor according to claim 1, characterized in that: The synchronous rectification speed control controller comprises: A detection signal gating unit selects a switch state signal of one phase from the three-phase switch state signals according to the three-phase enable signal, including the high-side tube state signal HO and the low-side tube state signal LO of the phase; The synchronous rectifier comparator acquires the DC feedback voltage of the bridge driver through an off-chip sampling resistor, compares it with the reference voltage, and generates a comparison signal; The rectifier time regulator outputs a control signal SR_Ctrl with a fixed pulse width when detecting the rising edge of the comparison signal. The pulse width is adjusted by the timing capacitor outside the chip. The dead time insertion module detects the rising edge of the control signal SR_Ctrl in two ways and inserts the dead time through delay to generate the synchronous rectification high side control signal HI and the synchronous rectification low side control signal LI; The state machine determines the optimal dead time by judging the signals SR_Ctrl, LO, HO, LI, and HI, thereby outputting the corresponding data signal; A digital-to-analog converter, which converts the data signal into analog levels; The dead time generator generates the corresponding dead time according to the analog level and provides it to the dead time insertion module.

3. The synchronous rectification speed regulation circuit of a brushless DC motor according to claim 2, characterized in that: When the trapezoidal controller controls the low-side tube of a phase in the bridge driver to turn on, the enable signal of the phase outputted by the trapezoidal controller is high level, and the detection signal gating unit selects the switch state signal of the phase according to the enable signal.

4. The synchronous rectification speed regulation circuit of a brushless DC motor according to claim 2, characterized in that: The synchronous rectification speed control controller also includes an anti-misjudgment module, which is used to detect the rising edge of the low-side tube state signal LO and generate a shielding pulse signal of a fixed duration to provide it to the rectification time regulator. When the corresponding low-side tube is turned on, the rectification time regulator will be briefly shielded to prevent erroneous operation caused by misjudgment of the synchronous rectification comparator.

5. The synchronous rectification speed regulation circuit of a brushless DC motor according to claim 4, characterized in that: The rectification time regulator includes an RS latch RS1, a three-input AND gate AND4, two-input AND gates AND1-AND3, an OR gate OR1, buffers BUF1 and BUF2, inverters INV1 and INV2, comparators CMP1 and CMP2, PMOS tubes PM1 and PM2, NMOS tube NM1 and a resistor R C , wherein the first input terminal of AND1 is connected to the comparison signal, the second input terminal of AND1 is connected to the output terminal of INV2 and the first input terminal of AND3, the input terminal of INV2 is connected to the shielding pulse signal, the output terminal of AND1 is connected to the S input terminal of RS1 and the first input terminal of AND4, the R input terminal of RS1 is connected to the third input terminal of AND4 and the output terminal of INV1, the Q output terminal of RS1 is connected to the second input terminal of AND4, the output terminal of AND4 is connected to the first input terminal of OR1, the second input terminal of OR1 is connected to the output terminal of AND2, the output terminal of OR1 is connected to the input terminal of BUF1, the output terminal of BUF1 is connected to the gate of PM1, the gate of PM2 and the gate of NM1, and the source of PM1 is connected to the power supply voltage V CC , the drain of PM1 is connected to the drain of NM1, the positive input terminal of CMP1 and one end of the timing capacitor, the source of NM1 is grounded, and the other end of the timing capacitor is connected to R C One end of PM2 is connected to the drain of PM2 and the inverting input of CMP2. C The other end is connected to the source of PM2 and connected to the power supply voltage V CC , the positive input of CMP2 and the negative input of CMP1 are connected to the threshold voltage V TH The output end of CMP1 is connected to the first input end of AND2 and the input end of INV1, the output end of CMP2 is connected to the second input end of AND2 and the second input end of AND3, the output end of AND3 is connected to the input end of BUF2, and the output end of BUF2 generates a control signal SR_Ctrl.

6. The synchronous rectification speed regulation circuit of a brushless DC motor according to claim 2, characterized in that: The dead time insertion module includes a buffer BUF3, an inverter INV3, rising edge detection modules S1 and S2, delay modules D1 and D2, and two-input AND gates AND5 and AND6, wherein the input end of BUF3 and the input end of INV3 are connected to the control signal SR_Ctrl, the output end of BUF3 is connected to the input end of S1 and the second input end of AND5, the output end of S1 is connected to the input end of D1, the output end of D1 is connected to the first input end of AND5, the output end of AND5 generates a synchronous rectification high-side control signal HI, the output end of INV3 is connected to the input end of S2 and the second input end of AND6, the output end of S2 is connected to the input end of D2, the output end of D2 is connected to the first input end of AND6, and the output end of AND6 generates a synchronous rectification low-side control signal LI.

7. The synchronous rectification speed regulation circuit of a brushless DC motor according to claim 2, characterized in that: The judgment logic of the state machine is: firstly, a fixed data signal DATA is set to indicate the dead time, and then the control signal SR_Ctrl is detected: If the rising edge of SR_CTRL is detected, it means that the bridge driver switches from the freewheeling state to the rectification state. The state machine then detects the sequence of the LO falling edge and the HI rising edge: if the HI rising edge is detected first, it means that the dead time is small, and the data signal DATA is increased by 1 bit; if the LO falling edge is detected first, it means that the dead time is large, and the data signal DATA is reduced by 1 bit; If the falling edge of SR_CTRL is detected, it means that the bridge driver switches from the rectification state to the freewheeling state. The state machine then detects the sequence of the HO falling edge and the LI rising edge: if the LI rising edge is detected first, it means that the dead time is small, and the data signal DATA is increased by 1 bit; if the HO falling edge is detected first, it means that the dead time is large, and the data signal DATA is reduced by 1 bit; In the next control cycle, the control signal SR_Ctrl is detected again and the dead time is adjusted according to the above method, so as to continuously optimize it.

8. The synchronous rectification speed regulation circuit of a brushless DC motor according to claim 2, characterized in that: The synchronous rectification speed control controller also includes an interlock protection module, which is used to prevent the dead time insertion from being too small, resulting in the high-side tube and the low-side tube in the bridge driver being turned on at the same time; the interlock protection module includes inverters INV4 and INV5 and NOR gates NOR1 and NOR2, wherein the input end of INV4 is connected to the synchronous rectification high-side control signal HI, the output end of INV4 is connected to the first input end of NOR1, the second input end of NOR1 is connected to the low-side tube state signal LO, the output end of NOR1 generates the synchronous rectification high-side control signal HC, the input end of INV5 is connected to the synchronous rectification low-side control signal LI, the output end of INV5 is connected to the second input end of NOR2, the first input end of NOR2 is connected to the high-side tube state signal HO, and the output end of NOR2 generates the synchronous rectification low-side control signal LC, and then provides HC and LC to the gate controller.

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