Multi-generation front-end modules (FEMs) with 2G VRAMP capability

Abstract

A multi-generation front-end module (FEM) with 2G Vramp capability is disclosed. Specifically, a FEM with a single transmission path can include a single power amplifier with supporting elements such as bias levels, load modulation, supply voltage, etc., which can be reconfigured and tuned to allow the single power amplifier to effectively adapt to and work with different generations of wireless protocols. In addition, this multi-generation FEM is able to adapt to 2G Vramp mode using multi-stage power amplifiers, each of which has its own gate or base control signal instead of collector signal control. This control is further achieved through efficient power detection.

Description

[0001] Priority application

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 586,870, filed on September 29, 2023, entitled "BASE / Gate 2G Vramp CONTROL USING COMPENSATED CLASS-CAND SHARED BIAS LINE FOR I+V POWER SHARING IN CONVERGEDPAs," the contents of which are incorporated herein by reference in their entirety.

[0003] This application also claims the benefit of U.S. Provisional Patent Application No. 63 / 607,736, filed on December 8, 2023, entitled “Multi-Generation Front-End Module (FEM) with 2G VRAMP Capability,” the contents of which are incorporated herein by reference in their entirety.

[0004] Related Applications

[0005] This application is related to U.S. Provisional Patent Application No. 63 / 586,807, filed on September 29, 2023, entitled “HYBRID RECONFIGURABLE AND CLASSADAPTIVE CONVERGED 2Glin / 2Gvramp / 3G / 4G / 5G TX PATH WITH BUCK-BOOST APT FEMsCURRENT”, the contents of which are incorporated herein by reference in their entirety.

[0006] This application is also related to U.S. Provisional Patent Application No. 63,607,710, filed on December 8, 2023, entitled “Multi-Generation Front End Module (FEM)”, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0007] The technology of the present disclosure generally relates to a technique for providing a front end module (FEM) that will work with multiple generations of wireless standards, and more particularly, to a technique for accommodating a 2G Vramp in combination with subsequent linear generations. Background Art

[0008] In modern society, computing devices are ubiquitous, and more specifically, mobile communication devices are becoming increasingly common. The popularity of these mobile communication devices is driven in part by the many functions currently enabled on such devices. The increase in processing power in such devices has meant that mobile communication devices have evolved from pure communication tools to sophisticated mobile entertainment centers, thereby enhancing the user experience. With the advent of the many functions available to such devices, there has been increasing pressure to find ways to increase the bandwidth for data transmission to and from user equipment or other wireless communication devices. This pressure has led to the evolution of wireless protocols and the current trend to use higher frequency signals.

[0009] Although newer wireless protocols have more bandwidth than older wireless protocols, infrastructure deployed to support older wireless protocols is still deployed in some locations. Therefore, many wireless communication devices may contain circuitry that supports multiple wireless protocols. Providing cost-effective solutions that fit within the space available in commercially viable wireless communication devices provides an opportunity for innovation. Summary of the invention

[0010] Aspects disclosed in the specific implementation include a multi-generation front-end module (FEM) with 2G Vramp capability. Specifically, a FEM with a single transmission path may include a single power amplifier with supporting elements such as bias level, load modulation, and supply voltage, which can be reconfigured and tuned to allow the single power amplifier to effectively adapt to different generations of wireless protocols and work with different generations of wireless protocols. Other aspects of the present disclosure contemplate that such a multi-generation FEM can adapt to the 2G Vramp mode using a multi-stage power amplifier, each of which has its own gate or base control signal instead of collector signal control. This control is further achieved through efficient power detection.

[0011] In this regard, in one aspect, a power amplifier chain is disclosed. The power amplifier chain includes: a first amplifier including a first transistor; a second amplifier including a second transistor, the second amplifier being serially coupled to the first amplifier; and a power detector coupled to an output of the second amplifier. The power amplifier chain also includes a Vramp control circuit coupled to the power detector and configured to: supply a first power control signal to the first transistor at a first base or a first gate based on a sensed power from the power detector; and supply a second power control signal to the second transistor at a second base or a second gate based on a sensed power from the power detector.

[0012] In another aspect, a wireless communication device is disclosed, the wireless communication device including a transmitter, the transmitter including a power amplifier chain, the power amplifier chain configured to operate across multiple generations of cellular standards, the power amplifier chain. The wireless communication device includes: a first amplifier, which includes a first transistor; a second amplifier, which includes a second transistor, the second amplifier is serially coupled to the first amplifier; and a power detector, which is coupled to the output of the second amplifier. The wireless communication device also includes a Vramp control circuit, the Vramp control circuit is coupled to the power detector and is configured to: supply a first power control signal to the first transistor at a first base or a first gate based on the sensed power from the power detector; and supply a second power control signal to the second transistor at a second base or a second gate based on the sensed power from the power detector.

[0013] In another aspect, a method for controlling a power amplifier chain is disclosed. The method includes: sensing a power level at an output of the power amplifier chain; comparing the power level to a Vramp signal at a Vramp control circuit; and sending a power control signal to a plurality of stages of the power amplifier chain at respective gates or bases of transistors in the plurality of stages. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a block diagram of a conventional collector-controlled power amplifier that can be used with a 2G Vramp signal;

[0015] Figure 2 is a block diagram of an exemplary 2G Vramp capable amplifier chain with power detection at an antenna coupler according to aspects of the present disclosure;

[0016] Figure 3 is a block diagram of an exemplary 2G Vramp capable amplifier chain with power detection at the amplifier according to aspects of the present disclosure;

[0017] Figure 4 is a block diagram of a first technique for transferring sensed power to a Vramp bias controller according to aspects of the present disclosure;

[0018] Figure 5 is a block diagram of a second technique for transferring sensed power to a Vramp bias controller according to aspects of the present disclosure;

[0019] Figure 6 supply Figure 5 Additional details of the second technique;

[0020] Figure 7 Providing an alternative structure with compensation current during low gain conditions;

[0021] Figure 8 is a block diagram illustrating individual bias controls provided to different stages of a power amplifier chain according to an exemplary aspect of the present disclosure;

[0022] Fig. 9 It is a hybrid circuit and block diagram that illustrates how the Vramp control generates the bias signal;

[0023] Fig.10 is a block diagram illustrating how aspects of the present disclosure may be distributed between a silicon chip and a gallium arsenide (GaAs) chip;

[0024] Fig.11 are hybrid circuits and block diagrams illustrating how different components may interact with the bias circuit and the corresponding impedance compensation that may be provided;

[0025] Fig. 12A and 12B Explain how impedance compensation can be provided for silicon or GaAs technology respectively;

[0026] Fig.13 is a circuit diagram illustrating an exemplary circuit for use with aspects of the present disclosure;

[0027] Fig.14 is a flow chart illustrating an exemplary process for controlling biasing of a convergent multi-generation power amplifier chain according to aspects of the present disclosure; and

[0028] Fig.15 is a block diagram of a mobile terminal according to the present disclosure, the mobile terminal may include Figures 2 to 13 Converging multi-generation power amplifier chains. DETAILED DESCRIPTION

[0029] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize the applications of these concepts not specifically described herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0030] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0031] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on another element" or "extending onto another element," it may be directly on another element or directly extending onto another element, or there may also be intervening elements. In contrast, when an element is referred to as being "directly on another element" or "extending directly onto another element," there are no intervening elements. Similarly, it will be understood that when an element, such as a layer, region, or substrate, is referred to as being "above another element" or "extending over another element," it may be directly over another element or directly extending over another element, or there may also be intervening elements. In contrast, when an element is referred to as being "directly over another element" or "extending directly over another element," there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0032] Relative terms such as "below" or "above" or "up" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0033] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of the features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0035] Consistent with the above statements about definitions, the present disclosure uses transceivers in a broad manner. Current industry literature widely uses transceivers to refer to multiple circuits that send and receive signals. Exemplary circuits may include a baseband processor coupled to one or more antennas, up / down conversion circuits, filters, amplifiers, couplers, etc. Similarly, some authors in industry literature refer to circuits positioned between a baseband processor and a power amplifier circuit as transceivers. This intermediate circuit may include up / down conversion circuits, mixers, oscillators, filters, etc., but typically does not include a power amplifier. As used herein, the term transceiver is used in the first sense. When relevant to distinguishing between the two definitions, the terms "transceiver chain" and "transceiver circuit" are used, respectively.

[0036] Aspects disclosed in the specific implementation include a multi-generation front-end module (FEM) with 2G Vramp capability. Specifically, a FEM with a single transmission path may include a single power amplifier with supporting elements such as bias level, load modulation, and supply voltage, which can be reconfigured and tuned to allow the single power amplifier to effectively adapt to different generations of wireless protocols and work with different generations of wireless protocols. Other aspects of the present disclosure contemplate that such a multi-generation FEM can adapt to the 2G Vramp mode using a multi-stage power amplifier, each of which has its own gate or base control signal instead of collector signal control. This control is further achieved through efficient power detection.

[0037] Before addressing certain aspects of the present disclosure, a brief overview of the conventional control process for 2G Vramp mode is provided with reference to FIG. Figure 2 Aspects of the disclosure are discussed first.

[0038] In this regard, FIG. 1 is a block diagram of a power amplifier chain 100 operating in a 2G Vramp mode. That is, the second generation cellular standard (2G) has a linear mode and a Vramp mode. Converging the linear mode into a single power amplifier chain is described in the related applications incorporated above. However, converging the 2G Vramp mode requires some additional power control options. In the past, the 2G Vramp mode power amplifier chain 100 would include one or more power amplifiers 102, which had a bias circuit 104 and a collector control circuit 106. The collector control circuit 106 is typically a low dropout (LDO) regulator that receives a Vramp signal at a comparator 108. Feedback from transistor 110 provides another input to comparator 108 to keep the input at the gate of transistor 110 at a desired level, as fully understood. The collector control circuit 106 is typically large, and the size is comparable to the actual high power power amplifier in the transmitter control circuit (not shown) and the power amplifier 102. Therefore, the size and cost of the FEM containing this control circuit increase. The collector control circuit 106 may also compete with other power management circuits and may require switching circuits to allow access to the collector of the power amplifier 102 .

[0039] Aspects of the present disclosure not only contemplate a converged power amplifier chain capable of supporting multiple generations of cellular standards, but also contemplate changing the power control for the 2G Vramp mode so that the large LDO can be eliminated. In this regard, the control is moved away from the collector to the base or gate of the transistor that forms the power amplifier. Changing the location of the control also requires a new way of detecting power to the Vramp control circuit. Figure 2 and 3 Two variations of this power detection are provided in .

[0040] At this point, Figure 2 A transmitter chain 200 is illustrated having a power amplifier chain 202, an output matching circuit 204, a switch 206, a harmonic filter 208, and an antenna switch 210 coupled to an antenna 212. Within the antenna switch 210, a coupler 214 may be provided. A power detector 216 may use information from the coupler 214 to provide a detected power signal to a 2G Vramp control circuit 218. The Vramp control circuit 218 may receive the Vramp signal and provide base or gate control to the amplifiers in the power amplifier chain 202, as better explained below. It should be noted that not every transmitter chain 200 will have a coupler 214. Furthermore, even when a coupler 214 is present, other circuits may use the coupler 214 for power detection, etc., so there may be reasons not to use a power detector 216.

[0041] As an alternative to the power detector 216, Figure 3 A transmitter chain 300 is illustrated having a power amplifier chain 302, an output matching circuit 304, a harmonic filter 308, and an antenna switch 310 coupled to an antenna 312. A power detector 316 may be coupled to the power amplifier chain 302 (as described below with reference to FIG. Figure 6 and 7 ). The power detector 316 may provide a detected power signal to a Vramp control circuit 318. The Vramp control circuit 318 may receive the Vramp signal and provide base or gate control to amplifiers in the power amplifier chain 302, as better explained below.

[0042] Although Figure 2 and 3 It is generally contemplated how the power detector 216, 316 provides the detected power signal to the Vramp control circuit 218, 318, but this can be accomplished in a variety of ways. It should be appreciated that although the following discussion and examples focus on Figure 3 structures similar to those described in , but the teachings of the present disclosure are also applicable to Figure 2 structure.

[0043] Figure 4 The transmitter chain 400 in can include a power amplifier 402 with a power detector 416 in the power amplifier die 404. In an exemplary aspect, the power amplifier die 404 can be a gallium arsenide (GaAs) die or the like (although silicon-based dies are also possible). A Vramp control circuit 418 can be present in the control die 406. In order to provide a communication path between the power detector 416 and the Vramp control circuit 418, a dedicated conductor 408 with its own pin (not shown) can be provided. The dedicated conductor 408 and its pin consume additional area and may not be optimal. Of interest is the additional pre-existing connection between the local bias circuit 410 and the regulator 412 in the amplifier dies 404, 406, respectively. In addition, the control die 406 may have an over-current protection (OCP) circuit 414. The control bias circuit 420 may also be present in the control die 406 and communicate with the local bias circuit 410.

[0044] Instead of dedicated wiring, aspects of the present disclosure contemplate reusing the connection between the local bias circuit 410 and the regulator 412, such as Figure 54. The transmitter chain 500 of FIG. 4 is better illustrated in FIG. 4. Many components are the same and have not been renumbered. However, conductor 502 now shares the signal from regulator 512 to local bias circuit 410 and the detected power signal from power detector 416. Regulator 512 may also be responsive to OCP circuit 414 when local bias circuit 410 is set. Note that, in general, these divergent signals will not conflict in regulator 512 because OCP circuit 414 may activate limiting when current is high (but voltage is low), and thus current alone may be a close indicator of detected power. Likewise, in situations where current alone is not a good indicator of detected power, OCP circuit 414 will not be invoked because the current is typically low.

[0045] To better understand power sensing and how it can interact with regulators and OCP circuits, refer to Figure 6 and 7 Specifically, Figure 6 An amplifier 600 is illustrated, which may be a bipolar junction transistor (BJT) having a collector 600C, a base 600B, and an emitter 600E. A current Ic flows from the collector 600C to the emitter 600E. An output voltage Vc exists at the collector 600C. It will be appreciated that the output power is equal to Vc*Ic. However, a reasonable approximation to this using a Taylor expansion is P=Vc+Ic. Aspects of the present disclosure provide a method of obtaining a reasonable approximation of P.

[0046] The current I flowing from the base 600B to the emitter 600E is proportional to Ic (i.e., I=a*Ic). This current I also flows from the bias transistor 604 through the resistor 602. The collector 604C of the bias transistor 604 can be coupled to the regulator 606 at the node 610. As mentioned, Vc is present at the collector 600C. This can be sensed by the DC voltage sensor circuit 608 and converted into a current Iv=b*Vc. This current Iv can also be provided to the regulator 606 at the node 610, thereby generating a current sum of a*Ic+b*Vc, which can be used as an indicator of power P. P is provided by the transistor 612 in the regulator 606. The current sensor 614 in the regulator can also work with the OCP circuit 616. The output of the current sensor 614 is provided to the 2GVramp control circuit 618 which also receives the Vramp signal. Although not shown, the Vramp control circuit 618 can control the bias signal provided at the base of the transistor 604.

[0047] Figure 7Additional details are provided in , where additional circuitry is added to provide a sensed current (Ilow) for low gain conditions. More specifically, the output voltage Vc is coupled to an alternating current (AC) capacitor 700 and a resistor 702, which effectively converts the voltage into a current (i.e., Figure 6 6. The power supply 604 of FIG. 6 is a portion of a DC voltage sensor circuit 608 of FIG. 604. This current is provided to a node 704 between a first transistor 706 and a second transistor 708. A current Iv=b*Vc flows through transistors 706, 708 and is present at a node 610. In addition to transistor 604, a low gain transistor 710 is coupled to node 610 and is coupled to ground through a resistor 712. The value of resistor 712 can be selected so that the current Ilow flows under low gain conditions but is negligible under medium and high gain conditions. Conversely, under low gain conditions, Ic may be smaller but is present under medium and high gain conditions. Therefore, under either condition, there will be a current summed with Iv to provide a power approximation. Transistor 604 can be coupled to ground through transistor 714.

[0048] Continue to refer Figure 7 , AC blocking capacitor 716 may be present at base 600B, and driver amplifier 718 may provide input signal RFIN to transistor 604. Additionally, bias input may be provided as a current by circuit 720A or as a voltage by circuit 720B. Although Figure 6 Not shown in the drawings, but these elements may be present for the described circuits without departing from the present disclosure.

[0049] The above discussion focuses on power detection locations and circuitry that will enable detection without the need for separate conductors, but the present disclosure is not limited to this innovation. The Vramp control circuit can generate separate power control signals for different amplifiers in the amplifier chain. Specifically, the 2G Vramp mode can be at a higher power and therefore can use the pre-driver amplifier 802, driver amplifier 804, and output amplifier 806 in the amplifier chain 800, such as Figure 8 . Each amplifier 802, 804, 806 may have a respective bias circuit 808, 810, 812 that is individually adjustable to allow converged operation, as explained in the related applications mentioned above. The outputs of the bias circuits 808, 810, and 812 are summed with power control signals 814, 816, and 818, respectively. The driver amplifier 804 and the output amplifier 806 may have a supply voltage provided from a power management integrated circuit (PMIC) 820, which may include a direct current to direct current (DC-DC) buck-boost converter. As previously described (e.g., in Figure 6Or 7), the power detector 822 can provide the detected power signal to the Vramp control circuit 824, and the Vramp control circuit can have a comparator 826 and a power control circuit 828, and the power control circuit uses the output from the comparator 826 to determine the power control signals 814, 816, 818.

[0050] Fig. 9 Additional details regarding the Vramp control and circuitry used to determine the power control signals 814, 816, and 818 are provided in Figure 8 The amplifier chain 800 has an input node 900 and an output node 902 .

[0051] Specifically, input node 900 is coupled to multiplexer 904 and ground 906 via variable capacitor 908, which may have a value between 2 pico-farads and 6 pico-farads, for example (although other values ​​are possible). In later modes (i.e., 3G+), multiplexer 904 sends the input signal through pre-driver amplifier 802 to, for example, inductor 910 for use by driver amplifier 804.

[0052] However, in 2G mode, where power requirements are higher, multiplexer 904 can send input signals to DC blocking capacitor 912 and pre-driver transistors 914(1), 914(2). Power control signal 814 controls variable current source 916, which provides current to pre-driver transistor 914(12). Common node 918 receives a bias signal through bias resistor 920. Common node 918 also provides an output to DC blocking capacitor 922. The pre-driver circuit system is arranged so that the first stage is a constant output stage.

[0053] The current form of the variable current source 916 is also coupled to ground through capacitor 924 and to a current mirror 926 of the bias circuit 810. When the current of the pre-driver changes, the current of the bias circuit 810 also changes, so a well-controlled pre-driver also helps control the driver stage. This mirror current is combined with the bias current (Ibias) before being applied to the gate of the driver amplifier 804. Inductor 910, capacitor 928 and resistor 930 provide a filter to remove harmonics and impedance matching of the driver amplifier 804.

[0054] Fig.10 An alternative technology partition is illustrated. That is, the pre-driver amplifier 802 and the driver amplifier 804 can be implemented in a digital or CMOS die 1000 , and the output amplifier can be in a GaAs die 1002 .

[0055] It should also be noted that aspects of the present disclosure make good use of protection loops as previously described above and as described in Fig.11 1104, where the bias circuit 810 is coupled to the protection loop 1100, the Vramp control signal 1102, and the APD linearization circuit 1104 can all provide input signals to the node 1106 in the bias circuit 810. Since the different actions (Vramp, protection, and APD) can have different requirements, different impedances may be required. For example, in Vramp mode, the transistor can operate in class C mode, and this can result in a large capacitance change relative to class A or class AB. Therefore, a variable capacitor 1200 or 1202 can be added, such as Fig. 12A and 12B As described in .

[0056] Fig.13 1300 is a more specific circuit implementation of various bias circuit systems 1300, which are provided to illustrate the best mode as of this writing time. It is not intended to be limiting and is provided for illustration purposes only. Simulations based on this circuit indicate that an operating range of fifty to sixty decibels is possible and can meet the stringent standards of modern cellular telephone and wireless standards.

[0057] Fig.14 14. The process of the present disclosure is described in detail in the following. Specifically, the process 1400 begins with the wireless transceiver or user element 1500 entering the 2G Vramp mode (box 1402). The power level is sensed at the power amplifier output (box 1404), for example by measuring the current and voltage and summing them. The detected power is compared with the Vramp signal (box 1406), and bias signals are generated for multiple amplifier stages such as pre-drivers, drivers, and output stages (box 1408). The bias signal controls the stage at the gate or base (box 1410). In addition, the user element 1500 can switch to a different cellular generation mode and reuse the power amplifier stage (box 1412).

[0058] refer to Fig.15, the concepts described above can be implemented in various types of user elements 1500 such as mobile terminals, smart watches, tablet computers, computers, navigation devices, access points, and similar wireless communication devices that support wireless communications such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication. The user element 1500 will generally include a control system 1502, a baseband processor 1504, a transmission circuit system 1506, a receiving circuit system 1508, an antenna switch circuit system 1510, a plurality of antennas 1512, and a user interface circuit system 1514. In a non-limiting example, as an example, the control system 1502 can be a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). In this regard, the control system 1502 can include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receiving circuit system 1508 receives radio frequency signals from one or more base stations via the antenna 1512 and through the antenna switch circuit system 1510. The low noise amplifier and filter of the receiving circuit system 1508 cooperate to amplify and eliminate broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) then downconverts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0059] The baseband processor 1504 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations. The baseband processor 1504 is typically implemented in one or more digital signal processors (DSPs) and ASICs.

[0060] For transmission, the baseband processor 1504 receives digitized data, which may represent voice, data, or control information, from the control system 1502, and the baseband processor encodes the digitized data for transmission. The encoded data is output to the transmit circuit system 1506, where a digital-to-analog converter (DAC) converts the digital encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmit frequencies. The power amplifier amplifies the modulated carrier signal to a level suitable for transmission, and the modulated carrier signal is delivered to the antenna 1512 through the antenna switch circuit system 1510 to the antenna 1512. Multiple antennas 1512 and duplicate transmit circuit systems 1506 and receive circuit systems 1508 can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0061] It should also be noted that the operation steps described in any of the exemplary aspects herein are described in order to provide examples and discussions. The described operations can be performed in a large number of different orders other than the order shown. In addition, the operations described in a single operation step can actually be performed in many different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It should be understood that it will be easy for those skilled in the art to understand that the operation steps shown in the flow chart can undergo a large number of different modifications. Those skilled in the art will also understand that any of a variety of different technologies and techniques can be used to represent information and signals. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description.

[0062] The previous description of the disclosure is provided so that any person skilled in the art can make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power amplifier chain, comprising: a first amplifier comprising a first transistor; a second amplifier including a second transistor, the second amplifier being serially coupled to the first amplifier; a power detector coupled to the output of the second amplifier; as well as A Vramp control circuit is coupled to the power detector and is configured to: supplying a first power control signal to the first transistor at a first base or a first gate based on the sensed power from the power detector; as well as A second power control signal is supplied to the second transistor at a second base or a second gate based on the sensed power from the power detector. 2 . The power amplifier chain of claim 1 , wherein the first transistor comprises a field effect transistor (FET) and the first power control signal is supplied to the first gate.

3. The power amplifier chain of claim 2, wherein the second transistor comprises a bipolar junction transistor (BJT), and the second power control signal is supplied to the second base.

4. The power amplifier chain of claim 1, wherein the second amplifier is configured to operate in a linear mode for multiple cellular standard generations and a 2G Vramp mode.

5. The power amplifier chain of claim 1, further comprising a power management integrated circuit (PMIC) comprising a direct current to direct current (DC-DC) converter coupled to the second transistor at a second collector.

6. The power amplifier chain of claim 1 , further comprising a pre-driver amplifier positioned in series before the first amplifier and coupled to the Vramp control circuit, wherein the Vramp control circuit is further configured to provide a third power control signal to the pre-driver amplifier.

7. The power amplifier chain of claim 1, wherein the power detector is configured to sense power at an antenna coupler. 8 . The power amplifier chain of claim 1 , wherein the power detector comprises a current sensor at the first base or the first gate and a voltage sensor at an output of the second transistor.

9. The power amplifier chain of claim 8, further comprising a low gain transistor configured to sink the current of the power detector during a low gain condition. 10 . The power amplifier chain of claim 8 , further comprising an overcurrent protection circuit coupled to the first amplifier and configured to share a feedback line with the power detector.

11. The power amplifier chain of claim 10, further comprising an analog pre-distortion (APD) circuit configured to share an input to the second base or second gate with the second power control signal.

12. A wireless communication device, the wireless communication device comprising a transmitter, the transmitter comprising a power amplifier chain, the power amplifier chain configured to operate across multiple generations of cellular standards, the power amplifier chain comprising: a first amplifier comprising a first transistor; a second amplifier including a second transistor, the second amplifier being serially coupled to the first amplifier; a power detector coupled to the output of the second amplifier; as well as A Vramp control circuit is coupled to the power detector and is configured to: supplying a first power control signal to the first transistor at a first base or a first gate based on the sensed power from the power detector; as well as A second power control signal is supplied to the second transistor at a second base or a second gate based on the sensed power from the power detector.

13. A method of controlling a power amplifier chain, comprising: sensing a power level at an output of the power amplifier chain; comparing the power level to a Vramp signal at a Vramp control circuit; as well as Power control signals are sent to the plurality of stages of the power amplifier chain at respective gates or bases of transistors in the plurality of stages. The method of claim 13 , further comprising switching from a Vramp mode to a linear mode.

15. The method of claim 13, wherein sensing the power level comprises sensing at an antenna coupler.

16. The method of claim 13, wherein sensing the power level comprises summing a current at a base of a transistor and a converted current from an output of the transistor.

17. The method of claim 16, further comprising providing a supply voltage to the power amplifier chain at the output of the transistor.

18. The method of claim 13, wherein sensing the power level comprises sensing prior to antenna switching.

19. The method of claim 13, further comprising entering a 2G Vramp mode of operation.

20. The method of claim 13, further comprising generating bias signals for a plurality of amplifier stages.

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