Switch

Abstract

A switching arrangement includes: a bidirectional metal oxide semiconductor (MOS) switch having a drain, a source and a gate and a body; a first circuit coupled between the drain, the gate, and the source for providing electrostatic discharge protection; a first transistor having a source coupled to the body of the MOS switch, a drain coupled to the source of the MOS switch, and a gate coupled to the gate of the MOS switch; and a second circuit for providing electrostatic discharge protection, the second circuit comprising a first diode of Zener diode type having an anode coupled to the body of the MOS switch and a cathode coupled to the source, and a second transistor having a source coupled to the body of the MOS switch, a drain coupled to the source of the MOS switch, and a gate coupled to the anode of the first diode.

Description

Technical Field

[0001] The present disclosure relates to a switch, such as a MOS-based bidirectional switch. In particular, the present disclosure relates to a MOS-based bidirectional switch arrangement including electrostatic discharge protection. Background Art

[0002] Transistors can be used as switches. Specifically, MOS-based switches, such as MOSFETs, can be used as bidirectional switches. Like any other component, switches may experience electrostatic discharge (ESD) events and may need protection from potential damage caused by ESD. In addition, such switches can be hot-swappable, so that they are connected to a battery or other energy source without being controlled by the stress applied to the switch. Effectively protecting switches from ESD and hot-swap events is a challenge. Summary of the invention

[0003] According to a first aspect of the present disclosure, there is provided a switch arrangement, the switch arrangement comprising:

[0004] A bidirectional metal oxide semiconductor (MOS) switch having a drain terminal, a source terminal, a gate terminal and a body terminal;

[0005] A first circuit coupled between the drain terminal, the gate terminal and the source terminal for providing electrostatic discharge protection;

[0006] a first transistor having a source terminal coupled to the body of the MOS switch, a drain terminal coupled to the source terminal of the MOS switch, and a gate terminal coupled to the gate terminal of the MOS switch; and

[0007] A second circuit for providing electrostatic discharge protection, the second circuit comprising a first diode of a Zener diode type having an anode terminal coupled to the body of the MOS switch and a cathode terminal coupled to the source terminal, and a second transistor having a source terminal coupled to the body of the MOS switch, a drain terminal coupled to the source terminal of the MOS switch, and a gate terminal coupled to the anode terminal of the first diode.

[0008] In one or more embodiments, the second circuit further includes a first resistor having a first end coupled to the body of the MOS switch and a second end coupled to the anode terminal of the first diode, such that the anode terminal of the first diode is coupled to the body of the MOS switch via the first resistor.

[0009] In one or more embodiments, the first circuit comprises:

[0010] A second diode and a third diode of the Zener diode type,

[0011] The cathode terminal of the second diode is coupled to the drain terminal, the anode terminal of the second diode is coupled to the anode terminal of the third diode, and the cathode terminal of the third diode is coupled to the gate terminal.

[0012] In one or more embodiments, the first circuit further includes a second resistor connected between the gate terminal and the source terminal.

[0013] In one or more embodiments, the first transistor comprises an nMOS MOSFET.

[0014] In one or more embodiments, the second transistor comprises an nMOS FET.

[0015] In one or more embodiments, the second transistor comprises an NPN transistor.

[0016] In one or more embodiments, the MOS switch has an on-resistance lower than an on-resistance of the first transistor.

[0017] In one or more embodiments, the MOS switch is an n-channel MOS switch. In one or more embodiments, the MOS switch is a p-channel MOS switch, and wherein the first circuit and the second circuit may be coupled to the other of the source terminal and the drain terminal.

[0018] In one or more embodiments, the forward threshold voltage of the third diode plus the Zener voltage of the second diode plus the threshold voltage of the MOS switch plus the overdrive voltage of the MOS switch are selected to be smaller than the roll-off voltage of the MOS switch.

[0019] In one or more embodiments, the first transistor is configured to be turned on to short the body terminal of the MOS switch to the source terminal of the first transistor when the MOS switch is turned on.

[0020] In one or more embodiments, the second transistor is configured to short the body of the MOS switch to the source terminal upon occurrence of a transient voltage applied to the source terminal that exceeds the Zener voltage of the first diode plus a threshold voltage of the second transistor.

[0021] In one or more embodiments, the Zener voltage of the first diode is selected so that upon occurrence of an electrostatic discharge event having a voltage greater than the Zener voltage plus a threshold voltage of the second transistor applied to the source terminal of the MOS switch, the second transistor is turned on to disconnect a current path from the source terminal of the MOS switch through the second transistor, the body, and to the drain terminal of the MOS switch.

[0022] In one or more embodiments, the switch arrangement comprises a MOS based bidirectional switch arrangement.

[0023] According to a second aspect of the present disclosure, there is provided a battery management system including the switch arrangement according to the first aspect.

[0024] Although the present disclosure allows various modifications and alternative forms, the characteristics of the present disclosure have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments outside the specific embodiments described are also possible. All modifications, equivalents and alternative embodiments within the spirit and scope of the appended claims are also covered.

[0025] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The following descriptions of the figures and the detailed description also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed description in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0027] Figure 1 An example embodiment of a switch arrangement is shown;

[0028] Figure 2 Show Figure 1 A switch arrangement is shown and operation during a positive ESD strike is shown;

[0029] Figure 3 Show Figure 1 A switch arrangement is shown and operation during a negative ESD strike is shown;

[0030] Figure 4 An example battery management system is shown. DETAILED DESCRIPTION

[0031] The described embodiments relate to a circuit arrangement including a MOS-based bidirectional switch and another circuit system for providing electrostatic discharge (ESD) protection. The another circuit system can also improve electromagnetic compatibility and protect the switch from voltage transients caused by hot plug events.

[0032] Figure 1 A switch arrangement 100 is shown comprising a metal oxide semiconductor MOS bidirectional switch 101 (referred to herein as a MOS switch) having a drain terminal 102, a source terminal 103, a gate terminal 104 and a body or substrate terminal 105. The arrangement 100 is configured as a MOS based bidirectional switch arrangement.

[0033] The switch arrangement 100 further comprises a first clamp circuit 107 coupled between the drain terminal 102, the gate terminal 104 and the source terminal 103. The first clamp circuit 107 is configured to activate when a voltage greater than a first threshold voltage is applied to the drain terminal 102, i.e., V DS The voltage is greater than the first threshold voltage. The first clamp circuit 107, when activated, is configured to boost the voltage at the gate terminal 104 of the switch 101. The operation of the arrangement 100 and the effect of boosting the gate voltage will be described in more detail below.

[0034] Returning to the switch arrangement 100, a first transistor 110 is provided having a source terminal 111 coupled to the body 105 of the MOS switch 101, a drain terminal 112 coupled to the source terminal 103 of the MOS switch 101, and a gate terminal 113 coupled to the gate terminal 104 of the MOS switch 101. The first transistor 110 may include an nMOS transistor, such as an nMOS field effect transistor FET. The first transistor 110 is configured to be turned on simultaneously with the MOS switch 101.

[0035] The switch arrangement 100 of the present example includes a second clamp circuit 115. In the present example, the second clamp circuit 115 includes a first diode 116 of the Zener diode type having an anode terminal 117 coupled to the body 105 of the MOS switch 101 and a cathode terminal 118 coupled to the source terminal 103. The second clamp circuit 115 further includes a second transistor 119 having a source terminal 120 coupled to the body 105 of the MOS switch 101, a drain terminal 121 coupled to the source terminal 103 of the MOS switch 101, and a gate terminal 122 coupled to the anode terminal 117 of the first diode 116. The second transistor 119 may include an nMOS transistor, such as an nMOS FET or an NPN transistor.

[0036] In one or more examples, the second clamping circuit 115 further includes a first resistor 123 having a first end coupled to the body 105 of the MOS switch 101 and a second end coupled to the anode terminal 117 of the first Zener diode 116, such that the anode terminal 117 of the first Zener diode 116 is coupled to the body 105 of the MOS switch 101 via the first resistor 123.

[0037] In one or more examples, the first clamp circuit 107 includes a Zener diode 125, referred to as a second diode 125, and a third diode 126, which may be a normal pn diode. A cathode terminal 127 of the Zener diode 125 is coupled to the drain terminal 102, and an anode terminal 128 of the Zener diode 125 is coupled to an anode terminal 129 of the third diode 126. A cathode terminal 130 of the third diode 126 is coupled to the gate terminal 104. The cathode terminal 130 is also coupled to the source terminal 103 via a second resistor 131. It should be appreciated that the first clamp circuit 107 may take other forms.

[0038] Therefore, the second resistor 131 is electrically coupled between the gate terminal 104 and the source terminal 103 of the MOS switch 101 .

[0039] exist Figure 1 , the second clamp circuit 115 is shown with a fourth diode 133 representing a parasitic component of the second transistor 119. As will be appreciated by those skilled in the art, the parasitic fourth diode 133 or "built-in body diode" actually has a cathode terminal coupled to the drain terminal 121 of the second transistor 119 and an anode terminal coupled to the source terminal 120 of the second transistor 119. Furthermore, in reality, the body of the second transistor 119 is connected to its source terminal 120.

[0040] exist Figure 1 , the first transistor 110 is shown with a fifth diode 134 representing a parasitic component of the first transistor 110. As will be appreciated by those skilled in the art, the parasitic fifth diode 134 or “built-in body diode” actually has a cathode terminal coupled to the drain terminal 112 of the first transistor 110 and an anode terminal coupled to the source terminal 111 of the first transistor 110. Furthermore, in reality, the body of the first transistor 110 is connected to its source terminal 111 through the parasitic fifth diode 134.

[0041] Furthermore, in this example, the MOS switch 101 also has parasitic components shown as being built into the body diodes 136, 167. Therefore, in practice, the drain terminal 102 of the MOS switch 101 is coupled to the cathode terminal of the parasitic sixth diode 136, and the source terminal of the MOS switch is coupled to the cathode terminal of the parasitic seventh diode 137, and wherein the anode terminals of the parasitic sixth diode 136 and the parasitic seventh diode 137 are both coupled to the body electrode 105.

[0042] In the event of a positive transient voltage applied to drain terminal 102 , such as would occur during an electrostatic discharge (ESD) event, first clamp circuit 107 is configured to bias gate terminal 104 of MOS switch 101 to turn on MOS switch 101 to allow ESD current due to the positive transient voltage to flow through MOS switch 101 .

[0043] Example Figure 2 The flow of current in the case of such a positive transient voltage is shown.

[0044] As briefly mentioned above, the first clamp circuit 107 is configured to generate a gate-to-source voltage across the transistor of the MOS switch 101 when the drain-to-source voltage of the transistor of the MOS switch 101 is above a first threshold voltage.

[0045] The Zener voltage of Zener diode 125 or the "second diode" is V ttrig_ZD2 The forward threshold voltage (or “activation voltage”) of the third diode is V d3 In one or more examples, V d3 can be about 0.6 V. The threshold voltage of MOS switch 101 is designated as V t_MOS Therefore, the first threshold voltage or "clamping voltage" is V t_MOS +V ttrig_ZD2 +V d3 Therefore, when the gate-to-source voltage of the transistor of MOS switch 101 is higher than its threshold voltage, the switch will therefore conduct the ESD stress current, thereby limiting the drain-to-source voltage to V t_MOS +V ttrig_ZD2 +V d3+ V od . V od is greater than V t_MOS The overdrive voltage is used to obtain a current with a limited V ds voltage and the expected ESD current.

[0046] Therefore, when a transient is applied to the drain terminal 102, the drain-source voltage V ds Can be greater than including V t_MOS +V ttrig_ZD2 +V d3 The first threshold voltage of 104 is set such that the first clamp circuit 107 causes the gate-to-source voltage to increase beyond its threshold voltage, thereby providing drain-to-source voltage limiting, as described.

[0047] For example: V DS >V ttrig_ZD2 +V d3 +V t_MOS

[0048] The first clamp circuit 107 makes the MOS switch 101 self-protecting because the resulting flow 200 of current through the Zener diode 125 and the third diode 126 serves to raise the voltage at the gate terminal 104 to the threshold voltage V t_MOS .

[0049] This allows the current caused by the transient voltage to follow a path 201 through the channel of the MOS switch 101 to the source terminal 103. Thus, the MOS switch is protected due to the drain-to-source voltage limitation provided by the first clamp circuit 107.

[0050] If the roll-off voltage of MOS switch 101 is V rf , then the Zener voltage V of the Zener diode 125 ttrig_ZD2 and the forward threshold voltage V of the third diode d3 can be chosen so that V ttrig_ZD2 +V d3 +V t_MOS Lower than V rf In one or more examples, under ESD stress, an overdrive voltage of 2 to 3 V is provided between the required maximum drain-source voltage and the breakdown voltage of the transistor of the MOS switch 101. Thus, such a configuration will increase the drain-source voltage V DS Clamped at about V ttrig_ZD2 +V d3 +V GS , where V GS includes the gate-source voltage of MOS switch 101. This is advantageous because the gate-source voltage of MOS switch 101 must be at least V t_MOS level so that the MOS switch 101 conducts current between the drain and the source. In practice, the gate-source voltage reaches a value greater than V t_MOS A few volts higher so that the drain-source on-resistance of the MOS switch x the ESD current limits the drain-source voltage to an appropriate level, such as the breakdown voltage of the MOS switch minus a margin of, for example, 2.5V.

[0051] In one or more examples, the resistance value of the second resistor 131 can be selected to ensure that the MOS switch 101 does not have a floating gate voltage that would cause excessive leakage in its channel.

[0052] As mentioned, when the MOS switch 101 is turned on, the first transistor 110 is also configured to be turned on substantially simultaneously, thereby shorting the body 105 of the MOS switch 101 to the source terminal 103 of the MOS switch 101. This is advantageous because when the body 105 and the source terminal 103 are shorted together, the transient voltage capacity (i.e., the drain-source voltage V DS ) is high, thereby preventing premature activation of the parasitic NPN represented by the parasitic diodes 136, 137. It will be appreciated that the switch arrangement 100 may be designed such that the Vbs (base-source voltage) of the MOS switch 101 must be low during ESD stress in order to obtain the maximum drain-source resistance performance of the transistors of the MOS switch 101, thereby allowing, for example, the lowest possible drain-to-source voltage to be achieved when an ESD current flows through the channel of the MOS switch 101.

[0053] In one or more examples, the MOS switch has a low on-resistance R on , and thus can have a large footprint. Therefore, in one or more examples, the first transistor 110 has a smaller footprint and is configured to turn on faster than the MOS switch 101 at least during an ESD event. However, in one or more examples, the first transistor 110 is configured to have a sufficiently low on-resistance to maintain the body-source voltage V BS Close to 0V, because the source of the MOS switch 101 is also pulled up together with the gate terminal 104 due to the first clamp circuit 107 .

[0054] It should be appreciated that the first transistor 110 has a smaller size than the MOS switch 101 , and therefore, the current into the first transistor 110 is much lower than the current into the MOS switch 101 .

[0055] Example Figure 3 1 shows the flow of current in the case of a negative transient voltage. In this example, primarily the second clamp circuit 115 is configured to protect the MOS switch 101 from a transient voltage event applied at the source terminal 103 of the MOS switch 101, i.e., as a source-drain voltage V SD Applied transient voltage.

[0056] The second clamp circuit 115 may function differently depending on whether the voltage transient at the source terminal 103 is a fast transient or a relatively slow transient, such as may occur during a hot-swap situation.

[0057] During the fast transient voltage applied at the source terminal 103, the transient may have a voltage high enough to cause the MOS switch 101 to turn on in the reverse direction, i.e., when the gate-drain voltage is > 0. Therefore, the first diode 116 is used to control the gate-source voltage of the second transistor 119 so that the second transistor 119 is turned on to receive the ESD current during the fast transient voltage applied at the source terminal 103, thereby limiting the body-to-source voltage of the MOS switch 101. It can also be noted that due to the built-in body diode 136 between the body and the drain, the body-to-drain voltage of the MOS switch 101 can also be limited to about 0.6V, and thus the V sd The voltage is also limited in response to negative ESD stress. Since the gate 104 is connected to the source 103 via the second resistor 131, a current path 300 is also created, which enables the MOS switch 101 to have a gate-to-drain voltage that causes the channel to also conduct negative ESD current.

[0058] After a voltage transient occurs at the source terminal 103, the first diode 116 can be configured to provide a gate voltage at the gate of the second transistor 119. If the transient voltage is greater than the Zener voltage of the first Zener diode 116 and the threshold voltage of the second transistor 119, the second transistor 119 turns on. This is advantageous because the second circuit 115 is configured to turn on the second transistor 119 when a transient voltage (e.g., V SD >V ttrig_ZD1 +V t_2nd_transistor ) provides for the second transistor 119 to be turned on to provide a current path 301 from the source terminal 103 through the channel of the second transistor 119, through the body 105 and to the drain terminal 102. This is more likely to occur if the MOS switch 101 is small.

[0059] During a slower transient voltage applied at the source terminal 103 (which may occur during a hot-swap event), the MOS switch 101 may not be easily reversed on. Subsequently, again, if the transient voltage is greater than the Zener voltage of the first Zener diode 116 plus the threshold voltage of the second transistor 119, the second transistor 119 may be configured to turn on. Thus, the second clamp circuit 115 is configured to provide for the turning on of the second transistor 119 in the event of a (slower) transient voltage applied at the source terminal 103 that exceeds the Zener voltage of the first diode 116 and the threshold voltage of the second transistor 119, because the reverse current 302 reaches the gate of the second transistor 119 through the first Zener diode 116. As previously described, this provides a current path 301 from the source terminal 103 through the channel of the second transistor 119, through the body 105, and to the drain terminal 102.

[0060] In summary, in the event of a negative transient (i.e., a transient applied at the source terminal), the second clamping circuit 115 is configured to short the body 105 to the source terminal 103 by means of the action of the first diode 116 and the second transistor 119, which gives an opportunity for self-protection of the MOS switch.

[0061] It should be understood that the triggering of the second transistor 119 can clamp the source-drain voltage of the MOS switch to a desired value through the Zener voltage of the first Zener diode 116 .

[0062] The first clamp circuit 107 and the second clamp circuit 115 are so named because, in some examples, at least one of the functions of the first clamp circuit 107 and the second clamp circuit 115 is to clamp the end-to-end voltage of the MOS switch 101. However, it should be understood that the first clamp circuit 107 and the second clamp circuit 115 may be more generally referred to as the first circuit 107 and the second circuit 115.

[0063] The switch arrangement 100 of the present disclosure has particular application in battery management systems. Figure 4 A battery management system 400 is shown, comprising the switch arrangement 100 of the aforementioned embodiment for coupling to a battery 401. In such an embodiment, several switch arrangements 100 may be provided together and coupled to the battery pack 401.

[0064] It should be understood that any components referred to as being coupled may be coupled or connected directly or indirectly. In the case of an indirect coupling, additional components may be disposed between the two components referred to as being coupled.

[0065] In this specification, example embodiments have been presented based on a selected set of details. However, those skilled in the art will appreciate that many other example embodiments may be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A switch arrangement, characterized in that include: A bidirectional metal oxide semiconductor (MOS) switch having a drain terminal, a source terminal, a gate terminal and a body terminal; A first circuit coupled between the drain terminal, the gate terminal and the source terminal for providing electrostatic discharge protection; a first transistor having a source terminal coupled to the body of the MOS switch, a drain terminal coupled to the source terminal of the MOS switch, and a gate terminal coupled to the gate terminal of the MOS switch; as well as A second circuit for providing electrostatic discharge protection, the second circuit comprising a first diode of a Zener diode type having an anode terminal coupled to the body of the MOS switch and a cathode terminal coupled to the source terminal, and a second transistor having a source terminal coupled to the body of the MOS switch, a drain terminal coupled to the source terminal of the MOS switch, and a gate terminal coupled to the anode terminal of the first diode.

2. The switch arrangement according to claim 1, characterized in that The second circuit further includes a first resistor having a first end coupled to the body of the MOS switch and a second end coupled to the anode terminal of the first diode, such that the anode terminal of the first diode is coupled in series to the body of the MOS switch via the first resistor.

3. A switch arrangement according to claim 1 or claim 2, characterised in that The first circuit comprises: A second diode and a third diode of the Zener diode type, The cathode terminal of the second diode is coupled to the drain terminal, the anode terminal of the second diode is coupled to the anode terminal of the third diode, and the cathode terminal of the third diode is coupled to the gate terminal.

4. The switch arrangement according to claim 3, characterized in that The first circuit additionally includes a second resistor connected between the gate terminal and the source terminal.

5. A switch arrangement according to any one of the preceding claims, characterised in that The first transistor comprises an nMOS MOSFET.

6. A switch arrangement according to any preceding claim, characterised in that The second transistor includes an nMOS FET.

7. A switch arrangement according to any preceding claim, characterised in that The second transistor includes an NPN transistor.

8. A switch arrangement according to any preceding claim, characterised in that The MOS switch has an on-resistance lower than an on-resistance of the first transistor.

9. A switch arrangement according to any preceding claim, characterised in that The MOS switch is an n-channel MOS switch.

10. A battery management system, characterized in that:

4. A switch arrangement as claimed in any preceding claim.

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