A multi-mode serial-to-parallel conversion circuit and deserializer

Abstract

The present invention provides a multi-mode serial-to-parallel conversion circuit and a deserializer, including a selection logic module, generating a selection signal; a clock frequency division module, dividing the clock signal to obtain a plurality of sub-clock signals with different frequencies; a data conversion module, converting serial data into multi-channel parallel data according to the clock signal, the sub-clock signal and the selection signal; and a data output module, outputting parallel data. The selection signal generated by the selection logic module controls the serial-to-parallel conversion of the data conversion module, so that the serial-to-parallel conversion circuit can flexibly adjust the selection signal to adapt to the serial-to-parallel conversion of data signals with different bits; the clock frequency division module generates a plurality of sub-clock modules with different frequencies, so that when the data conversion module performs serial-to-parallel conversion, the number of D flip-flops working at the highest frequency is small, thereby reducing the power consumption of the serial-to-parallel conversion circuit, and solving the problem that the existing serial-to-parallel conversion circuit can only perform serial-to-parallel conversion on signals with one bit number and has high power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a multi-mode serial-to-parallel conversion circuit and a deserializer. Background Art

[0002] A deserializer (SerDes) is a device that converts multiple low-speed parallel signals at the transmitting end into high-speed serial signals, and converts high-speed serial signals at the receiving end back into low-speed parallel signals. Therefore, the serial-to-parallel conversion circuit is an important module in the deserializer design. It works at the highest speed in the entire deserializer, directly affecting the jitter of the output data signal and the accuracy of the recovered data signal, thereby affecting the bit error rate of the output signal.

[0003] Existing serial-to-parallel conversion circuits are usually implemented based on D flip-flops, and due to the design of the circuit structure, there are a large number of D flip-flops working at the highest frequency, which makes the power consumption of the entire serial-to-parallel conversion circuit large, affecting the working speed of the serial-to-parallel conversion circuit. In addition, the existing serial-to-parallel conversion circuit can usually only realize the serial-to-parallel conversion function of a signal with a certain number of bits, and cannot meet the conversion requirements of multiple serial-to-parallel signals, which limits the application of the serial-to-parallel conversion circuit. Summary of the invention

[0004] The object of the present invention is to provide a multi-mode serial-to-parallel conversion circuit and a deserializer, so as to at least solve the problem that the existing serial-to-parallel conversion circuit can only perform serial-to-parallel conversion on signals of one bit number and has high power consumption.

[0005] In order to solve the above technical problems, the present invention provides a multi-mode serial-to-parallel conversion circuit, comprising: A selection logic module, used for generating a selection signal; A clock frequency division module is used to divide the frequency of a clock signal to obtain multiple sub-clock signals with different frequencies; A data conversion module, used for converting serial data into multi-channel parallel data according to a clock signal, a sub-clock signal and a selection signal; The data output module is used to output parallel data.

[0006] Optionally, in the multi-mode serial-to-parallel conversion circuit, the clock division module includes a first divider and a second divider; the first divider is used to divide the clock signal to obtain a two-divided clock signal; the second divider is used to divide the clock signal to obtain a 2n-divided clock signal, where n is an integer greater than or equal to 2.

[0007] Optionally, in the multi-mode serial-to-parallel conversion circuit, the data conversion module includes a branch unit and a reading unit; the branch unit is used to convert serial data into multiple data according to a clock signal; the reading unit is used to read data from the multiple data according to a sub-clock signal and a selection signal to obtain parallel data.

[0008] Optionally, in the multi-mode serial-to-parallel conversion circuit, the branching unit includes a first-level branching unit and a second-level branching unit; the first-level branching unit is used to convert serial data into multiple paths of first-level data according to a clock signal; the number of the second-level branching units is consistent with the number of paths of the first-level data, and each of the second-level branching units receives one path of first-level data, and different second-level branching units receive different paths of first-level data; the second-level branching unit is used to divide the first-level data into multiple paths of second-level data according to the clock signal.

[0009] Optionally, in the multi-mode serial-to-parallel conversion circuit, the first-level splitter and the second-level splitter are both parity extractors; the first-level splitter is used to convert the serial data into one odd-bit data and one even-bit data according to the parity extraction principle based on the clock signal; the number of the second-level splitters is 2, one of the second-level splitters is used to receive odd-bit data, and convert the received odd-bit data into one odd-bit data and one even-bit data according to the parity extraction principle based on the clock signal; the other second-level splitter is used to receive even-bit data, and convert the received even-bit data into one odd-bit data and one even-bit data according to the parity extraction principle based on the clock signal.

[0010] Optionally, in the multi-mode serial-to-parallel conversion circuit, the number of the reading units is consistent with the number of multiple data paths, and each of the reading units receives one path of data, and different reading units receive different paths of data.

[0011] Optionally, in the multi-mode serial-to-parallel conversion circuit, the reading unit includes multiple multiplexers, shift registers and reading registers; the multiplexer is used to read data from multiple data channels according to a selection signal; the shift register is used to shift and register the data read out by the multiplexer; and the reading register is used to read the data stored in the shift register according to a sub-clock signal to obtain parallel data.

[0012] Optionally, in the multi-mode serial-to-parallel conversion circuit, the bit widths of the selection signals received by the multiple multiplexers are different.

[0013] Optionally, in the multi-mode serial-to-parallel conversion circuit, when the frequency of the sub-clock signal obtained by the clock division module is 1 / 2n of the clock signal, the bit width of the selection signal corresponds to 4n bits, where n is an integer greater than or equal to 2.

[0014] In order to solve the above technical problems, the present invention provides a deserializer, comprising the multi-mode serial-to-parallel conversion circuit as described in any one of the above items.

[0015] The multi-mode serial-to-parallel conversion circuit and deserializer provided by the present invention include: a selection logic module for generating a selection signal; a clock frequency division module for dividing the clock signal to obtain a plurality of sub-clock signals with different frequencies; a data conversion module for converting serial data into multi-channel parallel data according to the clock signal, the sub-clock signal and the selection signal; and a data output module for outputting parallel data. The selection signal generated by the selection logic module controls the data conversion module to convert serial data into parallel data, so that the serial-to-parallel conversion circuit can flexibly adjust the selection signal to adapt to the serial-to-parallel conversion of data signals with different bits; the clock frequency division module generates a plurality of sub-clock modules with different frequencies, so that when the data conversion module performs serial-to-parallel conversion, each D flip-flop uses a different sub-clock module, thereby reducing the number of D flip-flops working at the highest frequency, thereby reducing the power consumption of the serial-to-parallel conversion circuit, and solving the problem that the existing serial-to-parallel conversion circuit can only perform serial-to-parallel conversion on signals with one bit number and has high power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A structural block diagram of a multi-mode serial-to-parallel conversion circuit provided in this embodiment; Figure 2 A schematic diagram of the structure of the branching unit provided in this embodiment; Figure 3 A schematic diagram of the structure of a splitter unit when the splitter provided in this embodiment is an odd-even extractor; Figure 4 A schematic diagram of the structure of a reading unit provided in this embodiment; Figure 5 This is a circuit schematic diagram of the multi-mode serial-to-parallel conversion circuit provided in this embodiment. DETAILED DESCRIPTION

[0017] The multi-mode serial-to-parallel conversion circuit and deserializer proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0018] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0019] This embodiment provides a multi-mode serial-to-parallel conversion circuit, such as Figure 1 As shown, including: A selection logic module, used for generating a selection signal; A clock frequency division module is used to divide the frequency of a clock signal to obtain multiple sub-clock signals with different frequencies; A data conversion module, used for converting serial data into multi-channel parallel data according to a clock signal, a sub-clock signal and a selection signal; The data output module is used to output parallel data.

[0020] The multi-mode serial-to-parallel conversion circuit provided in this embodiment controls the data conversion module to convert serial data into parallel data by a selection signal generated by a selection logic module, so that the serial-to-parallel conversion circuit can flexibly adjust the selection signal to adapt to the serial-to-parallel conversion of data signals with different bits; a plurality of sub-clock modules with different frequencies are generated by a clock division module, so that when the data conversion module performs serial-to-parallel conversion, each D flip-flop uses a different sub-clock module, thereby reducing the number of D flip-flops operating at the highest frequency, thereby reducing the power consumption of the serial-to-parallel conversion circuit, and solving the problem that the existing serial-to-parallel conversion circuit can only perform serial-to-parallel conversion on signals with one bit number and has high power consumption.

[0021] Specifically, in this embodiment, the selection logic module is used to convert the input bit selection signal into multiple selection signals according to different bit width requirements.

[0022] In a specific embodiment, the bit width of the bit selection signal can be 2 bits, the bit width of multiple selection signals generated after passing through the selection logic module can be 1 bit, and the multiple selection signals can respectively control the output of signals with a bit width of 8 bits, 12 bits, 16 bits, etc.

[0023] Furthermore, in this embodiment, the clock division module includes a first divider and a second divider; the first divider is used to divide the clock signal to obtain a two-divided clock signal; the second divider is used to divide the clock signal to obtain a 2n-divided clock signal, where n is an integer greater than or equal to 2.

[0024] In a specific embodiment, the first frequency divider divides the clock signal CK to obtain a two-divided clock signal CK / 2; the second frequency divider divides the clock signal CK to obtain multiple divided clock signals, such as a four-divided clock signal CK / 4, a six-divided clock signal CK / 6, an eight-divided clock signal CK / 8, etc.

[0025] Furthermore, in this embodiment, the data conversion module includes a branch unit and a reading unit; the branch unit is used to convert serial data into multiple data according to a clock signal; the reading unit is used to read data from the multiple data according to a sub-clock signal and a selection signal to obtain parallel data.

[0026] Specifically, in this embodiment, if Figure 2 As shown, the branching unit includes a first-level branching device and a second-level branching device; the first-level branching device is used to convert serial data into multiple first-level data according to a clock signal; the number of the second-level branching devices is consistent with the number of first-level data paths, and each of the second-level branching devices receives one first-level data path, and different second-level branching devices receive different first-level data paths; the second-level branching device is used to divide the first-level data into multiple second-level data paths according to the clock signal.

[0027] In practical applications, such as Figure 3 As shown, the first-level splitter and the second-level splitter are both parity extractors; the first-level splitter is used to convert serial data into one odd-bit data and one even-bit data according to the parity extraction principle based on the clock signal; the number of the second-level splitters is 2, one of the second-level splitters is used to receive odd-bit data, and convert the received odd-bit data into one odd-bit data and one even-bit data according to the parity extraction principle based on the clock signal; the other second-level splitter is used to receive even-bit data, and convert the received even-bit data into one odd-bit data and one even-bit data according to the parity extraction principle based on the clock signal.

[0028] At present, in other embodiments, in order to improve the efficiency of serial-to-parallel conversion, there can be more levels of splitters, so as to divide the serial data into more paths of data. Of course, since the number of reading units needs to be consistent with the number of paths of multi-path data, and each of the reading units receives one path of data, and different reading units receive different paths of data, in order to realize the reading of each path of data to form parallel data, therefore, as the number of paths of data divided increases, the number of corresponding reading units also increases, which will increase the area and cost of the multi-mode serial-to-parallel conversion circuit to a certain extent. Therefore, in practical applications, the number of levels of splitters and the number of data paths divided need to be reasonably set according to actual needs.

[0029] Further, in this embodiment, the reading unit includes a plurality of multiplexers (MUX), a shift register and a read register. In this embodiment, the shift register and the read register are both D flip-flops (DFF). The multiplexer is used to read data from multiple data channels according to a selection signal; the shift register is used to shift and register the data read by the multiplexer; and the read register is used to read the data stored in the shift register according to a sub-clock signal to obtain parallel data.

[0030] In a specific embodiment, if Figure 4 As shown, it includes three multiplexers MUX1, MUX2 and MUX3, and each multiplexer receives a different selection signal, wherein the selection signal received by MUX1 can make the signal bit width of its output 16 bits, the selection signal received by MUX2 can make the signal bit width of its output 12 bits, and the selection signal received by MUX3 can make the signal bit width of its output 8 bits. Different selection signals are generated by the selection logic module according to the bit selection signal. In this way, multiple multiplexers read different data from the data chain according to the different selection signals received.

[0031] And, in this specific embodiment, it includes 4 shift registers DFF1, DFF2, DFF3 and DFF4, and 4 read registers DFF5, DFF6, DFF7 and DFF8. Since in this embodiment, the two-stage splitter used by the data conversion module divides the data into odd and even paths according to the two-frequency clock signal CK / 2, the four shift registers of this embodiment all receive the two-frequency clock signal CK / 2 generated by the first frequency divider, thereby ensuring that the data selected by the multiplexer can be correctly and timely stored in the shift register. At the same time, since in this embodiment, the sub-clock signal generated by the first frequency divider is the two-frequency clock signal CK / 2, the second frequency divider can generate a four-frequency clock signal CK / 4, a six-frequency clock signal CK / 6 and an eight-frequency clock signal CK / 8 according to the selection signal, the multiplexer can output the correct value according to different selection signals, the shift register and the read register and then according to the corresponding sub-clock signal.

[0032] The connection relationship between the various components in the reading unit provided in this embodiment is as follows: the input signal of MUX1 is the data DATA after being branched by the branch unit and the low level 0, and the output of MUX1 is the input of DFF1; the input signal of MUX2 is the data DATA after being branched by the branch unit and the output signal of DFF1, and the output of MUX2 is the input of DFF2; the input signal of MUX3 is the data DATA after being branched by the branch unit and the output signal of DFF2, and the output of MUX3 is the input of DFF3; the output of DFF3 is the input of DFF4; the input of DFF5 is the output of DFF4, the input of DFF6 is the output of DFF3, the input of DFF7 is the output of DFF2, and the input of DFF8 is the output of DFF1.

[0033] When reading data, when the selection signal bit8 is high level 1, the selection signal bit12 and the selection signal bit16 are low level 0, so only MUX3 is directly connected to DATA, reads the data at this time, and transmits the read data to DFF3 and DFF4 at the rising edge of the two-divided clock signal CK / 2 and stores them; at this time, the clock signal output by the second divider is CK / 4, and when the rising edge of the clock arrives, D is output through DFF6 and DFF5. <0> and D <4> When the selection signal bit12 is at a high level and the selection signal bit16 is at a high level, the data is read out in a similar manner, so that within a clock signal CK / 4 cycle, the data of the path is read out from serial to parallel.

[0034] from Figure 4It can be seen that the shift registers are all controlled by CK / 2, and the various read registers are controlled by CK / 4, CK / 6 and CK8 according to the corresponding selection signals. Compared with the prior art, the number of registers (D flip-flops) operating at the highest frequency in the read unit provided in this embodiment is significantly reduced, thereby reducing the power consumption of the serial-to-parallel conversion circuit.

[0035] In practical applications, there is a certain correspondence between the multiplexer, the shift register, the read register, the selection signal and the sub-clock signal, so that the serial data can be completely and accurately converted into parallel data according to the correspondence.

[0036] Specifically, when the frequency of the clock (sub-clock signal) currently used to read the register is 1 / 2n of the clock signal, the selection signal of the multiplexer in front of the corresponding shift register controls the output of a signal with a bit width of 4n bits, where n is an integer greater than or equal to 2.

[0037] Furthermore, the data output module is used to output parallel data. Specifically, the data output by each read register is input to the data output module, and after being sorted by the data output module, the parallel data is output according to the requirements of the subsequent circuit.

[0038] The following is a specific example of how the multi-mode serial-to-parallel conversion circuit provided by the present application realizes the conversion of serial data into parallel data: like Figure 5 As shown, in this embodiment, the selection logic module generates three selection signals according to the bit selection signal BIT_SEL, and the bit widths of the signals controlled by the three selection signals are 16 bits ( Figure 5 middle red dotted line), 12bit ( Figure 5 Green dashed line) and 8bit ( Figure 5 The clock signal CK is used as the input of the first frequency divider, the input of the second frequency divider and the clock of the first-stage parity extractor, respectively. The first frequency divider divides the clock signal CK into CK / 2 ( Figure 5 The second frequency divider divides the clock signal CK into CK / 4, CK / 6, and CK / 8 ( Figure 5 The divided-by-two clock signal CK / 2 is used as the clock of the secondary parity extractor and the clock of the shift register.

[0039] Under the control of the clock signal CK, the first-level parity extractor separates the parity of the serial data DATA, wherein the odd-numbered data bits are sent to the second-level parity extractor via the ODD port of the first-level parity extractor, and the even-numbered data bits are sent to another second-level parity extractor via the EVEN port of the first-level parity extractor; similarly, the second-level parity extractor separates the parity of the data again under the control of the sub-clock signal CK / 2, thus obtaining 4 columns of output data.

[0040] Each column of output data is read out through a readout unit, and each readout unit includes 3 multiplexers, 4 shift registers and 4 readout registers. Each multiplexer receives a selection signal to select data, the shift registers receive a CK / 2 clock signal to shift and store data, and the readout registers receive CK / 4, CK6 and CK8 clock signals according to the corresponding selection signals to read out data.

[0041] Taking the readout unit corresponding to the EVEN port of the secondary parity extractor as an example, the connection relationship of each component in the readout unit and the data readout method are explained: The input signal of MUX1 is the data output by the EVEN port of the secondary parity extractor and the low level 0. The selection signal of MUX1 is the bit16 selection signal ( Figure 5 The input signal of DFF1 is the output signal of MUX1; the input signal of MUX2 is the data output by the EVEN port of the secondary parity extractor and the output signal of DFF1, and the selection signal of MUX2 is the bit12 selection signal ( Figure 5 The green dotted line in the middle); the input signal of DFF2 is the output signal of MUX2; the input signal of MUX3 is the data output by the EVEN port of the secondary parity extractor and the output signal of DFF2, and the selection signal of MUX3 is the bit8 selection signal ( Figure 5 The input signal of DFF3 is the output signal of MUX3; the input signal of DFF4 is the output signal of DFF3; the input signal of DFF5 is the output signal of DFF4; the input signal of DFF6 is the output signal of DFF3; the input signal of DFF7 is the output signal of DFF2; the input signal of DFF8 is the output signal of DFF1.

[0042] When the selection signal bit8 is high level 1, bit12 and bit16 are low level 0, so only MUX3 is directly connected to DATA, reads the data at this time, and transmits the read data to DFF3 and DFF4 at the rising edge of the two-divided clock signal CK / 2 and stores them; at this time, the clock signal output by the second divider is CK / 4, and when the rising edge of the clock arrives, D is output through DFF6 and DFF5. <0> and D <4> Similarly, D <2> , D <6> , D <1> , D <5> , D <3> and D <7> is also read out, and the circuit is finally completed. <7> ~D <0> The serial-to-parallel conversion, the remaining bits are D <15> ~D <8> Output low level 0.

[0043] When the selection signal bit12 is high level 1, bit8 and bit16 are low level 0, so only MUX2 is directly connected to DATA, reads the data at this time, and transmits the read data to DFF2 at the rising edge of the two-divided clock signal CK / 2, and then to MUX3, DFF3 and DFF4 in sequence; at this time, the clock signal output by the second divider is CK / 6, and when the rising edge of the clock arrives, D is output through DFF5, DFF6 and DFF7. <0> , D <4> and D <8> , the rest is D <2> , D <6> , D <10> , D <1> , D <5> , D <9> , D <3> , D <7> and D <11> And so on, the final circuit is completed D <11> ~D <0> The serial-to-parallel conversion, the remaining bits are D <15> ~D <12> Output low level 0.

[0044] When the selection signal bit16 is high level 1, bit8 and bit12 are low level 0, so only MUX1 is directly connected to DATA, reads the data at this time, and transmits the read data to DFF1 at the rising edge of the two-frequency clock signal CK / 2, and then sequentially transmits it to MUX2, DFF2, MUX3, DFF3 and DFF4. At this time, the clock signal output by the second divider is CK / 8. When the rising edge of the clock arrives, D is output through DFF5, DFF6, DFF7 and DFF8. <0> , D <4> , D <8> and D <12> , the rest is D <2> , D <6> , D <10> , D <14> , D <1> , D <5> , D <9> , D <13> , D <3> , D <7> , D <11> and D <15> And so on, the final circuit is completed D <15> ~D <0> Serial-to-parallel conversion.

[0045] In this way, by selecting signals with different numbers of bits, the serial-to-parallel conversion function with different numbers of bits can be flexibly realized, broadening the application scenarios of the serial-to-parallel conversion circuit. At the same time, in the serial-to-parallel conversion, the clock signal frequencies used by different registers are not exactly the same, thereby reducing the number of registers working at the highest frequency, thereby reducing the power consumption of the serial-to-parallel conversion circuit.

[0046] This embodiment also provides a deserializer, including the multi-mode serial-to-parallel conversion circuit as described above.

[0047] The deserializer provided in this embodiment controls the conversion of serial data to parallel data by the data conversion module in the multi-mode serial-to-parallel conversion circuit through the selection signal generated by the selection logic module in the multi-mode serial-to-parallel conversion circuit, so that the serial-to-parallel conversion circuit can flexibly adjust the selection signal to adapt to the serial-to-parallel conversion of data signals with different bits; a plurality of sub-clock modules with different frequencies are generated by the clock division module in the multi-mode serial-to-parallel conversion circuit, so that when the data conversion module in the multi-mode serial-to-parallel conversion circuit performs serial-to-parallel conversion, each D flip-flop uses a different sub-clock module, thereby realizing hierarchical processing of data, thereby reducing the number of D flip-flops operating at the highest frequency, thereby reducing the power consumption of the serial-to-parallel conversion circuit, solving the problem that the existing serial-to-parallel conversion circuit can only perform serial-to-parallel conversion on signals with one bit number and has high power consumption, thereby reducing the power consumption of the deserializer.

[0048] It should be noted that the above embodiments are only the main implementation methods of the serial-to-parallel conversion circuit provided by the present application. Those skilled in the art can obtain other serial-to-parallel conversion circuits with the number of modules / units / components changed under the technical enlightenment of the above embodiments. Other serial-to-parallel conversion circuits that do not violate the main purpose of the present application should also fall within the scope of protection of the present application.

[0049] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0050] The multi-mode serial-to-parallel conversion circuit and deserializer provided in this embodiment include: a selection logic module for generating a selection signal; a clock frequency division module for dividing the clock signal to obtain multiple sub-clock signals with different frequencies; a data conversion module for converting serial data into multiple parallel data according to the clock signal, the sub-clock signal and the selection signal; and a data output module for outputting parallel data. The selection signal generated by the selection logic module controls the data conversion module to convert serial data into parallel data, so that the serial-to-parallel conversion circuit can flexibly adjust the selection signal to adapt to the serial-to-parallel conversion of data signals with different bits; the clock frequency division module generates multiple sub-clock modules with different frequencies, so that when the data conversion module performs serial-to-parallel conversion, each D flip-flop uses a different sub-clock module, realizing hierarchical processing of data, thereby reducing the number of D flip-flops working at the highest frequency, thereby reducing the power consumption of the serial-to-parallel conversion circuit, and solving the problem that the existing serial-to-parallel conversion circuit can only perform serial-to-parallel conversion on signals with one bit number and has high power consumption.

[0051] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A multi-mode serial-to-parallel conversion circuit, characterized in that: include: A selection logic module, used for generating a selection signal; A clock frequency division module is used to divide the frequency of a clock signal to obtain multiple sub-clock signals with different frequencies; A data conversion module, used for converting serial data into multi-channel parallel data according to a clock signal, a sub-clock signal and a selection signal; The data output module is used to output parallel data.

2. The multi-mode serial-to-parallel conversion circuit according to claim 1, characterized in that: The clock frequency divider module includes a first frequency divider and a second frequency divider; the first frequency divider is used to divide the clock signal to obtain a two-frequency divided clock signal; the second frequency divider is used to divide the clock signal to obtain a 2n-frequency divided clock signal, wherein n is an integer greater than or equal to 2.

3. The multi-mode serial-to-parallel conversion circuit according to claim 1, characterized in that: The data conversion module includes a branch unit and a reading unit; the branch unit is used to convert serial data into multiple data according to a clock signal; the reading unit is used to read data from the multiple data according to a sub-clock signal and a selection signal to obtain parallel data.

4. The multi-mode serial-to-parallel conversion circuit according to claim 3, characterized in that: The branching unit includes a first-level branching device and a second-level branching device; the first-level branching device is used to convert serial data into multiple first-level data according to a clock signal; the number of the second-level branching devices is consistent with the number of first-level data paths, and each of the second-level branching devices receives one first-level data path, and different second-level branching devices receive different first-level data paths; the second-level branching device is used to divide the first-level data into multiple second-level data paths according to a clock signal.

5. The multi-mode serial-to-parallel conversion circuit according to claim 4, characterized in that: The first-level splitter and the second-level splitter are both parity extractors; the first-level splitter is used to convert serial data into one path of odd-bit data and one path of even-bit data according to the parity extraction principle based on a clock signal; the number of the second-level splitters is 2, one of which is used to receive odd-bit data, and convert the received odd-bit data into one path of odd-bit data and one path of even-bit data according to the parity extraction principle based on a clock signal; the other second-level splitter is used to receive even-bit data, and convert the received even-bit data into one path of odd-bit data and one path of even-bit data according to the parity extraction principle based on a clock signal.

6. The multi-mode serial-to-parallel conversion circuit according to claim 3, characterized in that: The number of the reading units is consistent with the number of paths of the multi-path data, and each of the reading units receives one path of data, and different reading units receive different paths of data.

7. The multi-mode serial-to-parallel conversion circuit according to claim 3, characterized in that: The reading unit includes multiple multiplexers, shift registers and reading registers; the multiplexers are used to read data from multiple data channels according to a selection signal; the shift registers are used to shift and register the data read by the multiplexers; and the reading registers are used to read the data stored in the shift registers according to a sub-clock signal to obtain parallel data.

8. The multi-mode serial-to-parallel conversion circuit according to claim 7, characterized in that: The selection signals received by the multiplexers have different bit widths.

9. The multi-mode serial-to-parallel conversion circuit according to claim 7, characterized in that: When the frequency of the sub-clock signal obtained by the clock frequency division module is 1 / 2n of the clock signal, the bit width of the selection signal is correspondingly 4n bits, where n is an integer greater than or equal to 2.

10. A deserializer, characterized in that: It comprises the multi-mode serial-to-parallel conversion circuit as described in any one of claims 1 to 9.

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