Memory device and control method and manufacturing method thereof

Abstract

The invention provides a memory device and a control method and a manufacturing method thereof, and relates to the technical field of semiconductors. One storage unit of the storage device provided by the invention is provided with two sub-units which are interconnected through the drain electrodes, and the threshold voltage stored in each sub-unit can be independently read by configuring different voltage signals, so that each sub-unit has independent storage capacity, the storage capacity of a single storage unit in the storage device is improved, and the storage efficiency of the storage device is improved. And the storage device can store more information. Besides, the two sub-units can be a P-type storage sub-unit and an N-type storage sub-unit respectively, a complementary semiconductor structure is formed, and therefore better electrical performance and stability are achieved.

Description

Technical Field

[0001] The present application relates to semiconductor technology, and in particular to a storage device and a control method and a manufacturing method thereof. Background Art

[0002] In the field of data storage, non-volatile memory based on metal oxide semiconductor (MOSFET) has a wide range of applications. Among them, non-volatile memory based on MOSFET has a floating gate and can store charges / holes through the floating gate effect, thereby forming a threshold voltage of the memory so that the memory works at the threshold voltage. When applied, the threshold voltage can be used as data, and the data can be read by reading the threshold voltage.

[0003] Therefore, how to further improve the storage performance of MOSFET-based non-volatile memory is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a memory device and a control method and a manufacturing method thereof. The present application integrates an N-type memory sub-unit and a P-type memory sub-unit in a memory cell of the memory device and connects them with a common drain, so that each memory sub-unit has an independent storage capacity and forms a complementary semiconductor structure, thereby improving the electrical properties and stability of the device.

[0005] In a first aspect, the present application provides a memory device. The memory device includes a plurality of memory cells. The memory cells include an N-type memory sub-cell, a P-type memory sub-cell, and a control lead. The N-type memory sub-cell is disposed on a first side of an isolation trench in a substrate and an N-type drain of the N-type memory sub-cell is close to the isolation trench. The P-type memory sub-cell is disposed on a second side of an isolation trench in a substrate and a P-type drain of the P-type memory sub-cell is close to the isolation trench. The control lead includes a common drain lead connected to both an N-type drain and a P-type drain, an N-type source lead connected to an N-type source of an N-type memory sub-cell, an N-type gate lead connected to an N-type gate of an N-type memory sub-cell, a P-type source lead connected to a P-type source of a P-type memory sub-cell, and a P-type gate lead connected to a P-type gate of a P-type memory sub-cell.

[0006] In a second aspect, the present application provides a storage structure, the storage structure includes a doped substrate, a source, a drain, a control gate and a floating gate. The source and the drain are arranged at two ends of the doped substrate, and the control gate is arranged between the source and the drain. The floating gate is arranged below the control gate and embedded in the substrate, and the floating gate includes at least two extensions, and the at least two extensions extend into the substrate.

[0007] In a third aspect, the present application provides a control method for a memory device, which is applied to the memory device described in the first aspect. The control method includes a method for reading a threshold voltage from a target memory sub-unit in an N-type memory sub-unit and a P-type memory sub-unit in the memory device, including: controlling the memory device to be in a read state corresponding to the target memory sub-unit; applying a scan voltage to a gate lead of the target memory sub-unit; and in response to the source and drain of the target memory sub-unit being turned on, determining an actual scan voltage at the turn-on moment and using it as a threshold voltage.

[0008] In a fourth aspect, the present application provides a method for preparing a memory device, the preparation method comprising: providing a substrate, wherein the substrate comprises an N-type memory sub-unit, a P-type memory sub-unit and an isolation trench, the N-type memory sub-unit and the P-type memory sub-unit are arranged on both sides of the isolation trench, the N-type drain of the N-type memory sub-unit is close to the isolation trench, and the P-type drain of the P-type memory sub-unit is close to the isolation trench; depositing a lead dielectric layer on the substrate; etching the lead dielectric layer to form a lead groove penetrating the lead dielectric layer; filling the lead groove to form a control lead of the memory device, wherein the control lead comprises a common drain lead connected to both the N-type drain and the P-type drain, an N-type source lead connected to the N-type source of the N-type memory sub-unit, an N-type gate lead connected to the N-type gate of the N-type memory sub-unit, a P-type source lead connected to the P-type source of the P-type memory sub-unit, and a P-type gate lead connected to the P-type gate of the P-type memory sub-unit.

[0009] Based on the memory device and its control method and manufacturing method provided by the embodiment of the present application, a memory cell of the memory device provided by the present application has two sub-units and is interconnected through a drain. By configuring different voltage signals, the threshold voltage stored in each sub-unit can be read independently, so that each sub-unit has an independent storage capacity, thereby improving the storage capacity of a single memory cell in the memory device, so that the memory device can store more information. In addition, the two sub-units can be a P-type memory sub-unit and an N-type memory sub-unit, respectively, forming a complementary semiconductor structure, so as to have better electrical performance and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 This is a structural schematic diagram of a storage unit provided in some embodiments of the present application.

[0012] Figure 2This is another structural schematic diagram of a storage unit provided in some embodiments of the present application.

[0013] Figure 3 is an exemplary flow chart of a threshold voltage reading method provided in some embodiments of the present application.

[0014] Figure 4 This is an exemplary flow chart of a threshold voltage adjustment method provided in some embodiments of the present application.

[0015] Figure 5 is an exemplary flow chart of a method for preparing a memory device provided in some embodiments of the present application.

[0016] Figure 6 is a schematic diagram of a substrate with storage subunits provided in some embodiments of the present application.

[0017] Figure 7 Schematic diagram of a lead dielectric layer provided in some embodiments of the present application.

[0018] Figure 8 It is a structural diagram of a storage structure provided in some embodiments of the present application.

[0019] Fig. 9 This is another structural diagram of the storage structure provided in some embodiments of the present application.

[0020] Fig.10 It is a schematic diagram of the structure of a memory cell with a fully embedded floating gate provided in some embodiments of the present application.

[0021] Among them, 100, storage unit; 110, N-type storage subunit; 120, P-type storage subunit; 130, isolation trench; 111, N-type drain; 112, N-type source; 113, N-type gate; 121, P-type drain; 122, P-type source; 123, P-type gate; 141, common drain lead; 142, N-type source lead; 143, N-type gate lead; 144, P-type source lead; 145, P-type gate lead; 1 50. drain connection structure; 160. substrate; 170. lead dielectric layer; 171. lead groove; 200. storage structure; 210. doped substrate; 220. source; 230. drain; 240. control gate; 250. floating gate; 251. extension portion; 252. connection portion; 2521. drive surface; 2522. extension surface; 231. drain lead; 221. source lead; 241. first isolation layer; 242. second isolation layer. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, and therefore the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0025] Example storage devices: In practical applications, a memory device often has multiple memory cells, each of which can store data. The memory device provided in the present application can be a non-volatile memory based on MOSFET. The threshold voltage in the memory cell can be used as storage data, and the data can be read by reading the threshold voltage. For example, the actual data corresponding to different threshold voltage values ​​can be determined first, and the actual data stored in the memory cell can be determined by reading the threshold voltage and combining the corresponding relationship between the actual data and the threshold voltage value.

[0026] In order to improve the storage capacity of a single memory cell, the present application integrates an N-type memory sub-cell and a P-type memory sub-cell in a memory cell, wherein both the N-type memory sub-cell and the P-type memory sub-cell are non-volatile MOSFET memories based on a floating gate structure.

[0027] The N-type storage sub-cell may be an N-type metal oxide semiconductor, and the conductivity of the N-type storage sub-cell mainly depends on free electrons. When the gate voltage (VGS) of the N-type storage sub-cell is higher than the threshold voltage, the N-type storage sub-cell is turned on. The data recorded in the N-type storage sub-cell can be reflected by the threshold voltage when the N-type storage sub-cell is turned on.

[0028] The substrate of the N-type storage sub-unit is doped with P-type ions, and the source and drain of the N-type storage sub-unit are N-type ion doped regions. The threshold voltage recorded in the N-type storage sub-unit is a positive voltage.

[0029] The P-type storage sub-unit may be a P-type metal oxide semiconductor, and the conductivity of the P-type storage sub-unit mainly depends on holes. When the gate voltage (VGS) of the P-type storage sub-unit is lower than the threshold voltage, the P-type storage sub-unit is turned on. The data recorded in the P-type storage sub-unit can be reflected by the threshold voltage when the P-type storage sub-unit is turned on.

[0030] The substrate of the P-type storage subunit is doped with N-type ions, and the source and drain of the P-type storage subunit are P-type ion doped regions. The threshold voltage recorded in the P-type storage subunit is a negative voltage.

[0031] In practical applications, the aforementioned N-type storage subunit and P-type storage subunit may be OTP (one time programming) devices whose threshold voltage cannot be rewritten, or may be MTP (multi time programming) devices whose threshold voltage can be rewritten. The subsequent contents of this application are described using MTP devices as an example, and if there is a practical need, they may be partially replaced with OTP devices and adaptively improved.

[0032] In order to construct the N-type storage subunit and the P-type storage subunit into one storage unit, the present application interconnects the drains of the N-type storage subunit and the P-type storage subunit, so that the N-type storage subunit and the P-type storage subunit can store data separately. To further illustrate the storage unit provided by the present application, the present application also provides a structural schematic diagram of a storage unit.

[0033] like Figure 1 As shown, the memory cell 100 may include an N-type memory sub-cell 110, a P-type memory sub-cell 120, an isolation trench 130, and a control lead. The N-type memory sub-cell 110 and the P-type memory sub-cell 120 may be disposed on both sides of the isolation trench 130, respectively.

[0034] As mentioned above, both the N-type storage subunit 110 and the P-type storage subunit 120 are non-volatile MOSFET memories. The N-type storage subunit 110 includes an N-type drain 111, an N-type source 112, and an N-type gate 113. Among them, the N-type gate 113 may include a control gate (Poly Control Gate) and a floating gate (Floating Gate) to achieve the recording of the threshold voltage. Correspondingly, the P-type storage subunit 120 includes a P-type drain 121, a P-type source 122, and a P-type gate 123.

[0035] To achieve interconnection between the N-type drain 111 of the N-type storage subunit 110 and the P-type drain 121 of the P-type storage subunit 120 , the N-type drain 111 of the N-type storage subunit 110 is disposed close to the isolation trench 130 and the P-type drain 121 of the P-type storage subunit 120 is disposed close to the isolation trench 130 .

[0036] Thus, the control lead may include a common drain lead 141 connected to both the N-type drain 111 and the P-type drain 121 .

[0037] In some embodiments, the common drain lead 141 is connected to both the N-type drain 111 and the P-type drain 121. Figure 1 In the memory cell 100 shown, the memory cell 100 may further include a drain connection structure 150 that crosses the isolation trench 130 and connects the P-type drain 121 and the N-type drain 111. Thus, the common drain lead 141 may be electrically connected to the drain connection structure 150 to achieve simultaneous connection with the P-type drain 121 and the N-type drain 111.

[0038] In some embodiments, to simplify the internal structure, the drain connection structure 150 can be omitted by adjusting the width of the common drain lead 141. To further illustrate this situation, the present application also includes another structural schematic diagram of the memory cell ( Figure 2 ).like Figure 2 As shown, the common drain lead 141 has a certain width in the lateral direction, so as to cross the isolation trench 130 in the lateral direction and be connected to both the P-type drain 121 and the N-type drain 111 .

[0039] like Figure 1 As shown, the control leads may also include other leads of the N-type storage sub-unit 110 and the P-type storage sub-unit 120. Specifically, the control leads also include an N-type source lead 142 connected to the N-type source 112 of the N-type storage sub-unit 110, an N-type gate lead 143 connected to the N-type gate 113 of the N-type storage sub-unit 110, a P-type source lead 144 connected to the P-type source 122 of the P-type storage sub-unit 120, and a P-type gate lead 145 connected to the P-type gate 123 of the P-type storage sub-unit 120.

[0040] In addition, the control leads may also include an N-type substrate lead (not shown in the figure) connected to the doped substrate of the N-type storage subunit 110 and a P-type substrate lead (not shown in the figure) connected to the doped substrate of the P-type storage subunit 120. Figure 1In the following figures, the names in the structure will have a background color to avoid the influence of the structure shading on the name display. A shading will be set under some names. It should be noted that this shading does not mean that an additional structure needs to be set, but is only a display style for displaying clear text content.

[0041] Exemplary control method of storage device: In practical applications, the working state of the memory cell 100 can be controlled by controlling the voltage of each specific lead in the leads, thereby realizing operations such as data reading.

[0042] Specifically, based on the storage principle of the non-volatile MOSFET memory, the reading process of the N-type storage subunit 110 is as follows: When the driving voltage of the N-type gate lead 143 is consistent with (or greater than) the threshold voltage stored in the N-type storage sub-unit 110 and the storage unit 100 is in the N-type read state, the common drain lead 141 is connected to the N-type source lead 142. When a positive voltage is applied to the common drain lead 141 and a voltage greater than the common drain lead 141 is also applied to the P-type substrate lead, the storage unit 100 is in the N-type read state.

[0043] As an exemplary illustration only, when the memory cell 100 is in the N-type read state, the N-type source voltage (VsN), the N-type substrate voltage (VbN), the P-type gate voltage (VgP) and the P-type source voltage (VsP) are all 0. The drain voltage (VdN / VdP) = 1.1v < P-type substrate voltage (VbP) = 2.2v. At this time, if the N-type gate voltage (VgN) ≥ the threshold voltage, the N-type memory sub-unit 110 is turned on (i.e., the common drain lead 141 and the N-type source lead 142 are turned on).

[0044] Similar to the aforementioned N-type storage sub-unit 110, the reading process of the P-type storage sub-unit 120 is as follows: When the driving voltage of the P-type gate lead 145 is consistent with (or lower than) the threshold voltage stored in the P-type memory sub-unit 120 and the memory cell 100 is in the P-type read state, the common drain lead 141 is connected to the P-type source lead 144. When a negative voltage is applied to the common drain lead 141 and a voltage lower than the common drain lead 141 is also applied to the N-type substrate lead, the memory cell 100 is in the P-type read state.

[0045] As an exemplary illustration only, when the memory cell 100 is in the P-type read state, the N-type gate voltage (VgN), the N-type source voltage (VsN), the P-type source voltage (VsP) and the P-type substrate voltage (VbP) are all 0. The drain voltage (VdN / VdP) = -1.1v>N-type substrate voltage (VbN) = -2.2v. At this time, if the P-type gate voltage (VgP) ≤ the threshold voltage, the P-type memory subunit 120 is turned on (i.e., the common drain lead 141 and the P-type source lead 144 are turned on).

[0046] It should be noted that, unless otherwise specified in the present application, the voltage comparison is calculated with a sign, for example, -1.1v>-2.2v.

[0047] like Figure 1 As shown, both the N-type gate 113 and the P-type gate 123 include a stacked control gate and a floating gate, so the N-type storage subunit 110 and the P-type storage subunit 120 can also be used as erasable non-volatile MOSFET memories, thereby supporting writing and erasing of threshold voltages.

[0048] Based on the storage principle of erasable non-volatile MOSFET memory, the process of writing the threshold voltage of the N-type storage sub-unit 110 is as follows: When the driving voltage of the N-type gate lead 143 is the write voltage and the memory cell 100 is in the N-type write state, the floating gate of the N-type memory sub-unit 110 absorbs electrons to form a threshold voltage. The write voltage is generally a high voltage (such as 9.5V), and the N-type write state is similar to the aforementioned N-type read state, and both need to ensure that a positive voltage is applied to the common drain lead 141 and a voltage greater than the common drain lead 141 is also applied to the P-type substrate lead, but the specific voltage values ​​are different.

[0049] As an exemplary illustration only, when the memory cell 100 is in the N-type write state, the N-type source voltage (VsN), the N-type substrate voltage (VbN), the P-type gate voltage (VgP) and the P-type source voltage (VsP) are all 0. The drain voltage (VdN / VdP) = 3.8v < P-type substrate voltage (VbP) = 5.8v. At this time, if a high voltage (such as 9.5V) is applied to the N-type gate voltage (VgN), the floating gate of the N-type storage subunit 110 absorbs electrons and changes the threshold voltage to form a threshold voltage that needs to be memorized. Among them, the adjustment value of the threshold voltage is generally related to the time when the N-type gate voltage (VgN) applies a high voltage. The specific relationship can be determined by laboratory measurement to guide data writing in subsequent work.

[0050] Correspondingly, the process of writing the threshold voltage of the P-type storage sub-unit 120 is as follows: When the driving voltage of the P-type gate lead 145 is a write voltage and the memory cell 100 is in a P-type write state, the floating gate of the P-type memory sub-unit 120 absorbs holes to form a threshold voltage. Among them, the threshold voltage of the P-type memory sub-unit 120 is generally a negative value. The write voltage of the P-type gate lead 145 is generally a negative voltage with a large absolute value (such as -9.5V). The P-type write state is similar to the aforementioned P-type read state. It is necessary to ensure that a negative voltage is applied to the common drain lead 141 and a negative voltage less than the common drain lead 141 is also applied to the N-type substrate lead, but the specific voltage values ​​are different.

[0051] As an exemplary illustration only, when the memory cell 100 is in the P-type write state, the N-type gate voltage (VgN), the N-type source voltage (VsN), the P-type source voltage (VsP) and the P-type substrate voltage (VbP) are all 0. The drain voltage (VdN / VdP) = -3.8v> N-type substrate voltage (VbN) = -5.8v. At this time, if the P-type gate voltage (VgP) is applied with a negative voltage with a large absolute value (such as -9.5V), the floating gate of the P-type memory subunit 120 absorbs holes and changes the threshold voltage to form a threshold voltage that needs to be memorized.

[0052] Based on the storage principle of erasable non-volatile MOSFET memory, the process of erasing the threshold voltage of the N-type storage sub-unit 110 is as follows: When the driving voltage of the N-type gate lead 143 is the erasing voltage and the memory cell 100 is in the N-type erasing state, the floating gate of the N-type memory sub-unit 110 releases electrons and erases the threshold voltage. Wherein, when the memory cell 100 is in the N-type erasing state, the N-type source voltage (VsN), the N-type substrate voltage (VbN), and the drain voltage (VdN / VdP) are all greater than the maximum value of the threshold voltage value range, and the P-type substrate voltage (VbP) is greater than the drain voltage (VdN / VdP). At this time, the N-type gate voltage (VgN) is at a negative voltage, so that the floating gate releases electrons and erases the threshold voltage.

[0053] As an exemplary illustration, when the memory cell 100 is in the N-type erase state, the threshold voltage of the N-type memory sub-cell 110 is 0-6V, and the N-type source voltage (VsN) = the N-type substrate voltage (VbN) = the drain voltage (VdN / VdP) = 7.7V < the P-type substrate voltage (VbP) = 8.8V. At this time, the driving voltage of the N-type gate lead 143 (i.e., the N-type gate voltage (VgN)) = -8.1V, so that the floating gate releases electrons and erases the threshold voltage.

[0054] Similar to the process of erasing the threshold voltage of the N-type storage sub-unit 110, the process of erasing the threshold voltage of the P-type storage sub-unit 120 is as follows: When the driving voltage of the P-type gate lead 145 is the erasing voltage and the memory cell 100 is in the P-type erasing state, the floating gate of the P-type memory sub-unit 120 releases holes and erases the threshold voltage. When the memory cell 100 is in the P-type erasing state, the drain voltage (VdN / VdP), the P-type source voltage (VsP), and the P-type substrate voltage (VbP) are all less than the minimum value of the threshold voltage range, and the N-type substrate voltage (VbN) is less than the drain voltage (VdN / VdP).

[0055] As an exemplary illustration only, when the memory cell 100 is in the N-type erase state, when the threshold voltage of the P-type memory sub-cell 120 is 0-6V, the P-type source voltage (VsP) = the P-type substrate voltage (VbP) = the drain voltage (VdN / VdP) = -7.7V> the P-type substrate voltage (VbP) = -8.8V. At this time, the driving voltage of the P-type gate lead 145 (i.e., the P-type gate voltage (VgP)) = 8.1V, so that the floating gate releases holes and erases the threshold voltage.

[0056] In some embodiments, in actual applications, the aforementioned writing threshold voltage can be regarded as a process of increasing the absolute value of the threshold voltage value (making the threshold voltage further away from 0V), and erasing the threshold voltage can be regarded as a process of reducing the absolute value of the threshold voltage value (making the threshold voltage closer to 0V).

[0057] When the threshold voltage is actually adjusted, erasing may be performed first and then writing may be performed based on the aforementioned process. As an alternative, one of erasing and writing may also be selected directly based on the difference in the threshold voltage.

[0058] In some embodiments, the threshold voltage may be verified after writing / erasing is completed, and here, the memory cell 100 may be in a corresponding read state, and a scan voltage is applied to its gate to determine the actual threshold voltage.

[0059] Considering that the above process only illustrates that the memory subunit is turned on under the corresponding circumstances, when actually reading the threshold voltage, a scanning voltage may be applied to the gate starting from 0V, thereby determining the gate voltage when the memory subunit is turned on and recording it as the read threshold voltage.

[0060] For illustrative purposes only, the voltage values ​​of each state in the above process can be found in the following table: Based on the different control states of the aforementioned storage sub-units, the present application also provides a control method for each storage unit 100 in a storage device, which may specifically include a threshold voltage reading method ( Figure 3 ) and threshold voltage adjustment method ( Figure 4 ).

[0061] like Figure 3 As shown, process P300 may include the following steps: S310 , determining a target storage sub-unit from N-type storage sub-units and P-type storage sub-units.

[0062] S320, controlling the storage unit to be in a read state corresponding to the target storage sub-unit.

[0063] S330 , applying a scan voltage to the gate lead of the target memory sub-unit.

[0064] S340 , in response to the source and drain of the target memory sub-unit being turned on, determining the gate voltage at the turn-on moment and using it as the threshold voltage of the target memory sub-unit.

[0065] In the aforementioned S310, the target storage subunit may be a storage subunit for data reading. In practical applications, each storage subunit in a storage unit of the present application works independently, but only one storage subunit can be controlled at a time. Therefore, during the use of the storage device provided by the present application, the relevant device needs to first determine the target storage subunit to be controlled.

[0066] In some embodiments, the selection of each storage subunit can also be performed according to its actual properties. For storage tasks that require fast response, N-type storage subunits can be called. For storage tasks that do not require high speed but require high stability, P-type storage subunits can be called first.

[0067] After determining the target memory sub-unit, the voltage of the control lead can be adjusted to put the memory cell in a read state corresponding to the target memory sub-unit. The specific voltage application conditions can refer to the related description of the read state.

[0068] Based on the above content, it can be known that when the threshold voltage of the N-type storage sub-unit is positive and greater than the threshold voltage, the N-type storage sub-unit is turned on, and when the threshold voltage of the P-type storage sub-unit is negative and less than the threshold voltage, the P-type storage sub-unit is turned on. When performing voltage scanning, the scan can be started with 0V, and as the absolute value of the scan voltage gradually increases, when the corresponding target storage sub-unit is turned on, the gate voltage value at that moment is the threshold voltage.

[0069] like Figure 4 As shown, the threshold voltage adjustment process P400 may include the following steps: S410 , determining a target storage sub-unit from N-type storage sub-units and P-type storage sub-units.

[0070] S420 , determining a current threshold voltage of the target memory sub-unit.

[0071] S430 , determining a target operation and process parameters of the target operation from the write operation and the erase operation based on the expected threshold voltage and the current threshold voltage.

[0072] S440 , performing a target operation on a target storage subunit based on a process parameter of the target operation.

[0073] The aforementioned S410 is similar to the aforementioned S310, and will not be described in detail herein. The aforementioned S420 can be implemented based on the steps of the aforementioned P400.

[0074] As mentioned above, the aforementioned write threshold voltage can be understood as increasing the absolute value of the threshold voltage, and the erase threshold voltage can be understood as reducing the absolute value of the threshold voltage. After determining the expected threshold voltage, the voltage adjustment value (= expected threshold voltage - current threshold voltage) can be determined first. If it is positive, the absolute value of the threshold voltage needs to be increased, and a write operation can be used. If it is negative, the absolute value of the threshold voltage needs to be reduced, and an erase operation can be used.

[0075] Before the storage device is actually used, the influence of different process parameters (such as process duration) on the threshold voltage can be calibrated experimentally. Then, when executing the aforementioned S430, appropriate process parameters can be determined based on the specific value of the aforementioned voltage adjustment value, so as to perform the corresponding target operation so that the threshold voltage of the target storage sub-unit is adjusted from the current threshold voltage to the desired threshold voltage.

[0076] In some embodiments, after the aforementioned adjustment operation is performed, the threshold voltage may be detected again to determine whether the adjustment is completed. If the adjustment is not completed, the aforementioned P400 is re-executed until the threshold voltage is adjusted to the desired threshold voltage.

[0077] In some embodiments, the threshold voltage may also be adjusted by rewriting, that is, an erase operation may be performed on the target storage sub-unit first, and then a write operation may be performed based on the expected threshold voltage, so that the threshold voltage of the target storage sub-unit is the expected threshold voltage.

[0078] Exemplary method of preparing a memory device: In order to form a memory cell (such as memory cell 100) of the aforementioned memory device, the present application also provides a method for preparing the memory cell. Figure 5 to Figure 7 The preparation method of the storage unit is described. Figure 5 Flowchart reflecting the preparation method. Figure 6 The substrate being processed may be reflected. Figure 7 It can reflect the bottoming of the dielectric layer with leads.

[0079] like Figure 5 As shown, the process P500 of the preparation method may include the following steps: S510, providing a substrate.

[0080] S520, depositing a lead dielectric layer on the substrate.

[0081] S530, etching the lead dielectric layer to form a lead groove penetrating the lead dielectric layer.

[0082] S540 , filling the lead groove to form a control lead of the memory device.

[0083] The substrate in the aforementioned S510 may be provided with N-type storage sub-units, P-type storage sub-units and isolation trenches. Figure 6 As shown, an N-type memory sub-unit 110 , a P-type memory sub-unit 120 and an isolation trench 130 are disposed on a substrate 160 .

[0084] The substrate 160 may be treated by metal ion doping to form a P-type doped sink (ie, P-Well) at the N-type storage subunit 110 and an N-type doped sink (ie, N-Well) at the P-type storage subunit 120 .

[0085] The present application does not limit the method for preparing the substrate 160 , which can be implemented according to existing semiconductor (especially CMOS) preparation processes, as long as it can provide suitable N-type storage subunits 110 , P-type storage subunits 120 and isolation trenches 130 .

[0086] For example, two N-type lightly doped regions (NLDD) may be formed in the N-type storage subunit 110 of the substrate 160, and an N-type doped region (N+) may be formed on the N-type lightly doped region. The N-type doped region may serve as an N-type source and an N-type drain (the N-type drain is close to the isolation trench 130). Similarly, the P-type storage subunit 120 may form a P-type lightly doped region (PLDD) on the N-type substrate, and further be provided with a P-type doped region (P+). To further optimize the lead performance, a metal silicide layer (such as low-resistance NIPTSi2, abbreviated as NISI) layer can be formed on the surface of the area that needs to be connected to the lead to optimize the lead performance. Figure 6 In the embodiment, the source, drain and gate (i.e. control gate) surfaces can form NISI layers. The control gate can be formed of polysilicon and is recorded as a polycrystalline control gate.

[0087] In addition, an isolation layer formed of silicon nitride and oxide may be provided between the control gate and the floating gate and on the side of the control gate. Figure 6 The aforementioned structures (such as lightly doped regions, NISI, isolation layers, etc.) can be implemented based on existing technologies and will not be described in detail herein.

[0088] based on Figure 6 The substrate shown in the figure can be deposited with silicon oxide to form a lead dielectric layer. Considering the thickness of the lead dielectric layer, when forming the lead dielectric layer, chemical vapor deposition (such as deposition 200A) can be performed first, and then ILD deposition (such as deposition 2100A) can be performed. Considering Figure 5 The deposited surface shown is not flat and can be subjected to chemical mechanical polishing (CMP) after deposition to form a flat surface.

[0089] After the lead dielectric layer is deposited again, the lead positions in the lead dielectric layer can be etched to form lead grooves (such as Figure 7 ).like Figure 7 As shown, a lead dielectric layer 170 is formed on the substrate 160 , and a plurality of lead grooves 171 are formed in the lead dielectric layer 170 .

[0090] In particular, in the present application, considering the common drain design of the N-type storage sub-unit 110 and the P-type storage sub-unit 120 , the lead groove can form a trench that crosses the isolation trench 130 and leaks out the drain of the N-type storage sub-unit 110 and the P-type storage sub-unit 120 .

[0091] In some embodiments, considering that the connection between the drain of the N-type storage subunit 110 and the P-type storage subunit 120 can also be realized through a drain connection structure, the drain connection structure can be formed after the aforementioned S510, and then the subsequent steps are performed. At this time, the width of the lead corresponding to the drain connection structure can be determined based on conventional settings, without crossing the isolation trench.

[0092] In some embodiments, the aforementioned S530 can be performed through a mask layer. For example, 1900A of aC (diamond-like carbon film) can be deposited on the aforementioned lead dielectric layer, and then an anti-reflective coating (220A of ARC SION + 50A of oxide (OX)) can be deposited, and finally 200A of bottom anti-reflective coating (BARC) can be deposited, and finally 1000A of photoresist (PhotoResist) can be coated. Then, the photoresist is exposed and developed based on the lead position, so as to expose the surface to be etched (that is, the area is not coated with photoresist).

[0093] Based on the aforementioned mask layer, multiple etching steps can be performed to obtain the aforementioned Figure 7 The results are shown in Figure 2. The polymer remaining in the groove can be cleaned after etching.

[0094] based on Figure 7 The structure shown in FIG. 1 is executed by performing the aforementioned S540 to form a control lead to form Figure 2The storage unit shown. When forming the control lead, it is generally necessary to deposit metal on the lead groove 171 and grind the surface to form the corresponding lead. Specifically, 100A of titanium (TI) and 50A of titanium nitride (TIN) can be deposited first, then filled with tungsten (W), and chemical mechanical grinding can be performed to form the above Figure 2 The structure shown.

[0095] Based on the above process, each memory cell of the memory device provided by the present application can be formed, and a specific wire drawing and wiring process can be performed subsequently to prepare a corresponding memory chip. More details about the subsequent process will not be described here.

[0096] Example storage structure: To further optimize the performance of the memory cell, the present application also optimizes the specific structure of each specific memory sub-unit. Specifically, the floating gate in the aforementioned memory sub-unit can adopt an embedded structure and be embedded in the substrate, thereby increasing the contact area between the floating gate and the substrate and improving its ability to attract electrons / holes.

[0097] Therefore, the present application also provides a storage structure ( Figure 8 ), the aforementioned P-type storage sub-unit and N-type storage sub-unit can both adopt this design (the storage device adopting this design can be found in Fig.10 ) to increase the threshold voltage write / erase speed.

[0098] like Figure 8 As shown, the storage structure 200 may include a doped substrate 210, a source 220, a drain 230, a control gate 240, and a floating gate 250. The source 220 and the drain 230 are disposed at both ends of the doped substrate 210, and the control gate 240 is disposed between the source 220 and the drain 230. The floating gate 250 is disposed below the control gate 240 and embedded in the doped substrate 210, and the floating gate 250 includes at least two extensions 251, and the at least two extensions 251 extend into the substrate.

[0099] Among them, the aforementioned doped substrate 210, source 220 and drain 230 can be determined according to the actual type. If the aforementioned storage structure 200 is configured as a P-type storage subunit, the aforementioned doped substrate 210 can be an N-type doped substrate, and the source 220 and drain 230 can be constructed based on the P-type doped region on the surface of the N-type doped substrate. If the aforementioned storage structure 200 is configured as an N-type storage subunit, the aforementioned doped substrate 210 can be a P-type doped substrate, and the source 220 and drain 230 can be constructed based on the N-type doped region on the surface of the P-type doped substrate.

[0100] The aforementioned floating gate 250 embedded in the doped substrate 210 may refer to that at least a portion of the floating gate 250 is disposed in the doped substrate 210. Figure 8As shown, the extension 251 of the floating gate 250 may be completely disposed within the doped substrate 210 .

[0101] The extension portion 251 is generally presented as a filling structure of a trench in the doped substrate 210 , that is, to form the extension portion 251 , a plurality of trenches may be formed in the doped substrate 210 , thereby filling the trenches to form the floating gate 250 , and the filling structure corresponding to the trench in the floating gate 250 is recorded as the extension portion 251 .

[0102] When the floating gate 250 absorbs electrons / holes, the extension portion 251 and the doped substrate 210 may form a larger contact area, thereby improving the efficiency of the absorption process.

[0103] In some embodiments, in order to connect the at least two extensions 251, the floating gate 250 may further include a connection structure of the extensions 251. The connection structure may connect the extensions 251. Specifically, the connection structure may be disposed at various parts of the extensions 251 as required.

[0104] In some embodiments, in order to facilitate the correspondence with the control gate 240, the aforementioned connection structure may be disposed close to the control gate 240. That is, the floating gate 250 may further include a connection portion 252, which is disposed below the control gate 240 (i.e., close to the control gate 240 and away from the bottom surface of the doped substrate 210), and includes a driving surface 2521 facing the control gate 240 and an extension surface 2522 facing the substrate. At least two extension portions 251 extend from the extension surface 2522 toward the substrate (e.g., the bottom surface of the doped substrate 210) in a direction away from the connection portion 252.

[0105] In some embodiments, considering the properties of the control gate 240, its side and bottom surfaces should form an isolation structure. At the same time, considering that the control gate 240 is generally arranged above the doped substrate 210, its side surfaces are generally drain leads 231 and source leads 221. In order to ensure the electrical properties of the control gate 240, a first isolation layer 241 is arranged between the control gate 240 and the floating gate 250, and a second isolation layer 242 is arranged between the control gate 240 and the source lead 221. A second isolation layer 242 is arranged between the control gate 240 and the drain lead 231. Among them, the first isolation layer 241 and the second isolation layer 242 each include at least one oxide isolation layer (such as silicon oxide) and at least one silicon nitride isolation layer.

[0106] Exemplarily, the first isolation layer 241 includes a layer of silicon oxide and a layer of silicon nitride. The second isolation layer 242 includes three layers of silicon oxide and two layers of silicon nitride.

[0107] To further improve the anti-interference performance of the floating gate, the floating gate 250 can be completely embedded in the aforementioned doped substrate 210. To this end, the present application also provides a structural schematic diagram of another storage structure ( Fig. 9 ).

[0108] like Fig. 9 As shown, the connection portion 252 of the floating gate 250 is embedded in the doped substrate 210 , and the driving surface 2521 is flush with the substrate surface of the doped substrate 210 .

[0109] Thus, the floating gate 250 is completely sunk into the doped substrate 210 to store the signal. On the one hand, the anti-interference ability of the device is increased by burying the floating gate 250, and on the other hand, the contact area between the floating gate 250 and the doped substrate 210 is increased (such as the side of the connecting portion 252), and the signal can be written into the floating gate 250 from multiple dimensions, thereby increasing the writing speed. At the same time, the channel length of the semiconductor device is increased to avoid the short channel effect caused by the reduction of the device size due to the process advancement.

[0110] Alternatively, the aforementioned connection portion 252 may be further embedded in the doped substrate 210 , so that the first isolation layer or the control gate is embedded in the doped substrate 210 .

[0111] In some embodiments, the aforementioned Fig. 9 The storage structure shown can be combined with the aforementioned Figure 2 The memory device shown is combined, and the structure of the memory device at this time can be seen in Fig.10 .Right now Fig.10 In the example, the N-type gate of the N-type storage subunit and the P-type gate of the P-type storage subunit are both shown as Fig. 9 The combination of embedded floating gate and control gate is shown.

[0112] In some embodiments, the present application also provides a Fig. 9 The preparation method of the storage structure shown in FIG. Fig. 9 The storage structure shown can be achieved through the following steps: First, a substrate is provided and an isolation trench is formed on the substrate, wherein the substrate is generally a silicon substrate, and the isolation trench can be realized by etching a mask layer and filling with silicon oxide, which will not be described in detail here.

[0113] Next, the substrate is ion doped to form a doped substrate, wherein specific doping ions can be selected according to actual needs, and for the aforementioned combination of PMOS and NMOS, step-by-step doping can be performed based on a mask layer.

[0114] Next, the substrate is etched to form a first groove. Fig. 9 Corresponding to the connection part 252 in the figure, mask etching can also be used to achieve it.

[0115] Next, the first trench is etched to form at least two second trenches. Fig. 9The extension portion 251 in the figure corresponds to the first groove, which is formed on the basis of the aforementioned first groove and can also be implemented by mask etching.

[0116] Next, the first trench and the second trench are filled to form a floating gate. When filling the floating gate, a gate oxide layer (Gate Oxide) of about 23A can be formed first, and then polysilicon (poly) is deposited, and chemical mechanical polishing is performed.

[0117] Next, a control gate and a first isolation layer between the control gate and the floating gate are formed. When further performed, an isolation layer (a layer of silicon oxide and then a layer of silicon nitride) and polysilicon of the control gate can be deposited first. Then, mask etching is used to form the control gate and the first isolation layer.

[0118] Next, the source and drain can be formed. Specifically, the lightly doped region can be formed first and then the doped region can be formed. Among them, PLDD is generally achieved by sequentially injecting Ge, C, and AS (pockect) to a certain depth. NLDD is generally achieved by sequentially injecting Ge, C, and B (pockect) to a certain depth. The N+ region is mainly injected with P\GE\P\As\F to a certain depth. The P+ region is mainly injected with Ge\B\BF2 to a certain depth.

[0119] Next, a metal silicide layer (such as low-resistance NIPTSi2, abbreviated as NISI) is formed on the surface of the source, drain and control gate.

[0120] For follow-up, please refer to the above Figure 5 The preparation process is then followed by subsequent processing, which will not be described in detail here.

[0121] In some embodiments, the second isolation layer on the side of the control gate can be formed during the process of forming the source and drain. For example, a layer of silicon oxide can be formed on the side of the control gate first, and then a layer of silicon nitride can be formed on the side, and then the preparation process of the lightly doped region is performed, and after the preparation process is completed, a layer of silicon oxide and a layer of silicon nitride are formed on the side of the control gate, and in the subsequent wiring process, a layer of silicon oxide is formed (i.e., part of the dielectric material is retained on the side) to form the second isolation layer.

[0122] Technical effect: In summary, the memory device and the control method and manufacturing method thereof provided in the present application have the following unexpected effects: ① A storage unit of the storage device provided in the present application has two sub-units and is interconnected through a drain. By configuring different voltage signals, the threshold voltage stored in each sub-unit can be independently read so that each sub-unit has independent storage capacity, thereby improving the storage capacity of a single storage unit in the storage device and enabling the storage device to store more information.

[0123] ② The two sub-units in a memory cell can be a P-type memory sub-unit and an N-type memory sub-unit, respectively, forming a complementary semiconductor structure, thereby having better electrical performance and stability.

[0124] ③ Each storage sub-unit can be set based on the floating gate, so as to achieve non-volatile multiple compilations and different operating voltages. The operating voltage after writing can also be erased as needed.

[0125] ④ The aforementioned storage unit is provided with a P-type storage sub-unit and an N-type storage sub-unit, which have different storage effects for different data, so as to adapt to different storage requirements.

[0126] ⑤ The present application also optimizes the read, write and erase process of the storage unit, especially when the threshold voltage changes, an operation can be directly performed according to the adjusted threshold voltage, thereby improving the speed of the threshold voltage change process.

[0127] ⑥ The present application optimizes the floating gate structure so that the floating gate structure has multiple extensions extending toward the substrate, thereby increasing the contact area between the floating gate and the substrate and increasing the writing speed.

[0128] ⑦ The channel length of the semiconductor device is increased by setting the extension part, thereby avoiding the short channel effect caused by the reduction of device size due to process advancement.

[0129] ⑧ The floating gate of the present application can be completely sunk into the doped substrate to store signals. Thus, the anti-interference ability of the device is increased by burying the floating gate, and the contact area between the floating gate and the doped substrate is further increased (such as the side of the connection part). The signal can be written into the floating gate from multiple dimensions, thereby increasing the writing speed.

[0130] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A storage device, characterized in that: The storage device comprises a plurality of storage units, wherein the storage unit comprises: An N-type storage sub-unit is arranged on a first side of an isolation trench in the substrate and an N-type drain of the N-type storage sub-unit is close to the isolation trench; A P-type storage subunit is disposed on a second side of the isolation trench in the substrate and a P-type drain of the P-type storage subunit is close to the isolation trench; and Control leads, the control leads comprising a common drain lead connected to both the N-type drain and the P-type drain, an N-type source lead connected to the N-type source of the N-type storage sub-unit, an N-type gate lead connected to the N-type gate of the N-type storage sub-unit, a P-type source lead connected to the P-type source of the P-type storage sub-unit, and a P-type gate lead connected to the P-type gate of the P-type storage sub-unit.

2. The memory device according to claim 1, wherein: The N-type gate of the N-type storage sub-unit and the P-type gate of the P-type storage sub-unit both include: a control gate, wherein the control gate is electrically connected to the gate lead and is disposed between the source lead and the drain lead; and A floating gate is disposed below the control gate and embedded in the substrate, wherein the floating gate includes at least two extensions extending into the substrate.

3. The memory device according to claim 2, wherein: The floating gate further includes a connection portion, which is disposed below the control gate and includes a driving surface facing the control gate and an extension surface facing the substrate. The at least two extension portions extend from the extension surface toward the substrate in a direction away from the connection portion.

4. The memory device according to claim 3, wherein: The connecting portion is embedded in the substrate, so that the driving surface is flush with the substrate surface of the substrate.

5. The memory device according to claim 2, wherein: A first isolation layer is arranged between the control gate and the floating gate, a second isolation layer is arranged between the control gate and the source lead, and the second isolation layer is arranged between the control gate and the drain lead, wherein the first isolation layer and the second isolation layer each include at least one oxide isolation layer and at least one silicon nitride isolation layer.

6. The memory device according to claim 1, wherein: The memory device further includes a drain connection structure that crosses the isolation trench and connects the P-type drain and the N-type drain. The common drain lead is electrically connected to the drain connection structure and is connected to both the P-type drain and the N-type drain.

7. The memory device according to claim 1, wherein: The common drain lead laterally crosses the isolation trench and is connected to both the P-type drain and the N-type drain.

8. A method for controlling a storage device, characterized in that: Applied to the memory device according to any one of claims 1 to 7, the control method comprises a method for reading a threshold voltage from a target memory sub-unit in an N-type memory sub-unit and a P-type memory sub-unit of the memory cell, comprising: Controlling the storage unit to be in a read state corresponding to the target storage sub-unit; Applying a scan voltage to a gate lead of the target memory subunit; In response to the source and drain of the target memory sub-unit being turned on, an actual scan voltage at the turn-on moment is determined and used as the threshold voltage.

9. The control method according to claim 8, characterized in that: The control method further comprises: Determining a current threshold voltage of the target storage subunit; Determine a target operation and a process parameter of the target operation from a write operation and an erase operation based on the expected threshold voltage and the current threshold voltage; The target operation is performed on the target storage sub-unit based on the process parameters of the target operation.

10. A method for preparing a memory device, characterized in that: The preparation method comprises: A substrate is provided, wherein the substrate comprises an N-type storage sub-unit, a P-type storage sub-unit and an isolation trench, the N-type storage sub-unit and the P-type storage sub-unit are arranged on both sides of the isolation trench, the N-type drain of the N-type storage sub-unit is close to the isolation trench, and the P-type drain of the P-type storage sub-unit is close to the isolation trench; depositing a lead dielectric layer on the substrate; Etching the lead dielectric layer to form a lead groove penetrating the lead dielectric layer; The lead groove is filled to form a control lead of the storage device, wherein the control lead includes a common drain lead connected to both the N-type drain and the P-type drain, an N-type source lead connected to the N-type source of the N-type storage sub-unit, an N-type gate lead connected to the N-type gate of the N-type storage sub-unit, a P-type source lead connected to the P-type source of the P-type storage sub-unit, and a P-type gate lead connected to the P-type gate of the P-type storage sub-unit.

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