Preparation method of semiconductor device and semiconductor device

Abstract

The embodiment of the invention relates to a preparation method of a semiconductor device and the semiconductor device. Comprising the steps of forming a gate material layer and a sacrificial material layer on a semiconductor material layer; a through groove is formed in the sacrificial material layer, and the inner wall comprises a first extension part, a second extension part and a bending part; forming a mask material layer; the part, covering the inner wall of the through groove, of the etching mask material layer is reserved to form a side wall mask, the side wall mask comprises a first side wall part, a second side wall part and a side wall bending part, and the line width of the side wall bending part is larger than that of the first side wall part and that of the second side wall part; removing the sacrificial material layer; etching the grid material layer by taking the side wall mask as a mask to form a grid layer which comprises a first grid part, a second grid part and a grid bending part which are positioned below the first side wall part, the second side wall part and the side wall bending part; removing the side wall mask; forming a dielectric layer; forming a gate opening exposing the gate bending part in the dielectric layer; and forming a gate conductive connection structure in the gate opening.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a field effect transistor based on the high mobility characteristics of the two-dimensional electron gas (2DEG) in a heterojunction. It has high electron mobility under low temperature and low electric field, and can achieve high-speed and low-noise operation.

[0003] In conventional HEMT devices, both the source and drain terminals are N-type ohmic contacts. The entire device conducts electricity using a two-dimensional electron gas as a single effective carrier. The channel region is located below the gate. The line width of the gate determines the width of the channel and the size of the resistance under the gate, which in turn affects the conductivity of the device. In addition, the gate width will obviously affect the size of the device. In particular, at low voltage (voltage < 100V) platforms, the gate width has a huge impact on the conductivity and size of the device.

[0004] At present, the field generally adopts photolithography process to prepare gates, and the gate width is determined by the photolithography capability of the photolithography machine. When the gate width of the device needs to be set below 100nm, the traditional DUV (Deep Ultraviolet) photolithography machine cannot achieve it, and more advanced immersion photolithography machines or other more advanced photolithography technologies need to be used, but the process is more complicated and sophisticated, and the technical cost is higher. Summary of the invention

[0005] In view of this, embodiments of the present application provide a method for preparing a semiconductor device and a semiconductor device to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor device, the method comprising:

[0007] forming a gate material layer on the semiconductor material layer;

[0008] forming a sacrificial material layer on the gate material layer;

[0009] A through groove exposing the gate material layer is formed in the sacrificial material layer, wherein the inner wall of the through groove comprises a first extension portion, a second extension portion, and a bending portion connecting the first extension portion and the second extension portion, extending in a direction parallel to the plane where the semiconductor material layer is located;

[0010] forming a mask material layer on the sacrificial material layer and the exposed gate material layer;

[0011] Etching the mask material layer, a portion of the mask material layer covering the inner wall of the through groove is retained to form a sidewall mask, the sidewall mask comprising a first sidewall portion covering the first extension portion, a second sidewall portion covering the second extension portion, and a sidewall bending portion covering the bending portion, the line width of the sidewall bending portion being greater than the line width of the first sidewall portion and the line width of the second sidewall portion;

[0012] removing the sacrificial material layer;

[0013] Etching the gate material layer using the sidewall mask as a mask to form a gate layer, wherein the gate layer includes a first gate portion, a second gate portion, and a gate bending portion, which are respectively located directly below the first sidewall portion, the second sidewall portion, and the sidewall bending portion;

[0014] removing the sidewall mask;

[0015] forming a dielectric layer covering the semiconductor material layer and the gate layer;

[0016] forming a gate opening in the dielectric layer to expose the gate bending portion;

[0017] A gate conductive connection structure is formed in the gate opening, and the gate conductive connection structure is in direct contact with the gate bending portion.

[0018] In combination with the first aspect of the present application, in an optional implementation, the semiconductor material layer includes a substrate and a semiconductor epitaxial stack located on the substrate, and at least a portion of the semiconductor epitaxial stack is used to form a two-dimensional electron gas channel;

[0019] The gate layer is a P-type gate layer.

[0020] In combination with the first aspect of the present application, in an optional implementation, the line width of the gate conductive connection structure is greater than the line width of the first gate portion and the line width of the second gate portion.

[0021] In conjunction with the first aspect of the present application, in an optional implementation manner, the method further includes:

[0022] Forming a drain opening and a source opening in the dielectric layer to expose the semiconductor material layer, wherein the drain opening includes a first drain opening and a second drain opening;

[0023] forming a first drain conductive connection structure, a second drain conductive connection structure and a source conductive connection structure in the first drain opening, the second drain opening and the source opening respectively;

[0024] Among them, the source conductive connection structure is located between the first gate part and the second gate part, the first drain conductive connection structure is located on the side of the first gate part away from the second gate part, and the second drain conductive connection structure is located on the side of the second gate part away from the first gate part.

[0025] In combination with the first aspect of the present application, in an optional implementation manner, the drain opening further includes a third drain opening and a fourth drain opening, and the third drain opening and the fourth drain opening respectively connect two ends of the first drain opening and the second drain opening;

[0026] The method further includes: forming a third drain conductive connection structure and a fourth drain conductive connection structure in the third drain opening and the fourth drain opening, respectively, wherein the first drain conductive connection structure, the third drain conductive connection structure, the second drain conductive connection structure and the fourth drain conductive connection structure are connected in a ring shape;

[0027] Along the direction perpendicular to the plane where the semiconductor material layer is located, the projection of the gate layer is ring-shaped, the projection of the source conductive connection structure is surrounded by the projection of the gate layer, and the projection of the gate layer is surrounded by the projection of the drain conductive connection structure.

[0028] In conjunction with the first aspect of the present application, in an optional implementation manner, the bending portion includes one of the following:

[0029] an arc-shaped bending portion connected between one end of the first extension portion and one end of the second extension portion;

[0030] A first sub-bending portion connected to one end of the first extending portion, and a second sub-bending portion connected between one end of the second extending portion and the first sub-bending portion, wherein an angle between the first sub-bending portion and the second sub-bending portion is less than or equal to 90 degrees;

[0031] A first sub-bend portion connected to one end of the first extension portion, a second sub-bend portion connected to one end of the second extension portion, and a third sub-bend portion connected between the first sub-bend portion and the second sub-bend portion, wherein the angle between the first sub-bend portion and the second sub-bend portion is less than or equal to 90 degrees, and the length of the third sub-bend portion is less than the length of the first sub-bend portion and less than the length of the second sub-bend portion;

[0032] A first sub-bending portion connected to one end of the first extension portion, a second sub-bending portion connected to one end of the second extension portion, a fourth sub-bending portion, a third sub-bending portion and a fifth sub-bending portion connected in sequence between the first sub-bending portion and the second sub-bending portion, wherein a spacing between the fourth sub-bending portion and the fifth sub-bending portion is greater than or equal to 100nm and less than or equal to 200nm.

[0033] In a second aspect, an embodiment of the present application provides a semiconductor device, including:

[0034] a semiconductor material layer;

[0035] a gate layer, located on the semiconductor material layer, the gate layer comprising a first gate portion and a second gate portion extending in a direction parallel to the plane where the semiconductor material layer is located, and a gate bending portion connecting the first gate portion and the second gate portion, the line width of the first gate portion and the line width of the second gate portion are both less than 100 nm, and the line width of the gate bending portion is greater than 100 nm;

[0036] a dielectric layer, covering the semiconductor material layer and the gate layer, wherein a gate opening exposing the gate bending portion is formed in the dielectric layer;

[0037] The gate conductive connection structure is located in the gate opening and directly contacts the gate bending portion.

[0038] In conjunction with the second aspect of the present application, in an optional implementation, the semiconductor material layer includes a substrate and a semiconductor epitaxial stack located on the substrate, and at least a portion of the semiconductor epitaxial stack is used to form a two-dimensional electron gas channel;

[0039] The gate layer is a P-type gate layer.

[0040] In combination with the second aspect of the present application, in an optional implementation, the line width of the gate conductive connection structure is greater than 100 nm and less than or equal to the line width of the gate bending portion.

[0041] In combination with the second aspect of the present application, in an optional implementation manner, a drain opening and a source opening exposing the semiconductor material layer are further formed in the dielectric layer, and the drain opening includes a first drain opening and a second drain opening;

[0042] The semiconductor device further comprises: a first drain conductive connection structure, a second drain conductive connection structure and a source conductive connection structure respectively located in the first drain opening, the second drain opening and the source opening;

[0043] Among them, the source conductive connection structure is located between the first gate part and the second gate part, the first drain conductive connection structure is located on the side of the first gate part away from the second gate part, and the second drain conductive connection structure is located on the side of the second gate part away from the first gate part.

[0044] In conjunction with the second aspect of the present application, in an optional implementation manner, the drain opening further includes a third drain opening and a fourth drain opening, and the third drain opening and the fourth drain opening respectively connect two ends of the first drain opening and the second drain opening;

[0045] A third drain conductive connection structure and a fourth drain conductive connection structure are formed in the third drain opening and the fourth drain opening, respectively, and the first drain conductive connection structure, the third drain conductive connection structure, the second drain conductive connection structure and the fourth drain conductive connection structure are connected to form a ring shape;

[0046] Along the direction perpendicular to the plane where the semiconductor material layer is located, the projection of the gate layer is ring-shaped, the projection of the source conductive connection structure is surrounded by the projection of the gate layer, and the projection of the gate layer is surrounded by the projection of the drain conductive connection structure.

[0047] In conjunction with the second aspect of the present application, in an optional implementation manner, the gate bending portion includes one of the following:

[0048] A gate bending portion having an arc-shaped outer wall profile connected between one end of the first gate portion and one end of the second gate portion;

[0049] A first sub-gate bent portion connected to one end of the first gate portion, a second sub-gate bent portion connected between one end of the second gate portion and the first sub-gate bent portion, wherein an angle between an outer side wall of the first sub-gate bent portion and an outer side wall of the second sub-gate bent portion is less than or equal to 90 degrees;

[0050] A first sub-gate bent portion connected to one end of the first gate portion, a second sub-gate bent portion connected to one end of the second gate portion, and a third sub-gate bent portion connected between the first sub-gate bent portion and the second sub-gate bent portion, wherein an angle between an outer side wall of the first sub-gate bent portion and an outer side wall of the second sub-gate bent portion is less than or equal to 90 degrees, and in a direction parallel to the plane where the semiconductor material layer is located, an extension length of the outer side wall of the third sub-gate bent portion is less than an extension length of the outer side wall of the first sub-gate bent portion and less than an extension length of the outer side wall of the second sub-gate bent portion;

[0051] A first sub-gate bending portion connected to one end of the first gate portion, a second sub-gate bending portion connected to one end of the second gate portion, and a third sub-gate bending portion connected between the first sub-gate bending portion and the second sub-gate bending portion, wherein in a direction parallel to the plane where the semiconductor material layer is located, the outer side wall of the third sub-gate bending portion includes a first sub-outer side wall, a second sub-outer side wall and a third sub-outer side wall connected in sequence, and a spacing between the first sub-outer side wall and the third sub-outer side wall is greater than or equal to 100nm and less than or equal to 200nm.

[0052] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0053] On the one hand, the method for preparing a semiconductor device provided in an embodiment of the present application prepares a mask for etching the gate material layer through a double patterning process of forming a through groove in a sacrificial material layer on the gate material layer and forming and etching a mask material layer, and determines the line width of the gate layer by using a sidewall mask covering the inner wall of the through groove, breaking through the lithography limit of a single patterning process for preparing a patterned photoresist layer by a traditional photolithography process, which is conducive to realizing the preparation of a small line width gate layer, reducing the channel resistance, improving the conductive performance of the device, and reducing the area of ​​the device; on this basis, the inner wall of the through groove is set to extend in a direction parallel to the plane where the semiconductor material layer is located. The first extension part, the second extension part and the bent part connecting the first extension part and the second extension part, compared with the flat plane, the mask material is more likely to accumulate at the corners or bends, and the etching difficulty at the corners or bends is higher, so the line width of the side wall bent part obtained by the process is larger than the line width of the first side wall part and the line width of the second side wall part, and then the line width of the gate bent part is larger than the line width of the first gate part and the line width of the second gate part, so that the dielectric layer is etched at the gate bent part with a larger line width to form a gate opening, thereby reducing the process difficulty and solving the problem of gate conductive lead-out after forming a small line width gate layer.

[0054] On the other hand, in the semiconductor device provided by the embodiment of the present application, the line width of the first gate portion and the line width of the second gate portion are both less than 100nm, that is, less than the line width limit that can be prepared by a traditional photolithography machine, thereby adopting a small line width gate layer to reduce the channel resistance, improve the conductivity of the device, and reduce the area, thereby obtaining a small gate width and high current semiconductor device; on this basis, since the gate layer is provided to include a first gate portion and a second gate portion extending in a direction parallel to the plane where the semiconductor material layer is located, and a gate bend portion connecting the first gate portion and the second gate portion, and the line width of the gate bend portion is greater than 100nm, the gate opening is provided in the dielectric layer at the gate bend portion, thereby solving the problem of gate conductive lead-out after the formation of a small line width gate layer.

[0055] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0057] Figure 1 A schematic diagram of a process for preparing a semiconductor device according to an embodiment of the present application;

[0058] Figures 2 to 15 A schematic diagram of the cross-sectional structure of a semiconductor device during the preparation process provided by an embodiment of the present application;

[0059] Fig.16 for Figure 6 A layout of the structure shown;

[0060] Fig.17 for Figure 7 A layout of the structure shown;

[0061] Fig.18 for Figure 8 A layout of the structure shown;

[0062] Fig.19 for Fig. 9 A layout of the structure shown;

[0063] Fig. 20 for Fig.11 A layout of the structure shown;

[0064] Fig.21 In an optional specific implementation Fig.13 A layout of the structure shown;

[0065] Fig. 22 In another optional specific implementation Fig.13 A layout of the structure shown;

[0066] Fig.23 for Fig.21 A schematic diagram of the cross-sectional structure of the structure shown on the AA section;

[0067] Fig.24 for Figure 6 A variation of the layout of the structure shown;

[0068] Fig.25 for Fig.11 A variation of the layout of the structure shown;

[0069] Fig.26 for Figure 6 Another variation of the layout of the structure shown;

[0070] Fig. 27 for Fig.11 Another variation of the layout of the structure shown;

[0071] Fig.28 for Figure 6 Another variation of the layout of the structure shown;

[0072] Fig.29 for Fig.11 Yet another variation of the layout of the structure shown.

[0073] Description of reference numerals:

[0074] 100, substrate; 110, nucleation layer; 120, buffer layer; 130, semiconductor epitaxial stack; 131, channel layer; 132, barrier layer; 140, gate material layer; 141, gate layer; 1411, first gate portion; 1412, second gate portion; 1413, gate bending portion; 1401, first sub-gate bending portion; 1402, second sub-gate bending portion; 1403, third sub-gate bending portion bend; 150, patterned first photoresist layer; 160, sacrificial material layer; 161, through groove; 1611, first extension; 1612, second extension; 1613, bend; 1601, first sub-bend; 1602, second sub-bend; 1603, third sub-bend; 1604, fourth sub-bend; 1605, fifth sub-bend; 170, mask material layer; 171, side Wall mask; 1711, first side wall portion; 1712, second side wall portion; 1713, side wall bending portion; 180, dielectric layer; 181, gate opening; 182, drain opening; 1821, first drain opening; 1822, second drain opening; 1823, third drain opening; 1824, fourth drain opening; 190, ohmic contact layer; 200, gate conductive connection structure; 210, drain conductive connection structure; 211, first drain conductive connection structure; 212, second drain conductive connection structure; 213, third drain conductive connection structure; 214, fourth drain conductive connection structure; 220, source conductive connection structure; 300, interlayer dielectric layer; 310, drain conductive plug; 320, source conductive plug; 400, protective layer; 410, source conductive layer; 420, drain conductive layer. DETAILED DESCRIPTION

[0075] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0076] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0077] Figure 1 A schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application is shown in the figure. The method comprises:

[0078] Step S101: forming a gate material layer on the semiconductor material layer;

[0079] Step S102: forming a sacrificial material layer on the gate material layer;

[0080] Step S103: forming a through groove in the sacrificial material layer to expose the gate material layer, wherein the inner wall of the through groove includes a first extension portion, a second extension portion, and a bending portion connecting the first extension portion and the second extension portion, extending in a direction parallel to the plane where the semiconductor material layer is located;

[0081] Step S104: forming a mask material layer on the sacrificial material layer and the exposed gate material layer;

[0082] Step S105: etching the mask material layer, wherein a portion of the mask material layer covering the inner wall of the through groove is retained to form a sidewall mask, wherein the sidewall mask comprises a first sidewall portion covering the first extension portion, a second sidewall portion covering the second extension portion, and a sidewall bending portion covering the bending portion, wherein a line width of the sidewall bending portion is greater than a line width of the first sidewall portion and a line width of the second sidewall portion;

[0083] Step S106: removing the sacrificial material layer;

[0084] Step S107: etching the gate material layer using the spacer mask as a mask to form a gate layer, wherein the gate layer includes a first gate portion, a second gate portion, and a gate bending portion, which are respectively located directly below the first spacer portion, the second spacer portion, and the spacer bending portion;

[0085] Step S108: removing the sidewall mask;

[0086] Step S109: forming a dielectric layer covering the semiconductor material layer and the gate layer;

[0087] Step S110: forming a gate opening in the dielectric layer to expose the gate bending portion;

[0088] Step S111: forming a gate conductive connection structure in the gate opening, wherein the gate conductive connection structure is in direct contact with the gate bending portion.

[0089] Therefore, the embodiment of the present application prepares a mask for etching the gate material layer through a double patterning process of forming a through groove in a sacrificial material layer on the gate material layer and forming and etching the mask material layer, and uses a sidewall mask covering the inner wall of the through groove to determine the line width of the gate layer, breaking through the lithography limit of a single patterning process of preparing a patterned photoresist layer by a traditional photolithography process, which is conducive to realizing the preparation of a small line width gate layer, reducing the channel resistance, improving the conductive performance of the device, and reducing the area of ​​the device; on this basis, the inner wall of the through groove is set to a first extension portion extending in a direction parallel to the plane where the semiconductor material layer is located, The second extension portion and the bent portion connecting the first extension portion and the second extension portion, compared with a flat plane, the mask material is more likely to accumulate at corners or bends, and the etching difficulty at corners or bends is higher, so the line width of the side wall bent portion obtained by the process is greater than the line width of the first side wall portion and the line width of the second side wall portion, and then the line width of the gate bent portion is made greater than the line width of the first gate portion and the line width of the second gate portion, so that the dielectric layer is etched at the gate bent portion with a larger line width to form a gate opening, thereby reducing the process difficulty and solving the problem of gate conductive lead-out after forming a small line width gate layer.

[0090] Please refer to Figure 2 , executing step S101: forming a gate material layer 140 on the semiconductor material layer.

[0091] Optionally, the semiconductor material layer includes a substrate 100 and a semiconductor epitaxial stack 130 located on the substrate 100, at least a portion of the semiconductor epitaxial stack 130 is used to form a two-dimensional electron gas channel; the gate layer is a P-type gate layer. Thus, a high electron mobility transistor (HEMT) can be formed.

[0092] In actual preparation, a substrate 100 may be provided first, and a semiconductor epitaxial stack 130 may be epitaxially grown on the substrate 100 .

[0093] The material of the substrate 100 may be any suitable material known to those skilled in the art, such as a silicon (Si) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a sapphire substrate.

[0094] The material of the semiconductor epitaxial stack 130 includes a gallium nitride-based semiconductor material, and the semiconductor epitaxial stack 130 may include a channel layer 131 and a barrier layer 132 stacked in a direction away from the substrate. Epitaxially growing the semiconductor epitaxial stack 130 on the substrate 100 may specifically include: epitaxially growing the channel layer 131 on the substrate 100; and epitaxially growing the barrier layer 132 on the channel layer 131. The channel layer 131 and the barrier layer 132 together form a heterojunction structure, thereby inducing a two-dimensional electron gas in a region of the channel layer 131 close to the barrier layer 132.

[0095] The material of the channel layer 131 may be an N-group alloy material, including but not limited to GaN, AlGaN, InGaN, InAlGaN, InAlScN, AlScN, InScN, etc. Further, the channel layer 131 may be an undoped material layer (e.g., an undoped GaN layer), so that at least the portion of the channel layer 131 below the two-dimensional electron gas presents a high resistance.

[0096] The material of the barrier layer 132 includes any material that can form a two-dimensional electron gas channel with the channel layer 131. Specifically, the material of the barrier layer 132 can also be an N-group alloy material, such as a gallium nitride-based alloy, specifically, for example, one or more of AlGaN, AlScN, InAlGaN and the like. Further, the material of the barrier layer 132 can be an undoped material (e.g., an undoped AlGaN layer); or, the barrier layer 132 can also be an N-doped material layer (e.g., an N-type doped AlGaN layer), so as to facilitate inducing a higher density of two-dimensional electron gas.

[0097] In a specific example, the material of the channel layer 131 includes GaN, and the material of the barrier layer 132 includes AlGaN. GaN and AlGaN form a heterojunction structure.

[0098] Please refer to Fig.10 A two-dimensional electron gas channel 133 is formed in at least a portion of the channel layer 131 in a region close to the barrier layer 132. Specifically, the band gap width of the barrier layer 132 is greater than the band gap width of the channel layer 131, so that the electrons in the barrier layer 132 with a wide band gap and the electrons on the surface of the barrier layer 132 overflow and move to the interface of the channel layer 131 close to the barrier layer 132 and are confined in the potential well formed at the interface, thereby forming a two-dimensional electron gas (2DEG).

[0099] Optionally, before growing the channel layer 131, the nucleation layer 110 and the buffer layer 120 may be epitaxially grown in sequence on the substrate 100, thereby releasing the interface stress, reducing the defect density, improving the film quality of the subsequent semiconductor material layer, reducing the static current leakage of the device, and improving the device performance.

[0100] In addition, those skilled in the art can directly use the purchased epitaxial wafer with the semiconductor epitaxial stack 130 to perform the subsequent process steps. In this case, it should be understood that the process necessarily includes the step of epitaxially growing the semiconductor epitaxial stack 130 .

[0101] The gate material layer 140 may be a P-type gate material layer. Fig.10 , the two-dimensional electron gas channel under the gate layer is depleted and serves as a channel region. Further, the material of the gate material layer 140 may include a P-type oxide or a P-type nitride. In a specific example, the material of the gate material layer 140 may include NiO or CuO; or, the material of the gate material layer 140 may include p-type doped GaN.

[0102] The process of forming the gate material layer 140 on the semiconductor material layer may include a deposition process. Specifically, step S101 may include: depositing the gate material layer 140 on the semiconductor epitaxial stack 130. It should be noted that although Figure 2 The gate material layer 140 is shown as not being in direct contact with the channel layer 131 (for example, being located on the barrier layer 132), but the present application does not exclude the gate material layer 140 being in direct contact with the channel layer 131. In some embodiments, the material of the gate material layer 140 may include NiO; step S101 may also include: etching the barrier layer 132 to form a groove (not shown in the figure) exposing the channel layer 131; and forming the gate material layer 140 in the groove. Thus, the gate material layer 140 is in direct contact with the channel layer 131. Those skilled in the art may adopt various deformations to set the gate material layer 140 without departing from the improved concept of the present application.

[0103] Please refer to Figure 3 and Figure 4 After executing step S101, the preparation method may further include: forming a patterned first photoresist layer 150 on the gate material layer 140; performing step etching using the patterned first photoresist layer 150 as a mask to define an active area of ​​the device; and removing the patterned first photoresist layer 150.

[0104] Please refer to Figure 5 , executing step S102 : forming a sacrificial material layer 160 on the gate material layer 140 .

[0105] The material of the sacrificial material layer 160 may include nitride. Further, the material of the sacrificial material layer 160 may include SiN and / or AlN.

[0106] The process of forming the sacrificial material layer 160 may include a deposition process.

[0107] Please refer to Figure 6 and Fig.16, Fig.16 for Figure 6 The layout of the structure shown, Figure 6 for Fig.16 The schematic diagram of the cross-sectional structure of the structure shown in the AA cross section, performing step S103: forming a through groove 161 exposing the gate material layer 140 in the sacrificial material layer 160, the inner wall of the through groove 161 includes a first extension portion 1611 extending in a direction parallel to the plane where the semiconductor material layer is located, a second extension portion 1612, and a bending portion 1613 connecting the first extension portion 1611 and the second extension portion 1612. Thus, the position of the sidewall mask formed in the subsequent process is defined by the through groove 161, so that the position of the sidewall mask is self-aligned, and no additional alignment steps are required, thereby reducing the process difficulty. Since the inner wall of the through groove 161 includes the first extension portion 1611 and the second extension portion 1612 extending in a direction parallel to the plane where the semiconductor material layer is located, in the subsequent steps, the corresponding first sidewall portion and the second sidewall portion can be formed on the inner wall, thereby obtaining the first gate portion and the second gate portion, and the preparation of the two gate portions is completed simultaneously, thereby improving the production efficiency. The first extension portion 1611 and the second extension portion 1612 may specifically be inner walls of the through groove 161 on both sides opposite to each other. The first extension portion 1611 and the second extension portion 1612 may be arranged in parallel, or be diagonally arranged at an angle within 30 degrees. The inner wall of the through groove 161 also includes a bending portion 1613 connecting the first extension portion 1611 and the second extension portion 1612. It is not difficult to understand that compared with a flat surface, the mask material is more likely to accumulate at a corner or a bend, and the etching difficulty at a corner or a bend is higher, thereby making the line width of the side wall bending portion obtained by subsequent etching larger than the line width of the first side wall portion and the line width of the second side wall portion, and then making the line width of the gate bending portion larger than the line width of the first gate portion and the line width of the second gate portion, so that the dielectric layer is etched at the gate bending portion with a larger line width to form a gate opening.

[0108] The process of forming the through groove 161 may include a photolithography-etching process. Specifically, forming the through groove 161 exposing the gate material layer 140 in the sacrificial material layer 160 may include: forming a second photoresist layer (not shown in the figure) on the sacrificial material layer 160; performing a photolithography process, exposing and developing the second photoresist layer to form a patterned second photoresist layer; using the patterned second photoresist layer as a mask, etching the sacrificial material layer 160 to form the through groove 161 exposing the gate material layer 140 in the sacrificial material layer 160. The size of the through groove 161 is relatively large, and when the second photoresist layer is exposed, the process requirements are low, so a conventional photolithography machine can be used to perform a conventional photolithography process, reducing the process difficulty and process cost. In actual preparation, a DUV photolithography machine can be used to perform the photolithography process.

[0109] In some embodiments, the first extension portion 1611 extends along a straight line; and / or the second extension portion 1612 extends along a straight line, which is helpful to reduce the process difficulty and reduce the process error.

[0110] In some embodiments, the bent portion includes an arc-shaped bent portion 1613 connected between one end of the first extension portion 1611 and one end of the second extension portion 1612. Therefore, the side of the sidewall bent portion prepared in the subsequent process away from the bent portion can also be arc-shaped, and the sidewall bent portion is fan-shaped, which in turn makes the gate bent portion also fan-shaped. Specifically, the bent portion 1613 extends in a direction away from the first extension portion 1611 and the second extension portion 1612.

[0111] In other embodiments, in order to facilitate the formation of the gate bending portion and thus better solve the problem of gate conductive extraction, the bending portion 1613 may also include a variety of other shapes, which will be further described below.

[0112] Optionally, the bending portion 1613 includes a first bending portion and a second bending portion; one end of the first extension portion 1611 and one end of the second extension portion 1612 are connected via the first bending portion, and the other end of the first extension portion 1611 and the other end of the second extension portion 1612 are connected via the second bending portion. Further, the first bending portion and the second bending portion are symmetrically arranged.

[0113] Please refer to Figure 7 and Fig.17 , Fig.17 for Figure 7 The layout of the structure shown, Figure 7 for Fig.17 The structure shown is a schematic cross-sectional structure diagram on the AA cross section, and step S104 is performed: a mask material layer 170 is formed on the sacrificial material layer 160 and the exposed gate material layer 140 .

[0114] The process of forming the mask material layer 170 may include a deposition process. It is easy to understand that during the deposition process, compared with the relatively flat surface of the first extension portion 1611 and the second extension portion 1612 , the material is more likely to accumulate at the bent portion 1613 .

[0115] The material of the mask material layer 170 may include nitride. Further, the material of the mask material layer 170 may include AlN.

[0116] Please refer to Figure 8 and Fig.18 , Fig.18 for Figure 8 The layout of the structure shown, Figure 8 for Fig.18The structure shown is a schematic diagram of the cross-sectional structure on the AA cross-section, executing step S105: etching the mask material layer 170, the portion of the mask material layer 170 covering the inner wall of the through groove 161 is retained to form a side wall mask 171, the side wall mask 171 includes a first side wall portion 1711 covering the first extension portion 1611, a second side wall portion 1712 covering the second extension portion 1612, and a side wall bending portion 1713 covering the bending portion 1613, and the line width of the side wall bending portion 1713 is greater than the line width of the first side wall portion 1711 and the line width of the second side wall portion 1712.

[0117] Understandably, please combine Figure 7 and Fig.17 When etching the mask material layer 170, the mask material at the corners or bends is more protected by the inner wall, and the etching difficulty is higher. The portion of the mask material layer 170 close to the first extension portion 1611 and the second extension portion 1612 is etched more, and the portion close to the bend portion 1613 is etched less, so that the line width of the sidewall bend portion 1713 is greater than the line width of the first sidewall portion 1711 and the line width of the second sidewall portion 1712 (such as Fig.18 shown).

[0118] It should be noted that, in the case where the widths of the upper and lower parts of the structure are different along the thickness direction of the semiconductor material layer, the line width refers to the width of its narrowest part.

[0119] Since the first extension portion 1611 and the second extension portion 1612 are connected via the bending portion 1613, the first sidewall portion 1711 and the second sidewall portion 1712 are also connected via the sidewall bending portion 1713. In some embodiments, the bending portion 1613 includes a first bending portion and a second bending portion; one end of the first extension portion 1611 and one end of the second extension portion 1612 are connected via the first bending portion, and the other end of the first extension portion 1611 and the other end of the second extension portion 1612 are connected via the second bending portion; the sidewall bending portion 1713 covers the first bending portion and / or the second bending portion. Fig.18 As shown, when the side wall bending portion 1713 covers the first bending portion and the second bending portion, one end of the first gate portion and one end of the second gate portion formed in the subsequent process are connected through the gate bending portion, and the other end of the first gate portion and the other end of the second gate portion are connected through the gate bending portion. After the device is turned on, more channels can be provided, which is beneficial to improving device performance.

[0120] Understandably, although Fig.18The figure shows the situation where both ends of the first side wall portion 1711 and the second side wall portion 1712 are connected by the side wall bending portion 1713, but the embodiment of the present application does not exclude the situation where one end of the first side wall portion 1711 and the second side wall portion 1712 is connected by the side wall bending portion 1713 while the other end is not connected, which makes the device layout smaller, saves the gate layer's occupation of the wafer area, and is conducive to reducing the device size.

[0121] The process of etching the mask material layer 170 may include a wet etching process or a dry etching process, which is not limited in this embodiment.

[0122] Please refer to Fig. 9 and Fig.19 , Fig.19 for Fig. 9 The layout of the structure shown, Fig. 9 for Fig.19 The structure shown is a schematic diagram of the cross-sectional structure on the AA cross section, and step S106 is performed: removing the sacrificial material layer 160. In actual preparation, an etching solution with a high etching selectivity ratio for the sacrificial material layer 160 and the sidewall mask 171 can be selected to remove the sacrificial material layer 160 by a wet etching process.

[0123] It can be understood that by removing the sacrificial material layer 160, only the spacer mask 171 is retained on the gate material layer 140, and the pattern of the spacer mask 171 is the same as the pattern of the gate layer to be formed later. The line width of the gate layer is determined by the spacer mask 171, which greatly breaks through the physical limit that traditional photolithography cannot reach.

[0124] Please refer to Fig.10 , Fig.11 and Fig. 20 , Fig. 20 for Fig.11 The layout of the structure shown, Fig.11 for Fig. 20 The schematic diagram of the cross-sectional structure of the structure shown in the AA cross section, performing step S107: etching the gate material layer 140 with the spacer mask 171 as a mask to form a gate layer 141, the gate layer 141 includes a first gate portion 1411, a second gate portion 1412 and a gate bending portion 1413 respectively located directly below the first spacer portion 1711, the second spacer portion 1712 and the spacer bending portion 1713. Thus, the preparation of the small line width gate layer 141 is achieved, the channel resistance is reduced, the conductive performance of the device is improved, and the area of ​​the device is reduced.

[0125] Execute step S108: remove the spacer mask 171. In actual preparation, an etching solution with a high etching selectivity ratio to the spacer mask 171 and the gate layer 141 can be selected to remove the spacer mask 171 by performing a wet etching process.

[0126] It can be understood that since the gate layer 141 is obtained by etching with the spacer mask 171 as a mask, the line width of each part of the gate layer 141 corresponds to the line width of each part of the spacer mask 171, so that the line width of the gate bending portion 1413 is greater than the line width of the first gate portion 1411 and the line width of the second gate portion 1412. Therefore, it is convenient to subsequently etch the dielectric layer at the gate bending portion with a larger line width to form a gate opening to achieve conductive extraction.

[0127] In some specific examples, the line width of the first gate portion 1411 and the line width of the second gate portion 1412 are both less than 100nm, and the line width of the gate bend portion 1413 is greater than 100nm. As a result, the line width of the first gate portion 1411 and the line width of the second gate portion 1413 break through the lithography limitations of conventional photolithography machines and can reach less than 100nm, which is beneficial to reducing channel resistance, improving device performance, and reducing the occupied wafer area, which is beneficial to reducing device size. It can be understood that in subsequent processes, the dielectric layer needs to be etched to form a gate opening that exposes the gate layer 141. When performing the etching process, the gate opening needs to be prepared in the dielectric layer, and the line width of the gate bend portion 1413 is set to be greater than 100nm, which is more convenient for preparing the gate opening in the portion of the dielectric layer located at the gate bend portion 1413, reducing the process difficulty. It is not difficult to understand that if the line width of each part of the gate layer 141 is less than 100nm, the gate opening prepared by the conventional photolithography-etching process will not only expose part of the gate layer 141, but also expose part of the semiconductor material layer, thereby affecting the position of the gate conductive connection structure and affecting the device performance.

[0128] Furthermore, since the first extension portion 1611 and the second extension portion 1612 are connected via the bending portion 1613, the first side wall portion 1711 and the second side wall portion 1712 are also connected via the side wall bending portion 1713. Correspondingly, the first gate portion 1411 and the second gate portion 1412 are connected via the gate bending portion 1413. Thus, by conductively leading out the gate bending portion 1413, the conductive lead-out of the entire gate layer 141 can be achieved.

[0129] In some embodiments, the bend portion 1613 includes a first bend portion and a second bend portion; one end of the first extension portion 1611 is connected to one end of the second extension portion 1612 through the first bend portion, and the other end of the first extension portion 1611 is connected to the other end of the second extension portion 1612 through the second bend portion; the sidewall bend portion 1713 covers the first bend portion and the second bend portion; one end of the first gate portion 1411 is connected to one end of the second gate portion 1412 through the gate bend portion 1413, and the other end of the first gate portion 1411 is connected to the other end of the second gate portion 1412 through the gate bend portion 1413. Fig. 20As shown, the gate layer 141 is ring-shaped, and both ends of the first gate portion 1411 and the second gate portion 1412 are connected by a gate bending portion 1413. After the device is turned on, more channels can be provided, which is beneficial to improving device performance. Specifically, the gate bending portion 1413 between one end of the first gate portion 1411 and one end of the second gate portion 1412 is symmetrically arranged with the gate bending portion 1413 between the other end of the first gate portion 1411 and the other end of the second gate portion 1412.

[0130] In some embodiments, the bend portion 1613 includes a first bend portion and a second bend portion; one end of the first extension portion 1611 and one end of the second extension portion 1612 are connected through the first bend portion, and the other end of the first extension portion 1611 and the other end of the second extension portion 1612 are connected through the second bend portion; the sidewall bend portion 1713 covers the first bend portion and / or the second bend portion; one end of the first gate portion 1411 and one end of the second gate portion 1412 are connected through the gate bend portion 1413, and the other end of the first gate portion 1411 and the other end of the second gate portion 1412 are independent of each other. The present application does not exclude the situation where the gate bend portion 1413 only connects one end of the first gate portion 1411 and the second gate portion 1412, thereby saving the wafer area occupied by the gate layer 141, which is conducive to reducing the device size.

[0131] In some embodiments, the first gate portion 1411 and the second gate portion 1412 are parallel to each other. It can be understood that after the device is turned on, a channel will be generated under the gate layer 141. Therefore, the position of the first gate portion 1411 and the second gate portion 1412 will affect the arrangement of the channel, and then affect the current distribution in the device. By setting the first gate portion 1411 and the second gate portion 1412 to be parallel to each other, a more uniform current distribution can be formed to ensure the stability of the device.

[0132] In some embodiments, the first gate portion 1411 extends along a straight line; and / or the second gate portion 1412 extends along a straight line, which is beneficial to forming a more uniform current distribution and ensuring the stability of the device.

[0133] In some embodiments, the gate bending portion 1413 includes a gate bending portion 1413 having an arc-shaped outer wall profile connected between one end of the first gate portion 1411 and one end of the second gate portion 1412. It can be understood that the gate bending portion 1413 is fan-shaped.

[0134] For some specific examples, see Fig. 20The gate layer 141 is annular, specifically a racetrack-shaped annular; the first gate portion 1411 and the second gate portion 1412 extend along a straight line and are parallel to each other; the gate bending portion 1413 is fan-shaped; both ends of the first gate portion 1411 and the second gate portion 1413 are connected by the gate bending portion 1413. This can be more conducive to ensuring electric field distribution and device performance.

[0135] Please refer to Fig.24 , Fig.24 for Figure 6 A variation of the layout of the structure shown, Figure 6 Likewise Fig.24 The schematic diagram of the cross-sectional structure of the structure shown in the AA cross section. The bending portion 1613 may include a first sub-bending portion 1601 connected to one end of the first extension portion 1611, and a second sub-bending portion 1602 connected between one end of the second extension portion 1612 and the first sub-bending portion 1601, and the angle between the first sub-bending portion 1601 and the second sub-bending portion 1602 is less than or equal to 90 degrees. Thus, a corner is formed between the first sub-bending portion 1601 and the second sub-bending portion 1602, and the mask material is more likely to accumulate at the corner and is more difficult to be etched, so that the line width of the finally formed sidewall bending portion and the corresponding gate bending portion can be larger, which is convenient for realizing conductive lead-out.

[0136] Specifically, the first sub-bending portion 1601 extends in a direction away from the first extending portion 1611 and the second extending portion 1612 ; and the second sub-bending portion 1602 extends in a direction away from the first extending portion 1611 and the second extending portion 1612 .

[0137] Optionally, the first sub-bending portion 1601 extends along a straight line; and / or the second sub-bending portion 1602 extends along a straight line.

[0138] Optionally, the first sub-bending portion 1601 and the second sub-bending portion 1602 are symmetrically arranged.

[0139] Please refer to Fig.25 , Fig.25 for Fig.11 A variation of the layout of the structure shown, Fig.11 Likewise Fig.25 The schematic diagram of the cross-sectional structure of the structure shown in the AA cross section. The gate bending portion 1413 may include a first sub-gate bending portion 1401 connected to one end of the first gate portion 1411, a second sub-gate bending portion 1402 connected between one end of the second gate portion 1412 and the first sub-gate bending portion 1401, and the angle between the outer side wall of the first sub-gate bending portion 1401 and the outer side wall of the second sub-gate bending portion 1402 is less than or equal to 90 degrees.

[0140] Optionally, an outer sidewall of the first sub-gate bent portion 1401 extends along a straight line; and / or an outer sidewall of the second sub-gate bent portion 1402 extends along a straight line.

[0141] Optionally, the first sub-gate bent portion 1401 and the second sub-gate bent portion 1402 are symmetrically arranged.

[0142] It can be understood that since the gate layer 141 is obtained by etching using the side wall mask 171 as a mask, the shape and line width of the side wall mask 171 correspond to the shape and line width of the gate layer 141. Therefore, the side wall bending portion 1713 of the side wall mask 171 is not described in detail here, and specific reference may be made to the description of the gate bending portion 1413.

[0143] Please refer to Fig.26 , Fig.26 for Figure 6 Another variation of the layout of the structure shown, Figure 6 Likewise Fig.26 The cross-sectional structure diagram of the structure shown in the AA cross section. The bending portion 1613 may include a first sub-bending portion 1601 connected to one end of the first extension portion 1611, a second sub-bending portion 1602 connected to one end of the second extension portion 1612, and a third sub-bending portion 1603 connected between the first sub-bending portion 1601 and the second sub-bending portion 1602, wherein the angle between the first sub-bending portion 1601 and the second sub-bending portion 1602 is less than or equal to 90 degrees, and the length of the third sub-bending portion 1603 is less than the length of the first sub-bending portion 1601 and the length of the second sub-bending portion 1602. As a result, a corner is formed between the first sub-bending portion 1601 and the third sub-bending portion 1603, and a corner is formed between the second sub-bending portion 1602 and the third sub-bending portion 1603. The mask material is more likely to accumulate at the corners and is more difficult to etch, so that the line width of the finally formed side wall bending portion and the corresponding gate bending portion can be larger, which facilitates the realization of conductive lead-out.

[0144] Specifically, the first sub-bending portion 1601 extends in a direction away from the first extending portion 1611 and the second extending portion 1612 ; and the second sub-bending portion 1602 extends in a direction away from the first extending portion 1611 and the second extending portion 1612 .

[0145] Optionally, at least one of the first sub-bending portion 1601, the second sub-bending portion 1602 and the third sub-bending portion 1603 extends along a straight line. Further, the first sub-bending portion 1601, the second sub-bending portion 1602 and the third sub-bending portion 1603 all extend along a straight line.

[0146] Optionally, the first sub-bending portion 1601 and the second sub-bending portion 1602 are symmetrically arranged.

[0147] Please refer to Fig. 27 , Fig. 27 for Fig.11 Another variation of the layout of the structure shown, Fig.11 Likewise Fig. 27 The schematic diagram of the cross-sectional structure of the structure shown in the AA cross section. The gate bending portion 1413 may include a first sub-gate bending portion 1401 connected to one end of the first gate portion 1411, a second sub-gate bending portion 1402 connected to one end of the second gate portion 1412, and a third sub-gate bending portion 1403 connected between the first sub-gate bending portion 1401 and the second sub-gate bending portion 1402. The angle between the outer side wall of the first sub-gate bending portion 1401 and the outer side wall of the second sub-gate bending portion 1402 is less than or equal to 90 degrees. In the direction parallel to the plane where the semiconductor material layer is located, the extension length of the outer side wall of the third sub-gate bending portion 1403 is less than the extension length of the outer side wall of the first sub-gate bending portion 1401 and less than the extension length of the outer side wall of the second sub-gate bending portion 1402.

[0148] Optionally, at least one of the outer sidewalls of the first sub-gate bend 1401, the outer sidewalls of the second sub-gate bend 1402, and the outer sidewalls of the third sub-gate bend 1403 extends along a straight line. Further, the outer sidewalls of the first sub-gate bend 1401, the outer sidewalls of the second sub-gate bend 1402, and the outer sidewalls of the third sub-gate bend 1403 all extend along a straight line.

[0149] Optionally, the first sub-gate bent portion 1401 and the second sub-gate bent portion 1402 are symmetrically arranged.

[0150] Please refer to Fig.28 , Fig.28 for Figure 6 Another variation of the layout of the structure shown, Figure 6 Likewise Fig.28The cross-sectional structure diagram of the structure shown in the AA cross section. The bending portion 1613 may include a first sub-bending portion 1601 connected to one end of the first extension portion 1611, a second sub-bending portion 1602 connected to one end of the second extension portion 1612, a fourth sub-bending portion 1604, a third sub-bending portion 1603 and a fifth sub-bending portion 1605 connected in sequence between the first sub-bending portion 1601 and the second sub-bending portion 1602, and the spacing between the fourth sub-bending portion 1604 and the fifth sub-bending portion 1605 is greater than or equal to 100nm and less than or equal to 200nm. It can be understood that a corner is formed between two sub-bending portions connected sequentially in the first sub-bending portion 1601, the fourth sub-bending portion 1604, the third sub-bending portion 1603, the fifth sub-bending portion 1605 and the second sub-bending portion 1602, so that the mask material fills up the part of the groove formed by the fourth sub-bending portion 1604, the third sub-bending portion 1603 and the fifth sub-bending portion 1605, and is more difficult to etch. At the same time, the spacing between the fourth sub-bending portion 1604 and the fifth sub-bending portion 1605 is set within this range. Under the joint action of these two, the line width of the finally formed side wall bending portion and the corresponding gate bending portion can be made larger. The side wall bending portion at least includes a portion with a line width of at least greater than or equal to 100nm. Therefore, the line width of the gate bending portion is at least greater than or equal to 100nm, which is convenient for realizing conductive lead-out.

[0151] Specifically, the first sub-bend portion 1601 extends in a direction away from the first extension portion 1611 and the second extension portion 1612; the second sub-bend portion 1602 extends in a direction away from the first extension portion 1611 and the second extension portion 1612; the fourth sub-bend portion 1604 extends in a direction away from the first sub-bend portion 1601 and the second sub-bend portion 1602; and the fifth sub-bend portion 1605 extends in a direction away from the first sub-bend portion 1601 and the second sub-bend portion 1602.

[0152] Optionally, at least one of the first sub-bend portion 1601, the second sub-bend portion 1602, the third sub-bend portion 1603, the fourth sub-bend portion 1604, and the fifth sub-bend portion 1605 extends along a straight line. Further, the first sub-bend portion 1601, the second sub-bend portion 1602, the third sub-bend portion 1603, the fourth sub-bend portion 1604, and the fifth sub-bend portion 1605 all extend along a straight line.

[0153] Optionally, the first sub-bending portion 1601 and the second sub-bending portion 1602 are symmetrically arranged; and / or the fourth sub-bending portion 1604 and the fifth sub-bending portion 1605 are symmetrically arranged.

[0154] Optionally, the fourth sub-bending portion 1604 and the fifth sub-bending portion 1605 are parallel to each other; or, the fourth sub-bending portion 1604 and the fifth sub-bending portion 1605 intersect each other in the extension direction, the minimum distance between the fourth sub-bending portion 1604 and the fifth sub-bending portion 1605 is greater than or equal to 100nm, and the maximum distance between the fourth sub-bending portion 1604 and the fifth sub-bending portion 1605 is less than or equal to 200nm.

[0155] Optionally, the third bending portion 1603 and the fourth sub-bending portion 1604 are perpendicular to each other; and / or the third bending portion 1603 and the fifth sub-bending portion 1605 are perpendicular to each other. This is more conducive to forming a gate bending portion with a larger line width and more conducive to ensuring device performance.

[0156] Optionally, the fourth sub-bending portion 1604 and the first extending portion 1611 are parallel to each other; and / or the fourth sub-bending portion 1604 and the second extending portion 1612 are parallel to each other.

[0157] Optionally, the fifth sub-bending portion 1605 and the first extending portion 1611 are parallel to each other; and / or the fifth sub-bending portion 1605 and the second extending portion 1612 are parallel to each other.

[0158] Furthermore, the first extending portion 1611 , the second extending portion 1612 , the fourth sub-bending portion 1604 and the fifth sub-bending portion 1605 are parallel to each other.

[0159] Optionally, the length of the third sub-bending portion 1603 is smaller than the length of the fourth sub-bending portion 1604 and smaller than the length of the fifth sub-bending portion 1605 .

[0160] Please refer to Fig.29 , Fig.29 for Fig.11 Another variation of the layout of the structure shown, Fig.11 Likewise Fig.29 The schematic diagram of the cross-sectional structure of the structure shown in the AA cross section. The gate bending portion 1413 may include a first sub-gate bending portion 1401 connected to one end of the first gate portion 1411, a second sub-gate bending portion 1402 connected to one end of the second gate portion 1412, and a third sub-gate bending portion 1403 connected between the first sub-gate bending portion 1401 and the second sub-gate bending portion 1402. In the direction parallel to the plane where the semiconductor material layer is located, the outer side wall of the third sub-gate bending portion 1403 includes a first sub-outer side wall, a second sub-outer side wall and a third sub-outer side wall connected in sequence, and the spacing between the first sub-outer side wall and the third sub-outer side wall is greater than or equal to 100nm and less than or equal to 200nm. Therefore, the line width of the third sub-gate bending portion 1403 is at least greater than or equal to 100nm, which is convenient for realizing conductive connection.

[0161] Optionally, at least one of the outer sidewall of the first sub-gate bend 1401, the outer sidewall of the second sub-gate bend 1402, the first sub-outer sidewall, the second sub-outer sidewall, and the third sub-outer sidewall extends in a straight line. Further, the outer sidewall of the first sub-gate bend 1401, the outer sidewall of the second sub-gate bend 1402, the first sub-outer sidewall, the second sub-outer sidewall, and the third sub-outer sidewall all extend in a straight line.

[0162] Optionally, the first sub-gate bent portion 1401 and the second sub-gate bent portion 1402 are symmetrically arranged.

[0163] Optionally, the first sub-outer wall and the third sub-outer wall are parallel to each other; or, the first sub-outer wall and the third sub-outer wall intersect each other in the extension direction, the minimum distance between the first sub-outer wall and the third sub-outer wall is greater than or equal to 100nm, and the maximum distance between the first sub-outer wall and the third sub-outer wall is less than or equal to 200nm.

[0164] Optionally, the first sub-outer side wall and the second sub-outer side wall are perpendicular to each other; and / or, the second sub-outer side wall and the third sub-outer side wall are perpendicular to each other.

[0165] Optionally, the first sub-outer side wall and the outer side wall of the first gate portion 1411 are parallel to each other; and / or, the first sub-outer side wall and the outer side wall of the second gate portion 1412 are parallel to each other.

[0166] Optionally, the third sub-outer side wall and the outer side wall of the first gate portion 1411 are parallel to each other; and / or, the third sub-outer side wall and the outer side wall of the second gate portion 1412 are parallel to each other.

[0167] Further, the outer side wall of the first gate portion 1411 , the outer side wall of the second gate portion 1412 , the first sub-outer side wall and the third sub-outer side wall are parallel to each other.

[0168] Optionally, the length of the second sub-outer side wall is shorter than the length of the first sub-outer side wall and shorter than the length of the third sub-outer side wall.

[0169] Next, please refer to Fig.12 , executing step S109: forming a dielectric layer 180 covering the semiconductor material layer and the gate layer 141 .

[0170] The process of forming the dielectric layer 180 may include a deposition process, such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), etc., or a combination of multiple processes, which is not limited in this embodiment.

[0171] The material of the dielectric layer 180 may include one or more of SiO, SiON, SiN and AlN, which is not limited in this embodiment.

[0172] Next, please refer to Fig.13 , step S110 is performed: forming a gate opening 181 exposing the gate bending portion 1413 in the dielectric layer 180. It can be understood that since the line width of the gate bending portion 1413 is greater than the line width of the first gate portion 1411 and the line width of the second gate portion 1412, the process difficulty of forming the gate opening 181 at the gate bending portion 1413 is lower.

[0173] The process of forming the gate opening 181 may include a photolithography-etching process. Specifically, forming the gate opening 181 exposing the gate bend 1413 in the dielectric layer 180 may include: forming a third photoresist layer (not shown in the figure) on the dielectric layer 180; performing a photolithography process, exposing and developing the third photoresist layer to form a patterned third photoresist layer; using the patterned third photoresist layer as a mask, etching the dielectric layer 180 to form the gate opening 181 exposing the gate bend 1413 in the dielectric layer 180. If the line width of the gate bend 1413 is large, the allowable size of the gate opening 181 is large. When exposing the third photoresist layer, a conventional photolithography machine can be used to reduce the process difficulty and process cost. In some specific examples, the line width of the first gate portion 1411 and the line width of the second gate portion 1412 are both less than 100nm, and the line width of the gate bend 1413 is greater than 100nm. Therefore, in actual preparation, a conventional DUV lithography machine can be used to reduce process difficulty and process cost.

[0174] In some embodiments, the gate bend portion 1413 includes at least two, one end of the first gate portion 1411 and one end of the second gate portion 1412 are connected through the gate bend portion 1413, and the other end of the first gate portion 1411 and the other end of the second gate portion 1412 are connected through the gate bend portion 1413; step S110 may include: forming at least one gate opening 181 in the dielectric layer 180 to expose at least one gate bend portion 1413.

[0175] Please refer to Fig.21 and Fig. 22 , Fig.21 and Fig. 22 In two optional specific implementations Fig.13 The layout of the structure shown, Fig.13 for Fig.21 and Fig. 22 The structure shown is a schematic diagram of the cross-sectional structure on the BB cross section. It can be understood that although Fig.21 and Fig. 22Only the situation of forming a gate conductive connection structure 200 is schematically shown, and correspondingly, it also corresponds to the situation of forming a gate opening 181 exposing a gate bend portion 1413. However, the embodiment of the present application does not exclude the situation of forming at least two gate openings 181 in the dielectric layer 180 at at least two gate bend portions 1413, and then forming at least two gate conductive connection structures 200 in the subsequent process, which is more conducive to realizing conductive lead-out.

[0176] Please refer to Fig.13 and Fig.21 , perform step S111: forming a gate conductive connection structure 200 in the gate opening 181, and the gate conductive connection structure 200 is in direct contact with the gate bending portion 1413. Thus, the gate bending portion 1413 connects the first gate portion 1411 and the second gate portion 1412, and by directly contacting the gate conductive connection structure 200 with the gate bending portion 1413, the conductive lead-out of the entire gate layer 141 can be achieved.

[0177] Optionally, the line width of the gate conductive connection structure 200 is greater than the line width of the first gate portion 1411 and the line width of the second gate portion 1412. It can be understood that in the embodiment of the present application, in the thickness direction of the semiconductor substrate, for the case where the width of the upper and lower parts of the structure is different, the line width refers to the width of the narrowest part of the structure. Here, the width of the narrowest part of the gate conductive connection structure 200 is greater than the line width of the first gate portion 1411 and the line width of the second gate portion 1412. It can be seen that the width of the portion of the gate conductive connection structure 200 that is in direct contact with the gate bending portion 1413 is also greater than the line width of the first gate portion 1411 and the line width of the second gate portion 1412, that is, the width of the gate opening 181 is greater than the line width of the first gate portion 1411 and the line width of the second gate portion 1412, which is more conducive to reducing the process difficulty of preparing the gate opening 181.

[0178] Furthermore, the line width of the gate conductive connection structure 200 is greater than 100nm and less than or equal to the line width of the gate bending portion 1413. Thus, it is avoided that the gate opening 181 exposes the semiconductor material layer, so that the gate conductive connection structure 200 is conductively connected to the semiconductor material layer, which affects the product yield; and the size of the gate opening 181 is greater than 100nm, and in actual preparation, it can be realized by using a traditional DUV lithography machine, without using a more expensive lithography machine or other more expensive etching technology, which is more conducive to reducing the process difficulty and saving production costs.

[0179] The material of the gate conductive connection structure 200 may include metal.

[0180] Please refer to Fig.13 and Fig.23The method may further include: forming a drain opening 182 and a source opening 183 exposing the semiconductor material layer in the dielectric layer 180, the drain opening 182 including a first drain opening 1821 and a second drain opening 1822; forming a first drain conductive connection structure 211, a second drain conductive connection structure 212 and a source conductive connection structure 220 in the first drain opening 1821, the second drain opening 1822 and the source opening 183, respectively; wherein the source conductive connection structure 220 is located between the first gate portion 1411 and the second gate portion 1412, the first drain conductive connection structure 211 is located on a side of the first gate portion 1411 away from the second gate portion 1412, and the second drain conductive connection structure 212 is located on a side of the second gate portion 1412 away from the first gate portion 1411. Thus, the conductive lead-out of the source and drain is realized; the source conductive connection structure 220 is located between the first drain conductive connection structure 211 and the second drain conductive connection structure 212, forming a common source semiconductor device, saving process and device area. In some embodiments, along the direction perpendicular to the plane where the semiconductor material layer is located, the projection of the gate layer 141 is annular, and the projection of the source conductive connection structure 220 is surrounded by the projection of the gate layer 141.

[0181] It can be understood that in some embodiments, the drain opening 182, the source opening 183 and the gate opening 181 can be formed in the same process; the first drain conductive connection structure 211, the second drain conductive connection structure 212, the source conductive connection structure 220 and the gate conductive connection structure 200 can be formed in the same process.

[0182] Please refer to Fig.13 and Fig.23 The preparation method may further include: forming an ohmic contact layer 190 in the source opening 183 , the drain opening 182 and the gate opening 181 , respectively, so as to reduce the contact resistance between the metal material and the semiconductor material.

[0183] In some embodiments, the first drain conductive connection structure 211 extends along a straight line; and / or the second drain conductive connection structure 212 extends along a straight line, so as to reduce the difficulty of the process.

[0184] In some embodiments, the first drain conductive connection structure 211 and the second drain conductive connection structure 212 are parallel to each other, which is more conducive to balancing the electric field distribution and ensuring the device morphology.

[0185] In an optional specific implementation, please refer to Fig.21The drain opening 182 also includes a third drain opening 1823 and a fourth drain opening 1824, and the third drain opening 1823 and the fourth drain opening 1824 respectively connect the two ends of the first drain opening 1821 and the second drain opening 1822; the preparation method also includes: forming a third drain conductive connection structure 213 and a fourth drain conductive connection structure 214 in the third drain opening 1823 and the fourth drain opening 1824 respectively, and the first drain conductive connection structure 211, the third drain conductive connection structure 213, the second drain conductive connection structure 212 and the fourth drain conductive connection structure 214 are connected into a ring shape; along the direction perpendicular to the plane where the semiconductor material layer is located, the projection of the gate layer 141 is ring-shaped, the projection of the source conductive connection structure 220 is surrounded by the projection of the gate layer 141, and the projection of the gate layer 141 is surrounded by the projection of the drain conductive connection structure 210. Thus, the first drain conductive connection structure 211 and the second drain conductive connection structure 212 are conductively connected through the third drain conductive connection structure 213 and the fourth drain conductive connection structure 214 to form a parallel structure; when the projection of the gate layer 141 is annular, a corresponding channel can be formed in the device, so that both ends of the first drain conductive connection structure 211 and the second drain conductive connection structure 212 are connected, and the drain conductive connection structure 210 is arranged around the gate layer 141, so that the formed channel can be more effectively utilized. In addition to the first gate portion 1411 and the second gate portion 1412, a source-gate-drain structure can also be formed in the area of ​​the gate bending portion 1413, which is beneficial to improving device performance.

[0186] In some embodiments, the third drain conductive connection structure 213 extends along a straight line; and / or the fourth drain conductive connection structure 214 extends along a straight line to reduce process difficulty.

[0187] In some embodiments, the third drain conductive connection structure 213 and the fourth drain conductive connection structure 214 are parallel to each other, which is more conducive to balancing the electric field distribution and ensuring the device performance.

[0188] Optionally, the line widths of the third drain conductive connection structure 213 and the fourth drain conductive connection structure 214 are smaller than the line widths of the first drain conductive connection structure 211 and the second drain conductive connection structure 212 to save layout.

[0189] In another optional specific implementation, please refer to Fig. 22The drain opening 182 also includes a third drain opening 1823, and the third drain opening 1823 connects one end of the first drain opening 1821 and the second drain opening 1822; the preparation method also includes: forming a third drain conductive connection structure 213 in the third drain opening 1823, and connecting the first drain conductive connection structure 211, the third drain conductive connection structure 213, and the second drain conductive connection structure 212. This can save layout.

[0190] Understandably, although Fig.21 and Fig. 22 The first drain conductive connection structure 211 and the second drain conductive connection structure 212 are respectively shown as having both ends connected and one end connected, but the present application does not exclude the situation where the first drain conductive connection structure 211 and the second drain conductive connection structure 212 are independent of each other.

[0191] Please refer to Fig.14 After executing step S111, the preparation method may further include: forming an interlayer dielectric layer 300, the interlayer dielectric layer (Inter Metal Dielectric, IMD) covers the surface of the entire structure; forming contact holes in the interlayer dielectric layer 300 that respectively expose the source conductive connection structure 220, the drain conductive connection structure 210 and the gate conductive connection structure 200, and filling the contact holes with metal materials to form source conductive plugs 320, drain conductive plugs 310 and gate conductive plugs, respectively.

[0192] Next, please refer to Fig.15 The preparation method further includes: forming a source conductive layer 410, a drain conductive layer 420 and a gate conductive layer; wherein the source conductive layer 410 is conductively connected to the source conductive connection structure 220 through the source conductive plug 320, the drain conductive layer 420 is conductively connected to the drain conductive connection structure 210 through the drain conductive plug 310, and the gate conductive layer is conductively connected to the gate conductive connection structure 200 through the gate conductive plug.

[0193] In actual preparation, a conductive layer covering the interlayer dielectric layer 300 may be formed first, and then the conductive layer may be patterned to form a source conductive layer 410 , a drain conductive layer 420 , and a gate conductive layer that are insulated and isolated from each other.

[0194] Please continue to refer to Fig.15 The preparation method further includes: forming a protection layer 400, wherein the protection layer 400 covers a portion of the source conductive layer 410, a portion of the drain conductive layer 420 and a portion of the gate conductive layer to play a protective role while ensuring conductive extraction.

[0195] The present application also provides a semiconductor device. Fig.15 , Figure 20 to Figure 23 , the semiconductor device comprises:

[0196] a semiconductor material layer;

[0197] The gate layer 141 is located on the semiconductor material layer. The gate layer 141 includes a first gate portion 1411 and a second gate portion 1412 extending in a direction parallel to the plane where the semiconductor material layer is located, and a gate bending portion 1413 connecting the first gate portion 1411 and the second gate portion 1412. The line width of the first gate portion 1411 and the line width of the second gate portion 1412 are both less than 100 nm, and the line width of the gate bending portion 1413 is greater than 100 nm.

[0198] The dielectric layer 180 covers the semiconductor material layer and the gate layer 141 , and a gate opening 181 exposing the gate bending portion 1413 is formed in the dielectric layer 180 ;

[0199] The gate conductive connection structure 200 is located in the gate opening 181 and directly contacts the gate bending portion 1413 .

[0200] In the semiconductor device provided in the embodiment of the present application, the line width of the first gate portion 1411 and the line width of the second gate portion 1412 are both less than 100nm, that is, less than the line width limit that can be prepared by a traditional photolithography machine, so that a small line width gate layer is used to reduce the channel resistance, improve the conductive performance of the device, and reduce the area, thereby obtaining a small gate width and high current semiconductor device; on this basis, since the gate layer 141 is provided to include the first gate portion 1411 and the second gate portion 1412 extending in a direction parallel to the plane where the semiconductor material layer is located, and the gate bending portion 1413 connecting the line width of the first gate portion 1411 and the second gate portion 1412, and the line width of the gate bending portion 1413 is greater than 100nm, the gate opening 181 is provided in the dielectric layer 180 at the gate bending portion 1413, thereby solving the problem of gate conductive lead-out after the small line width gate layer is formed.

[0201] Optionally, the semiconductor material layer includes a substrate 100 and a semiconductor epitaxial stack 130 located on the substrate, at least a portion of the semiconductor epitaxial stack 130 is used to form a two-dimensional electron gas channel 133; and the gate layer 141 is a P-type gate layer. Thus, a high electron mobility transistor (HEMT) can be formed.

[0202] Optionally, the line width of the gate conductive connection structure 200 is greater than 100nm and less than or equal to the line width of the gate bending portion 1413. Thus, it is avoided that the gate opening 181 exposes the semiconductor material layer, so that the gate conductive connection structure 200 is conductively connected to the semiconductor material layer, which affects the product yield; and the size of the gate opening 181 is greater than 100nm. In actual preparation, it can be realized by using a traditional DUV lithography machine, without using a more expensive lithography machine or other more expensive etching technology, which is more conducive to reducing the process difficulty and saving production costs.

[0203] In some embodiments, please refer to Fig. 20 , the semiconductor device includes at least two gate bends 1413; one end of the first gate portion 1411 and one end of the second gate portion 1412 are connected through the gate bend 1413, and the other end of the first gate portion 1411 and the other end of the second gate portion 1412 are connected through the gate bend 1413. After the device is turned on, more channels can be provided, which is beneficial to improving device performance. It can be understood that although Fig.21 and Fig. 22 Only the situation of forming a gate conductive connection structure 200 is schematically shown, and correspondingly, it also corresponds to the situation of forming a gate opening 181. However, the present application does not exclude the situation of forming at least two gate openings 181 in the dielectric layer 180 at at least two gate bends 1413, thereby forming at least two gate conductive connection structures 200, which is more conducive to realizing conductive lead-out.

[0204] It should be noted that although Fig. 20 The situation is shown where both ends of the first gate portion 1411 and the second gate portion 1412 are connected by the gate bending portion 1413, but the present application does not exclude the situation where the gate bending portion 1413 only connects one end of the first gate portion 1411 and the second gate portion 1412, thereby saving the wafer area occupied by the gate layer 141, which is beneficial to reducing the device size.

[0205] In some embodiments, the first gate portion 1411 and the second gate portion 1412 are parallel to each other. It can be understood that after the device is turned on, a channel will be generated under the gate layer 141. Therefore, the position of the first gate portion 1411 and the second gate portion 1412 will affect the arrangement of the channel, and then affect the current distribution in the device. By setting the first gate portion 1411 and the second gate portion 1411 to be parallel to each other, a more uniform current distribution can be formed to ensure the stability of the device.

[0206] In some embodiments, the first gate portion 1411 extends along a straight line; and / or the second gate portion 1411 extends along a straight line. This is beneficial for forming a more uniform current distribution and ensuring the stability of the device.

[0207] In some embodiments, the gate bending portion 1413 includes a gate bending portion 1413 having an arc-shaped outer wall profile connected between one end of the first gate portion 1411 and one end of the second gate portion 1412. It can be understood that the gate bending portion 1413 is fan-shaped.

[0208] For some specific examples, see Fig. 20 The gate layer 141 is annular, specifically a racetrack-shaped annular; the first gate portion 1411 and the second gate portion 1412 extend along a straight line and are parallel to each other; the gate bending portion 1413 is fan-shaped; both ends of the first gate portion 1411 and the second gate portion 1413 are connected by the gate bending portion 1413. This can be more conducive to ensuring electric field distribution and device performance.

[0209] In some embodiments, please refer to Fig.25 The gate bending portion 1413 may include a first sub-gate bending portion 1401 connected to one end of the first gate portion 1411, and a second sub-gate bending portion 1402 connected between one end of the second gate portion 1412 and the first sub-gate bending portion 1401. The angle between the outer wall of the first sub-gate bending portion 1401 and the outer wall of the second sub-gate bending portion 1402 is less than or equal to 90 degrees.

[0210] In some embodiments, please refer to Fig. 27 The gate bending portion 1413 may include a first sub-gate bending portion 1401 connected to one end of the first gate portion 1411, a second sub-gate bending portion 1402 connected to one end of the second gate portion 1412, and a third sub-gate bending portion 1403 connected between the first sub-gate bending portion 1401 and the second sub-gate bending portion 1402. The angle between the outer wall of the first sub-gate bending portion 1401 and the outer wall of the second sub-gate bending portion 1402 is less than or equal to 90 degrees. In the direction parallel to the plane where the semiconductor material layer is located, the extension length of the outer wall of the third sub-gate bending portion 1403 is less than the extension length of the outer wall of the first sub-gate bending portion 1401 and less than the extension length of the outer wall of the second sub-gate bending portion 1402.

[0211] In some embodiments, please refer to Fig.29The gate bending portion 1413 may include a first sub-gate bending portion 1401 connected to one end of the first gate portion 1411, a second sub-gate bending portion 1402 connected to one end of the second gate portion 1412, and a third sub-gate bending portion 1403 connected between the first sub-gate bending portion 1401 and the second sub-gate bending portion 1402. In a direction parallel to the plane where the semiconductor material layer is located, the outer side wall of the third sub-gate bending portion 1403 includes a first sub-outer side wall, a second sub-outer side wall and a third sub-outer side wall connected in sequence, and the spacing between the first sub-outer side wall and the third sub-outer side wall is greater than or equal to 100nm and less than or equal to 200nm. Therefore, the line width of the third sub-gate bending portion 1403 is at least greater than or equal to 100nm, which is convenient for realizing conductive connection.

[0212] Optionally, refer to Fig.21 and Fig.23 A drain opening 182 and a source opening 183 exposing the semiconductor material layer are also formed in the dielectric layer 180, and the drain opening includes a first drain opening 1821 and a second drain opening 1822; the semiconductor device also includes: a first drain conductive connection structure 211, a second drain conductive connection structure 212 and a source conductive connection structure 220 respectively located in the first drain opening 1821, the second drain opening 1822 and the source opening 183; wherein the source conductive connection structure 220 is located between the first gate portion 1411 and the second gate portion 1412, the first drain conductive connection structure 211 is located on a side of the first gate portion 1411 away from the second gate portion 1412, and the second drain conductive connection structure 212 is located on a side of the second gate portion 1412 away from the first gate portion 1411. Thus, the conductive lead-out of the source and drain is realized; the source conductive connection structure 220 is located between the first drain conductive connection structure 211 and the second drain conductive connection structure 212, forming a common source semiconductor device, saving process and device area. In some embodiments, along the direction perpendicular to the plane where the semiconductor material layer is located, the projection of the gate layer 141 is annular, and the projection of the source conductive connection structure 220 is surrounded by the projection of the gate layer 141.

[0213] In some embodiments, the first drain conductive connection structure 211 and the second drain conductive connection structure 212 are parallel to each other, which is more conducive to balancing the electric field distribution and ensuring the device performance.

[0214] In some embodiments, the first drain conductive connection structure 211 extends along a straight line; and / or the second drain conductive connection structure 212 extends along a straight line. This is more conducive to balancing the electric field distribution and ensuring device performance.

[0215] Please refer to Fig.15The device further includes an ohmic contact layer 190 located in the gate opening, the source opening 183 and the drain opening 182, thereby reducing the contact resistance between the metal material and the semiconductor material.

[0216] In an optional specific implementation, please refer to Fig.21 The drain opening 182 also includes a third drain opening 1823 and a fourth drain opening 1824, which respectively connect the two ends of the first drain opening 1821 and the second drain opening 1822; a third drain conductive connection structure 213 and a fourth drain conductive connection structure 214 are respectively formed in the third drain opening 1823 and the fourth drain opening 1824, and the first drain conductive connection structure 211, the third drain conductive connection structure 213, the second drain conductive connection structure 212 and the fourth drain conductive connection structure 214 are connected in a ring shape; along the direction perpendicular to the plane where the semiconductor material layer is located, the projection of the gate layer 141 is ring-shaped, the projection of the source conductive connection structure 220 is surrounded by the projection of the gate layer 141, and the projection of the gate layer 141 is surrounded by the projection of the drain conductive connection structure 210. Thus, the first drain conductive connection structure 211 and the second drain conductive connection structure 212 are conductively connected through the third drain conductive connection structure 213 and the fourth drain conductive connection structure 214 to form a parallel structure; when the projection of the gate layer 141 is annular, a corresponding channel can be formed in the device, so that both ends of the first drain conductive connection structure 211 and the second drain conductive connection structure 212 are connected, and the drain conductive connection structure 210 is arranged around the gate layer 141, so that the formed channel can be more effectively utilized. In addition to the first gate portion 1411 and the second gate portion 1412, a source-gate-drain structure can also be formed in the area of ​​the gate bending portion 1413, which is beneficial to improving device performance.

[0217] In some embodiments, the third drain conductive connection structure 213 and the fourth drain conductive connection structure 214 are parallel to each other, which is more conducive to balancing the electric field distribution and ensuring the device performance.

[0218] In some embodiments, the third drain conductive connection structure 213 extends along a straight line; and / or the fourth drain conductive connection structure 214 extends along a straight line, which is more conducive to balancing the electric field distribution and ensuring the device performance.

[0219] Optionally, the line widths of the third drain conductive connection structure 213 and the fourth drain conductive connection structure 214 are smaller than the line widths of the first drain conductive connection structure 211 and the second drain conductive connection structure 212 to save layout.

[0220] In another optional specific implementation, please refer to Fig. 22The drain opening further includes a third drain opening 1823, which connects the first drain opening 1821 and one end of the second drain opening 1822; a third drain conductive connection structure 213 is formed in the third drain opening 1823, and the first drain conductive connection structure 211, the third drain conductive connection structure 213 and the second drain conductive connection structure 212 are connected. This can save layout.

[0221] Understandably, although Fig.21 and Fig. 22 The first drain conductive connection structure 211 and the second drain conductive connection structure 212 are respectively shown as having both ends connected and one end connected, but the present application does not exclude the situation where the first drain conductive connection structure 211 and the second drain conductive connection structure 212 are independent of each other.

[0222] Please refer to Fig.15 The semiconductor device may further include: an interlayer dielectric layer 300, covering the surface of the entire structure; a source conductive plug 320, a drain conductive plug 310 and a gate conductive plug, penetrating the interlayer dielectric layer 300, and conductively connected to the source conductive connection structure 220, the drain conductive connection structure 210 and the gate conductive connection structure 200 respectively; a source conductive layer 410, a drain conductive layer 420 and a gate conductive layer, located on the interlayer dielectric layer 300; wherein the source conductive layer 410 is conductively connected to the source conductive connection structure 220 through the source conductive plug 320, the drain conductive layer 420 is conductively connected to the drain conductive connection structure 210 through the drain conductive plug 310, and the gate conductive layer is conductively connected to the gate conductive connection structure 200 through the gate conductive plug.

[0223] Please continue to refer to Fig.15 The device further includes a protective layer 400, which covers a portion of the source conductive layer 410, a portion of the drain conductive layer 420 and a portion of the gate conductive layer, so as to ensure the conductive lead-out and play a protective role.

[0224] It should be noted that the semiconductor device embodiment provided in the present application and the semiconductor device preparation method embodiment belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the semiconductor device provided in the embodiment of the present application, the combination of its various technical features can already solve the technical problem to be solved by the present application; therefore, the semiconductor device provided in the embodiment of the present application may not be limited by the semiconductor device preparation method provided in the embodiment of the present application, and any semiconductor device prepared by the preparation method that can form the semiconductor device structure provided in the embodiment of the present application is within the scope of protection of the present application.

[0225] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: forming a gate material layer on the semiconductor material layer; forming a sacrificial material layer on the gate material layer; A through groove exposing the gate material layer is formed in the sacrificial material layer, wherein the inner wall of the through groove comprises a first extension portion, a second extension portion, and a bending portion connecting the first extension portion and the second extension portion, extending in a direction parallel to the plane where the semiconductor material layer is located; forming a mask material layer on the sacrificial material layer and the exposed gate material layer; Etching the mask material layer, a portion of the mask material layer covering the inner wall of the through groove is retained to form a sidewall mask, the sidewall mask comprising a first sidewall portion covering the first extension portion, a second sidewall portion covering the second extension portion, and a sidewall bending portion covering the bending portion, the line width of the sidewall bending portion being greater than the line width of the first sidewall portion and the line width of the second sidewall portion; removing the sacrificial material layer; Etching the gate material layer using the sidewall mask as a mask to form a gate layer, wherein the gate layer includes a first gate portion, a second gate portion, and a gate bending portion, which are respectively located directly below the first sidewall portion, the second sidewall portion, and the sidewall bending portion; removing the sidewall mask; forming a dielectric layer covering the semiconductor material layer and the gate layer; forming a gate opening in the dielectric layer to expose the gate bending portion; A gate conductive connection structure is formed in the gate opening, and the gate conductive connection structure is in direct contact with the gate bending portion.

2. The method for preparing a semiconductor device according to claim 1, wherein: The semiconductor material layer includes a substrate and a semiconductor epitaxial stack located on the substrate, and at least a portion of the semiconductor epitaxial stack is used to form a two-dimensional electron gas channel; The gate layer is a P-type gate layer.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The line width of the gate conductive connection structure is greater than the line width of the first gate portion and the line width of the second gate portion.

4. The method for preparing a semiconductor device according to claim 1, wherein: The method further comprises: Forming a drain opening and a source opening in the dielectric layer to expose the semiconductor material layer, wherein the drain opening includes a first drain opening and a second drain opening; forming a first drain conductive connection structure, a second drain conductive connection structure and a source conductive connection structure in the first drain opening, the second drain opening and the source opening respectively; Among them, the source conductive connection structure is located between the first gate part and the second gate part, the first drain conductive connection structure is located on the side of the first gate part away from the second gate part, and the second drain conductive connection structure is located on the side of the second gate part away from the first gate part.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The drain opening further includes a third drain opening and a fourth drain opening, wherein the third drain opening and the fourth drain opening respectively connect two ends of the first drain opening and the second drain opening; The method further includes: forming a third drain conductive connection structure and a fourth drain conductive connection structure in the third drain opening and the fourth drain opening, respectively, wherein the first drain conductive connection structure, the third drain conductive connection structure, the second drain conductive connection structure and the fourth drain conductive connection structure are connected in a ring shape; Along the direction perpendicular to the plane where the semiconductor material layer is located, the projection of the gate layer is ring-shaped, the projection of the source conductive connection structure is surrounded by the projection of the gate layer, and the projection of the gate layer is surrounded by the projection of the drain conductive connection structure.

6. The method for preparing a semiconductor device according to claim 1, wherein: The bending portion includes one of the following: an arc-shaped bending portion connected between one end of the first extension portion and one end of the second extension portion; A first sub-bending portion connected to one end of the first extending portion, and a second sub-bending portion connected between one end of the second extending portion and the first sub-bending portion, wherein an angle between the first sub-bending portion and the second sub-bending portion is less than or equal to 90 degrees; A first sub-bend portion connected to one end of the first extension portion, a second sub-bend portion connected to one end of the second extension portion, and a third sub-bend portion connected between the first sub-bend portion and the second sub-bend portion, wherein the angle between the first sub-bend portion and the second sub-bend portion is less than or equal to 90 degrees, and the length of the third sub-bend portion is less than the length of the first sub-bend portion and less than the length of the second sub-bend portion; A first sub-bending portion connected to one end of the first extension portion, a second sub-bending portion connected to one end of the second extension portion, a fourth sub-bending portion, a third sub-bending portion and a fifth sub-bending portion connected in sequence between the first sub-bending portion and the second sub-bending portion, wherein a spacing between the fourth sub-bending portion and the fifth sub-bending portion is greater than or equal to 100nm and less than or equal to 200nm.

7. A semiconductor device, characterized in that: include: a semiconductor material layer; a gate layer, located on the semiconductor material layer, the gate layer comprising a first gate portion and a second gate portion extending in a direction parallel to the plane where the semiconductor material layer is located, and a gate bending portion connecting the first gate portion and the second gate portion, the line width of the first gate portion and the line width of the second gate portion are both less than 100 nm, and the line width of the gate bending portion is greater than 100 nm; a dielectric layer, covering the semiconductor material layer and the gate layer, wherein a gate opening exposing the gate bending portion is formed in the dielectric layer; The gate conductive connection structure is located in the gate opening and directly contacts the gate bending portion.

8. The semiconductor device according to claim 7, characterized in that The semiconductor material layer includes a substrate and a semiconductor epitaxial stack located on the substrate, and at least a portion of the semiconductor epitaxial stack is used to form a two-dimensional electron gas channel; The gate layer is a P-type gate layer.

9. The semiconductor device according to claim 7, characterized in that The line width of the gate conductive connection structure is greater than 100 nm and less than or equal to the line width of the gate bending portion.

10. The semiconductor device according to claim 7, wherein: A drain opening and a source opening exposing the semiconductor material layer are also formed in the dielectric layer, and the drain opening includes a first drain opening and a second drain opening; The semiconductor device further comprises: a first drain conductive connection structure, a second drain conductive connection structure and a source conductive connection structure respectively located in the first drain opening, the second drain opening and the source opening; Among them, the source conductive connection structure is located between the first gate part and the second gate part, the first drain conductive connection structure is located on the side of the first gate part away from the second gate part, and the second drain conductive connection structure is located on the side of the second gate part away from the first gate part.

11. The semiconductor device according to claim 10, characterized in that The drain opening further includes a third drain opening and a fourth drain opening, wherein the third drain opening and the fourth drain opening respectively connect two ends of the first drain opening and the second drain opening; A third drain conductive connection structure and a fourth drain conductive connection structure are formed in the third drain opening and the fourth drain opening, respectively, and the first drain conductive connection structure, the third drain conductive connection structure, the second drain conductive connection structure and the fourth drain conductive connection structure are connected to form a ring shape; Along the direction perpendicular to the plane where the semiconductor material layer is located, the projection of the gate layer is ring-shaped, the projection of the source conductive connection structure is surrounded by the projection of the gate layer, and the projection of the gate layer is surrounded by the projection of the drain conductive connection structure.

12. The semiconductor device according to claim 7, wherein: The gate bending portion includes one of the following: A gate bending portion having an arc-shaped outer wall profile connected between one end of the first gate portion and one end of the second gate portion; A first sub-gate bent portion connected to one end of the first gate portion, a second sub-gate bent portion connected between one end of the second gate portion and the first sub-gate bent portion, wherein an angle between an outer side wall of the first sub-gate bent portion and an outer side wall of the second sub-gate bent portion is less than or equal to 90 degrees; A first sub-gate bent portion connected to one end of the first gate portion, a second sub-gate bent portion connected to one end of the second gate portion, and a third sub-gate bent portion connected between the first sub-gate bent portion and the second sub-gate bent portion, wherein an angle between an outer side wall of the first sub-gate bent portion and an outer side wall of the second sub-gate bent portion is less than or equal to 90 degrees, and in a direction parallel to the plane where the semiconductor material layer is located, an extension length of the outer side wall of the third sub-gate bent portion is less than an extension length of the outer side wall of the first sub-gate bent portion and less than an extension length of the outer side wall of the second sub-gate bent portion; A first sub-gate bending portion connected to one end of the first gate portion, a second sub-gate bending portion connected to one end of the second gate portion, and a third sub-gate bending portion connected between the first sub-gate bending portion and the second sub-gate bending portion, wherein in a direction parallel to the plane where the semiconductor material layer is located, the outer side wall of the third sub-gate bending portion includes a first sub-outer side wall, a second sub-outer side wall and a third sub-outer side wall connected in sequence, and a spacing between the first sub-outer side wall and the third sub-outer side wall is greater than or equal to 100nm and less than or equal to 200nm.

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