P-type field effect transistor based on single-layer tungsten diselenide and preparation method thereof

Abstract

The invention discloses a p-type field effect transistor based on single-layer tungsten diselenide and a preparation method of the p-type field effect transistor, and relates to the technical field of semiconductors. The semiconductor layer is located on the upper surface of the middle area of the substrate; the source electrode and the drain electrode are located on the upper surfaces of the areas on the two sides of the substrate, located on the two sides of the semiconductor layer respectively and adjacent to the semiconductor layer; p-type doped regions are arranged between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer; the gate dielectric layer is located on the upper surface of the semiconductor layer; and the gate is located on the upper surface of the gate dielectric layer. According to the invention, the mobility of the field effect transistor hole can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a p-type field effect transistor based on a single-layer tungsten diselenide and a preparation method thereof. Background Art

[0002] As the size of metal oxide semiconductor field effect transistors (MOSFETs) continues to shrink, the performance of integrated circuits has been greatly improved, the integration has become increasingly higher, and the power consumption has continued to decrease, but it has also brought new challenges.

[0003] The working principle of the metal oxide semiconductor field effect transistor in the prior art is mainly that the gate voltage controls the opening and closing of the channel, and the drain voltage controls the transport of carriers; however, with the continuous advancement of the process, the characteristic size of the MOSFET is continuously reduced in proportion, and many effects that are not conducive to the operation of the device have appeared, collectively referred to as the short channel effect. For example, the operating voltage VDD and the threshold voltage VT of the MOSFET must be reduced at the same time to ensure that the driving voltage (VDD-VT) remains unchanged. However, the subthreshold swing of the MOSFET at room temperature cannot exceed 60mV / decade, resulting in a significant increase in the leakage current of the device. The development of integrated circuits has encountered a bottleneck, and traditional silicon-based MOSFETs can no longer meet the needs of high-performance integrated circuits.

[0004] Therefore, there is an urgent need to improve the performance of field effect transistors in the prior art. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a p-type field effect transistor based on a single layer of tungsten diselenide and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a p-type field effect transistor based on a single layer of tungsten diselenide, comprising:

[0007] substrate;

[0008] A semiconductor layer is located on the upper surface of the middle region of the substrate;

[0009] The source electrode and the drain electrode are located on the upper surface of the two side regions of the substrate, the source electrode and the drain electrode are respectively located on the two sides of the semiconductor layer and are adjacent to the semiconductor layer; a P-type doped region is provided between the source electrode and the semiconductor layer, and between the drain electrode and the semiconductor layer;

[0010] A gate dielectric layer, located on the upper surface of the semiconductor layer;

[0011] The gate is located on the upper surface of the gate dielectric layer.

[0012] In a second aspect, the present invention further provides a method for preparing a p-type field effect transistor based on a single-layer tungsten diselenide, which is used to prepare the p-type field effect transistor based on the single-layer tungsten diselenide provided above, comprising:

[0013] providing a substrate;

[0014] epitaxially growing a semiconductor layer on an upper surface of a middle region of the substrate;

[0015] Depositing metal on the upper surface of the two side regions of the substrate to form a source electrode and a drain electrode respectively, wherein the source electrode and the drain electrode are both connected to the semiconductor layer; annealing the source electrode and the drain electrode to form an ohmic contact with the semiconductor layer;

[0016] Depositing a gate dielectric layer on the upper surface of the semiconductor layer;

[0017] Depositing a gate electrode on the upper surface of the gate dielectric layer;

[0018] In a nitrogen atmosphere, nitrogen dioxide is introduced and the temperature is maintained at 140-150° C. for 8-12 minutes to obtain a P-type doped region between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.

[0019] Beneficial effects of the present invention:

[0020] The present invention provides a p-type field effect transistor based on a single-layer tungsten diselenide and a preparation method thereof, comprising a substrate, a semiconductor layer, a source electrode and a drain electrode located on the substrate, wherein the semiconductor layer is located in the middle region of the substrate, the source electrode and the drain electrode are divided into two side regions located on the substrate, the source electrode and the drain electrode are connected to the semiconductor layer, a gate dielectric layer is arranged on the semiconductor layer, the orthographic projection of the gate dielectric layer is located within the range of the orthographic projection of the semiconductor layer in a direction perpendicular to the substrate, a gate is arranged on the upper surface of the gate dielectric layer, and the region on the upper surface of the semiconductor layer where no structure is arranged is a p-type doped region; in this embodiment, p-type doping is realized in the active region of the device, which greatly reduces the contact resistance between the metal and the semiconductor, improves the mobility of holes, and the subthreshold swing is close to the theoretical limit of 60mV / decade, which points out the direction for future high-performance electronic products.

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of a p-type field effect transistor based on a single layer of tungsten diselenide provided in an embodiment of the present invention;

[0023] Figure 2 It is a flow chart of a method for preparing a p-type field effect transistor based on a single-layer tungsten diselenide provided in an embodiment of the present invention;

[0024] Figure 3 It is a schematic diagram of a transfer characteristic curve of a p-type field effect transistor based on a single layer of tungsten diselenide provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0026] See also Figure 1 , Figure 1 1 is a schematic diagram of a p-type field effect transistor based on a single layer of tungsten diselenide provided by an embodiment of the present invention. The p-type field effect transistor based on a single layer of tungsten diselenide provided by the present invention includes:

[0027] substrate;

[0028] A semiconductor layer is located on the upper surface of the middle region of the substrate;

[0029] The source electrode and the drain electrode are located on the upper surface of the two side regions of the substrate, the source electrode and the drain electrode are respectively located on the two sides of the semiconductor layer and are adjacent to the semiconductor layer; a P-type doped region is provided between the source electrode and the semiconductor layer, and between the drain electrode and the semiconductor layer;

[0030] A gate dielectric layer, located on the upper surface of the semiconductor layer;

[0031] The gate is located on the upper surface of the gate dielectric layer.

[0032] For more details, please see Figure 1 The present embodiment provides a p-type field effect transistor based on a single-layer tungsten diselenide, comprising a substrate, a semiconductor layer, a source electrode and a drain electrode located on the substrate, wherein the semiconductor layer is located in the middle region of the substrate, the source electrode and the drain electrode are divided into two regions located on both sides of the substrate, the source electrode and the drain electrode are connected to the semiconductor layer, a gate dielectric layer is arranged on the semiconductor layer, along a direction D1 perpendicular to the substrate, the orthographic projection of the gate dielectric layer is located within the range of the orthographic projection of the semiconductor layer, a gate electrode is arranged on the upper surface of the gate dielectric layer, and the region on the upper surface of the semiconductor layer where no structure is arranged is a P-type doped region; in the present embodiment, P-type doping is realized in the active region of the device, which greatly reduces the contact resistance between the metal and the semiconductor, improves the mobility of the holes, and the subthreshold swing is close to the theoretical limit of 60mV / decade, which points out the direction for future high-performance electronic products.

[0033] It should be noted that Figure 1 The illustrated embodiment only schematically shows the positional relationship of the various film layers and does not represent their actual sizes.

[0034] In an optional embodiment of the present invention, the material of the semiconductor layer is either WSe2 or MoSe2.

[0035] In an optional embodiment of the present invention, the material of the semiconductor layer is a single layer of WSe2;

[0036] Along a direction D1 perpendicular to the substrate, the thickness of the semiconductor layer is 0.6-0.8 nm. Optionally, the thickness of the semiconductor is 0.7 nm.

[0037] In this embodiment, WSe2 is a layered semiconductor with an indirect band gap of about 1.2 eV. WSe2 itself has a natural P-type conductivity, which is due to its band structure making holes easily become the main carriers. In addition, P-type doping can further enhance the hole transport ability of WSe2, reduce the subthreshold swing and increase the on-state current of the device.

[0038] In an optional embodiment of the present invention, the material of the gate dielectric layer is any one of h-BN, Si3N4, HfO2, Al2O3 or ZrO2.

[0039] In an optional embodiment of the present invention, the materials of the source electrode and the drain electrode are both Pd and Au.

[0040] In this embodiment, the source and drain materials are selected from Pd and Au, so that the source and drain form good ohmic contacts with the semiconductor layer, reduce contact resistance, and increase operating current. It should be noted that in this embodiment, the source and drain materials are selected from Pd and Au, which can overcome the defect that WSe2 is often difficult to form an ideal ohmic contact when in contact with most metal electrodes due to its semiconductor properties and high work function, and usually forms a Schottky contact.

[0041] Based on the same inventive concept, see Figure 2 , Figure 2 The present invention further provides a method for preparing a p-type field effect transistor based on a single layer of tungsten diselenide, which is used to prepare the p-type field effect transistor based on a single layer of tungsten diselenide provided in the above embodiment of the present invention. The embodiments of the field effect transistor are referred to above and will not be described in detail here. The preparation method comprises:

[0042] S101, providing a substrate.

[0043] Specifically, the substrate may be intrinsic silicon with a thickness of 285 nm.

[0044] S102 , epitaxially growing a semiconductor layer on the upper surface of the middle region of the substrate.

[0045] Specifically, 380-420 mg of selenium powder is placed in a first quartz boat, and 90-110 mg of tungsten trioxide is placed in a second quartz boat;

[0046] The substrate is inverted on the second quartz boat, and the temperature of the first quartz boat is raised to 260-300°C and the temperature of the second quartz boat is raised to 900-940°C by chemical vapor deposition. At the same time, a mixed gas of hydrogen and argon is introduced, with a hydrogen flow rate of 28-32sccm and an argon flow rate of 280-320sccm. The growth time is 9-11 minutes to obtain a semiconductor layer.

[0047] In this embodiment, a single-layer tungsten diselenide thin film is directly grown on a substrate by chemical vapor deposition, without the need for transfer and other related operations. The obtained semiconductor layer does not contain impurities, thereby ensuring excellent electrical properties of the device.

[0048] S103, depositing metal on the upper surface of the two side regions of the substrate to form a source electrode and a drain electrode respectively, wherein the source electrode and the drain electrode are both connected to the semiconductor layer; annealing the source electrode and the drain electrode to form an ohmic contact with the semiconductor layer.

[0049] Specifically, polymethyl methacrylate is dripped on the upper surface of the two side regions of the substrate, and the coating is spread on a coating machine at a speed of 2800 to 3200 r / min for 55 to 65 seconds; and baked on a heating table at 90 to 110° C. for 80 to 100 seconds;

[0050] After exposure by electron beam lithography, the substrate is placed in a developer for 80 to 100 seconds, then soaked and cleaned with an isopropyl alcohol solution, and dried with nitrogen gas to form a source region and a drain region.

[0051] Using an electron beam evaporation process, metal Pd and Au are deposited in the source region and the drain region, and then placed in an acetone solution for stripping to obtain a source electrode and a drain electrode; optionally, the thickness of the source electrode and the drain electrode is 30 to 40 nm.

[0052] S104, depositing a gate dielectric layer on the upper surface of the semiconductor layer.

[0053] Specifically, the thickness of the gate dielectric layer is 15-20 nm.

[0054] S105 , depositing a gate electrode on the upper surface of the gate dielectric layer.

[0055] Specifically, a photolithography process is used to form a gate region, and a Pt metal with a thickness of 180 to 220 nm is deposited on the gate region by an electron beam evaporation process, and then placed in a stripping solution to form a gate by stripping; optionally, the thickness of the gate is 100 to 200 nm.

[0056] S106. In a nitrogen atmosphere, nitrogen dioxide is introduced and the temperature is maintained at 140-150° C. for 8-12 minutes to obtain a P-type doped region between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.

[0057] Specifically, in the quartz tube, a central control pump is used to evacuate the vacuum degree in the quartz tube to less than 10 mtoor, and nitrogen is introduced into the quartz tube at a flow rate of 650 to 750 sccm for 2 to 4 minutes;

[0058] Nitrogen dioxide is introduced into the quartz tube at a flow rate of 45 to 55 sccm, the temperature is raised to 140 to 150°C, maintained for 8 to 12 minutes, and in a nitrogen atmosphere, a P-type doped region between the source and the semiconductor layer, and between the drain and the semiconductor layer is obtained.

[0059] In this embodiment, the NO2 exposure doping method is used. The principle of this method is to use the chemical adsorption of NO2 on the surface of tungsten diselenide. NO2 is chemically adsorbed on the surface of WSe2 and a large number of defect sites (such as selenium vacancies) to form a stable WSe2. 2-x-y O x N y The doping concentration can be dynamically adjusted by the time the device is exposed to the NO2 environment, and the highest hole concentration can reach 1×10 19 cm -3 The device is exposed to a NO2 environment, thereby performing P-type doping on the active region of the device, while the region protected by the gate dielectric is the intrinsic region, thereby realizing a P-type field effect transistor. The device provided in this embodiment improves the mobility of holes and reduces the subthreshold swing of the device, thereby reducing the power consumption of the device and improving the switching speed.

[0060] In an optional embodiment of the present invention, a p-type field effect transistor based on a single-layer tungsten diselenide is prepared by the following process, specifically:

[0061] S1. Provide a substrate and ultrasonically clean the substrate.

[0062] Specifically, Si / SiO2 with a thickness of 285 nm was selected, and ultrasonic cleaning was performed using acetone, alcohol, and deionized water in sequence. The cleaning time was 10 min, 10 min, and 5 min, respectively, and the surface was dried using nitrogen gas.

[0063] S2. Growing a semiconductor layer.

[0064] Specifically, 400 mg of selenium powder was weighed and put into the first quartz boat, 100 mg of tungsten trioxide was weighed and put into the second quartz boat, the cleaned substrate was inverted on the second quartz boat, and the first quartz boat and the second quartz boat were put into the chemical vapor deposition system.

[0065] Turn on the chemical vapor deposition system and increase the temperature. The heating temperature of the second quartz boat is set to 920°C, and the heating temperature of the first quartz boat is set to 280°C. At the same time, a mixed gas of hydrogen and argon is introduced into the system. The flow rate of hydrogen is 30sccm, and the flow rate of argon is 300sccm. The growth time is 10 minutes. After the growth is completed, take out the sample to obtain a single-layer tungsten diselenide film, i.e., a semiconductor layer.

[0066] S3. Deposit source and drain electrodes.

[0067] Specifically, polymethyl methacrylate (PMMA) was dropped on the surface of a silicon wafer with a single layer of tungsten diselenide grown on it, and the sample was spun on a 3000r / min spun coater for 60 seconds, and baked on a 100°C heating table for 90 seconds. Electron beam lithography (EBL) was used for exposure, and then the exposed sample was placed in a developer for 90 seconds, and then soaked and cleaned with an isopropyl alcohol solution, and dried with nitrogen gas to obtain the source region and the drain region.

[0068] Subsequently, an electron beam evaporation system (E-Beam) was used to deposit metal in the source and drain regions, and Pd / Au metal with a thickness of 40nm / 30nm was deposited. The deposited metal sample was placed in an acetone solution for stripping, and the source and drain electrodes were formed after stripping.

[0069] S4, preparing ohmic contacts between the source electrode, the drain electrode and the semiconductor layer.

[0070] The sample was placed in a rapid annealing furnace, set at 500°C, and annealed in a N2 environment for 1 min to form an ohmic contact.

[0071] S5. Prepare a gate dielectric layer.

[0072] Specifically, an atomic layer deposition (ALD) technique is used to deposit a 20 nm ZrO2 film in the gate dielectric region, wherein the deposition precursors are water and tetrazirconium, and the deposition temperature is set at 120°C.

[0073] S6. Prepare a gate.

[0074] Specifically, a photolithography process is used to form a gate region, and then a Pt metal with a thickness of 200 nm is deposited on the gate region by an electron beam evaporation system (E-Beam), and then placed in a stripping solution to form a gate electrode by stripping.

[0075] S7 and NO2 are used for P-type doping.

[0076] Specifically, the sample is placed in a quartz tube, and a vacuum pump is used to draw the vacuum degree in the quartz tube to below 10 mtorr, and 700 sccm of N2 is introduced into the quartz tube for 3 minutes to ensure that the quartz tube is filled with N2. Subsequently, NO2 is slowly introduced into the quartz tube at a flow rate of 50 sccm, and at the same time, the center position of the sample is heated to 150°C for 10 minutes. After completion, the sample is taken out under the protection of N2 to obtain a NO2-doped P-type field effect transistor device.

[0077] In an optional embodiment of the present invention, the p-type field effect transistor based on the single-layer tungsten diselenide provided in the above embodiment is simulated through a simulation experiment, specifically:

[0078] See also Figure 3 , Figure 3 : This is a schematic diagram of the transfer characteristic curve of a p-type field effect transistor based on a single-layer tungsten diselenide provided by an embodiment of the present invention. The field effect transistor based on a single-layer tungsten diselenide is modeled and simulated using TCAD (semiconductor process simulation and device simulation tool) software, wherein the hole concentration in the doped region of the device is set to 1×10 16 cm -3 The gate dielectric is set to ZrO2 with a thickness of 20nm, the gate uses Schottky contact, and the source and drain use ohmic contact. After modeling, the transfer characteristic curve of the device is derived using the electrical characteristic simulation tool. Figure 3 It can be seen that the device is in the on state under negative gate voltage and in the off state under positive gate voltage, indicating that the device is P-type. The off-state current is close to 0A, while the on-state current is close to 10 -8 The subthreshold swing is close to 60mV / decade, indicating that the device has extremely high switching speed and extremely low power consumption.

[0079] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0080] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0081] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A p-type field effect transistor based on a single layer of tungsten diselenide, characterized in that: include: substrate; A semiconductor layer, located on the upper surface of the middle region of the substrate; A source electrode and a drain electrode are located on the upper surface of the two side regions of the substrate, the source electrode and the drain electrode are respectively located on the two sides of the semiconductor layer and are adjacent to the semiconductor layer; a P-type doped region is provided between the source electrode and the semiconductor layer, and between the drain electrode and the semiconductor layer; A gate dielectric layer, located on the upper surface of the semiconductor layer; The gate is located on the upper surface of the gate dielectric layer.

2. The p-type field effect transistor based on a single layer of tungsten diselenide according to claim 1, characterized in that: The material of the semiconductor layer is either WSe2 or MoSe2.

3. The p-type field effect transistor based on a single layer of tungsten diselenide according to claim 1, characterized in that: The material of the semiconductor layer is a single layer of WSe2; Along the direction perpendicular to the substrate, the thickness of the semiconductor layer is 0.6-0.8 nm.

4. The p-type field effect transistor based on a single layer of tungsten diselenide according to claim 1, characterized in that: The material of the gate dielectric layer is any one of h-BN, Si3N4, HfO2, Al2O3 or ZrO2.

5. The p-type field effect transistor based on a single layer of tungsten diselenide according to claim 1, characterized in that: The materials of the source electrode and the drain electrode are both Pd and Au.

6. A method for preparing a p-type field effect transistor based on a single layer of tungsten diselenide, for preparing a p-type field effect transistor based on a single layer of tungsten diselenide as claimed in any one of claims 1 to 5, characterized in that: include: providing a substrate; epitaxially growing a semiconductor layer on the upper surface of the middle region of the substrate; Depositing metal on the upper surface of the two side regions of the substrate to form a source electrode and a drain electrode respectively, wherein the source electrode and the drain electrode are both connected to the semiconductor layer; annealing the source electrode and the drain electrode to form an ohmic contact with the semiconductor layer; Depositing a gate dielectric layer on the upper surface of the semiconductor layer; Depositing a gate on the upper surface of the gate dielectric layer; In a nitrogen atmosphere, nitrogen dioxide is introduced and the temperature is maintained at 140-150° C. for 8-12 minutes to obtain a P-type doped region between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.

7. The method for preparing a p-type field effect transistor based on a single-layer tungsten diselenide according to claim 6, characterized in that: Epitaxially growing a semiconductor layer on the upper surface of the middle region of the substrate, comprising: Put 380-420 mg of selenium powder into the first quartz boat, and put 90-110 mg of tungsten trioxide into the second quartz boat; The substrate is inverted on top of the second quartz boat, and the temperature of the first quartz boat is raised to 260-300°C and the temperature of the second quartz boat is raised to 900-940°C by chemical vapor deposition. At the same time, a mixed gas of hydrogen and argon is introduced, the flow rate of the hydrogen is 28-32sccm, the flow rate of the argon is 280-320sccm, and the growth time is 9-11min to obtain the semiconductor layer.

8. The method for preparing a p-type field effect transistor based on a single-layer tungsten diselenide according to claim 6, characterized in that: Depositing metal on the upper surface of the two side regions of the substrate to form a source electrode and a drain electrode respectively, wherein the source electrode and the drain electrode are both connected to the semiconductor layer; annealing the source electrode and the drain electrode to form an ohmic contact with the semiconductor layer, including: Add polymethyl methacrylate to the upper surface of the two side regions of the substrate, and spread the coating on a coating machine at a speed of 2800 to 3200 r / min for 55 to 65 seconds; bake on a heating table at 90 to 110° C. for 80 to 100 seconds; After exposure by electron beam lithography, the substrate is placed in a developer for 80 to 100 seconds, then soaked and cleaned with an isopropyl alcohol solution, and dried with nitrogen gas to form a source region and a drain region. The electron beam evaporation process is used to deposit metal Pd and Au in the source region and the drain region, and then the metals are placed in an acetone solution for stripping to obtain a source electrode and a drain electrode.

9. The method for preparing a p-type field effect transistor based on a single-layer tungsten diselenide according to claim 6, characterized in that: Depositing a gate on the upper surface of the gate dielectric layer includes: The gate region is formed by using a photolithography process, and a Pt metal with a thickness of 180 to 220 nm is deposited on the gate region by an electron beam evaporation process, and then placed in a stripping solution to form a gate by stripping.

10. The method for preparing a p-type field effect transistor based on a single-layer tungsten diselenide according to claim 6, characterized in that: In a nitrogen atmosphere, nitrogen dioxide is introduced, the temperature is maintained at 140-150° C., and maintained for 8-12 minutes to obtain a P-type doped region between the source electrode and the semiconductor layer, and between the drain electrode and the semiconductor layer, including: In the quartz tube, use a central control pump to draw the vacuum degree in the quartz tube to below 10 mtoor, and introduce nitrogen into the quartz tube at a flow rate of 650-750 sccm for 2-4 minutes; Nitrogen dioxide is introduced into the quartz tube at a flow rate of 45 to 55 sccm, the temperature is raised to 140 to 150° C., maintained for 8 to 12 minutes, and a P-type doped region between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer is obtained in a nitrogen atmosphere.

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