Semiconductor devices and constant current diode circuits

Abstract

This disclosure relates to semiconductor devices and constant current diode circuits. A semiconductor device includes a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a doped channel layer, a gate insulating layer, a gate contact, and a source contact. The drift layer is disposed on a substrate and has an upper surface. A junction field-effect transistor region is defined between adjacent first doped regions. The second doped regions and the first doped regions define a plurality of channel regions along the upper surface. The doped channel layer is disposed adjacent to the upper surface and extends across the drift layer between the second doped regions. The gate insulating layer is disposed on the upper surface. The gate contact contacts the gate insulating layer. The source contact contacts the plurality of second doped regions and the plurality of third doped regions.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a constant current diode circuit. Background Technology

[0002] A constant current diode (CRD) is a semiconductor device that maintains a constant current value within a certain operating voltage range. Its output current ranges from a few milliamperes (mA) to tens of milliamperes, capable of driving a load. It offers advantages such as simple circuit structure, high reliability, and small size. Furthermore, the constant current diode features a wide operating range and high dynamic resistance, enabling the circuit structure to achieve constant current characteristics and achieving low power supply variability, low load variability, and low ripple voltage through a single diode. The inflection point voltage of a constant current diode refers to the voltage at which the current begins to increase rapidly under forward bias.

[0003] However, current constant current diode circuits still suffer from problems such as high inflection point voltage, unstable current characteristics at high temperatures, small operating current range, and difficulty in adjusting the positive or negative trend of the temperature coefficient. How to improve the above-mentioned shortcomings of constant current diode circuits is a problem that those skilled in the art want to solve. Summary of the Invention

[0004] The main purpose of this invention is to solve the problems of high inflection point voltage, unstable current characteristics at high temperatures, small operating current range, and difficulty in adjusting the positive and negative tendencies of the temperature coefficient of constant current diodes.

[0005] This invention discloses a semiconductor device including a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a doped channel layer, a gate insulating layer, a gate contact, and a source contact. The drift layer is disposed on a substrate and has a first conductivity type and an upper surface. The first doped regions are disposed in the drift layer adjacent to the upper surface and spaced apart from each other. Each first doped region has a second conductivity type opposite to the first conductivity type. The first doped regions and the drift layer form a plurality of first pn junctions. A junction field-effect transistor region is defined between adjacent first doped regions. The first doped regions have a depth between 3 μm and 5 μm and a depth between 8 μm and 16 cm. -3 With 2e15cm -3The doping concentration is within the range of the first doped region. The second doped region is disposed within the first doped region, the second doped region has the first conductivity type, the second doped region and the first doped region form a plurality of second pn junctions, and a plurality of channel regions are defined along the upper surface between the first pn junctions and the second pn junctions. The second doped region has a depth between 0.4 μm and 1 μm and a doping concentration between 2e19 cm. -3 With 2e17cm -3 The doping concentration is within the range of the second doped region. The third doped region is disposed within the second doped region, and the plurality of third doped regions have the second conductivity type. The doped channel layer is disposed adjacent to the upper surface and extends across the drift layer between the second doped regions, and the doped channel layer has a doping concentration within the range of the second doped region. and The thickness is between 1e17cm. -3 With 1e16cm -3 The doping concentration is within a range of 1 μm to 6 μm, and the width is within a range of 1 μm to 6 μm. A gate insulating layer is disposed on the upper surface and extends over a portion of the junction field-effect transistor region, the plurality of channel regions, and the plurality of second doped regions. A gate contact contacts the gate insulating layer. A source contact contacts the plurality of second doped regions and the plurality of third doped regions.

[0006] In one embodiment, a source contact is also included, which contacts a bottom surface of the substrate.

[0007] In one embodiment, a knee voltage of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

[0008] In one embodiment, a peak current of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

[0009] In one embodiment, a temperature coefficient of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

[0010] In one embodiment, the semiconductor device has a peak current greater than 500mA.

[0011] In one embodiment, the semiconductor device has a temperature coefficient between -0.01% and +0.01%.

[0012] In one embodiment, the semiconductor device is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0013] The present invention also discloses a constant current diode circuit, comprising the semiconductor device as described above. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0015] Figure 2 The IV curve characteristics are shown in the experimental examples of this invention.

[0016] Figure 3 The IV curve characteristics are shown in the experimental examples of this invention.

[0017] Figure 4 The IV curve characteristics of the experimental and comparative examples of the present invention are shown.

[0018] Figure 5A The IV curve characteristics are shown in the experimental examples of this invention.

[0019] Figure 5B The IV curve characteristics are for a comparative example of the present invention. Detailed Implementation

[0020] It should be understood that the thicknesses of each layer and region have been exaggerated for clarity. It should also be understood that when an element such as a layer, portion, region, or substrate is referred to as "on," "covering," or "above" another element, it can be directly on, directly covering, or directly above that element; or there may be other elements in between. Conversely, when an element is referred to as "directly on," "directly covering," or "directly above" another element, there are no intermediate elements. Similarly, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements between them.

[0021] Relative terms such as "above," "below," "above," "below," "horizontal," "lateral," or "vertical" may be used here to describe the relationship between one element, layer, portion, or region in the figure and another element, layer, portion, or region. It should be understood that these terms, along with those described above, are intended to cover different orientations of elements other than those depicted in the figures. Several embodiments will be described below, with the same structural features identified by the same or similar reference numerals in the figures. As used herein, "lateral" or "lateral direction" should be understood to mean a direction or extent that extends generally parallel to the lateral extent of the semiconductor element, thus extending generally parallel to its surface or side. Conversely, the term "thickness direction" is understood to mean a direction that is generally perpendicular to its surface or side and therefore perpendicular to the lateral direction.

[0022] Throughout this document, the terminology used in the description of various embodiments is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates or intentionally limits the number of elements, the singular forms "a" and "the" used herein may also include plural forms. Furthermore, the terms "comprising" and / or "including" as used herein indicate the presence of the described features, elements, and / or components, but do not preclude the addition or presence of one or more other features, elements, components, and / or groups thereof. Indefinite and definite articles should include both plural and singular forms unless the opposite is clearly apparent from the context.

[0023] The terms "first conductivity type" and "second conductivity type" refer to opposite conductivity types, such as n-type or p-type. However, the descriptions and figures of each embodiment herein also include complementary embodiments thereof, and the same numbers denote the same elements.

[0024] See Figure 1This invention discloses a semiconductor device 100, which includes a substrate 110, a drift layer 120, a plurality of first doped regions 130, a plurality of second doped regions 140, a plurality of third doped regions 150, a doped channel layer 160, a gate insulating layer 170, a gate contact 181, a source contact 182, and a source contact 183. In one example, the substrate 110 is made of silicon (Si). The first doped regions 130 can be formed using techniques such as epitaxy, diffusion, ion implantation, or chemical vapor deposition (CVD). For example, a p-type layer can be continuously grown directly on an n-type drift layer in an MOCVD reactor, or aluminum ions can be implanted into the n-type drift layer as a dopant using ion implantation technology to form a reverse-doped p-type region adjacent to a major surface of the drift layer 120. Similarly, the second doped region 140 and the third doped region 150 can be formed by techniques such as epitaxial growth, diffusion, ion implantation or vapor phase doping.

[0025] The substrate 110 has a top surface 111 and a bottom surface 112. The drift layer 120 is disposed on the top surface 111 of the substrate 110 and has a first conductivity type (such as n-type). The drift layer 120 includes an upper surface 121.

[0026] The first doped regions 130 are disposed in the drift layer 120 adjacent to the upper surface 121 and spaced apart from each other. Specifically, these first doped regions 130 are doped downwards from the upper surface 121 into the drift layer 120. Each first doped region 130 has a second conductivity type (e.g., p-type). The first doped regions 130 and the drift layer 120 form a plurality of first pn junctions PN1, and a junction field-effect transistor region J is defined between adjacent first doped regions 130. In this embodiment, the first doped regions 130 have a depth D1 between 3 μm and 5 μm and a depth between 8 μm and 16 cm. -3 With 2e15cm -3 The doping concentration is within the range between these values.

[0027] The second doped region 140 is disposed within the first doped region 130. The second doped region has the first conductivity type. The second doped region 140 and the first doped region 130 form a plurality of second pn junctions PN2, and the second doped region 140 and the first doped region 130 define a plurality of channel regions CH along the upper surface 121 between the first pn junctions PN1 and the second pn junctions PN2. In this embodiment, the second doped region 140 has a depth D2 in the range of 0.4 μm to 1 μm and a depth between 2e19 cm. -3 With 2e17cm-3 The doping concentration is within the range between these values.

[0028] The third doped region 150 is disposed in the second doped region 140 and contacts the first doped region 130 and the second doped region 140, and the plurality of third doped regions 150 have the second conductivity type.

[0029] The doped channel layer 160 is disposed adjacent to the upper surface 121 and extends across the drift layer 120 between the second doped regions 140. The doped channel layer 160 is formed by downward doping from the upper surface 121 of the drift layer 120 between the second doped regions 140 and across the drift layer 120. In this embodiment, the doped channel layer 160 has a depth between... and The thickness T is between 1e17cm. -3 With 1e16cm -3 The doping concentration is within a range of 1 μm and the width W is within a range of 6 μm.

[0030] The gate insulating layer 170 is disposed on the upper surface 121 of the drift layer 120, and the gate insulating layer 170 extends and contacts the junction field-effect transistor region J, the channel regions CH and a portion of the second doped regions 140.

[0031] In one example, the depth D1 of the first doped region 130 and the depth D2 of the second doped region 140 are the vertical distances from the upper surface 121 to the bottom of the first doped region 130 and the second doped region 140, respectively. The thickness T of the doped channel layer 160 is also the vertical distance from the upper surface 121 to the bottom of the doped channel layer 160. The width W of the doped channel layer 160 is the horizontal distance between adjacent second doped regions 140.

[0032] The gate contact 181 contacts the gate insulating layer 170 and is a contact structure for connecting the gate to external circuitry. The source contact 182 contacts the second doped regions 140 and the third doped regions 150 and is a contact structure for connecting the source to external circuitry. The source contact 183 contacts the bottom surface 112 of the substrate 110 and is a contact structure for connecting the drain to external circuitry. In one example, the gate contact 181, the source contact 182, and the source contact 183 may be made of a metal or alloy material, such as platinum, nickel, aluminum, or a combination thereof.

[0033] In this invention, a knee voltage, a peak current, and a temperature coefficient of the semiconductor device 100 are adjusted according to the thickness T of the doped channel layer 160. In one example, the peak current is greater than 500 mA, and in another example, the temperature coefficient is between -0.01% and +0.01%. In this embodiment, the semiconductor device 100 is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET) and can be applied to a constant current diode circuit.

[0034] When applied to this constant current diode circuit, when a bias voltage is applied, current flows through the doped channel layer 160. When the bias voltage rises to the channel cutoff voltage (Vk), a constant current state is achieved (i.e., the current no longer increases with the voltage but remains at a constant value). In this invention, by first setting the doping concentration conditions of the first doped region 130 and the second doped region 140, and under these conditions, finding specific parameters of the structure and doping concentration of the doped channel layer 160, the following effects are achieved: enabling the semiconductor device 100 to maintain a close constant current at different operating temperatures; reducing the inflection point voltage of the semiconductor device 100, thus saving on the circuit's own component consumption; increasing the range of constant current values; and adjusting the positive or negative trend of the temperature coefficient of the semiconductor device 100. In one example, the semiconductor device 100 can have a close constant current when the operating temperature is between 25°C and 150°C, and the range of the constant current of the semiconductor device 100 can be between 0.1mA and 500mA. Specifically, the doped channel layer 160 is a back-end process, which is less susceptible to the influence of other processes, thus having advantages in manufacturing, making it easier to control the process range, and reducing the challenges of mass production.

[0035] Figure 2 The IV curve characteristics of different experimental examples are shown. The applied voltage was 5V, the operating temperature of the experimental examples was 25℃, and the voltage as the current increased were respectively... Figure 2 Curves E1, E2, and E3 are shown in the figures. In experimental examples E1, E2, and E3, the depth D1 of the first doped region 130 is approximately 3.5 μm and the doping concentration is approximately 3e16 cm⁻¹. -3 The depth D2 of the second doped region 140 is approximately 0.5 μm and the doping concentration is approximately 5e18 cm⁻¹. -3 The width W of the doped channel layer 160 is approximately 5 μm and the doping concentration is approximately 5e16 cm⁻¹. -3 Furthermore, the thickness T of the doped channel layer 160 in experimental examples E1, E2, and E3 are respectively...

[0036] The thickness T of the doped channel layer 160 is At that time, the inflection point voltage of experimental example E1 was 2.8V, and the temperature coefficient was -0.07%; the thickness T of the doped channel layer 160 was... At that time, the inflection point voltage of experimental example E2 was 2.3V, and the temperature coefficient was -0.05%; the thickness T of the doped channel layer 160 was... At that time, the inflection point voltage of experimental example E3 was 2.0V, and the temperature coefficient was 0.00%.

[0037] By measuring the peak current (constant current) of the semiconductor device 100 at a voltage of 5V, it can be found that the thickness T of the doped channel layer 160 is... At that time, the peak current of experimental example E1 was 119.87 mA, and the thickness T of the doped channel layer 160 was... At that time, the peak current of experimental example E2 was 71.82 mA, and the thickness T of the doped channel layer 160 was... At that time, the peak current of experimental example E3 was 80.13mA.

[0038] Depend on Figure 2 The IV curve shows that the inflection point voltage of the semiconductor device 100 can be adjusted by controlling the thickness T of the doped channel layer 160. The thickness T of the doped channel layer 160 is positively correlated with the inflection point voltage; that is, the thicker the thickness T, the higher the inflection point voltage, and the thinner the thickness T, the lower the inflection point voltage. In addition, the positive or negative trend of the temperature coefficient can also be adjusted to meet the application requirements.

[0039] Figure 3 The IV curve characteristics of different experimental examples are shown. The applied voltage was 10V, the operating temperature of the experimental examples was 25℃, and the voltage as the current increased were respectively... Figure 3 Curves E4, E5, and E6 are shown in the figure. Experimental Examples E4, E5, and E6 are devices with the same structure as Experimental Examples E1, E2, and E3, meaning the width, depth, and doping concentration of the first doped region 130, the second doped region 140, and the doped channel layer 160 are the same. However, the thickness T of the doped channel layer 160 in Experimental Examples E4, E5, and E6 are respectively...

[0040] In experimental examples E4, E5, and E6, the inflection point voltage was 1.8V, while the thickness T of the doped channel layer 160 was... At that time, the temperature coefficient of experimental example E4 was -0.12%; the thickness T of the doped channel layer 160 was... At that time, the temperature coefficient of experimental example E2 was -0.09%; the thickness T of the doped channel layer 160 was... At that time, the temperature coefficient of experimental example E3 was -0.06%.

[0041] Further measurements were taken of the peak current (constant current) of the semiconductor device 100 at a voltage of 5V, and the thickness T of the doped channel layer 160 was determined. At that time, the peak current of experimental example E4 was 556 mA, and the thickness T of the doped channel layer 160 was... At that time, the peak current of experimental example E5 was 551 mA, and the thickness T of the doped channel layer 160 was... At that time, the peak current of experimental example E6 was 490mA. Therefore, the semiconductor device 100 according to the embodiment of the present invention can obtain a high constant current of more than 500mA.

[0042] Depend on Figure 3 The IV curves show that, with the inflection point voltage constant, the peak current of the semiconductor device 100 can be adjusted by controlling the thickness T of the doped channel layer 160. The thickness T of the doped channel layer 160 is positively correlated with the peak current; that is, the thicker the thickness T, the higher the peak current, and the thinner the thickness T, the lower the peak current. By increasing the thickness T of the doped channel layer 160, the peak current value can be increased to greater than 500 mA, as shown in curves E4 and E5.

[0043] Figure 4 The IV curve characteristics of other experimental examples and comparative examples are shown. Experimental examples E7, E8, and E9 were tested at operating temperatures of 25°C, 75°C, and 125°C, respectively. Comparative examples C1, C2, and C3 were tested at operating temperatures of 25°C, 75°C, and 125°C, respectively. The voltages as current increases are as follows: Figure 4 Curves E7, E8, E9, C1, C2, and C3 are shown in the figure.

[0044] As can be seen from Experimental Examples E7, E8, and E9, the IV curves at different temperatures are similar, indicating that the temperature coefficient of the experimental examples is relatively low (i.e., the relative rate of change of the peak current at that operating temperature is small), approximately -0.021%. In contrast, the temperature coefficients of Comparative Examples C1, C2, and C3 are relatively high, approximately -0.325%.

[0045] Figure 5A as well as Figure 5B The IV curve characteristics of other experimental examples E10 and E11, and comparative examples C4 and C5 are shown respectively. Figure 5A It is a semiconductor device according to the present invention. Figure 5BThis refers to semiconductor devices based on other conditions. In experimental examples E10 and E11, the depth D1 of the first doped region 130 is approximately 4 μm and the doping concentration is approximately 8e15 cm⁻¹. -3 The depth D2 of the second doped region 140 is approximately 0.7 μm and the doping concentration is approximately 5e18 cm⁻¹. -3 The width W of the doped channel layer 160 is approximately 5 μm and the doping concentration is approximately 5e16 cm⁻¹. -3 In experimental examples E10 and E11, the thickness T of the doped channel layer 160 is divided into... and The difference between comparative examples C4 and C5 and experimental examples E10 and E11 is that the thickness T of the doped channel layer 160 in comparative examples C4 and C5 is divided into... and

[0046] The inflection point voltages of experimental examples E10 and E11 were 2.3V and 2.0V, respectively, with temperature coefficients of -0.05% and 0.00%, respectively; the inflection point voltages of comparative examples C4 and C5 were 6.0V and 5.5V, respectively, with temperature coefficients of -0.17% and -0.14%, respectively.

[0047] In addition to previous experiments and comparisons, to verify the present invention, it was discovered that the channel cutoff voltage (Vk) of the constant current diode circuit can be appropriately adjusted by changing the width W of the doped channel layer 160. Furthermore, constant current diode circuits with the same parameters but different widths W of the doped channel layer 160 were tested. The depth D1 of the first doped region 130 is approximately 4 μm and the doping concentration is approximately 9e15 cm⁻¹. -3 The depth D2 of the second doped region 140 is approximately 0.5 μm and the doping concentration is approximately 5e18 cm⁻¹. -3 The width W of the doped channel layer 160 is shown in Table 1, and the doping concentration is approximately 5e16cm. -3 .

[0048] Table 1 shows the channel cutoff voltage (Vk) for different widths W of the doped channel layer 160, where the width W is in micrometers (μm) and the measured input current is in milliamperes (mA). In experimental examples #1 to #13, the temperature coefficient (TC) is in the range of 0.000% to -0.050%, exhibiting good thermal stability; the channel cutoff voltage (Vk) decreases inversely with increasing channel width.

[0049] As can be seen from the above, the semiconductor device according to the present invention has a low inflection point voltage and an excellent temperature coefficient.

[0050]

[0051] [Symbol Explanation]

[0052] 100: Semiconductor devices

[0053] 110: Substrate

[0054] 111: Top surface

[0055] 112: Bottom

[0056] 120: Drift Layer

[0057] 121: Upper surface

[0058] 130: First doped region

[0059] 140: Second doped region

[0060] 150: Third doped region

[0061] 160: Doped channel layer

[0062] 170: Gate insulating layer

[0063] 181: Gate contact

[0064] 182: Source Contact

[0065] 183: Source Contact

[0066] D1: Depth

[0067] D2: Depth

[0068] T: Thickness

[0069] W: Width

[0070] J: Junction Field-Effect Transistor Region

[0071] CH: Channel area

[0072] PN1: First pn junction

[0073] PN2: Second pn junction

[0074] E1, E2, E3, E4, E5, E6, E7, E8, E9, E10, E11, C1, C2, C3, C4, C5: Curves.

Claims

1. A semiconductor device, characterized by comprising: comprising: a drift layer disposed on a substrate, the drift layer having a first conductivity type and an upper surface; a plurality of first doped regions disposed in the drift layer adjacent the upper surface and spaced apart from one another, the first doped regions having a second conductivity type opposite the first conductivity type, the first doped regions forming a plurality of first p-n junctions with the drift layer, a junction field effect transistor region being defined between adjacent ones of the first doped regions, the first doped regions having a depth in a range between 3 microns and 5 microns, a doping concentration in a range between 8e16 cm -3 and 2e15 cm -3 . a plurality of second doped regions disposed in the first doped region, the second doped regions having the first conductivity type, the second doped regions forming a plurality of second p-n junctions with the first doped region and defining a plurality of channel regions between the first p-n junctions and the second p-n junctions along the upper surface, the second doped regions having a depth in a range between 0.4 microns and 1 micron, a doping concentration in a range between 2e19 cm -3 and 2e17 cm -3 between 2e20 cm a plurality of third doped regions disposed in the second doped regions, the plurality of third doped regions having the second conductivity type; a doped channel layer disposed adjacent the upper surface and extending across the drift layer between the second doped regions, the doped channel layer having a thickness in a range between 75 Angstroms and 90 Angstroms, a doping concentration in a range between 1e17 cm -3 and 1e16 cm -3 and a width in a range between 1 micron and 6 microns; a gate insulating layer disposed on the upper surface, the gate insulating layer extending over the junction field effect transistor region, the plurality of channel regions, and a portion of the plurality of second doped regions; a gate contact contacting the gate insulating layer; and a source contact contacting the plurality of second doped regions and the plurality of third doped regions. further comprising a source contact contacting a bottom surface of the substrate.

2. The semiconductor device according to claim 1, wherein a knee voltage of the semiconductor device is adjusted with a change in the thickness of the doped channel layer.

3. The semiconductor device according to claim 1, wherein a peak current of the semiconductor device is adjusted with a change in the thickness of the doped channel layer.

4. The semiconductor device according to claim 1, wherein a temperature coefficient of the semiconductor device is adjusted with a change in the thickness of the doped channel layer.

5. The semiconductor device according to claim 1, wherein the semiconductor device has a peak current greater than 500 milliampere.

6. The semiconductor device according to claim 1, wherein the semiconductor device has a temperature coefficient between -0.01% to +0.01%.

7. The semiconductor device according to claim 1, wherein the semiconductor device is configured as a metal oxide semiconductor field effect transistor.

8. The semiconductor device according to claim 1, wherein 9. A constant current diode circuit comprising a semiconductor device according to any one of claims 1 to 7. ​

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