Improved recessed region for junction termination extension of semiconductor devices

Abstract

The present disclosure proposes a semiconductor device including a semiconductor body, where the semiconductor body includes one or more recessed regions in a P-doped junction termination extension (JTE) region and an N + implant at the bottom of the recessed regions, where the depth of the recessed regions is less than the depth of the JTE region. A method of manufacturing such a semiconductor device is also presented.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. More particularly, the present disclosure relates to an improved recessed region for a junction termination extension (JTE) of a semiconductor device. Background Art

[0002] Most planar and trench power devices are based on one or a few n-type / p-type junctions. When the active part of the junction is toward the side of the device, very high electric fields may occur under reverse voltage bias due to the junction curvature or trench angle.

[0003] Therefore, peripheral protection, also known as edge termination, may be required. Edge termination is an important part of power devices. Passivation charge in the termination may cause reliability failures, low reverse blocking capability, and low unclamped inductive load switching (UIS) strength.

[0004] Reliable and robust high-voltage devices require effective edge termination structures to protect the device periphery, so that blocking values ​​close to the ideal 1D avalanche voltage values ​​can be achieved. Several physical limitations make the design of edge terminations in, for example, silicon carbide (SiC) quite complex. The main limitation is the low diffusion coefficient of dopant atoms inside the semiconductor. Deep junctions (greater than 1 μm) are difficult to achieve, and lateral dopant diffusion is very limited. In addition, the higher interface trap levels observed in the SiC / passivation interface relative to silicon also affect the efficiency of standard Si termination architectures in SiC power devices. Charges can accumulate at the interface, causing breakdown voltage instabilities and early failures, especially with temperature.

[0005] In bipolar transistors, there are parasitic components such as collector-base and emitter-base junction capacitances that can affect the high-frequency performance of the transistor. JTE technology involves intentionally adding lightly doped regions (usually P-type regions) near the collector or emitter junction to create a gradual transition between the highly doped and lightly doped regions. This helps reduce the capacitance at the junction, which in turn reduces the impact on the high-frequency response of the transistor. In addition, JTE distributes the electric field laterally from the active area to the edge of the die in a way that the peak field can be minimized and no lateral or terminal breakdown occurs. At the same time, the terminals should be able to resist the movement or accumulation of charge under stress testing or operating conditions.

[0006] A common termination design for SiC is the JTE. It can be used to reduce the impact of unwanted parasitic elements in the device structure and improve its performance. The breakdown voltage of the JTE region in the rectifier is highly sensitive to the doping concentration of the JTE (not limited to low p-type here). This also means that the JTE termination is sensitive to charge accumulation in the region. Summary of the invention

[0007] The summary of the aspects of the specific examples disclosed herein is as follows. It should be understood that these aspects are merely provided to the reader with a brief overview of these specific embodiments and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may encompass a combination of multiple aspects and / or aspects that may not be described.

[0008] The present disclosure is directed to overcoming the disadvantages identified in the Background section. More specifically, the present disclosure is directed to reducing the electric field in the critical interface region between the JTE and the passivation stack.

[0009] Here, the present disclosure proposes a "reverse" Kao ring structure in the JTE region, which can be formed by a dry etching step after an N+ implant. The dry etching step allows the reverse Kao ring structure to penetrate deeper into the JTE, so that the surface electric field is further reduced. In addition, since high implantation energy is not required for deep junctions, standard implantation tools can be used. The distributed N+ Kao ring structure balances the charge in the terminal and distributes the electric field, making it more capable of resisting doping and charge changes. Due to the implant dispersion, the formation of the Kao ring structure by a dry etching process allows very fine patterning without corner effects.

[0010] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method may include forming one or more recessed regions in a P-doped junction termination extension (JTE) implant of a semiconductor body. The depth of the recessed region may be less than the depth of the JTE implant. The method may also include forming an N+ implant at the bottom of the recessed region.

[0011] In one embodiment, the depth of the recessed region may be less than half the depth of the JTE implant.

[0012] In one embodiment, the method may include further forming an N+ implant at the bottom and sidewalls of the recessed region.

[0013] In one embodiment, the method may include forming an N+ implant by depositing a screen oxide layer in the recessed region and polymer spacer along the sidewalls defined by previous photolithography and etching steps.

[0014] In one embodiment, the method may include forming a plurality of N+ implants with increasing doping at the bottom of the recessed region.

[0015] In one embodiment, the method may include forming a plurality of N+ implants using a plurality of implant steps with increasing dose and energy, generating a graded doping profile wherein doping increases from the bottom of the trench to the bottom of the N+ implants.

[0016] In one embodiment, the plurality of N+ implants may be two N+ implants.

[0017] In one embodiment, the method may include forming a plurality of recessed regions having a substantially constant width and a substantially constant spacing.

[0018] In one embodiment, the method may include forming a plurality of recessed regions having increasing spacing along an outer edge of the JTE implant from an active area to a terminal end.

[0019] In one embodiment, the method may further include etching a further recessed region outside the JTE implant and near the edge of the mold in the zigzag channel, wherein the further recessed region is etched during the same process used to form the recessed region in the JTE.

[0020] In one embodiment, the method may further include forming an N+ implant at the bottom of the further recessed region during the same process used to form the N+ implant at said bottom of the recessed region.

[0021] In one embodiment, the method further includes forming a P-doped surface layer in a region between the recessed regions and a top portion of the top surface of the JTE implant.

[0022] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a semiconductor body. The semiconductor body may include one or more recessed regions in a P-doped junction termination extension JTE region. The depth of the recessed region is less than the depth of the JTE region. The semiconductor body may also include an N+ implant at the bottom of the recessed region.

[0023] In one embodiment, the N+ implant may also cover the sidewalls of the recessed region.

[0024] In one embodiment, the semiconductor device may include a plurality of N+ implants with increasing doping at the bottom of the recessed region.

[0025] In one embodiment, the semiconductor body may further include a P-doped surface layer in the region between the recessed regions.

[0026] In one embodiment, the semiconductor device is formed using a method having one or more of the above features. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings, wherein corresponding reference characters indicate corresponding parts, and wherein:

[0028] Figures 1 to 5 shows a cross-sectional side view of an exemplary embodiment of a semiconductor body;

[0029] Figure 6 schematically illustrates a semiconductor device including a semiconductor body according to an exemplary embodiment; and

[0030] Figure 7 A flow chart illustrating a method of an exemplary embodiment is shown.

[0031] The drawings are intended for illustration purposes only and are not intended to limit the scope of protection provided by the claims. DETAILED DESCRIPTION

[0032] It is readily understood that the components of the embodiments described herein and in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of various embodiments, as shown in the accompanying drawings, is not intended to limit the scope of the present disclosure but merely represents various embodiments. Although various aspects of the embodiments are shown in the accompanying drawings, unless otherwise indicated, the accompanying drawings are not necessarily drawn to scale.

[0033] The embodiments described are to be considered in all respects as illustrative and non-restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes within the equivalent meaning and range of the claims are included within their scope.

[0034] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achieved by the present disclosure should be or are any single example of the present disclosure. Rather, language about features and advantages is understood to mean that a particular feature, advantage, or characteristic described with respect to one embodiment is included in at least one embodiment of the present disclosure. Therefore, discussions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same example.

[0035] Moreover, the features, advantages and characteristics described in the present disclosure may be combined in one or more embodiments in any appropriate manner. Those skilled in the relevant art will recognize that, based on the description herein, the present disclosure may be practiced without one or more specific features or advantages of a particular embodiment. In other examples, additional features and advantages may be identified in certain embodiments that may not exist in all embodiments of the present disclosure. References to "one embodiment", "one embodiment" or similar language throughout this specification refer to specific features, structures, or features described with respect to the illustrated embodiment included in at least one embodiment of the present disclosure. Therefore, all phrases "in one embodiment", "in one embodiment" and similar language in this specification may, but not necessarily, refer to the same embodiment.

[0036] Improvements in terminal behavior can be obtained by etching recessed regions with possibly different geometries (i.e., widths and / or spacings) inside the JTE and implanting N+ implants at the bottom of the etched regions. The recessed regions have a depth less than the depth of the JTE, and in some embodiments, they can have different widths and / or spacings along the JTE. Thus, the electric field at the surface of the JTE can be diffused and reduced, and lateral doping across the same terminal can be modulated. That is, the lateral P doping profile and electric field uniformity growth in the JTE are modulated by using recessed regions whose features can be defined by layout (e.g., width and / or spacing) and / or process (e.g., depth, aspect ratio, and / or taper angle).

[0037] A continuous or segmented P-doped surface layer can be formed in the area between consecutive recessed regions with the aim of reducing the risk of surface inversion, making the termination more resistant to processes that induce high surface charge density on the JTE surface (e.g., PECVD deposition, reactive ion etching (RIE), etc.).

[0038] Figure 1 An exemplary embodiment of a semiconductor body 100 is shown including a P-doped JTE 102 having a recessed region 104 with an N+ implant 106 at the bottom of the recessed region 104. The recessed region 104 may be etched inside the P-doped JTE 102.

[0039] In one example, the P-doped layer 102 may have a doping between 3E16 cm-3 and 8E17 cm-3, preferably 1E17 cm-3, and may have a depth between 0.5 um and 1.5 um, preferably 1 um.

[0040] The recessed region 104 may have a depth less than half the depth of the JTE 102 , and preferably less than 0.5 um.

[0041] In a preferred embodiment, the recessed regions 104 have a constant width and spacing, for example, a width in the range of 0.5-1.5 um and a spacing in the range of 3-5 um, preferably a width of 1 um and a spacing of 4 um.

[0042] In another embodiment, the spacing of the recessed regions 104 is not constant and increases along the outer edge of the JTE 102 from the active area to the terminal, for example, by 50%.

[0043] A larger recessed region 108 may be etched in the die edge and sawtooth channels. This region 108 may be etched during the same process used to form the recessed region 104 in the JTE 102, and therefore, may have the same depth as these areas.

[0044] exist Figure 1In an exemplary embodiment, an N+ doped implanted region 106 is at the bottom of the recessed region 104, including a region 108 defined at the edge of the mold and acting as a channel stop layer. In one example, the N+ region 106 may have a doping between 1E18 cm-3 and 1E19 cm-3, preferably 5E18 cm-3, and may have a depth between 0.1 um and 0.3 um, preferably 0.2 um.

[0045] The sum of the depths of the recessed regions 104 including the N+ implanted region 106 in the JTE 102 is preferably less than the depth of the JTE 102 itself.

[0046] In one exemplary embodiment, the N+ implant 106 is accomplished by depositing a screen oxide layer in the recessed region and a polymer spacer along the sidewalls defined by previous photolithography and etching steps. A polymer spacer may be used to prevent the sidewalls of the recessed region from being implanted with N-type dopants.

[0047] Figure 1 The semiconductor body 100 may include a suitable passivation layer in the form of a single layer or a passivation layer stack including oxide-based and nitride-based dielectric layers (not shown in the figure). The passivation layer may cover the entire termination region.

[0048] The use of the recessed region 104 inside the JTE 102 and the shallow N+ implant 106 at the bottom of the recessed region 104 allows the electric field at the surface of the JTE where interface states exist to be reduced due to the passivation layer deposition and / or other process steps (e.g., oxidation or etching). The high electric field in the surface region with a high density of interface states can trigger the capture or emission of carriers, ultimately leading to increased leakage and unstable termination behavior due to the unbalanced operation of the JTE, especially under high bias and temperature conditions.

[0049] Advantageously, placing the N+ implant region 106 in the recessed region 104 can effectively keep the electric field away from the surface because the inverted Kao ring structure penetrates deep into the SiC. This is not possible with standard known implants.

[0050] Furthermore, the use of etched regions with possibly different widths and / or spacings allows for lateral modulation of JTE doping, where doping control along the termination region is defined by the geometry of the recessed region. Advantageously, this allows for improved and more flexible control of lateral doping relative to using standard known implantation techniques.

[0051] The N+ implant 106 inside the recessed region 104 can advantageously be implemented during the same implantation step used to form the channel stop region at the die edge, typically at least included in high voltage power devices. Thus, a semiconductor body 100 with improved JTE operation can be obtained using a device / process architecture with reduced process complexity and production cost.

[0052] Figure 2 An exemplary embodiment of a semiconductor body 200 is shown, comprising a P-doped JTE 202 having a recessed region 204 with a plurality of N+ implants 206, 207 with increasing doping at the bottom of the recessed region 204. The recessed region 204 may be etched inside the P-doped JTE 202.

[0053] and Figure 1 Similar to the example of the N+ implant 106 at the bottom of the recessed regions 104 and 108, Figure 2 In the example of FIG. 4 , a plurality of N+ implants 206 , 207 may be present at the bottom of the recessed region 204 and at the bottom of the channel stop region 208 .

[0054] The plurality of N+ implants 206, 207 are formed using multiple implant steps with increasing dose and energy, generating a graded doping profile where the doping increases from the bottom of the trench to the bottom of the N+ implant.

[0055] exist Figure 2 In the example of FIG. 2 , two N-type implant regions are formed at the bottom of the trench 204 , the first implant region 206 having a lower doping around the bottom of the trench 204 and the second implant region 207 having a higher doping deeper into the JTE 202 . Typically, the second N-type implant region 207 is adjacent to the first N-type implant region 207 .

[0056] Both N-type implanted regions 206 and 207 may have the same depth, for example 0.15 um. Both N-type implanted regions 206 and 207 may have different doping, for example, the first surface region 206 is about 1E18 cm-3, and the deeper second region 207 is about 1E19 cm-3.

[0057] Compared to Figure 1 With multiple N+ implants 206, 207 at the bottom of the recessed region 204, the graded doping profile can help to further reduce the electric field at the JTE surface and may be beneficial in reducing implant damage at the bottom of the recessed region, which is usually a serious defect due to the etching process used to form the recessed area.

[0058] Figure 3 An exemplary embodiment of a semiconductor body 300 is shown, including a P-doped JTE 302 having a recessed region 304 having a bottom of the recessed region 304 and an N+ implant 306 along the sidewalls of the recessed region. The recessed region 304 may be etched inside the P-doped JTE 302. The semiconductor body 300 and Figure 1 Similar to the semiconductor body 100 , the additional N+ dopant 306 is also implanted along the sidewalls of the recessed region 304 .

[0059] N-type dopants are implanted into the sidewalls of the recessed region, such as Figure 3 As shown, it can be beneficial to further reduce the electric field at the JTE surface because the N+ implant volume increases and also expands in the vertical direction.

[0060] Figure 4 An exemplary embodiment of a semiconductor body 400 is shown, including a P-doped JTE 402 having a recessed region 404 with an N+ implant 406 at the bottom of the recessed region 404. The recessed region 404 may be etched inside the P-doped JTE 402. Figure 1 Similar to the semiconductor body 100 of FIG. 4 , an additional P+ enriched layer 410 is defined on the surface of the JTE 402 in the region between the consecutive recessed regions 404. In this example, the P+ enriched layer 410 does not extend to the terminal end.

[0061] The P+ layer 410 may be defined by implantation. In one example, the P+ layer 408 may have a doping between 1E18 cm-3 and 1E19 cm-3, preferably 5E18 cm-3, and may have a depth between 0.1 μm and 0.3 μm, preferably 0.2 μm.

[0062] In one exemplary embodiment, the P+ layer 410 may be implanted prior to the recessed region 404 etch and subsequent N+ implant 406 .

[0063] The use of an increased P+ enriched layer 410 may advantageously reduce the risk of surface inversion and increase the electric field uniformity along the termination, thereby reducing the likelihood of early failures after zero-time or stress testing.

[0064] Figure 5 An exemplary embodiment of a semiconductor body 500 is shown, including a P-doped JTE 502 having a recessed region 504 with an N+ implant 506 at the bottom of the recessed region 504. The recessed region 504 may be doped inside the P-doped JTE 502. Figure 4 The semiconductor body 400 is similar to the semiconductor body 400, but the P+ layer 510 is only defined between the consecutive recessed regions 504 and is laterally spaced apart from them.

[0065] The peripheral region between the outer recessed region 508 and the end of the JTE 502 may ultimately not include the P+ enriched layer 510. Figure 5 In the example of FIG. 5 , the P+ layer 510 may be equivalently implanted before the recessed region 504 is etched or after the recessed region 504 is etched and the N+ dopant 506 is subsequently implanted.

[0066] A P+ surface layer, such as P+ surface layer 410 or P+ surface layer 510 , may be similarly integrated in semiconductor body 200 or semiconductor body 300 .

[0067] The present disclosure can be used in SiC semiconductors, where SiC plasma etching may involve both chemical and physical mechanisms. The etching of recessed areas 104, 204, 304, 404, 505 in SiC requires Si-C bond rupture, followed by chemical interactions of active species with silicon and carbon to generate volatile compounds. Plasma chemistry based on highly active fluorine free radicals can generate volatile SiFx and CFx products. Therefore, CF4, SF6, NF3, CBrF3, and CHF3 are typical reaction gases, although some gas mixtures are sometimes used. Usually, with the help of additional inert gases for mass transfer, fluorinated gases are used to etch SiC.

[0068] One of the characteristics of the etched recessed regions 104, 204, 304, 404, 504 is the taper angle, which is defined as the supplementary angle between the sidewall and the bottom plane of a given trench. The taper angle can be calculated using the following formula: Taper angle = tan -1 (2x(groove depth / (top groove width-bottom groove width))).

[0069] Reduction of the inert gas flow for the gas mixture during a SiC plasma etch, low power inductively coupled plasma (ICP) and / or reactive ion etch (RIE) process for etching the recessed regions 104, 204, 304, 404, 504 can be used, for example, to generate a taper angle below 90°, Figure 3 In the example of , the range between 85° and 90° is preferred. The N+ dopant 306 can be implanted through the screen oxide layer at the bottom of the recessed area and / or along the sidewalls of the recessed area without using a tilted implant step for sidewall implantation. In this case, the sidewalls are not protected by any polymer spacer during implantation, and the etching parameter variation can be used to determine the geometry of the recessed area and the doping profile of the N+ doped implanted area 306 along the sidewalls.

[0070] The present disclosure may be advantageously used in semiconductor devices such as power devices (Schottky, PN and MPS diodes, field effect transistors, JFETs), in particular such semiconductor devices comprising wide bandgap semiconductor materials such as SiC or gallium nitride (GaN). Figure 6 An abstract representation of an implementation of a semiconductor body 600 , such as semiconductor body 100 , 200 , 300 , 400 or 500 , in a semiconductor device 650 is shown.

[0071] Figure 7 An exemplary embodiment of a method 700 for fabricating a semiconductor device, such as semiconductor device 650, is shown. Dashed boxes and dashed lines describe optional steps.

[0072] In step 702, the one or more recessed regions 104, 204, 304, 404, 504 may be formed in the P-doped junction JTE implant 102, 202, 302, 402, 502 of the semiconductor body 100, 200, 300, 400, 500, 600. The depth of the recessed region may be less than the depth of the JTE implant. In an exemplary embodiment, the depth of the recessed region may be less than half the depth of the JTE implant.

[0073] In step 704, an N+ implant 106, 206, 306, 406, 506 may be formed at the bottom of the recessed region. In one exemplary embodiment, the N+ implant may be formed by depositing a screen oxide layer in the recessed region and polymer spacer along the sidewalls defined by previous photolithography and etching steps.

[0074] In step 706 , N+ implants may be further formed on the sidewalls of the recessed region.

[0075] A plurality of N+ implants, such as two N+ implants, with increasing doping may be formed at the bottom of the recessed region via step 708. In an exemplary embodiment, the plurality of N+ implants are formed using multiple implant steps with increasing dose and energy to generate a graded doping profile in which doping increases from the bottom of the trench to the bottom of the N+ implant.

[0076] Through step 710, a plurality of recessed regions having substantially constant width and substantially constant spacing may be formed. Alternatively, through step 712, a plurality of recessed regions having increasing spacing along the outer edge of the JTE implant from the active area to the terminal may be formed.

[0077] In step 714, further recessed regions may be etched near the edges of the mold outside the JTE implant and in the zigzag channels. The further recessed regions may be etched during the same process 702, 710, 712 used to form the recessed regions in the JTE.

[0078] In step 716 , during the same process 704 used to form the N+ implant at the bottom of the recessed region, an N+ implant may be formed at the bottom of the further recessed region.

[0079] In step 718, a P-doped surface layer may be formed on top of the top surface or in the region between the mesas and recessed regions of the JTE implant.

[0080] It will be appreciated that the steps may be performed in a different order, depending on the production process of the semiconductor body.

Claims

1. A method (700) for manufacturing a semiconductor device, comprising: forming (702) one or more recessed regions in a P-doped junction termination extension (JTE) implant of a semiconductor body such that a depth of the recessed regions is less than a depth of the JTE implant; as well as An N+ implant is formed (704) at the bottom of the recessed region.

2. The method of claim 1, wherein the depth of the recessed area is less than half the depth of the JTE implant.

3. The method of claim 1 or 2, wherein the method comprises further forming (706) the N+ implant at sidewalls of the recessed region.

4. A method according to any one of the preceding claims, wherein the method comprises forming the N+ implant by depositing a screen oxide layer in the recessed region and polymer spacer defined along the sidewalls by previous photolithography and etching steps.

5. The method according to any of the preceding claims, wherein the method comprises forming (708) a plurality of N+ implants of increasing doping at the bottom of the recessed region.

6. The method of claim 5, wherein the method comprises forming the plurality of N+ implants using a plurality of implant steps with increasing dose and energy, generating a graded doping profile wherein doping increases from the bottom of the trench to the bottom of the N+ implants.

7. The method according to any one of claims 1 to 6, wherein the method comprises forming (710) a plurality of recessed areas having a substantially constant width and a substantially constant spacing.

8. The method of any one of claims 1-7, wherein the method includes forming (712) a plurality of recessed regions having increasing spacing along an outer edge of the JTE implant from an active area to a terminal end.

9. The method according to any of the preceding claims, further comprising etching (714) a further recessed area outside the JTE implant and near the edge of the mold in the serrated channel, wherein the further recessed area is etched during the same process used to form the recessed area in the JTE.

10. The method of claim 9, further comprising forming (716) an N+ implant at the bottom of the further recessed region during the same process used to form the N+ implant at the bottom of the recessed region.

11. The method of any of the preceding claims, further comprising forming (718) a P-doped surface layer on top of a top surface of the JTE implant and in an area between the recessed regions.

12. A semiconductor device (650), comprising a semiconductor body (100, 200, 300, 400, 500, 600), wherein the semiconductor body comprises: One or more recessed regions (104, 204, 304, 404, 504) in a P-doped junction termination extension JTE region (102, 202, 302, 402, 502), wherein the depth of the recessed regions is less than the depth of the JTE region; and N+ implant (106, 206, 306, 406, 506) at the bottom of the recessed region.

13. The semiconductor device of claim 12, wherein the N+ implant (306) also covers sidewalls of the recessed region.

14. The semiconductor device according to any one of claims 12-13, wherein the semiconductor body further comprises a P-doped surface layer (410, 510) in the region between the recessed regions.

15. The semiconductor device of claim 12, formed using the method of any one of claims 1-11.

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