A gallium oxide-based power device and a method of manufacturing the same

Abstract

The application discloses a gallium oxide-based power device and a preparation method thereof, and relates to the field of semiconductor devices. The device comprises a cathode layer, an n-type gallium oxide substrate and an n-type gallium oxide epitaxial layer which are sequentially and layerwisely arranged from bottom to top. The device further comprises a p-type semiconductor layer, a first field limiting ring and a second field limiting ring which are sequentially and intervalwisely arranged on the n-type gallium oxide epitaxial layer and form PN junctions with the n-type gallium oxide epitaxial layer respectively; a first dielectric layer which is located on the n-type gallium oxide epitaxial layer, the second field limiting ring, the first field limiting ring and the p-type semiconductor layer; a first anode layer which is located on the p-type semiconductor layer and the first dielectric layer; in the horizontal direction, the projection of the end of the first anode layer which is far away from the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer; a second dielectric layer which is located on the first dielectric layer and the first field plate; and a second anode layer which is located on the first anode layer and the second dielectric layer. The device has a higher breakdown voltage and better voltage resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a gallium oxide-based power device and its fabrication method. Background Technology

[0002] As a typical representative of next-generation ultra-wide bandgap semiconductor materials, gallium oxide (Ga2O3) possesses an ultra-wide bandgap of approximately 4.8 eV and an ultra-high critical breakdown field strength of approximately 8 MV / cm. Therefore, theoretically, gallium oxide-based power devices can achieve a Baliga figure of merit exceeding 3000, which is four times that of gallium nitride (GaN)-based power devices and ten times that of silicon carbide (SiC)-based power devices, demonstrating promising applications with ultra-high voltage withstand capability and ultra-high power density. Furthermore, unlike SiC and GaN, two third-generation semiconductors whose substrates can only be grown via vapor phase methods, gallium oxide substrates can be grown via melt methods, thus possessing both high quality and low cost application potential.

[0003] However, due to the current lack of effective p-type doping in gallium oxide, mature termination technologies used in silicon (Si) or SiC-based power devices cannot be directly applied to gallium oxide-based power devices. This results in significant electric field concentration in the device termination region, reducing the device's breakdown voltage. Therefore, based on the unique material properties of gallium oxide, developing suitable termination technologies and fabrication processes for gallium oxide-based power devices is of great significance for improving device performance.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a gallium oxide-based power device and its fabrication method, which aims to solve the problem that the breakdown voltage of existing gallium oxide-based power devices still needs to be improved.

[0006] The technical solution of the present invention is as follows:

[0007] In a first aspect, the present invention provides a gallium oxide-based power device, wherein the gallium oxide-based power device comprises a cathode layer, an n-type gallium oxide substrate, and an n-type gallium oxide epitaxial layer, which are stacked sequentially from bottom to top;

[0008] The gallium oxide-based power device further includes:

[0009] The p-type semiconductor layer, the second field limiting ring, and the first field limiting ring located between the p-type semiconductor layer and the second field limiting ring are disposed on the n-type gallium oxide epitaxial layer at intervals, and form PN junctions with the n-type gallium oxide epitaxial layer respectively.

[0010] The first dielectric layer is continuously located on the surface of the n-type gallium oxide epitaxial layer, the surface of the second field-limiting ring, the surface of the first field-limiting ring, and a portion of the surface of the p-type semiconductor layer.

[0011] A first anode layer is continuously located on the surface of the p-type semiconductor layer and a portion of the surface of the first dielectric layer. The portion of the first anode layer located on the portion of the first dielectric layer is the first field plate. In the horizontal direction, the projection of the end of the first field plate away from the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer.

[0012] The second dielectric layer is continuously located on the surface of the first dielectric layer and on a portion of the surface of the first field plate;

[0013] The second anode layer is continuously located on the surface of the first anode layer and a portion of the surface of the second dielectric layer.

[0014] Optionally, the portion of the second anode layer located on the surface of the second dielectric layer is the second field plate; in the horizontal direction, the projection of the end of the second field plate away from the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in the projection of the second field limiting ring on the n-type gallium oxide epitaxial layer.

[0015] Optionally, the thickness of the n-type gallium oxide substrate is 50–650 μm;

[0016] The n-type gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10. 18 ~10 20 cm -3 ;

[0017] The thickness of the n-type gallium oxide epitaxial layer is 2–20 μm;

[0018] The n-type gallium oxide epitaxial layer is a lightly doped n-type gallium oxide epitaxial layer with a doping concentration of 10. 15 ~10 17 cm -3 .

[0019] Optionally, the thickness of the p-type semiconductor layer is 100-1000 nm; the p-type semiconductor layer includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride, and p-type gallium oxide.

[0020] Optionally, the thickness of the first field limiting ring is 100-1000 nm; the first field limiting ring includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride, and p-type gallium oxide.

[0021] Optionally, the thickness of the second field limiting ring is 100-1000 nm; the second field limiting ring includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride, and p-type gallium oxide.

[0022] Optionally, the thickness of the first dielectric layer is 50 nm to 2 μm; the first dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

[0023] Optionally, the thickness of the second dielectric layer is 50 nm to 2 μm; the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

[0024] Optionally, the cathode layer comprises at least one of Ti, Ni, Ag, and Au;

[0025] The thickness of the first anode layer is 20-300 nm, and the first anode layer includes at least one of Ni, Al, Au, Mo and Pt;

[0026] The thickness of the second anode layer is 200 nm to 4 μm, and the second anode includes at least one of Ti, Al, Ag and Au.

[0027] A second aspect of the present invention provides a method for fabricating a gallium oxide-based power device as described above, comprising the following steps:

[0028] Provide n-type gallium oxide substrates;

[0029] An n-type gallium oxide epitaxial layer is formed on the n-type gallium oxide substrate;

[0030] A cathode layer is formed on the surface of the n-type gallium oxide substrate on the side opposite to the n-type gallium oxide epitaxial layer;

[0031] A p-type semiconductor layer, a first field limiting ring, and a second field limiting ring are sequentially formed at intervals on the surface of the n-type gallium oxide epitaxial layer.

[0032] A first dielectric layer is formed on the surface of the n-type gallium oxide epitaxial layer, the surface of the second field limiting ring, the surface of the first field limiting ring, and a portion of the surface of the p-type semiconductor layer;

[0033] A first anode layer is formed on the surface of the p-type semiconductor layer and on a portion of the surface of the first dielectric layer; the portion of the first anode layer located on the surface of the first dielectric layer is the first field plate, and in the horizontal direction, the projection of the end of the first field plate away from the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer;

[0034] A second dielectric layer is formed on the surface of the first dielectric layer and on a portion of the surface of the first field plate;

[0035] A second anode layer is formed on the surface of the first anode layer and a portion of the surface of the second dielectric layer.

[0036] Beneficial effects: The p-type semiconductor layer, the first field limiting ring, and the second field limiting ring in this invention can uniformly distribute the electric field in the device's terminal region, i.e., equalize the surface electric field in the terminal region, thereby improving the device's breakdown voltage and withstand voltage performance. Furthermore, the extension of the first field plate onto the first field limiting ring can flatten the electric field distribution between the p-type semiconductor layer and the first field limiting ring, further equalizing the electric field, further improving the device's breakdown voltage, and further enhancing its withstand voltage performance. Simultaneously, even with a large gap between the p-type semiconductor layer and the first field limiting ring, it can still optimize the electric field, reducing dimensional accuracy requirements and processing difficulty. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of a gallium oxide-based power device in an embodiment of the present invention.

[0038] Figure 2 This is a schematic diagram of the fabrication process of a gallium oxide power device in an embodiment of the present invention, wherein (a) is a schematic diagram of forming an n-type gallium oxide epitaxial layer and a cathode layer on both sides of an n-type gallium oxide substrate, respectively; (b) is a schematic diagram of forming a p-type semiconductor layer, a first field limiting ring and a second field limiting ring sequentially and spaced apart on the surface of the n-type gallium oxide epitaxial layer; (c) is a schematic diagram of forming a first dielectric layer on the surface of the n-type gallium oxide epitaxial layer, the surface of the first field limiting ring, the surface of the second field limiting ring and a portion of the surface of the p-type semiconductor layer; (d) is a schematic diagram of forming a first anode layer on the surface of the p-type semiconductor layer and a portion of the surface of the first dielectric layer; (e) is a schematic diagram of forming a second dielectric layer on the surface of the first dielectric layer and a portion of the surface of the first field plate; and (f) is a schematic diagram of forming a second anode layer on the surface of the first anode layer and a portion of the surface of the second dielectric layer.

[0039] Figure 3 This is a schematic diagram of a gallium oxide-based power device with a field-limiting ring.

[0040] Figure 4 This is a schematic diagram of a gallium oxide-based power device with a double field plate.

[0041] Figure 5 The graphs show the surface electric field distribution of a gallium oxide-based power device with a field limiting ring, a gallium oxide-based power device with a dual field plate, and the gallium oxide-based power device in Example 1. Attached image description:

[0043] 1. Cathode layer; 2. n-type gallium oxide substrate; 3. n-type gallium oxide epitaxial layer; 4. p-type semiconductor layer; 5. First field confinement ring; 6. Second field confinement ring; 7. First dielectric layer; 8. First anode layer; 81. First field plate; 82. Second portion of the first anode layer; 9. Second dielectric layer; 10. Second anode layer; 101. Second field plate; 102. Second portion of the second anode layer. Detailed Implementation

[0044] This invention provides a gallium oxide-based power device and its fabrication method. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0046] The terms used in this document, such as “vertical,” “horizontal,” “up,” “down,” “left,” “right,” and similar expressions, are for illustrative purposes only and do not represent the only possible implementation.

[0047] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0048] If the embodiments of the present invention involve descriptions such as "first" or "second", such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated.

[0049] This invention provides a gallium oxide-based power device, wherein, as shown in the embodiments of the present invention... Figure 1 As shown, the gallium oxide-based power device includes a cathode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3, which are stacked sequentially from bottom to top;

[0050] The gallium oxide-based power device further includes:

[0051] The p-type semiconductor layer 4, the second field limiting ring 6, and the first field limiting ring 5 located between the p-type semiconductor layer 4 and the second field limiting ring 6 are disposed on the n-type gallium oxide epitaxial layer 3 at intervals, and form PN junctions with the n-type gallium oxide epitaxial layer respectively.

[0052] The first dielectric layer 7 is continuously located on the surface of the n-type gallium oxide epitaxial layer 3, the surface of the second field confinement ring 6, the surface of the first field confinement ring 5, and a portion of the surface of the p-type semiconductor layer 4 (the portion of the surface mentioned in this invention refers to not all of the surface).

[0053] The first anode layer 8 is continuously located on the surface of the p-type semiconductor layer 4 and a portion of the surface of the first dielectric layer 7. The portion of the first anode layer 8 located on the surface of the first dielectric layer 7 constitutes the first field plate 81. In the horizontal direction (i.e., as shown in the image), Figure 1 As shown in the left-right direction, the projection of the end (or end face) of the first field plate away from the p-type semiconductor layer onto the n-type gallium oxide epitaxial layer lies within (or falls into) the projection of the first field limiting ring onto the n-type gallium oxide epitaxial layer. That is, the rightmost end of the projection of the first field plate onto the n-type gallium oxide epitaxial layer lies within the projection of the first field limiting ring onto the n-type gallium oxide epitaxial layer.

[0054] The second dielectric layer 9 is continuously located on the surface of the first dielectric layer 7 and on a portion of the surface of the first field plate 81;

[0055] The second anode layer 10 is continuously located on the surface of the first anode layer 8 and a portion of the surface of the second dielectric layer 9.

[0056] In this embodiment of the invention, the p-type semiconductor layer, the first field limiting ring, and the second field limiting ring can uniformly distribute the electric field in the device's terminal region, i.e., equalize the surface electric field in the terminal region, thereby improving the device's breakdown voltage and withstand voltage performance. Furthermore, due to the superior ultra-high critical breakdown field strength of gallium oxide, the electron concentration in the epitaxial layer of gallium oxide-based power devices is significantly higher than that of Si or SiC-based power devices at the same voltage level. Therefore, a more significant electric field curvature effect exists in the terminal region, which requires more precise dimensional control of the field limiting ring to modulate the electric field distribution, greatly increasing the difficulty of control. In this embodiment of the invention, extending the first field plate above the first field limiting ring not only flattens the electric field distribution between the p-type semiconductor layer and the first field limiting ring, further equalizing the electric field and further improving the device's breakdown voltage and withstand voltage performance, but also optimizes the electric field even when the distance between the p-type semiconductor layer and the first field limiting ring is large, reducing the requirements for dimensional accuracy and the difficulty of processing.

[0057] In this embodiment of the invention, the p-type semiconductor layer, the first field limiting ring, and the second field limiting ring respectively form PN junctions with the n-type gallium oxide epitaxial layer. Generally, these are heterojunctions, but homojunctions are also possible. The first anode layer comprises two parts: a first part and a second part. The first part of the first anode layer 8, also known as the first field plate 81, is located on a portion of the surface of the first dielectric layer 7. The second part 82 of the first anode layer is located on the p-type semiconductor layer 4. Specifically, in the horizontal direction, the second part 82 of the first anode layer is connected to the first dielectric layer 7. The first dielectric layer 7 is continuously located on the surface of the n-type gallium oxide epitaxial layer 3, the surface and side surface of the first field limiting ring 5, the surface and side surface of the second field limiting ring 6, and the side surface and a portion of the surface of the p-type semiconductor layer 4.

[0058] In some embodiments, the portion of the second anode layer 10 located on the surface of the second dielectric layer 9 constitutes the second field plate 101. In the horizontal direction (i.e., as shown below) Figure 1 As shown in the left-right direction, the projection of the end (or end face) of the second field plate away from the p-type semiconductor layer onto the n-type gallium oxide epitaxial layer lies within (or falls into) the projection of the second field limiting ring onto the n-type gallium oxide epitaxial layer. That is, the rightmost end of the projection of the second field plate onto the n-type gallium oxide epitaxial layer lies within the projection of the second field limiting ring onto the n-type gallium oxide epitaxial layer.

[0059] In this embodiment, the second field plate extends above the second field limiting ring, which can flatten the electric field distribution between the first and second field limiting rings, further equalize the electric field, further improve the breakdown electric field of the device, and further improve the breakdown voltage performance of the device. Simultaneously, even with a large gap between the first and second field limiting rings, it can still optimize the electric field, reducing the requirements for dimensional accuracy and the difficulty of fabrication. That is, this invention simultaneously utilizes dual field plates to balance the electric field between the junction field limiting rings, enabling the different field limiting rings to achieve high breakdown voltage performance even with a larger size, reducing the difficulty of device fabrication.

[0060] In this embodiment, the second anode layer consists of two parts, namely a first part and a second part. The first part of the second anode layer 10, namely the second field plate 101, is located on a portion of the surface of the second dielectric layer 9, and the second part 102 of the second anode layer is located on the surface of the first anode layer 8.

[0061] In some embodiments, the doping concentration (i.e., electron concentration) of the n-type gallium oxide substrate is greater than that of the n-type gallium oxide epitaxial layer.

[0062] In some embodiments, the thickness of the n-type gallium oxide substrate is 50–650 μm (unless otherwise specified, all thicknesses referred to herein are as shown). Figure 1The thickness shown in the vertical direction can be, for example, 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm or 650μm, etc.

[0063] In some embodiments, the n-type gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration (i.e., electron concentration) of 10. 18 ~10 20 cm -3 For example, it can be 10 18 cm -3 5×10 18 cm -3 10 19 cm -3 5×10 19 cm -3 Or 10 20 cm -3 In some specific embodiments, the highly doped n-type gallium oxide substrate comprises n-type Si or Sn-doped β-Ga₂O₃.

[0064] In some embodiments, the thickness of the n-type gallium oxide epitaxial layer is 2 to 20 μm, for example, it can be 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm.

[0065] In some embodiments, the n-type gallium oxide epitaxial layer is a lightly doped n-type gallium oxide epitaxial layer with a doping concentration (i.e., electron concentration) of 10. 15 ~10 17 cm -3 For example, it can be 10 15 cm -3 5×10 15 cm -3 10 16 cm -3 5×10 16 cm -3 Or 10 17 cm -3 In some specific embodiments, the lightly doped n-type gallium oxide epitaxial layer comprises n-type Si or Sn-doped β-Ga₂O₃.

[0066] In some embodiments, the thickness of the p-type semiconductor layer is 100–1000 nm, for example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm; the p-type semiconductor layer includes, but is not limited to, at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride, and p-type gallium oxide, and the doping concentration (i.e., hole concentration) is 10. 16 ~10 19 cm -3 For example, it can be 10 16 cm -3 5×10 16 cm -3 10 17 cm -3 5×10 17 cm -3 10 18 cm -3 5×10 18 cm -3 Or 10 19 cm -3 wait.

[0067] In some embodiments, the thickness of the first field-limiting ring is 100–1000 nm, for example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm; the first field-limiting ring includes, but is not limited to, at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride, and p-type gallium oxide, and the doping concentration (i.e., hole concentration) is 10. 16 ~10 19 cm -3 For example, it can be 10 16 cm -3 5×10 16 cm -3 10 17 cm -3 5×10 17 cm -3 10 18 cm -3 5×10 18 cm -3 Or 10 19 cm -3 wait.

[0068] In some embodiments, the thickness of the second field-limiting ring is 100–1000 nm, for example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm; the second field-limiting ring includes, but is not limited to, at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride, and p-type gallium oxide, with a doping concentration (i.e., hole concentration) of 10. 16 ~10 19 cm -3 For example, it can be 10 16 cm -3 5×10 16 cm -3 10 17 cm -3 5×10 17 cm -3 10 18 cm -3 5×10 18 cm -3 Or 10 19 cm -3 wait.

[0069] In some embodiments, the thickness of the first dielectric layer is 50 nm to 2 μm (i.e., the thickness of all portions of the first dielectric layer is 50 nm to 2 μm; the thickness of the portion of the first dielectric layer on the surface of the n-type gallium oxide epitaxial layer is 50 nm to 2 μm; the thickness of the portion of the first dielectric layer on the surface of the second field limiting ring is 50 nm to 2 μm; the thickness of the portion of the first dielectric layer on the side of the second field limiting ring in the left-right direction is 50 nm to 2 μm; the thickness of the portion of the first dielectric layer on the surface of the first field limiting ring is 50 nm to 2 μm; the thickness of the portion of the first dielectric layer on the side of the first field limiting ring in the left-right direction is 50 nm to 2 μm). The thickness of the portion of the dielectric layer located on the surface of the p-type semiconductor layer is 50 nm to 2 μm, and the thickness of the portion of the first dielectric layer located on the side of the p-type semiconductor layer in the left-right direction is 50 nm to 2 μm. For example, it can be 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, or 2 μm, etc.; the first dielectric layer includes at least one of silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and hafnium oxide (HfO2), but is not limited thereto.

[0070] In some embodiments, the thickness of the second dielectric layer is 50 nm to 2 μm (i.e., the thickness of all portions of the second dielectric layer is 50 nm to 2 μm, the thickness of the portion of the second dielectric layer located on the first dielectric layer is 50 nm to 2 μm, and the thickness of the portion of the second dielectric layer located on the first anode layer is 50 nm to 2 μm), for example, it can be 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, or 2 μm, etc.; the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide, but is not limited thereto.

[0071] When the first dielectric layer and the second dielectric layer are made of the above-mentioned materials, the electric field distribution on the surface of the device can be further homogenized, thereby improving the device's withstand voltage performance.

[0072] In some embodiments, the thickness of the cathode layer is 150 nm to 1.5 μm, for example, it can be 150 nm, 300 nm, 500 nm, 800 nm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm or 1.5 μm, etc., and the cathode layer includes at least one of Ti, Ni, Ag and Au, but is not limited thereto.

[0073] In some embodiments, the thickness of the first anode layer is 20-300 nm (i.e., the thickness of all portions of the first anode layer is 20-300 nm, the thickness of the portion of the first anode layer located on the p-type semiconductor layer is 20-300 nm, and the thickness of the portion of the first anode layer located on the first dielectric layer is 20-300 nm), for example, it can be 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm, etc.; the first anode layer includes at least one of Ni, Al, Au, Mo, and Pt, but is not limited thereto.

[0074] In some embodiments, the thickness of the second anode layer is 200 nm to 4 μm (i.e., the thickness of all portions of the second anode layer is 200 nm to 4 μm, the thickness of the portion of the second anode layer located on the first anode layer is 200 nm to 4 μm, and the thickness of the portion of the second anode layer located on the second dielectric layer is 200 nm to 4 μm), for example, it can be 200 nm, 250 nm, 300 nm, 500 nm, 700 nm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm or 4 μm, etc., and the second anode includes at least one of Ti, Al, Ag and Au, but is not limited thereto.

[0075] This invention also provides a method for fabricating a gallium oxide-based power device, comprising the following steps:

[0076] S1, such as Figure 2 As shown in (a), an n-type gallium oxide substrate 2 is provided;

[0077] S2, such as Figure 2 As shown in (a), an n-type gallium oxide epitaxial layer 3 is formed on the n-type gallium oxide substrate 2;

[0078] S3, such as Figure 2 As shown in (a), a cathode layer 1 is formed on the surface of the n-type gallium oxide substrate 2 on the side opposite to the n-type gallium oxide epitaxial layer 3;

[0079] S4, such as Figure 2 As shown in (b), a p-type semiconductor layer 4, a first field limiting ring 5, and a second field limiting ring 6 are sequentially and spaced apart on the surface of the n-type gallium oxide epitaxial layer 3.

[0080] S5, such as Figure 2 As shown in (c), a first dielectric layer 7 is formed on the surface of the n-type gallium oxide epitaxial layer 3, the surface of the second field confinement ring 6, the surface of the first field confinement ring 5, and a portion of the surface of the p-type semiconductor layer 4.

[0081] S6, such as Figure 2 As shown in (d), a first anode layer 8 is formed on the surface of the p-type semiconductor layer 4 and on a portion of the surface of the first dielectric layer 7; the portion of the first anode layer 8 located on the partial surface of the first dielectric layer 7 is the first field plate 81.

[0082] S7, such as Figure 2 As shown in (e), a second dielectric layer 9 is formed on the surface of the first dielectric layer 7 and on a portion of the surface of the first field plate 81;

[0083] S8, such as Figure 2 As shown in (f), a second anode layer 10 is formed on the surface of the first anode layer 8 and a portion of the surface of the second dielectric layer 9. The portion of the second anode layer 10 located on the surface of the second dielectric layer 9 is the second field plate 101.

[0084] In step S1, the selection of the material and thickness of the n-type gallium oxide substrate is as described above and will not be repeated here.

[0085] In step S2, the selection of the material and thickness of the n-type gallium oxide epitaxial layer is described above and will not be repeated here.

[0086] In step S3, the selection of the cathode layer material and thickness is as described above and will not be repeated here. Specifically, the cathode layer is formed by deposition using electron beam evaporation or magnetron sputtering.

[0087] In step S4, a p-type semiconductor is deposited on the surface of an n-type gallium oxide epitaxial layer by magnetron sputtering, pulsed laser deposition, metal thermal oxidation, MOCVD (metal-organic chemical vapor deposition), or Mist-CVD (ultrasonic atomization-assisted chemical vapor deposition). After patterning (which can be done by a combination of dry and wet etching or wet etching), a p-type semiconductor layer, a first field confinement ring, and a second field confinement ring are obtained.

[0088] In step S5, a first dielectric layer material (including but not limited to at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide) can be deposited by methods such as PECVD (plasma-enhanced chemical vapor deposition), ALD (atomic layer deposition), LPCVD (low-pressure chemical vapor deposition), pulsed laser deposition, and magnetron sputtering. Then, after opening holes by a combination of wet and dry etching or wet etching, the first dielectric layer is obtained.

[0089] In step S6, specifically, a first anode metal (including but not limited to at least one of Ni, Al, Au, Mo and Pt) is deposited using electron beam evaporation or magnetron sputtering, and then patterned using a stripping process to form a first anode layer.

[0090] In step S7, a second dielectric layer material (including but not limited to at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide) can be deposited by methods such as PECVD, ALD, LPCVD, pulsed laser deposition, and magnetron sputtering. Then, after opening holes by a combination of dry and wet etching or wet etching, the second dielectric layer is obtained.

[0091] In step S8, specifically, a second anode metal (including but not limited to at least one of Ti, Al, Ag and Au) is deposited using electron beam evaporation or magnetron sputtering, and then patterned using a stripping process to form a second anode layer.

[0092] The present invention will be further described below through specific embodiments.

[0093] Example 1

[0094] This embodiment provides a gallium oxide-based power device, wherein, as... Figure 1 As shown, the gallium oxide-based power device includes a cathode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3, stacked sequentially from bottom to top. The cathode layer comprises a Ti layer (100 nm thick), a Ni layer (300 nm thick), and an Ag layer (1 μm thick), stacked sequentially, with the Ti layer side-mounted in contact with the n-type gallium oxide substrate. The n-type gallium oxide substrate has a thickness of 400 μm and is specifically an n-type Sn-doped β-Ga₂O₃ substrate with an electron concentration of 10⁻⁶. 20cm -3 The thickness of the n-type gallium oxide epitaxial layer is 10 μm, specifically an n-type Si-doped β-Ga₂O₃ epitaxial layer with an electron concentration of 10. 16 cm -3 ;

[0095] The gallium oxide-based power device further includes:

[0096] A p-type semiconductor layer 4, a second field-limiting ring 6, and a first field-limiting ring 5 located between the p-type semiconductor layer 4 and the second field-limiting ring 6 are disposed on the n-type gallium oxide epitaxial layer 3 at intervals, and form heterojunctions with the n-type gallium oxide epitaxial layer 3 respectively; the thickness of the p-type semiconductor layer, the first field-limiting ring, and the second field-limiting ring is 500 nm, their material is p-type nickel oxide, and their hole concentration is 10. 18 cm -3 In the left-right direction, the widths of the p-type semiconductor layer, the first field limiting ring, and the second field limiting ring are all 5 μm. The gap between the p-type semiconductor layer and the first field limiting ring is 6 μm, and the gap between the first field limiting ring and the second field limiting ring is 8 μm. The overall device width (i.e., the width of the n-type gallium oxide substrate) is 50 μm.

[0097] The first dielectric layer 7 is continuously located on the surface of the n-type gallium oxide epitaxial layer 3, the surface of the second field confinement ring 6, the surface of the first field confinement ring 5, and a portion of the surface of the p-type semiconductor layer 4; the thickness of the first dielectric layer is 1 μm, and the material is SiO2;

[0098] The first anode layer 8 is continuously located on the surface of the p-type semiconductor layer 4 and a portion of the surface of the first dielectric layer 7. The portion of the first anode layer 8 located on the surface of the first dielectric layer 7 is the first field plate 81. The first anode layer is a Ni layer with a thickness of 100 nm. The rightmost end of the projection of the first field plate onto the n-type gallium oxide epitaxial layer is located at the exact center of the projection of the first field limiting ring onto the n-type gallium oxide epitaxial layer.

[0099] The second dielectric layer 9 is continuously located on the surface of the first dielectric layer 7 and on a portion of the surface of the first field plate 81; the thickness of the second dielectric layer is 1 μm and the material is Si3N4;

[0100] The second anode layer 10 is continuously located on the surface of the first anode layer 8 and a portion of the surface of the second dielectric layer 9. The portion of the second anode layer 10 located on the surface of the second dielectric layer 9 is the second field plate 101. The second anode layer is an Al layer with a thickness of 1 μm. The rightmost end of the projection of the second field plate onto the n-type gallium oxide epitaxial layer is located at the exact center of the projection of the second field limiting ring onto the n-type gallium oxide epitaxial layer.

[0101] Example 1 introduces a gallium oxide-based power device with a heterojunction field limiting ring and a double field plate, and a gallium oxide-based power device with a field limiting ring (the schematic diagram of which is shown in Figure 1). Figure 3 As shown, it includes a cathode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3 stacked sequentially from bottom to top; it also includes a p-type semiconductor layer 4, a first field limiting ring 5, and a second field limiting ring 6 sequentially spaced on the n-type gallium oxide epitaxial layer 3; a first dielectric layer 7 located on the surfaces of the n-type gallium oxide epitaxial layer 3, the second field limiting ring 6, and the first field limiting ring 5, as well as on a portion of the surface of the p-type semiconductor layer 4; a first anode layer 8 located on the surface of the p-type semiconductor layer 4 and on a portion of the surface of the first dielectric layer 7; and a second anode layer 10 located on the first anode layer 8, wherein the rightmost end of the projection of the first anode layer 8 onto the p-type semiconductor layer 4 is located within the p-type semiconductor layer 4, and the materials and thicknesses of each layer are the same as in Embodiment 1), and a gallium oxide-based power device with a dual field plate (its structural schematic diagram is shown in Figure 1). Figure 4 As shown, it includes, from bottom to top, a cathode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3; it also includes a p-type semiconductor layer 4 on the n-type gallium oxide epitaxial layer 3, a first dielectric layer 7 on the surface of the n-type gallium oxide epitaxial layer 3 and a portion of the surface of the p-type semiconductor layer 4, a first anode layer 8 on the surface of the p-type semiconductor layer 4 and a portion of the surface of the first dielectric layer 7, a second dielectric layer 9 on the surface of the first dielectric layer 7 and a portion of the surface of the first anode layer 8, and a second anode layer 10 on the surface of the first anode layer 8 and a portion of the surface of the second dielectric layer 9 (the materials and thicknesses of each layer are the same as in Example 1). The surface electric field distribution curves are shown in the figure. Figure 5 As shown, the electric field distribution of gallium oxide-based power devices with field limiting rings and gallium oxide-based power devices with double field plates is uneven, and the breakdown voltage performance of the devices is low. However, the gallium oxide-based power device in Embodiment 1 of the present invention can achieve a more uniform electric field distribution and has a higher breakdown voltage.

[0102] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A gallium oxide-based power device, characterized by, The gallium oxide-based power device comprises, from bottom to top, a cathode layer, an n-type gallium oxide substrate and an n-type gallium oxide epitaxial layer; The gallium oxide-based power device further comprises: a p-type semiconductor layer, a second field limiting ring and a first field limiting ring between the p-type semiconductor layer and the second field limiting ring, the p-type semiconductor layer, the first field limiting ring and the second field limiting ring are arranged on the n-type gallium oxide epitaxial layer and form PN junctions with the n-type gallium oxide epitaxial layer respectively; a first dielectric layer continuously located on the surface of the n-type gallium oxide epitaxial layer, the surface of the second field limiting ring, the surface of the first field limiting ring and part of the surface of the p-type semiconductor layer; a first anode layer continuously located on the surface of the p-type semiconductor layer and part of the surface of the first dielectric layer, the part of the first anode layer located on the part of the surface of the first dielectric layer is a first field plate, and the projection of the end of the first field plate away from one end of the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer in the horizontal direction; a second dielectric layer continuously located on the surface of the first dielectric layer and part of the surface of the first field plate; a second anode layer continuously located on the surface of the first anode layer and part of the surface of the second dielectric layer; the part of the second anode layer located on the part of the surface of the second dielectric layer is a second field plate, and the projection of the end of the second field plate away from one end of the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in the projection of the second field limiting ring on the n-type gallium oxide epitaxial layer in the horizontal direction.

2. The gallium oxide-based power device of claim 1, wherein, The thickness of the n-type gallium oxide substrate is 50-650 μm; The n-type gallium oxide substrate is a high-doped n-type gallium oxide substrate, and the doping concentration is 10 18 10 20 cm -3 ; The thickness of the n-type gallium oxide epitaxial layer is 2-20 μm; The n-type gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration is 10 15 ~10 17 cm -3 .

3. The gallium oxide-based power device of claim 1, wherein, The thickness of the p-type semiconductor layer is 100-1000 nm, and the p-type semiconductor layer comprises at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

4. The gallium oxide-based power device of claim 1, wherein, The thickness of the first field limiting ring is 100-1000 nm, and the first field limiting ring comprises at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

5. The gallium oxide-based power device of claim 1, wherein, The thickness of the second field limiting ring is 100-1000 nm, and the second field limiting ring comprises at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

6. The gallium oxide-based power device of claim 1, wherein, The thickness of the first dielectric layer is 50 nm-2 μm, and the first dielectric layer comprises at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

7. The gallium oxide-based power device of claim 1, wherein, The thickness of the second dielectric layer is 50 nm-2 μm, and the second dielectric layer comprises at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

8. The gallium oxide-based power device of claim 1, wherein, The cathode layer comprises at least one of Ti, Ni, Ag and Au; The thickness of the first anode layer is 20-300 nm, and the first anode layer comprises at least one of Ni, Al, Au, Mo and Pt; The thickness of the second anode layer is 200 nm-4 μm, and the second anode comprises at least one of Ti, Al, Ag and Au.

9. A method of fabricating a gallium oxide-based power device according to claim 1, characterized by, The method comprises the following steps: Providing an n-type gallium oxide substrate; forming an n-type gallium oxide epitaxial layer on the n-type gallium oxide substrate; forming a cathode layer on the surface of the n-type gallium oxide substrate away from the n-type gallium oxide epitaxial layer; forming a p-type semiconductor layer, a first field limiting ring and a second field limiting ring arranged in sequence on the surface of the n-type gallium oxide epitaxial layer; forming a first dielectric layer on the surface of the n-type gallium oxide epitaxial layer, the surface of the second field limiting ring, the surface of the first field limiting ring and part of the surface of the p-type semiconductor layer; forming a first anode layer on the surface of the p-type semiconductor layer and part of the surface of the first dielectric layer; the part of the first anode layer on the surface of the first dielectric layer is a first field plate, and in the horizontal direction, the projection of the end of the first field plate away from the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer; forming a second dielectric layer on the surface of the first dielectric layer and part of the surface of the first field plate; forming a second anode layer on the surface of the first anode layer and part of the surface of the second dielectric layer.

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