Back contact battery, non-etching manufacturing method thereof and battery assembly

Abstract

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell, an etching-free manufacturing method thereof and a cell assembly, and the method comprises the steps: depositing an intrinsic amorphous silicon layer on a backlight surface of a silicon wafer; forming first doped regions, second doped regions and co-doped regions between the first doped regions and the second doped regions on the outer surface of the intrinsic amorphous silicon layer, wherein the first doped regions and the second doped regions are alternately distributed; and arranging a hard mask on the outer surface of the co-doped region, and depositing a conductive film layer and a metal electrode on the backlight surface. According to the invention, the use of high-temperature laser and chemical etching is avoided, so that the damage to the battery and the environmental pollution are reduced, the production yield is remarkably improved, the production cost is remarkably reduced, the reliability of the battery is improved, the service life of the battery is prolonged, and good battery efficiency can be obtained.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery and an etching-free manufacturing method thereof and a battery assembly. Background Art

[0002] In the field of solar cells, back-contact cells are valued for their high efficiency and low temperature coefficient. However, the NP semiconductor layer of traditional back-contact cells is set on the back. In order to obtain higher cell efficiency, the preparation technology used in the current cell structure has some significant defects. These technologies usually require growth masks and etching steps to form the back contact structure of the cell. These steps involve high-temperature processes such as lasers and the use of acids and alkalis. These high temperatures and chemical treatments may not only damage the cell, reduce cell performance and reliability, but also cause environmental pollution.

[0003] Moreover, the high temperature and chemical treatment steps in the prior art increase production costs, limiting its application in large-scale production. In addition, these process steps are complicated and require high equipment, which is not conducive to large-scale production and cost control.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the prior art that the preparation process required for the traditional back-contact battery structure requires the use of high-temperature laser and chemical etching steps, which may cause damage to the battery, reduce battery performance and reliability, cause environmental pollution and have high costs. A back-contact battery and its etching-free manufacturing method and battery assembly are provided, which avoid the use of high-temperature laser and chemical etching, thereby reducing damage to the battery and environmental pollution, significantly improving production yield, significantly reducing production costs, while improving battery reliability and service life, and obtaining good battery efficiency.

[0006] In order to achieve the above object, in a first aspect, the present invention provides a method for manufacturing a back contact cell without etching, comprising the following steps: S1, provide silicon wafers; S2, depositing an intrinsic amorphous silicon layer on the backlit side of the silicon wafer; S3, a first doping region, a second doping region and a co-doping region between the first doping region and the second doping region are preset on the outer surface of the intrinsic amorphous silicon layer and are distributed alternately; one of the first doping region and the second doping region is N-type and the other is P-type; the doping source of the co-doping region includes a doping source A of the first doping region and a doping source B of the second doping region; First, a first hard mask is used to cover the preset second doping region and the preset co-doping region of the backlight surface, and a first doped silicon with a target thickness is grown on the backlight surface to form a first doped region; wherein a distance D between the first hard mask and the intrinsic amorphous silicon layer is controlled to be greater than the target thickness of the first doped silicon; S4, then using a second hard mask to cover the preset first doping region and the preset co-doping region of the backlight surface, and growing a second doped silicon of a target thickness to form a second doped region; wherein the distance d between the second hard mask and the intrinsic amorphous silicon layer is greater than the target thickness of the second doped silicon; and at the same time, a co-doping region is naturally formed in the contact area of ​​the first doped silicon and the second doped silicon; S5, setting a hard mask on the outer surface of the co-doped region, and depositing a conductive film layer on the backlight side; S6. Form metal electrodes on the outer surfaces of the first doping region and the second doping region respectively.

[0007] In some preferred embodiments of the present invention, the ratio of D in S3 to the target thickness of the first doped silicon is 10-20000:1, and / or the ratio of d in S4 to the target thickness of the second doped silicon is 10-20000:1.

[0008] In some preferred embodiments of the present invention, the target thickness of the first doped silicon is controlled within a range of 8-20 nm; and / or the target thickness of the second doped silicon is controlled within a range of 8-20 nm.

[0009] In some preferred embodiments of the present invention, the width of the co-doped region is 5-150 μm; and / or, D in S3 is controlled to be maintained at 0.2-200 μm, and d in S4 is controlled to be maintained at 0.2-200 μm.

[0010] In some preferred embodiments of the present invention, the thickness of the co-doped region is 5-30 nm.

[0011] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the doping concentration of the doping source A in the co-doped region is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner.

[0012] In some more preferred embodiments of the present invention, in the diagonal direction of the co-doped region with the first doped region close to the inner end of the silicon wafer as the starting point, the co-doped region is divided into a first region, a second intermediate region, and a third region in sequence, and the second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

[0013] In some preferred embodiments of the present invention, the doping source A comprises phosphorus, the doping source B comprises boron, and the phosphorus doping concentration in the second intermediate region is between 1e15 cm -3 -2e20cm-3 , boron doping concentration is 1e15cm -3 -2e20cm -3 The phosphorus doping concentrations in the first region and the third region are independently 5e15cm -3 -2e20cm -3 , boron doping concentrations are independently 5e15cm -3 -2e20cm -3 .

[0014] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth of the concentrated double-doped region in the A-doped substrate accounts for 25%-80%; and / or the depth of the concentrated double-doped region is 5-30nm.

[0015] In some preferred embodiments of the present invention, the ratio of the minimum doping concentration of the doping source A in the co-doping region to the doping concentration of the doping source A in the first doping region is 0.01-100:100, and the ratio of the minimum doping concentration of the doping source B in the co-doping region to the doping concentration of the doping source B in the second doping region is 0.01-100:100.

[0016] In some preferred embodiments of the present invention, the phosphorus doping concentration in the co-doped region is 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 ; and / or, controlling the flow rate of the corresponding phosphorus source during the growth process of the first doped silicon and the second doped silicon to be 1-12 sccm, and the flow rate of the boron source to be 1-12 sccm.

[0017] In some preferred embodiments of the present invention, the first doped silicon grown in S3 and the second doped silicon grown in S4 are each independently formed by plasma enhanced chemical vapor deposition or hot filament chemical vapor deposition.

[0018] In some preferred embodiments of the present invention, the conditions for growing the first doped silicon in S3 include: introducing silane, ammonia, and a gas source corresponding to the doping source A, where the flow rate of silane is 45-50sccm; the conditions for growing the second doped silicon in S4 include: introducing silane and a gas source corresponding to the doping source B, where the flow rate of silane is 45-50sccm; wherein, the gas source corresponding to the doping source A and the gas source corresponding to the doping source B, one of which is a boron source and the other is a phosphorus source, the flow rate of the boron source is 1-12sccm, and the flow rate of the phosphorus source is 1-12sccm.

[0019] Preferably, in the present invention, one of the doping source A of the first doping region and the doping source B of the second doping region is phosphorus and the other is boron, wherein the phosphorus doping concentration is between 2e18cm -3 -2e20cm -3 , the boron doping concentration is 2e18cm -3 -2e20cm -3 .

[0020] In some preferred embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer in S2 is 5-15 nm.

[0021] In some preferred embodiments of the present invention, the first doped silicon and the second doped silicon in S3 are each independently selected from correspondingly doped amorphous silicon or microcrystalline silicon.

[0022] In some preferred embodiments of the present invention, the distance between the hard mask and the backlight surface of the silicon wafer in S5 is controlled to be 0.2-200 μm.

[0023] In some preferred embodiments of the present invention, the thickness of the conductive film layer in S5 is 30-100 nm.

[0024] In some preferred embodiments of the present invention, the conductive film layer in S5 is deposited by magnetron sputtering.

[0025] In some preferred embodiments of the present invention, the thickness of the metal electrode in S6 is 3-20 μm.

[0026] In some preferred embodiments of the present invention, the silicon wafer in S1 is a silicon wafer with a light-receiving surface textured and a back-light surface polished.

[0027] In some preferred embodiments of the present invention, the etching-free manufacturing method of the back contact cell further includes the step of forming a passivation anti-reflection layer on the light-receiving surface of the silicon wafer in S1.

[0028] In a second aspect, the present invention provides a high-reliability back-contact battery, which is manufactured by the etching-free manufacturing method of the back-contact battery described in the first aspect.

[0029] In a third aspect, the present invention provides a back-contact battery, comprising a silicon wafer, an intrinsic amorphous silicon layer is arranged on the backlight surface of the silicon wafer, a first doping region and a second doping region are arranged outside the intrinsic amorphous silicon layer, and a co-doping region is arranged between the first doping region and the second doping region; one of the first doping region and the second doping region is N-type, and the other is P-type; the doping source of the co-doping region includes a doping source A in the first doping region and a doping source B in the second doping region; in the diagonal direction of the co-doping region with the first doping region close to the inner end of the silicon wafer as the starting point, the doping concentration of the doping source A in the co-doping region is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner.

[0030] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region with the first doped region close to the inner end of the silicon wafer as the starting point, the co-doped region is divided into a first region, a second intermediate region, and a third region in sequence, and the second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

[0031] In some preferred embodiments of the present invention, the doping source A comprises phosphorus, the doping source B comprises boron, and the phosphorus doping concentration in the second intermediate region is between 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 The phosphorus doping concentrations in the first region and the third region are independently 5e15cm -3 -2e20cm -3 , boron doping concentrations are independently 5e15cm -3 -2e20cm -3 .

[0032] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth of the concentrated double-doped region in the A-doped substrate accounts for 25%-80%; and / or the depth of the concentrated double-doped region is 5-30nm.

[0033] In some preferred embodiments of the present invention, the ratio of the minimum doping concentration of the doping source A in the co-doping region to the doping concentration of the doping source A in the first doping region is 0.01-100:100, and the ratio of the minimum doping concentration of the doping source B in the co-doping region to the doping concentration of the doping source B in the second doping region is 0.01-100:100.

[0034] In some preferred embodiments of the present invention, the phosphorus doping concentration in the co-doped region is 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 .

[0035] In some preferred embodiments of the present invention, the ratio of the width of the co-doped region to the width of the first doped region or the second doped region is 0.01-0.5:1.

[0036] In some preferred embodiments of the present invention, the ratio of the thickness of the co-doped region to the thickness of the first doped region or the second doped region is 0.5-1.4:1, more preferably 0.8-1.4:1.

[0037] In some preferred embodiments of the present invention, the width of the co-doped region is 5-150 μm.

[0038] In some preferred embodiments of the present invention, the thickness of the co-doped region is 5-30 nm.

[0039] In some preferred embodiments of the present invention, the thickness of the first doping region and the second doping region are independently 8-20 nm.

[0040] In some preferred embodiments of the present invention, the widths of the first doping region and the second doping region are independently 100-600 μm.

[0041] In some preferred embodiments of the present invention, one of the doping source A of the first doping region and the doping source B of the second doping region is phosphorus and the other is boron, wherein the phosphorus doping concentration is 2e18cm -3 -2e20cm -3 , the boron doping concentration is 2e18cm -3 -2e20cm -3 .

[0042] In some preferred embodiments of the present invention, the first doped region and the second doped region are each independently selected from correspondingly doped amorphous silicon or microcrystalline silicon.

[0043] In some preferred embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer is 5-15 nm; and / or the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the first doping region or the second doping region is 0.5-2:1.

[0044] In some preferred embodiments of the present invention, the back contact cell further comprises at least one of the following structures: Structure 1: In the width direction, the first doping region and the co-doping region, and the co-doping region and the second doping region are in contact with each other and are continuously distributed as a whole; Structure 2: The back contact cell also includes a light-receiving surface passivation anti-reflection layer disposed on the light-receiving surface of the silicon wafer; Structure 3: The light-receiving side of the silicon substrate is a velvet surface, and the backlight side is a polished surface; Structure 4. The back-contact battery also includes a conductive film layer and a metal electrode sequentially arranged on the outer surfaces of the first doping region and the second doping region, an isolation groove is arranged between the conductive film layer arranged on the outer surface of the first doping region and the conductive film layer arranged on the outer surface of the second doping region, and at least a part of the isolation groove is located on the outer surface of the co-doped region.

[0045] In a fourth aspect, the present invention provides a battery assembly, which includes the high-reliability back-contact battery described in the second aspect, or includes the back-contact battery described in the third aspect.

[0046] Beneficial effects: The present invention, through the above-mentioned technical scheme, especially S2-S4, can form a back-contact battery structure without high-temperature laser process and chemical etching process (such as wet etching), can avoid the use of acid and alkali in high-temperature process and chemical etching, effectively reduce the damage to the battery, significantly improve the production yield, significantly reduce the production cost, and at the same time improve the reliability and service life of the battery, and can obtain good battery efficiency. Moreover, since the use of high-temperature processes such as lasers and acids and alkalis is avoided, the present invention reduces environmental pollution in the preparation process and meets the requirements of green manufacturing; at the same time, since no etching steps are required, the production process is simplified, the consumption of materials and energy is reduced, thereby significantly reducing the production cost. Moreover, the etching-free manufacturing method of the present invention can be applied to different battery sizes and shapes, has good adaptability, and can meet diverse market demands.

[0047] The present invention uses hard mask technology to perform precise regional control, and controls the distance D between the first hard mask and the intrinsic amorphous silicon layer to be greater than the target thickness of the first doped silicon, and the distance d between the second hard mask and the intrinsic amorphous silicon layer to be greater than the target thickness of the second doped silicon, so that sufficient specific co-doped regions are naturally formed in the contact area between the first doped silicon and the second doped silicon, which can achieve more sophisticated battery structure preparation, wherein the specific co-doped region can effectively insulate and isolate the first doped region and the second doped region, and can significantly reduce the conductivity between the first doped region and the second doped region, avoiding lateral leakage current, thereby improving the lateral insulation of the back contact battery. The doping structure, combined with the passivation structure of the intrinsic amorphous silicon layer, can improve the battery consistency, reliability and other performance while obtaining good battery efficiency.

[0048] The back contact battery of the present invention, by setting a first doping region, a second doping region, and a co-doping region of specific structures, and the doping concentration of the doping source A in the co-doping region is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner, can utilize the double doping effect of the co-doping region (i.e., doping with two ions at the same time) to effectively insulate and isolate the first doping region and the second doping region, and can significantly reduce the conductivity between the first doping region and the second doping region, avoiding lateral leakage current, thereby improving the lateral insulation of the back contact battery, and improving battery performance such as production yield, battery efficiency, battery stability, reliability, etc., to meet the market demand for high-efficiency solar cells. The present invention can significantly reduce the conductivity between the first doped region and the second doped region (in a specific embodiment, the applicant unexpectedly found that, compared with a single-doped (i.e., only N-type doping or P-type doping) film layer under the same conditions, the resistivity can be increased from 1e3 Ω.cm to 1e5 Ω.cm to 1e7 Ω.cm to 1e10 Ω.cm, and the conductivity can be decreased from 1e-3 S / cm to 1e-5 S / cm to 1e-7 S / cm to 1e-10 S / cm) by co-doping with N-type doping ions and P-type doping ions. The possible speculative principles include that the difference in size between the two ions leads to local structural distortion, destroying the channel suitable for the migration of a single electron or hole; the two ions create different local environments, resulting in site energy mismatch; and because the two ions need to compete for the mobile sites in the doped substrate, the doped substrate makes the distribution of the potential barrier complicated due to the doping of multiple ions, etc., multiple unfavorable factors lead to a decrease in the carrier concentration and the overall mobility by an order of magnitude, and ultimately obtain significant insulation.

[0049] Among them, compared with tunneling oxide layer passivation (tunneling oxide layer generally requires high temperature annealing to form holes in order to improve the tunneling ability of carriers, high temperature annealing will crystallize amorphous silicon, and the conductivity of crystallized thickness will be greatly improved), the present invention uses intrinsic amorphous silicon to passivate the first doping region and the second doping region. The use of intrinsic amorphous silicon does not require high temperature annealing, so it can effectively control the conductivity, and the passivation effect is better, which is conducive to controlling the conductivity of the first doping region and the second doping region, so that the lateral leakage current between the first doping region and the second doping region can be effectively controlled, which is conducive to improving the battery efficiency. The present invention also cooperates with the provision of a conductive film layer to greatly improve the carrier collection ability of the first doping region and the second doping region, further improving the battery efficiency.

[0050] Moreover, the structure of the back contact battery of the present invention is beneficial to reduce the NP interface on the surface of the silicon wafer and improve the passivation effect compared to using intrinsic amorphous silicon, polycrystalline silicon or silicon nitride and other materials for partitioning. Moreover, the back contact battery structure of the present invention can form the back contact battery structure without the need for high temperature laser process and chemical etching process, which is convenient for simplifying the battery preparation process, reducing the production cost, and at the same time improving the battery stability and extending the battery life. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 It is a schematic structural diagram of a specific embodiment of the back contact battery of the present invention.

[0053] Figure 2 The flowchart of the etching-free manufacturing method of the back contact battery of the present invention.

[0054] Figure 3 The figure is a process flow chart of a specific implementation mode of the etching-free manufacturing method of the present invention.

[0055] Description of Reference Numerals 1. Silicon wafer, 2. Intrinsic amorphous silicon layer, 3. First doped region, 4. Second doped region, 5. Co-doped region, 6. Conductive film layer, 7. Metal electrode. Mask1, first hard mask, mask2, second hard mask, mask3, hard mask. DETAILED DESCRIPTION

[0056] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0057] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0058] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0059] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0060] In a first aspect, the present invention provides a method for manufacturing a back contact cell without etching, such as Figure 2 As shown, the following steps are included: S1, provide silicon wafer; S2, depositing an intrinsic amorphous silicon layer on the backlit side of the silicon wafer; S3, a first doping region, a second doping region and a co-doping region between the first doping region and the second doping region are preset on the outer surface of the intrinsic amorphous silicon layer and are distributed alternately; one of the first doping region and the second doping region is N-type and the other is P-type; the doping source of the co-doping region includes a doping source A of the first doping region and a doping source B of the second doping region; First, a first hard mask is used to cover the preset second doping region and the preset co-doping region of the backlight surface, and a first doped silicon with a target thickness is grown on the backlight surface to form a first doped region; wherein a distance D between the first hard mask and the intrinsic amorphous silicon layer is controlled to be greater than the target thickness of the first doped silicon; S4, then using a second hard mask to cover the preset first doping region and the preset co-doping region of the backlight surface, and growing a second doped silicon of a target thickness to form a second doped region; wherein the distance d between the second hard mask and the intrinsic amorphous silicon layer is greater than the target thickness of the second doped silicon; and at the same time, a co-doping region is naturally formed in the contact area of ​​the first doped silicon and the second doped silicon; S5, setting a hard mask on the outer surface of the co-doped region, and depositing a conductive film layer on the backlight side; S6. Form metal electrodes on the outer surfaces of the first doping region and the second doping region respectively.

[0061] The first doping region, the second doping region, and the co-doping region between the first doping region and the second doping region are preset on the outer surface of the intrinsic amorphous silicon layer to be alternately distributed, which means that the first doping region, the second doping region, and the co-doping region are divided into three regions at the positions where the first doping region, the second doping region, and the co-doping region are required to be set, so as to facilitate the subsequent steps. The doping source of the co-doping region includes the doping source A of the first doping region and the doping source B of the second doping region. It can be understood that when the first doping region is N-type, the doping source A is phosphorus, and when the second doping region is P-type, the doping source B is boron; conversely, when the first doping region is P-type, the doping source A is boron, and when the second doping region is N-type, the doping source B is phosphorus.

[0062] In S3 of the present invention, when growing the first doped silicon of the target thickness, a first doped region of the target thickness is formed, and doped silicon of the doping source A is formed in a portion near the second doping region in a preset co-doped region; when growing the second doped silicon of the target thickness in S4, a second doped region of the target thickness is formed, and doped silicon of the doping source B is formed from the outside to the inside in a portion near the second doping region in the preset co-doped region, and the doped silicon of the doping source A is at least partially doped with the doping source B, thereby forming a co-doped region.

[0063] In some preferred embodiments of the present invention, the ratio of D in S3 to the target thickness of the first doped silicon is 10-20000:1, more preferably 10-12000:1, further preferably 10-10000:1, for example, it can be 10:1, 15:1, 20:1, 25:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, 100:1, 110:1, 130:1, 150:1, 170:1, 200:1, 230:1, 250:1, 280:1, 300:1, 310:1. 20:1, 350:1, 370:1, 400:1, 430:1, 450:1, 480:1, 500:1, 530:1, 550:1, 580:1, 600:1, 650:1, 700:1, 750:1, 800:1, 850:1, 890:1, 900:1, 920:1, 950:1, 970:1, 10000:1, 11000:1, 12000:1, 15000:1, 17000:1, 20000:1 and the like, and the range between any two point values. The preferred solution is more conducive to controlling the appropriate width of the co-doped region.

[0064] Preferably, in the present invention, the ratio of d in S4 to the target thickness of the second doped silicon is 10-20000:1, more preferably 10-12000:1, and further preferably 10-10000:1, for example, it can be 10:1, 15:1, 20:1, 25:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, 100:1, 110:1, 130:1, 150:1, 170:1, 200:1, 230:1, 250:1, 280:1, 300:1, 320:1 , 350:1, 370:1, 400:1, 430:1, 450:1, 480:1, 500:1, 530:1, 550:1, 580:1, 600:1, 650:1, 700:1, 750:1, 800:1, 850:1, 890:1, 900:1, 920:1, 950:1, 970:1, 10000:1, 11000:1, 12000:1, 15000:1, 17000:1, 20000:1 and the like, and the range between any two point values. The preferred solution is more conducive to controlling the appropriate width of the co-doped region.

[0065] In some preferred embodiments of the present invention, the target thickness of the first doped silicon is controlled at 8-20nm, for example, it can be any value such as 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, and the range between any two point values.

[0066] Preferably, in the present invention, the target thickness of the second doped silicon is controlled at 8-20nm, for example, it can be any value such as 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, and the range between any two point values.

[0067] In the present invention, the first doped silicon or the second doped silicon with a preferred appropriate thickness is used, which is more conducive to improving the battery efficiency.

[0068] In some preferred embodiments of the present invention, the width of the co-doped region is in the range of 5-150 μm, for example, it can be 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm or any other value, and the range between any two point values.

[0069] Preferably, in the present invention, D in S3 is controlled to be maintained at 0.2-200μm, for example, it can be 0.2μm, 0.5μm, 1μm, 2μm, 3μm, 4μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm or any other value, and the range between any two point values.

[0070] Preferably, d in S4 is maintained at 0.2-200μm, for example, it can be 0.2μm, 0.5μm, 1μm, 2μm, 3μm, 4μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm or any other value, and the range between any two point values.

[0071] In the present invention, preferably, when the width of the co-doped region is required to be 5-150 μm, D in S3 is controlled to be maintained at 0.2-200 μm, and d in S4 is controlled to be maintained at 0.2-200 μm. This preferred solution is more conducive to controlling the appropriate width of the co-doped region.

[0072] In some preferred embodiments of the present invention, the thickness of the co-doped region is 5-30 nm, for example, it can be any value such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 12 nm, 14 nm, 15 nm, 17 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, and the range between any two point values. Using a co-doped region with an appropriate thickness is more conducive to improving battery efficiency.

[0073] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the doping concentration of the doping source A in the co-doped region is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner. The co-doped region using this doping distribution is more conducive to reducing the leakage current between the first doped region and the second doped region.

[0074] In some more preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the co-doped region is divided into a first region, a second intermediate region, and a third region in sequence, and the second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate. The A-doped substrate refers to a substrate doped with a doping source A. The concentrated double-doped region is doped with AB at the same time, which is more conducive to improving the insulation between the first doped region and the second doped region; in conjunction with the first region and the third region, it is more conducive to improving the insulation between the first doped region and the second doped region and reducing the leakage current between the first doped region and the second doped region.

[0075] It can be understood that the first region and the third region are both doped with corresponding doping sources, and the doping sources doped in the two regions are different. The first region and the third region may also be doped with a small amount of different doping sources. For example, the first region is doped with doping source A and may optionally be doped with a small amount of doping source B.

[0076] In some preferred embodiments of the present invention, the doping source A comprises phosphorus, the doping source B comprises boron, and the phosphorus doping concentration in the second intermediate region is between 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 The phosphorus doping concentrations in the first region and the third region are independently 5e15cm -3 -2e20cm -3 , more preferably 2e18cm -3 -2e20cm -3 ; their boron doping concentrations are independently 5e15cm -3 -2e20cm -3 , more preferably 2e18cm -3 -2e20cm -3 The first region, the second middle region, and the third region with appropriate doping concentrations are used to form a co-doping region with a specific doping distribution, which is more conducive to improving the battery efficiency.

[0077] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth proportion of the concentrated double doped region in the A-doped substrate is 25%-80%, for example, it can be any value such as 25%, 27%, 30%, 32%, 35%, 38%, 40%, 42%, 45%, 47%, 80%, and the range between any two point values. The use of a concentrated double doped region with an appropriate depth proportion is more conducive to improving the insulation between the first doped region and the second doped region and reducing the leakage current between the first doped region and the second doped region.

[0078] In some preferred embodiments of the present invention, the depth of the concentrated double-doped region is 5-30nm, for example, it can be any value such as 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, and the range between any two point values. The use of a concentrated double-doped region with an appropriate depth is more conducive to improving the insulation between the first doping region and the second doping region and reducing the leakage current between the first doping region and the second doping region.

[0079] The depth of the concentrated double-doped region in the present invention can be controlled according to the corresponding deposition time and deposition rate during the process of growing the first doped silicon in S3 and the second doped silicon in S4, as long as the target film layer of the required depth can be obtained.

[0080] In some preferred embodiments of the present invention, the ratio of the minimum doping concentration of the doping source A in the co-doping region to the doping concentration of the doping source A in the first doping region is 0.01-100: 100, and the ratio of the minimum doping concentration of the doping source B in the co-doping region to the doping concentration of the doping source B in the second doping region is 0.01-100: 100. This preferred solution is used to balance the doping concentrations of the co-doping region and the first doping region and the second doping region to form a suitable concentration gradient, which is more conducive to improving the insulation between the first doping region and the second doping region and reducing the leakage current between the first doping region and the second doping region.

[0081] The ratio of the minimum doping concentration of the doping source A in the co-doping region to the doping concentration of the doping source A in the first doping region is 0.01-100:100, for example, it can be any value such as 0.01:100, 0.05:100, 0.10:100, 0.20:100, 0.50:100, 0.7:100, 1.0:100, 2:100, 5:100, 7:100, 10:100, 15:100, 20:100, 30:100, 40:100, 50:100, 60:100, 70:100, 80:100, 90:100, 100:100, etc., and the range between any two point values. The ratio of the minimum doping concentration of the doping source B in the co-doping region to the doping concentration of the doping source B in the second doping region is in the selection range of 0.01-100:100. The same is true.

[0082] The minimum doping concentration of the doping source A in the co-doping region refers to the minimum doping concentration of the doping source A in the first region, the second middle region, and the third region; the same is true for the minimum doping concentration of the doping source B in the co-doping region.

[0083] In some preferred embodiments of the present invention, the phosphorus doping concentration in the co-doped region is 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 .

[0084] In some preferred embodiments of the present invention, the flow rates of the phosphorus sources during the growth of the first doped silicon and the second doped silicon are controlled to be 1-12 sccm, more preferably 8-12 sccm, and the flow rates of the boron sources are controlled to be 1-12 sccm, more preferably 8-12 sccm.

[0085] Preferably, the phosphorus doping concentration in the desired co-doping region is 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 When the first doped silicon and the second doped silicon are grown in the corresponding growth process, the flow rate of the phosphorus source is controlled to be 1-12sccm, more preferably 8-12sccm, and the flow rate of the boron source is controlled to be 1-12sccm, more preferably 8-12sccm. The flow rates of the phosphorus source and the boron source of the first doped silicon and the second doped silicon can be adjusted according to the doping concentration of the co-doped region, which is more conducive to improving the insulation between the first doped region and the second doped region and reducing the leakage current between the first doped region and the second doped region.

[0086] In some preferred embodiments of the present invention, the first doped silicon grown in S3 and the second doped silicon grown in S4 are each independently formed by plasma enhanced chemical vapor deposition or hot wire chemical vapor deposition. Plasma enhanced chemical vapor deposition is more preferably used, which is beneficial to improving the uniformity of the film layer and the efficiency of the battery.

[0087] In some preferred embodiments of the present invention, the conditions for growing the first doped silicon in S3 include: introducing silane, ammonia, and a gas source corresponding to the doping source A, where the flow rate of silane is 45-50 sccm.

[0088] Preferably, in the present invention, the conditions for growing the second doped silicon in S4 include: introducing silane and a gas source corresponding to the doping source B, wherein the flow rate of silane is 45-50 sccm.

[0089] In the present invention, one of the gas sources corresponding to the doping source A and the gas sources corresponding to the doping source B is a boron source and the other is a phosphorus source. Further preferably, the flow rate of the boron source is 1-12 sccm, more preferably 8-12 sccm, and the flow rate of the phosphorus source is 1-12 sccm, more preferably 8-12 sccm. The boron source may be, for example, borane, and the phosphorus source may be, for example, phosphine; in practice, the phosphorus source and the boron source may be introduced separately, or may be introduced by carrying the corresponding doping source through hydrogen.

[0090] In some preferred embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer in S2 is 5-15 nm. Using an intrinsic amorphous silicon layer of appropriate thickness is more conducive to taking into account both the passivation effect and the series resistance, thereby improving the battery efficiency.

[0091] The method for depositing intrinsic amorphous silicon in S2 of the present invention may adopt PECVD technology, for example.

[0092] In some preferred embodiments of the present invention, the first doped silicon and the second doped silicon in S3 are each independently selected from correspondingly doped amorphous silicon or microcrystalline silicon, more preferably amorphous silicon.

[0093] In some preferred embodiments of the present invention, the distance between the hard mask and the backlight surface of the silicon wafer in S5 is controlled to be 0.2-200 μm, which is more conducive to controlling the width of the co-doped region.

[0094] In some preferred embodiments of the present invention, the thickness of the conductive film layer in S5 is 30-100 nm.

[0095] The conductive film layer of the present invention is preferably a transparent conductive film layer.

[0096] In some preferred embodiments of the present invention, the conductive film layer in S5 is deposited by magnetron sputtering.

[0097] Exemplarily, the magnetron sputtering deposition conditions of the conductive film layer include: a deposition temperature of 50-250° C. and a deposition time of 5-20 s.

[0098] In some preferred embodiments of the present invention, the thickness of the metal electrode in S6 is 3-20 μm.

[0099] In some preferred embodiments of the present invention, the silicon wafer in S1 is a silicon wafer with a light-receiving surface textured and a back-light surface polished.

[0100] In some preferred embodiments of the present invention, the etching-free manufacturing method of the back contact cell further includes the step of forming a passivation anti-reflection layer on the light-receiving surface of the silicon wafer in S1. The passivation anti-reflection layer may, for example, include a passivation layer and an anti-reflection layer arranged in sequence, which are prior arts and can be used in the present invention, and will not be described in detail here.

[0101] The size of the silicon wafer in S1 can be selected according to actual needs, for example, the size can be 156mm×156mm.

[0102] In a second aspect, the present invention provides a high-reliability back-contact battery, which is manufactured by the non-etching manufacturing method of the back-contact battery described in the first aspect. The back-contact battery manufactured by the non-etching manufacturing method of the back-contact battery of the present invention has improved reliability, stability and battery efficiency.

[0103] In a third aspect, the present invention provides a back-contact battery, comprising a silicon wafer, an intrinsic amorphous silicon layer being arranged on the backlight surface of the silicon wafer, a first doping region and a second doping region being arranged alternately outside the intrinsic amorphous silicon layer, and a co-doping region being arranged between the first doping region and the second doping region; one of the first doping region and the second doping region is N-type, and the other is P-type; the doping source of the co-doping region comprises a doping source A of the first doping region and a doping source B of the second doping region.

[0104] In the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the doping concentration of the doping source A in the co-doped region is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner.

[0105] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region with the first doped region close to the inner end of the silicon wafer as the starting point, the co-doped region is divided into a first region, a second intermediate region, and a third region in sequence, and the second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

[0106] In some preferred embodiments of the present invention, the doping source A comprises phosphorus, the doping source B comprises boron, and the phosphorus doping concentration in the second intermediate region is between 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 The phosphorus doping concentrations in the first region and the third region are independently 5e15cm -3 -2e20cm -3 , boron doping concentrations are independently 5e15cm -3 -2e20cm -3 .

[0107] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth of the concentrated double-doped region in the A-doped substrate accounts for 25%-80%.

[0108] In some preferred embodiments of the present invention, the depth of the concentrated dual-doped region is 5-30 nm.

[0109] In some preferred embodiments of the present invention, the ratio of the minimum doping concentration of the doping source A in the co-doping region to the doping concentration of the doping source A in the first doping region is 0.01-100:100.

[0110] Preferably, in the present invention, the ratio of the minimum doping concentration of the doping source B in the co-doping region to the doping concentration of the doping source B in the second doping region is 0.01-100:100.

[0111] In some preferred embodiments of the present invention, the phosphorus doping concentration in the co-doped region is 1e15 cm -3 -2e20cm -3 , preferably 1e15cm -3 -5e19cm -3 ; Its boron doping concentration is 1e15cm -3 -2e20cm -3 .

[0112] In some preferred embodiments of the present invention, the ratio of the width of the co-doped region to the width of the first doped region or the second doped region is 0.01-0.5:1, more preferably 0.01-0.20:1, and further preferably 0.10-0.20:1.

[0113] In some preferred embodiments of the present invention, the ratio of the thickness of the co-doped region to the thickness of the first doped region or the second doped region is 0.5-1.4:1, more preferably 0.8-1.4:1, and even more preferably 0.8-1.2:1.

[0114] In some preferred embodiments of the present invention, the width of the co-doped region is 5-150 μm.

[0115] In some preferred embodiments of the present invention, the thickness of the co-doped region is 5-30 nm.

[0116] In some preferred embodiments of the present invention, the thickness of the first doping region and the second doping region are independently 8-20 nm.

[0117] In some preferred embodiments of the present invention, the widths of the first doping region and the second doping region are independently 100-600 μm.

[0118] In some preferred embodiments of the present invention, one of the doping source A of the first doping region and the doping source B of the second doping region is phosphorus and the other is boron, wherein the phosphorus doping concentration is 2e18cm -3 -2e20cm -3 , the boron doping concentration is 2e18cm -3 -2e20cm -3 .

[0119] In some preferred embodiments of the present invention, the first doped region and the second doped region are each independently selected from correspondingly doped amorphous silicon or microcrystalline silicon.

[0120] In some preferred embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer is 5-15 nm.

[0121] In some preferred embodiments of the present invention, the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the first doping region or the second doping region is 0.5-2:1.

[0122] In some preferred embodiments of the present invention, in the width direction, the first doping region and the co-doping region, and the co-doping region and the second doping region are in contact with each other and are continuously distributed as a whole.

[0123] In some preferred embodiments of the present invention, the back contact cell further comprises a light-receiving surface passivation anti-reflection layer disposed on the light-receiving surface of the silicon wafer. The light-receiving surface passivation anti-reflection layer may be, for example, a passivation layer and an anti-reflection layer disposed in sequence. The passivation layer and the anti-reflection layer may refer to the front structure of the prior art, and both may be used in the present invention, which is prior art and will not be described in detail herein.

[0124] In some preferred embodiments of the present invention, the light-receiving surface of the silicon substrate is a textured surface, and the backlight surface is a polished surface.

[0125] In some preferred embodiments of the present invention, the back contact battery also includes a conductive film layer and a metal electrode sequentially arranged on the outer surfaces of the first doping region and the second doping region, an isolation trench is arranged between the conductive film layer arranged on the outer surface of the first doping region and the conductive film layer arranged on the outer surface of the second doping region, and at least a portion of the isolation trench is located on the outer surface of the co-doped region.

[0126] The back contact cell of the present invention can be made by the manufacturing method as described in the first aspect, or obtained by other existing processes. The back contact cell of the present invention is conducive to achieving higher photoelectric conversion efficiency, helping to reduce the cost of photovoltaic power generation, while improving cell stability, reliability and cell efficiency, and has broad market demand and good application prospects. And the back contact cell structure of the present invention can form a back contact cell structure without the need for high-temperature laser process and chemical etching process.

[0127] In a fourth aspect, the present invention provides a battery assembly, which includes the high reliability back contact battery described in the second aspect, or includes the back contact battery described in the third aspect. The battery assembly may include any combination of battery modules including the specific back contact battery of the present invention.

[0128] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0129] Example 1 A back contact battery having a structure as follows Figure 1 As shown, through Figure 3 The non-etching manufacturing method shown is prepared, which specifically includes the following steps: S1, providing a silicon wafer 1, performing texturing and cleaning on the silicon wafer 1, so that the light-receiving surface of the silicon wafer 1 is texturized, the backlight surface is polished, and a passivation anti-reflection layer is formed on the light-receiving surface of the silicon wafer 1; S2, depositing an intrinsic amorphous silicon layer 2 with a thickness of 7 nm on the backlight surface of the silicon wafer 1 by PECVD; S3, a first doping region 3 (N-type amorphous silicon), a second doping region 4 (P-type amorphous silicon) and a co-doping region 5 between the first doping region 3 and the second doping region 4 are preset to be alternately distributed on the outer surface of the intrinsic amorphous silicon layer 2; the doping source of the co-doping region 5 includes a doping source A of the first doping region 3, namely phosphorus, and a doping source B of the second doping region 4, namely boron; First, a first hard mask mask1 is used to cover the preset second doping region 4 and the preset co-doping region 5 on the backlight surface, and a first doped silicon with a thickness of 10 nm is grown on the backlight surface by PECVD to form a first doped region 3; wherein the distance D between the first hard mask mask1 and the intrinsic amorphous silicon layer 2 is controlled to be maintained at 0.12 mm; the gas concentration during the growth of the first doped silicon is: a silane flow rate of 50 sccm, and a mixed gas flow rate of hydrogen carrying phosphine (hydrogen volume accounting for 98%) is 100 sccm.

[0130] S4. Then, a second hard mask mask2 is used to block the preset first doping region 3 and the preset co-doping region 5 on the backlight surface, and a second doped silicon with a thickness of 10nm is grown by PECVD to form a second doped region 4; wherein, the distance d between the second hard mask mask2 and the intrinsic amorphous silicon layer 2 is maintained at 0.12mm; at the same time, a co-doped region 5 is naturally formed in the contact area between the first doped silicon and the second doped silicon; the width of the co-doped region 5 is 70μm and the thickness is 12nm, and the ratio of the thickness of the co-doped region 5 to the thickness of the first doped region 3 and the second doped region 4 is 1.2:1. The gas concentration during the growth of the second doped silicon is: the silane flow rate is 50 sccm, and the mixed gas flow rate of hydrogen carrying borane B2H6 (hydrogen volume accounts for 98%) is 150sccm. The phosphorus doping concentration of the first doped region 3 is 8e19cm -3 The boron doping concentration of the second doping region 4 is 2e19cm -3 The width of the first doping region 3 is 430 μm, the width of the second doping region 4 is 500 μm, and the ratios of the width of the co-doping region 5 to the width of the first doping region 3 and the width of the second doping region 4 are 0.16:1 and 0.14:1 respectively.

[0131] According to secondary ion mass spectrometry (SIMS), in the diagonal direction of the co-doped region 5 starting from the inner end of the first doped region 3 close to the silicon wafer 1 (eg Figure 1 In the direction of the arrow shown in the figure), the doping concentration of the doping source A in the co-doped region 5 is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner. In this regard, the co-doped region 5 is divided into a first region, a second intermediate region, and a third region in sequence. The second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by partially doping B in the A-doped substrate. The depth of the concentrated double-doped region in the A-doped substrate accounts for 50%; the depth of the concentrated double-doped region is 12nm. The phosphorus doping concentration in the second intermediate region is 5e15cm -3 -8e19cm -3 , boron doping concentration is 5e15cm -3 -2e19cm -3 The phosphorus doping concentration in the first region is 8e18cm -3 -8e19cm -3 , boron doping concentration is 5e15cm -3 -2e18cm -3 ; The phosphorus doping concentration in the third region is 5e15cm -3 -2e18cm -3 , boron doping concentration is 5e18cm -3 -2e19cm -3 .

[0132] S5, a hard mask mask 3 is set on the outer surface of the co-doped region 5, and a transparent conductive film layer 6 with a thickness of 60 nm is deposited on the backlight surface by magnetron sputtering; the distance between the hard mask mask 3 and the backlight surface of the silicon wafer 1 is controlled to be 50 μm; the deposition temperature is 150° C., and the deposition time is 10 s; S6. Print copper-silver paste on the outer surfaces of the first doping region 3 and the second doping region 4 respectively to form a metal electrode 7. The thickness of the metal electrode 7 is 10 μm.

[0133] Example 2 The method is carried out in accordance with Example 1, except that the width of the co-doped region is adjusted to 120 μm. To meet this condition, D in S3 needs to be controlled to be maintained at 200 μm, and d in S4 needs to be controlled to be maintained at 200 μm. After conversion, the ratio of D in S3 to the target thickness of the first doped silicon is 20000:1, and the ratio of d in S4 to the target thickness of the second doped silicon is 20000:1. After conversion, the ratios of the width of the co-doped region to the width of the first doped region and the width of the second doped region are 0.28:1 and 0.24:1, respectively.

[0134] In this embodiment, the phosphorus doping concentration in the second intermediate region is 5e15cm -3 -8e19cm -3, boron doping concentration is 5e15cm -3 -2e19cm -3 The corresponding phosphorus doping concentrations in the first and third regions are both 5e15cm -3 -8e19cm -3 , boron doping concentration is 5e15cm -3 -2e19cm -3 .

[0135] Example 3 The method is carried out in accordance with Example 1, except that the target thickness of the first doped silicon is adjusted to 15 nm; the target thickness of the second doped silicon is adjusted to 15 nm, and the thickness of the co-doped region is 20 nm. After conversion, the ratio of D in S3 to the target thickness of the first doped silicon is 8000:1, and the ratio of d in S4 to the target thickness of the second doped silicon is 8000:1.

[0136] Example 4 The method is carried out in accordance with Example 1, except that, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth of the concentrated double doped region is adjusted so that the depth of the concentrated double doped region in the A-doped substrate accounts for 70%. The process parameters that need to be adjusted to meet this condition are: D in S3 is adjusted to be maintained at 200 μm, and d in S4 is adjusted to be maintained at 100 μm.

[0137] Example 5 The method is carried out in accordance with Example 1, except that the phosphorus doping concentration in the co-doped region is adjusted to 5e15cm -3 -8e19cm -3 The minimum phosphorus doping concentration is 5e15cm -3 The process parameters for adjusting the first doped silicon in the corresponding preparation are: silane flow rate is 50 sccm, and the mixed gas flow rate of hydrogen carrying phosphine (hydrogen volume accounts for 98%) is 50 sccm. According to the corresponding detection, the phosphorus doping concentration in the second middle region of this embodiment is 5e15cm -3 -5e19cm -3 , boron doping concentration is 5e15cm -3 -2e19cm -3 The corresponding phosphorus doping concentrations in the first and third regions are both 8e18cm -3 -8e19cm -3 , boron doping concentration is 2e18cm -3 -2e19cm -3 .

[0138] Comparative Example 1 The method is carried out with reference to Example 1, except that a conventional interdigital structure is adopted instead of a co-doped region, and a conventional preparation process is adopted for this: after forming the intrinsic amorphous silicon layer, an N-type amorphous silicon layer and a mask layer are also formed, and the intrinsic amorphous silicon layer and the N-type amorphous silicon layer form a first semiconductor layer; then a first etching opening is performed on the obtained back surface to etch away the first semiconductor layer and its corresponding mask layer to form a second semiconductor opening region; then cleaning is performed to remove the mask layer and the first semiconductor layer remaining in the second semiconductor opening region; then a second semiconductor layer is deposited on the obtained back surface (i.e., the intrinsic amorphous silicon layer and the P-type amorphous silicon layer formed in sequence), and then a second etching opening is performed on part of the second semiconductor layer on the back surface of the silicon wafer to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region; then a conductive film layer is deposited to fully cover the obtained back surface; and a third etching opening is performed on part of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; and then metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0139] Comparative Example 2 The process is carried out with reference to Example 1, except that the co-doped region is replaced by an undoped intrinsic amorphous silicon layer; the process that needs to be modified accordingly to meet this condition is: In steps S3 and S4, a polymer mask layer is applied instead of a corresponding hard mask for masking. A polymer mask layer is applied to the preset second doping region and co-doping region, an N-type doped amorphous silicon layer, i.e., the first doping region, is deposited, and the polymer mask layer is removed. A polymer mask layer is then applied to the N-type doped amorphous silicon layer and the co-doping region, a P-type doped amorphous silicon layer, i.e., the second doping region, is deposited, and the polymer mask layer is removed; a polymer mask layer is then applied to the first doping region and the second doping region to prepare an intrinsic amorphous silicon layer in the region between the first doping region and the second doping region.

[0140] Comparative Example 3 The process is carried out with reference to Example 1, except that the intrinsic amorphous silicon layer is replaced by a tunnel oxide layer with a thickness of 1.5 nm.

[0141] Test Case The back-contact batteries obtained in the above-mentioned embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The method for measuring the production line equipment investment cost is: the production line investment cost corresponding to the annual production of 1GW of batteries. The method for measuring the production cycle is the production cycle from the input of silicon wafers to the finished battery. Among them, the production line equipment investment cost and production cycle of each embodiment and comparative examples 2-3 are respectively converted with comparative example 1 as the reference benchmark. The data of comparative example 1 is the normalized benchmark 1.0, and other examples are converted based on comparative example 1, such as the production line equipment investment cost of embodiment 1 / the production line equipment investment cost of comparative example 1 is 0.8. In addition, the test method for the production yield of the battery is: in a batch, the ratio of the number of qualified back-contact batteries produced in step S6 to the number of silicon wafers input in step S1. The reverse leakage current is measured according to GB / T 6495.

[0142] Table 1

[0143] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention avoids the use of high-temperature laser and chemical etching, thereby reducing damage to the battery and environmental pollution, significantly improving production yield, significantly reducing production costs, while improving battery reliability and service life, and achieving good battery efficiency.

[0144] Furthermore, according to Example 1 and Examples 2-5, it can be seen that the use of the preferred solution of the present invention is more conducive to improving the production yield, significantly reducing the production cost, while improving the reliability and service life of the battery, and obtaining good battery efficiency.

[0145] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A method for manufacturing a back contact battery without etching, characterized in that: The steps include: S1, provide silicon wafers; S2, depositing an intrinsic amorphous silicon layer on the backlit side of the silicon wafer; S3, a first doping region, a second doping region and a co-doping region between the first doping region and the second doping region are preset on the outer surface of the intrinsic amorphous silicon layer and are distributed alternately; one of the first doping region and the second doping region is N-type and the other is P-type; the doping source of the co-doping region includes a doping source A of the first doping region and a doping source B of the second doping region; First, a first hard mask is used to cover the preset second doping region and the preset co-doping region of the backlight surface, and a first doped silicon with a target thickness is grown on the backlight surface to form a first doped region; wherein a distance D between the first hard mask and the intrinsic amorphous silicon layer is controlled to be greater than the target thickness of the first doped silicon; S4, then using a second hard mask to cover the preset first doping region and the preset co-doping region of the backlight surface, and growing a second doped silicon of a target thickness to form a second doped region; wherein the distance d between the second hard mask and the intrinsic amorphous silicon layer is greater than the target thickness of the second doped silicon; and at the same time, a co-doping region is naturally formed in the contact area of ​​the first doped silicon and the second doped silicon; S5, setting a hard mask on the outer surface of the co-doped region, and depositing a conductive film layer on the backlight side; S6. Form metal electrodes on the outer surfaces of the first doping region and the second doping region respectively.

2. The method for manufacturing a back contact battery without etching according to claim 1, characterized in that: The ratio of D in S3 to the target thickness of the first doped silicon is 10-20000:1, and / or the ratio of d in S4 to the target thickness of the second doped silicon is 10-20000:

1.

3. The etching-free manufacturing method of a back contact battery according to claim 1 or 2, characterized in that: The target thickness of the first doped silicon is controlled within a range of 8-20 nm; and / or the target thickness of the second doped silicon is controlled within a range of 8-20 nm.

4. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The width of the co-doped region is 5-150 μm; and / or, Control D in S3 to be maintained at 0.2-200 μm, and control d in S4 to be maintained at 0.2-200 μm.

5. The non-etching manufacturing method of a back contact battery according to claim 1 or 4, characterized in that: The thickness of the co-doped region is 5-30 nm.

6. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: In the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the doping concentration of the doping source A in the co-doped region is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner.

7. The method for manufacturing a back contact cell without etching according to claim 6, characterized in that: In the diagonal direction of the co-doped region with the inner end of the first doped region close to the silicon wafer as the starting point, the co-doped region is divided into a first region, a second middle region, and a third region in sequence. The second middle region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

8. The method for manufacturing a back contact cell without etching according to claim 7, characterized in that: The doping source A contains phosphorus, the doping source B contains boron, and the phosphorus doping concentration in the second intermediate region is 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 The phosphorus doping concentrations in the first region and the third region are independently 5e15cm -3 -2e20cm -3 , boron doping concentrations are independently 5e15cm -3 -2e20cm -3 .

9. The method for manufacturing a back contact cell without etching according to claim 7, characterized in that: In the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth of the concentrated double-doped region in the A-doped substrate accounts for 25%-80%; and / or the depth of the concentrated double-doped region is 5-30nm.

10. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The ratio of the minimum doping concentration of the doping source A in the co-doping region to the doping concentration of the doping source A in the first doping region is 0.01-100:100, and the ratio of the minimum doping concentration of the doping source B in the co-doping region to the doping concentration of the doping source B in the second doping region is 0.01-100:100; and / or, One of the doping sources A of the first doping region and the second doping source B of the second doping region is phosphorus and the other is boron, wherein the phosphorus doping concentration is 2e18cm -3 -2e20cm -3 , the boron doping concentration is 2e18cm -3 -2e20cm -3 .

11. The method for manufacturing a back contact cell without etching according to any one of claims 8 or 10, characterized in that: The phosphorus doping concentration in the co-doped region is 1e15cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 and / or, The flow rates of the phosphorus source and the boron source during the growth processes of the first doped silicon and the second doped silicon are controlled to be 1-12 sccm and 1-12 sccm, respectively.

12. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The first doped silicon grown in S3 and the second doped silicon grown in S4 are each independently formed by plasma enhanced chemical vapor deposition or hot wire chemical vapor deposition; and / or, The conditions for growing the first doped silicon in S3 include: introducing silane and the doping source A corresponding to the gas source, where the flow rate of silane is 45-50sccm; the conditions for growing the second doped silicon in S4 include: introducing silane and the doping source B corresponding to the gas source, where the flow rate of silane is 45-50sccm; wherein, the doping source A corresponding to the gas source and the doping source B corresponding to the gas source, one of which is a boron source and the other is a phosphorus source, the flow rate of the boron source is 1-12sccm, and the flow rate of the phosphorus source is 1-12sccm.

13. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The thickness of the intrinsic amorphous silicon layer in S2 is 5-15 nm; and / or, The first doped silicon and the second doped silicon in S3 are independently selected from correspondingly doped amorphous silicon or microcrystalline silicon; and / or, The thickness of the conductive film layer in S5 is 30-100 nm; and / or, In S5, the conductive film layer is deposited by magnetron sputtering; and / or, The thickness of the metal electrode in S6 is 3-20 μm.

14. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: In S5, the distance between the hard mask and the backlight surface of the silicon wafer is controlled at 0.2-200μm.

15. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The silicon wafer in S1 is a silicon wafer with a light-receiving surface textured and a back-lighting surface polished; and / or, The etching-free manufacturing method of the back contact cell also includes the step of forming a passivation anti-reflection layer on the light-receiving surface of the silicon wafer in S1.

16. A high reliability back contact battery, characterized in that: The back contact cell is manufactured by the etching-free manufacturing method of the back contact cell according to any one of claims 1 to 15.

17. A back contact battery, characterized in that: The invention comprises a silicon wafer, an intrinsic amorphous silicon layer is arranged on the backlight surface of the silicon wafer, a first doping region and a second doping region are arranged outside the intrinsic amorphous silicon layer, and a co-doping region is arranged between the first doping region and the second doping region; one of the first doping region and the second doping region is N-type, and the other is P-type; the doping source of the co-doping region comprises a doping source A of the first doping region and a doping source B of the second doping region; in the diagonal direction of the co-doping region with the inner end of the first doping region close to the silicon wafer as the starting point, the doping concentration of the doping source A in the co-doping region is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner.

18. The back contact cell according to claim 17, characterized in that In the diagonal direction of the co-doped region with the inner end of the first doped region close to the silicon wafer as the starting point, the co-doped region is divided into a first region, a second middle region, and a third region in sequence. The second middle region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

19. The back contact cell according to claim 18, characterized in that The doping source A contains phosphorus, the doping source B contains boron, and the phosphorus doping concentration in the second intermediate region is 1e15 cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 The phosphorus doping concentrations in the first region and the third region are independently 5e15cm -3 -2e20cm -3 , boron doping concentrations are independently 5e15cm -3 -2e20cm -3 .

20. The back contact cell according to claim 18, characterized in that In the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth of the concentrated double-doped region in the A-doped substrate accounts for 25%-80%; and / or the depth of the concentrated double-doped region is 5-30nm.

21. The back contact cell according to any one of claims 17 to 20, characterized in that The ratio of the minimum doping concentration of the doping source A in the co-doping region to the doping concentration of the doping source A in the first doping region is 0.01-100:100, and the ratio of the minimum doping concentration of the doping source B in the co-doping region to the doping concentration of the doping source B in the second doping region is 0.01-100:100; and / or, The phosphorus doping concentration in the co-doped region is 1e15cm -3 -2e20cm -3 , boron doping concentration is 1e15cm -3 -2e20cm -3 .

22. The back contact cell according to claim 17, characterized in that The ratio of the width of the co-doped region to the width of the first doped region or the second doped region is 0.01-0.5:1; and / or, The ratio of the thickness of the co-doped region to the thickness of the first doped region or the second doped region is 0.5-1.4:

1.

23. The back contact cell according to claim 17 or 22, characterized in that: The width of the co-doped region is 5-150 μm; and / or, The thickness of the co-doped region is 5-30 nm; and / or, The thickness of the first doping region and the second doping region are independently 8-20 nm; and / or, The widths of the first doping region and the second doping region are independently 100-600 μm; and / or, One of the doping sources A of the first doping region and the second doping source B of the second doping region is phosphorus and the other is boron, wherein the phosphorus doping concentration is 2e18cm -3 -2e20cm -3 , the boron doping concentration is 2e18cm -3 -2e20cm -3 and / or, The first doped region and the second doped region are independently selected from correspondingly doped amorphous silicon or microcrystalline silicon.

24. The back contact cell according to claim 17, characterized in that The thickness of the intrinsic amorphous silicon layer is 5-15 nm; and / or the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the first doping region or the second doping region is 0.5-2:

1.

25. The back contact cell according to claim 17, characterized in that The back contact cell also includes at least one of the following structures: Structure 1: In the width direction, the first doping region and the co-doping region, and the co-doping region and the second doping region are in contact with each other and are continuously distributed as a whole; Structure 2: The back contact cell also includes a light-receiving surface passivation anti-reflection layer disposed on the light-receiving surface of the silicon wafer; Structure 3: The light-receiving side of the silicon substrate is a velvet surface, and the backlight side is a polished surface; Structure 4. The back-contact battery also includes a conductive film layer and a metal electrode sequentially arranged on the outer surfaces of the first doping region and the second doping region, an isolation groove is arranged between the conductive film layer arranged on the outer surface of the first doping region and the conductive film layer arranged on the outer surface of the second doping region, and at least a part of the isolation groove is located on the outer surface of the co-doped region.

26. A battery assembly, characterized in that: It comprises the high reliability back contact cell as claimed in claim 16, or comprises the back contact cell as claimed in any one of claims 17-25.

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