Array substrate and preparation method thereof, display panel and display device

Abstract

The invention discloses an array substrate and a preparation method thereof, a display panel and a display device. The array substrate comprises a substrate (1); the first electrode layer (4) is arranged on one side of the substrate (1) and comprises a first electrode (41); the first conducting layer (5) is arranged on the side, away from the substrate (1), of the first electrode layer (4) and comprises a source electrode (51) and a drain electrode (52), a first gap (54) is formed between the source electrode (51) and the drain electrode (52), and the orthographic projection of the drain electrode (52) on the substrate (1) and the orthographic projection of the first electrode layer (4) on the substrate (1) are overlapped; the organic planarization layer (6) comprises a plurality of organic flat portions (61) arranged at intervals, and the organic flat portions (61) are at least arranged in the first gaps (54) and at least do not cover the ends, away from the first gaps (54), of the source electrode (51) and the drain electrode (52). The included angle between the side wall, close to the first gap (54), of the organic flat part (61) and the face, close to the organic flat layer (6), of the first conductive layer (5) is smaller than the included angle between the side wall, close to the first gap (54), of the first conductive layer (5) and the face, close to the first conductive layer (5), of the first electrode layer (4). The organic active layer (7) is arranged on the side, away from the substrate (1), of the organic planarization layer (6) and is connected with the source electrode (51) and the drain electrode (52) on the side, away from the first gap (54), of the organic flat part (61).

Description

Array substrate and manufacturing method thereof, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0002] Flexible display devices are highly sought after by consumers due to their excellent flexibility, thin size, low power consumption, and resistance to rubbing. Flexible OLED (Organic Electroluminescence Display) displays are relatively mature, but flexible LCD (Liquid Crystal Display) devices have not yet reached mass production.

[0003] Summary of the Invention

[0004] The purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art and to provide an array substrate and a manufacturing method thereof, a display panel, and a display device.

[0005] According to one aspect of the present disclosure, there is provided an array substrate, comprising:

[0006] substrate;

[0007] A first electrode layer is provided on one side of the base substrate, wherein the first electrode layer includes a first electrode;

[0008] a first conductive layer, disposed on a side of the first electrode layer facing away from the base substrate, the first conductive layer comprising a source electrode and a drain electrode, a first gap being provided between the source electrode and the drain electrode, and an orthographic projection of the drain electrode on the base substrate overlapping with an orthographic projection of the first electrode layer on the base substrate;

[0009] an organic planarization layer comprising a plurality of spaced-apart organic planar portions, the organic planar portions being disposed at least within the first gap and at least not covering ends of the source and drain electrodes facing away from the first gap, wherein an angle between a sidewall of the organic planar portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a sidewall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer;

[0010] An organic active layer is provided on a side of the organic planarization layer away from the base substrate, and the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planar portion away from the first gap.

[0011] In an exemplary embodiment of the present disclosure, a distance between a side of the organic planar portion facing away from the base substrate and the base substrate is greater than or equal to a distance between a side of the first conductive layer facing away from the base substrate and the base substrate.

[0012] In an exemplary embodiment of the present disclosure, a portion of the organic flat portion is arranged on a side of the first conductive layer facing away from the base substrate. At a position close to the first gap, the orthographic projection of the organic flat portion on the base substrate overlaps with the orthographic projection of the source electrode on the base substrate, and the orthographic projection of the organic flat portion on the base substrate overlaps with the orthographic projection of the drain electrode on the base substrate.

[0013] In an exemplary embodiment of the present disclosure, an angle between a sidewall of the organic planar portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is less than or equal to 70°.

[0014] In an exemplary embodiment of the present disclosure, a distance between a side of the organic flat portion facing away from the base substrate and the first conductive layer is smaller than a thickness of the first conductive layer in a third direction perpendicular to a side of the base substrate close to the first electrode layer.

[0015] In an exemplary embodiment of the present disclosure, a surface of the organic planar portion facing away from the base substrate is connected to a sidewall of the organic planar portion via a curved surface.

[0016] In an exemplary embodiment of the present disclosure, the first conductive layer further includes a data line connected to the source electrode, and the first electrode layer further includes:

[0017] The resistance-reducing connection portion is spaced apart from the first electrode, and the orthographic projections of the source electrode and the data line on the base substrate are located within the orthographic projection of the resistance-reducing connection portion on the base substrate.

[0018] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0019] a gate insulating layer group, provided on a side of the organic active layer facing away from the base substrate, wherein an orthographic projection of the gate insulating layer group on the base substrate coincides with an orthographic projection of the organic active layer on the base substrate;

[0020] The gate layer is provided on a side of the gate insulating layer group away from the base substrate. The gate layer includes a gate. The orthographic projection of the gate on the base substrate coincides with the orthographic projection of the organic active layer on the base substrate.

[0021] In an exemplary embodiment of the present disclosure, the gate insulation layer group includes:

[0022] a first gate insulating layer, provided on a side of the organic active layer facing away from the base substrate;

[0023] The second gate insulating layer is provided on a side of the first gate insulating layer away from the base substrate, and the second gate insulating layer has a stronger barrier performance to the etching liquid of the gate layer than the first gate insulating layer.

[0024] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0025] a passivation layer, disposed on a side of the gate layer facing away from the substrate;

[0026] The second electrode layer is provided on a side of the passivation layer away from the base substrate. The second electrode layer includes second electrodes and gate connecting portions that are spaced apart. The gate connecting portions are connected to two adjacent gates.

[0027] In an exemplary embodiment of the present disclosure, the gate layer further includes:

[0028] A gate extension portion is connected to at least one side of the gate in a first direction, where the first direction is parallel to a surface of the array substrate close to the first electrode layer.

[0029] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0030] a passivation layer, disposed on a side of the gate layer facing away from the substrate;

[0031] The second electrode layer is provided on a side of the passivation layer away from the base substrate. The second electrode layer includes a second electrode and a gate connecting portion that are spaced apart. The gate connecting portion is connected to two adjacent gate extension portions.

[0032] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0033] The conductive enhancement layer is provided on a side of the second electrode layer away from the base substrate, and the orthographic projection of the conductive enhancement layer on the base substrate is located within the orthographic projection of the gate connecting portion on the base substrate.

[0034] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0035] a light shielding layer provided on one side of the base substrate, wherein the orthographic projection of the organic active layer on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate;

[0036] a second planarization layer, disposed on a side of the light shielding layer away from the base substrate; the first electrode layer is disposed on a side of the second planarization layer away from the base substrate; and a third via hole is disposed on the second planarization layer;

[0037] a passivation layer, disposed on a side of the gate layer facing away from the base substrate, the passivation layer being provided with a first via hole and a second via hole, the first via hole being connected to the gate, the second via hole being connected to the third via hole and connected to the light shielding layer;

[0038] The second electrode layer is arranged on the side of the passivation layer away from the base substrate. The second electrode layer includes a second electrode and a gate connecting portion arranged at intervals. The gate connecting portion is connected to the gate through the first via hole, and is connected to the light-shielding layer through the second via hole and the third via hole. The light-shielding layer is multiplexed as a gate line and a second gate.

[0039] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0040] The protective layer at least covers the sidewalls of the organic active layer.

[0041] In an exemplary embodiment of the present disclosure, the protective layer is arranged between the gate layer and the first electrode and the passivation layer, and covers the organic active layer, the gate insulation layer group and the side wall of the gate, and the matching between the protective layer and the organic active layer is stronger than the matching between the passivation layer and the organic active layer.

[0042] In an exemplary embodiment of the present disclosure, a work function of the first conductive layer is greater than 4.5 eV.

[0043] In an exemplary embodiment of the present disclosure, the array substrate is a flexible array substrate.

[0044] According to another aspect of the present disclosure, a method for preparing an array substrate is provided, comprising:

[0045] providing a substrate;

[0046] A first electrode layer and a first conductive layer are sequentially stacked on one side of the base substrate, wherein the first electrode layer includes a first electrode, and the first conductive layer includes a source electrode and a drain electrode, a first gap is provided between the source electrode and the drain electrode, and an orthographic projection of the drain electrode on the base substrate overlaps with an orthographic projection of the first electrode layer on the base substrate;

[0047] forming an organic planarization layer, the organic planarization layer comprising a plurality of organic planar portions spaced apart from each other, the organic planar portions being at least disposed within the first gap;

[0048] forming an organic active layer on a side of the organic planarization layer away from the base substrate, wherein the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planar portion away from the first gap;

[0049] The organic flat portion at least does not cover the end portions of the source and the drain facing away from the first gap, and the angle between the side wall of the organic flat portion close to the first gap and the side of the first conductive layer close to the organic planarization layer is smaller than the angle between the side wall of the first conductive layer close to the first gap and the side of the first electrode layer close to the first conductive layer.

[0050] In an exemplary embodiment of the present disclosure, a gate insulating layer group and a gate layer are formed simultaneously with forming the organic active layer on a side of the organic planarization layer facing away from the base substrate.

[0051] In an exemplary embodiment of the present disclosure, forming an organic active layer on a side of the organic planarization layer facing away from the base substrate and forming a gate insulating layer group and a gate layer at the same time include:

[0052] forming an organic active material layer, a gate insulating material layer group, and a gate material layer in sequence on a side of the organic planarization layer facing away from the base substrate;

[0053] performing patterning on the gate material layer to form the gate layer;

[0054] The gate insulating material layer group and the organic active material layer are patterned using the gate layer as a mask to form the gate insulating layer group and the organic active layer.

[0055] In an exemplary embodiment of the present disclosure, a first electrode layer and a first conductive layer stacked in sequence are formed on one side of the base substrate, including:

[0056] A first electrode material layer and a first conductive material layer are sequentially formed on one side of the base substrate.

[0057] forming a mask layer on a side of the first conductive material layer facing away from the base substrate, and performing a half-mask process on the mask layer to form a mask pattern, wherein the mask pattern includes a first portion and a second portion, the first portion is thicker than the second portion, the first portion is disposed opposite to the first conductive layer and a portion of the first electrode layer, and the second portion is disposed opposite to another portion of the first electrode layer;

[0058] Etching and removing the exposed first conductive material layer, and etching and removing the first electrode material layer to form the first electrode layer;

[0059] performing an ashing process on the mask pattern to remove the second portion, so as to expose the first conductive material layer covered by the second portion;

[0060] The remaining first conductive material layer is patterned to form the first conductive layer.

[0061] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0062] A passivation layer is formed on a side of the gate layer facing away from the substrate, and the passivation layer is patterned to form a first via hole.

[0063] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0064] A protection layer and a passivation layer are sequentially formed on a side of the gate layer facing away from the base substrate, and the passivation layer is patterned to form a first via hole, and the protection layer is patterned to form a fourth via hole.

[0065] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0066] A protective layer and a passivation layer are sequentially formed on a side of the gate layer facing away from the base substrate, and the passivation layer is patterned to form a first via and a second via, and the protective layer is simultaneously patterned to form a fourth via and a fifth via, and the second planarization layer is simultaneously patterned to form a third via, the fourth via is connected to the first via, and the fifth via is connected to the second via and the third via.

[0067] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0068] A second electrode material layer is formed on a side of the passivation layer facing away from the substrate, and the second electrode material layer is patterned to form a second electrode layer.

[0069] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0070] A second electrode material layer and a conductive enhancement material layer are sequentially formed on a side of the passivation layer facing away from the substrate, and the conductive enhancement material layer and the second electrode material layer are patterned to form a conductive enhancement layer and a second electrode layer.

[0071] According to another aspect of the present disclosure, there is provided a display panel, comprising:

[0072] An array substrate is any one of the array substrates described above;

[0073] a color filter substrate, arranged opposite to the array substrate;

[0074] The liquid crystal layer is arranged between the array substrate and the color filter substrate.

[0075] In an exemplary embodiment of the present disclosure, the array substrate is a flexible array substrate, and the color filter substrate is a flexible color filter substrate.

[0076] According to another aspect of the present disclosure, a display device is provided, comprising: a display panel as described in any one of the above, wherein the display device is a rollable display device, a foldable display device, or a curved display device.

[0077] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0079] FIG1 is a schematic structural diagram of a first exemplary embodiment of an array substrate disclosed herein.

[0080] FIG2 is a schematic structural diagram of the light-shielding layer in FIG1 .

[0081] FIG3 is a schematic structural diagram after a first electrode layer and a first conductive layer are formed on the basis of FIG2 .

[0082] FIG. 4 is a schematic structural diagram after an organic planarization layer is formed on the basis of FIG. 3 .

[0083] FIG5 is a schematic structural diagram of the structure after an organic active layer, a gate insulating layer group and a gate layer are formed on the basis of FIG4 .

[0084] FIG6 is a schematic structural diagram of the organic active layer, the gate insulating layer group and the gate layer in FIG5 .

[0085] FIG. 7 is a schematic structural diagram after a second electrode layer is formed on the basis of FIG. 5 .

[0086] FIG8 is a schematic structural diagram of the second electrode layer in FIG7 .

[0087] FIG9 is a schematic cross-sectional view taken along line BB in FIG7 .

[0088] FIG10 is a schematic structural diagram of a second exemplary embodiment of an array substrate disclosed herein.

[0089] FIG11 is a schematic structural diagram of a third exemplary embodiment of an array substrate disclosed herein.

[0090] FIG12 is a structural diagram of another exemplary embodiment after an organic active layer, a gate insulating layer group, and a gate layer are formed on the basis of FIG4 .

[0091] FIG13 is a schematic structural diagram of the organic active layer, the gate insulating layer group and the gate layer in FIG12 .

[0092] FIG14 is a schematic structural diagram after a second electrode layer is formed on the basis of FIG12 .

[0093] FIG15 is a schematic structural diagram of the second electrode layer in FIG14 .

[0094] FIG16 is a structural schematic diagram of a fourth exemplary embodiment of an array substrate according to the present disclosure, cut along line BB in FIG7 or 14 .

[0095] FIG17 is a schematic structural diagram of a fourth exemplary embodiment of an array substrate according to the present disclosure, cut along AA in FIG7 or 14 .

[0096] FIG18 is a structural schematic diagram of a fifth exemplary embodiment of an array substrate according to the present disclosure, cut along AA in FIG7 or 14 .

[0097] FIG19 is a structural schematic diagram of the fifth exemplary embodiment of the array substrate disclosed herein, cut along line BB in FIG7 or 14 .

[0098] FIG20 is a schematic structural diagram of a sixth exemplary embodiment of an array substrate according to the present disclosure.

[0099] FIG21 is a schematic flow chart of an exemplary embodiment of a method for preparing an array substrate disclosed herein.

[0100] 22 to 40 are schematic structural diagrams of various steps of the method for preparing an array substrate disclosed herein.

[0101] Description of reference numerals:

[0102] 1. Base substrate; 21. First planarization layer; 22. Second planarization layer; 221. Third via hole;

[0103] 3. Light-shielding layer; 31. Light-shielding portion;

[0104] 40. First electrode material layer; 4. First electrode layer; 41. First electrode; 42. Resistance-reducing connection portion; 43. Second gap;

[0105] 50. First conductive material layer; 5. First conductive layer; 51. Source electrode; 52. Drain electrode; 53. Data line; 54. First gap;

[0106] 6. Organic planarization layer; 61. Organic planar portion;

[0107] 70. Organic active material layer; 7. Organic active layer;

[0108] 8. Gate insulating layer group; 810. First gate insulating material layer; 81. First gate insulating layer; 820. Second gate insulating material layer; 82. Second gate insulating layer;

[0109] 90. Gate material layer; 9. Gate layer; 91. Gate; 92. Gate extension;

[0110] 10. passivation layer; 101. first via hole; 102. second via hole;

[0111] 11. Second electrode layer; 111. Second electrode; 112. Gate connecting portion;

[0112] 12. Adhesive layer; 13. Glass substrate; 14. Protective layer; 141. Fourth via hole;

[0113] 15. Conductive reinforcement layer;

[0114] 16. Mask pattern; 161. First portion; 162. Second portion; 17. Second mask pattern;

[0115] X, first direction; Y, second direction; Z, third direction. DETAILED DESCRIPTION

[0116] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0117] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0118] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0119] An example embodiment of the present disclosure provides an array substrate, as shown in Figures 1 to 20 and Figures 22 to 40. Figure 1 is a schematic cross-sectional view taken along line AA in Figure 7. Since the organic active layer 7, the gate insulating layer group 8, and the gate layer 9 are formed through the same patterning process, only the topmost gate layer 9 is shown in Figures 5, 12, and 37. In order to illustrate the connection relationship of the gate, Figures 2 to 8 and 12 to 15 only illustrate the specific structure of a complete sub-pixel and the data line of another adjacent sub-pixel, part of the gate, and part of the light-shielding layer. Figure 20 is a schematic cross-sectional view taken along line CC in Figure 40. In Figure 40, in order to avoid the second electrode 111 blocking the lower layer, the second electrode 111 is omitted and only the gate connection portion 112 is drawn.

[0120] The array substrate may include a base substrate 1, a first electrode layer 4, a first conductive layer 5, an organic planarization layer 6, and an organic active layer 7; the first electrode layer 4 is provided on one side of the base substrate 1, and the first electrode layer 4 includes a first electrode 41; the first conductive layer 5 is provided on the side of the first electrode layer 4 away from the base substrate 1, and the first conductive layer 5 includes a source electrode 51 and a drain electrode 52, a first gap 54 is provided between the source electrode 51 and the drain electrode 52, and the orthographic projection of the drain electrode 52 on the base substrate 1 overlaps with the orthographic projection of the first electrode layer 4 on the base substrate 1; the organic planarization layer 6 may include a plurality of organic planar portions 61 provided at intervals. The organic flat portion 61 is at least arranged in the first gap 54, and the organic flat portion 61 does not at least cover the ends of the source electrode 51 and the drain electrode 52 facing away from the first gap 54. The angle between the side wall of the organic flat portion 61 close to the first gap 54 and the surface of the first conductive layer 5 close to the organic planarization layer 6 is smaller than the angle between the side wall of the first conductive layer 5 close to the first gap 54 and the surface of the first electrode layer 4 close to the first conductive layer 5. The organic active layer 7 is arranged on the side of the organic planarization layer 6 facing away from the base substrate 1, and the organic active layer 7 is connected to the source electrode 51 and the drain electrode 52 on the side of the organic flat portion 61 facing away from the first gap 54.

[0121] In the array substrate disclosed herein, on one hand, the angle between the sidewall of the organic planarization layer 6 near the first gap 54 and the side of the first conductive layer 5 near the organic planarization layer 6 is smaller than the angle between the sidewall of the first conductive layer 5 near the first gap 54 and the side of the first electrode layer 4 near the first conductive layer 5. Thus, the organic active layer 7 does not form a gap on the sidewall of the organic planarization layer 6 and will not break due to the gap. On the other hand, the organic planarization portion 61 is at least provided within the first gap 54. The distance between the side of the organic planarization portion 61 facing away from the base substrate 1 and the base substrate 1 is greater than or equal to the distance between the side of the first conductive layer 5 facing away from the base substrate 1 and the base substrate 1. This allows the organic planarization portion 61 to shield the corners of the source electrode 51 and the drain electrode 52 near the first gap 54, preventing the sharp corners formed by the corners of the source electrode 51 and the drain electrode 52 near the first gap 54 from being covered by the organic active layer 7. This ensures that the organic active layer 7 can effectively cover the organic planarization portion 61 and the first conductive layer 5, achieving a good conductive effect. On the other hand, the array substrate uses an organic active layer 7 and an organic planarization layer 6, and the overall process temperature is less than 100° C., so that the array substrate has sufficient flexibility and can be used for a flexible display panel.

[0122] In this exemplary embodiment, the array substrate is a flexible array substrate. Therefore, the base substrate 1 is a flexible substrate. The base substrate 1 is made of a flexible material. Specifically, the base substrate 1 can be made of a resin material such as triacetate film, polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The base substrate 1 can be formed from multiple layers of material. For example, the base substrate 1 can include multiple base material layers, each of which can be made of any of the aforementioned materials. Of course, the base substrate 1 can also be a single layer, made of any of the aforementioned materials.

[0123] In order to facilitate the preparation, transportation, etc. of the array substrate, the base substrate 1 can be adhered to the peeling substrate through the adhesive layer 12, and the glass substrate 13 can be peeled off when used. Of course, when the array substrate is used as a rigid base substrate 1, the glass substrate 13 can be left intact, or the glass substrate 13 can be omitted, and other hard substrates can be used.

[0124] A plurality of thin film transistors arranged in an array may be provided on one side of the base substrate 1 . The thin film transistors may include at least a source electrode 41 , a drain electrode 42 , an organic active layer 7 and a first gate electrode 91 .

[0125] As shown in Figure 1, a first planarization layer 21 can be provided on one side of the base substrate 1. The material of the first planarization layer 21 has strong adhesion, strong resistance to chemical solvents, good planarization, and high light transmittance. It also has low polarity to reduce channeling and leakage current. The material of the first planarization layer 21 can be an epoxy resin-based photoresist, such as SU-8 series epoxy resin-based photoresist. A light shielding layer 3 is provided on the side of the first planarization layer 21 facing away from the base substrate 1. Light entering the organic active layer 7 from the base substrate 1 side generates photogenerated carriers in the organic active layer 7, which in turn significantly affects the characteristics of the thin-film transistor and ultimately the display quality of the display device. The light shielding layer 3 can block light entering from the base substrate 1 side, thereby preventing it from affecting the characteristics of the thin-film transistor and the display quality of the display device. Depending on the type of thin-film transistor, the light shielding layer 3 may be omitted.

[0126] 1 and 2 , the light shielding layer 3 may include a plurality of spaced-apart light shielding portions 31, with one light shielding portion 31 corresponding to each thin-film transistor. Referring to FIG22 , the light shielding layer 3 may include a plurality of strip-shaped light shielding portions 31 extending along a first direction, with one strip-shaped light shielding portion 31 corresponding to a plurality of thin-film transistors arranged along the first direction. That is, the organic active layer 7 of the plurality of thin-film transistors arranged along the first direction is shielded by one strip-shaped light shielding portion 31.

[0127] A second planarization layer 22 may be provided on the side of the light-shielding layer 3 facing away from the base substrate 1. The second planarization layer 22 is made of an insulating material and serves to insulate and isolate the light-shielding layer 3 from the first conductive layer 5. The material of the second planarization layer 22 has strong adhesion, strong resistance to chemical solvents, good planarization, and high light transmittance. It also has low polarity to reduce channeling and leakage current. Specifically, the second planarization layer 22 may be made of an epoxy resin photoresist, such as an SU-8 series epoxy resin photoresist. The thickness of the second planarization layer 22 is greater than or equal to 1 micron.

[0128] In this example embodiment, as shown in Figures 1 and 3, a first electrode layer 4 may be provided on the side of the second planarization layer 22 facing away from the base substrate 1. The first electrode layer 4 may include spaced first electrodes 41 and resistance-reducing connectors 42. The first electrodes 41 may be pixel electrodes, and therefore, multiple first electrodes 41 are spaced apart. One first electrode 41 is provided for each sub-pixel. The resistance-reducing connector 42 is configured as a strip extending along the second direction. The first electrode layer 4 may be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), or the like.

[0129] In this exemplary embodiment, a first conductive layer 5 may be provided on a side of the first electrode layer 4 facing away from the base substrate 1. The first conductive layer 5 may include a data line 53, a source electrode 51, and a drain electrode 52. The data line 53 extends along the second direction Y, and a portion of the data line 53 may be reused as the source electrode 51. Alternatively, the data line 53 connects multiple source electrodes 51 arranged along the second direction Y, allowing data signals to be input to the multiple source electrodes 51 arranged along the second direction Y via a single data line 53. A first gap 54 is provided between the source electrode 51 and the drain electrode 52.

[0130] Since the first electrode layer 4 and the first conductive layer 5 are formed through the same patterning process, and the first conductive layer 5 is located above the first electrode layer 4, there must be a first electrode layer 4 between the first conductive layer 5 and the base substrate 1, that is, the area of ​​the first electrode layer 4 is at least the same as the area of ​​the first conductive layer 5, or the area of ​​the first electrode layer 4 is larger than the area of ​​the first conductive layer 5; specifically, the orthographic projection of the drain 52 on the base substrate 1 overlaps with the orthographic projection of the first electrode layer 4 on the base substrate 1, for example, the orthographic projection of the first electrode layer 4 on the base substrate 1 covers the orthographic projection of the drain 52 on the base substrate 1, and the area of ​​the orthographic projection of the first electrode layer 4 on the base substrate 1 is larger than the area of ​​the orthographic projection of the drain 52 on the base substrate 1. Moreover, the orthographic projections of the source electrode 51 and the data line 53 on the base substrate 1 are located within the orthographic projection of the resistance reduction connection portion 42 on the base substrate 1. For example, the orthographic projection of the resistance reduction connection portion 42 on the base substrate 1 coincides with the orthographic projections of the source electrode 51 and the data line 53 on the base substrate 1; or, the orthographic projection of the resistance reduction connection portion 42 on the base substrate 1 covers the orthographic projections of the source electrode 51 and the data line 53 on the base substrate 1, and the orthographic projection area of ​​the resistance reduction connection portion 42 on the base substrate 1 is larger than the orthographic projection area of ​​the source electrode 51 and the data line 53 on the base substrate 1.

[0131] The thickness of the first conductive layer 5 is greater than or equal to 500 angstroms and less than or equal to 8000 angstroms. For example, the thickness of the first conductive layer 5 can be 650 angstroms, 982 angstroms, 1020 angstroms, 1190 angstroms, 1380 angstroms, 1850 angstroms, 2340 angstroms, 2840 angstroms, 3240 angstroms, 3840 angstroms, 4180 angstroms, 4586 angstroms, 5170 angstroms, 5760 angstroms, 6230 angstroms, 6840 angstroms, 7520 angstroms, 7850 angstroms, etc.

[0132] It should be noted that the so-called "overlap" does not mean complete overlap, but has a certain error. The error range varies depending on the equipment and preparation process. Therefore, within the error range of the equipment and preparation process, it is considered to be overlap.

[0133] The functions of the "source electrode 41" and the "drain electrode 42" may be interchanged when using thin film transistors with opposite polarities or when the current direction changes during circuit operation. Therefore, in this specification, the "source electrode 41" and the "drain electrode 42" may be interchanged.

[0134] In this example embodiment, referring to Figures 1 and 4, an organic planarization layer 6 can be provided on the side of the first conductive layer 5 away from the base substrate 1. Specifically, the material of the organic planarization layer 6 needs to be resistant to chemical solvents and can protect the first conductive layer 4; and it has high light transmittance to avoid affecting the light transmittance of the display panel; and it has low polarity. Low polarity means that the dipole in the molecule is small and the charge distribution is more uniform. Simply put, it is relatively symmetrical and generally has few lone pairs of electrons. Low polarity can reduce the induced charge to form polarization, thereby reducing the back channel effect and reducing leakage current. For example, the material of the organic planarization layer 6 can be SU-8 series epoxy photoresist, and other materials with low dielectric constants can also be selected.

[0135] The organic planarization layer 6 may include a plurality of organic planar portions 61 arranged at intervals, that is, the organic planar portions 61 are arranged as an island structure, and one thin film transistor may include one organic planar portion 61 .

[0136] The organic flat portion 61 is at least arranged in the first gap 54, and the organic flat portion 61 does not cover at least the ends of the source electrode 51 and the drain electrode 52 away from the first gap 54; such an arrangement enables the source electrode 51 and the drain electrode 52 to ensure connection with the organic active layer 7 even when the area is small, so that the area of ​​the subsequently formed organic active layer 7 is smaller, the area of ​​the thin film transistor is smaller, and the aperture ratio of the entire array substrate and the display panel is increased.

[0137] The orthographic projection of the organic active layer 7 on the base substrate 1 is located within the orthographic projection of the light shielding layer 3 on the base substrate 1, so that the light shielding layer 3 can block light from reaching the organic active layer 7. Specifically, the orthographic projection of the organic active layer 7 on the base substrate 1 can overlap with the orthographic projection of the light shielding layer 3 on the base substrate 1, or the orthographic projection of the light shielding layer 3 on the base substrate 1 covers the orthographic projection of the organic active layer 7 on the base substrate 1, and the orthographic projection area of ​​the light shielding layer 3 on the base substrate 1 is larger than the orthographic projection area of ​​the organic active layer 7 on the base substrate 1. For example, the distance between the edge of the orthographic projection of the light shielding layer 3 on the base substrate 1 and the edge of the orthographic projection of the organic active layer 7 on the base substrate 1 is greater than or equal to 2 microns. This configuration ensures that even if there are process or equipment errors, the orthographic projection of the organic active layer 7 on the base substrate 1 can still be located within the orthographic projection of the light shielding layer 3 on the base substrate 1.

[0138] For example, as shown in Figure 10, the organic flat portion 61 is only arranged in the first gap 54, so that the distance between the side of the organic flat portion 61 facing away from the substrate 1 and the substrate 1 is equal to the distance between the side of the first conductive layer 5 facing away from the substrate 1 and the substrate 1, that is, the organic flat portion 61 fills the first gap 54 between the source 51 and the drain 52, and the organic flat portion 61 covers the sharp corners of the corners of the source 51 and the drain 52; so that the subsequently formed organic active layer 7 does not need to climb, the organic active layer 7 will not form gaps, and will not be broken due to the gaps.

[0139] As shown in Figure 11, the organic flat portion 61 is not only arranged in the first gap 54, but also protrudes from the first conductive layer 5, so that the distance between the side of the organic flat portion 61 facing away from the base substrate 1 and the base substrate 1 is greater than the distance between the side of the first conductive layer 5 facing away from the base substrate 1 and the base substrate 1. However, the organic flat portion 61 does not cover the first conductive layer 5. This arrangement allows the organic flat portion 61 to fill the first gap 54 between the source 51 and the drain 52, and the organic flat portion 61 covers the sharp corners of the corners of the source 51 and the drain 52; so that the subsequently formed organic active layer 7 does not need to climb the side walls of the source 51 and the drain 52, thereby avoiding gaps in the organic active layer 7 and preventing it from breaking due to the gaps.

[0140] Furthermore, the distance H1 between the surface of the organic flat portion 61 facing away from the base substrate 1 and the first conductive layer 5 is less than the thickness H2 of the first conductive layer 5 in the third direction Z. That is, the height of the organic flat portion 61 protruding from the first conductive layer 5 is less than the thickness of the first conductive layer 5. The third direction Z is perpendicular to the surface of the base substrate 1 near the first electrode layer 4. This allows the subsequently formed organic active layer 7 to slope along the sidewalls of the organic flat portion 61, but at a low slope height, preventing gaps in the organic active layer 7 and preventing breakage due to gaps.

[0141] When the organic active layer 77 is directly in contact with the first conductive layer 54, the thickness of the first conductive layer 54 needs to be set relatively low to prevent the organic active layer 77 from climbing too high. The material of the first conductive layer 54 also needs to be considered to prevent the sidewalls formed by the first conductive layer 54 from being too steep. However, the slope of the sidewalls of the first conductive layer 54 is still relatively steep. For example, the angle between the sidewall of the first conductive layer 54 near the first gap 54 and the surface of the substrate 11 near the first conductive layer 54 is generally greater than 70 degrees. In addition, a sharp angle structure is easily formed at the corner of the first conductive layer 54 facing away from the substrate 11. The subsequently formed organic active layer 77 will form a gap in the sidewall of the first conductive layer 54. Due to the gap, the organic active layer 77 is easily broken, resulting in a short circuit. Moreover, the existence of the sharp angle structure results in poor coverage of the organic active layer 77 at the corner of the first conductive layer 54 facing away from the substrate 11, which is also likely to cause the organic active layer 77 to break, resulting in a short circuit.

[0142] Furthermore, the angle α between the side wall of the organic planarization layer 6 close to the first gap 54 and the side of the first conductive layer 5 close to the organic planarization layer 6 is smaller than the angle β between the side wall of the first conductive layer 5 close to the first gap 54 and the side of the first electrode layer 4 close to the first conductive layer 5; that is, the inclination angle of the side wall of the organic planarization layer 6 is smaller than the inclination angle of the side wall of the source 51 and the drain 52 of the first conductive layer 5; specifically, the angle α between the side wall of the organic flat portion 61 close to the first gap 54 and the side of the first conductive layer 5 facing away from the base substrate 1 is less than or equal to 70°, that is, although the organic flat portion 61 has a side wall, the slope of the side wall of the organic flat portion 61 is relatively gentle. Even if the subsequently formed organic active layer 7 climbs the side wall of the organic flat portion 61, no gap will appear and the layer will not break due to the gap.

[0143] Furthermore, the organic flat portion 61 is made of an organic material, and its corners are relatively smooth. These corners can be curved, meaning that the side of the organic flat portion 61 facing away from the base substrate 1 is connected to the sidewall via a curved surface. This prevents sharp corners from forming at the corners of the source 51 and drain 52. Consequently, the subsequently formed organic active layer 7 provides excellent coverage of the corners of the organic flat portion 61, preventing cracking at the corners.

[0144] However, the above-mentioned two structures require high process precision. Therefore, as shown in FIG1 , the organic planar portion 61 is not only disposed within the first gap 54 but also protrudes from the first conductive layer 5, such that the distance between the side of the organic planar portion 61 facing away from the base substrate 1 and the base substrate 1 is greater than the distance between the side of the first conductive layer 5 facing away from the base substrate 1 and the base substrate 1. Furthermore, a portion of the organic planar portion 61 is disposed on the side of the first conductive layer 5 facing away from the base substrate 1, that is, a portion of the organic planarization layer 6 is disposed on the side of the source electrode 51 facing away from the base substrate 1, and another portion of the organic planarization layer 6 is disposed on the side of the drain electrode 52 facing away from the base substrate 1. This results in the orthographic projection of the organic planar portion 61 on the base substrate 1 overlapping with the orthographic projection of the source electrode 51 on the base substrate 1, and the orthographic projection of the organic planar portion 61 on the base substrate 1 overlapping with the orthographic projection of the drain electrode 52 on the base substrate 1. Specifically, the width of the overlapping portion of the orthographic projection of the organic flat portion 61 on the base substrate 1 and the orthographic projection of the source electrode 51 on the base substrate 1 is less than 5 microns, and the width of the overlapping portion of the orthographic projection of the organic flat portion 61 on the base substrate 1 and the orthographic projection of the drain electrode 52 on the base substrate 1 is also less than 5 microns, so as to avoid the organic flat portion 61 covering too much of the source electrode 51 and the drain electrode 52, thereby preventing the subsequently formed organic active layer 7 from being unstable in connection with the source electrode 51 and the drain electrode 52.

[0145] In addition, to prevent the organic flat portion 231 from being unable to fill the first gap due to errors in the process or equipment, the width of the overlapping portion between the orthographic projection of the organic flat portion 61 on the base substrate 1 and the orthographic projection of the source electrode 51 on the base substrate 1 is greater than or equal to 2 microns, for example, it can be 2.5 microns, 2.85 microns, 3.1 microns, 3.6 microns, 4.25 microns, 4.7 microns, etc.; similarly, the width of the overlapping portion between the orthographic projection of the organic flat portion 61 on the base substrate 1 and the orthographic projection of the drain electrode 52 on the base substrate 1 is also greater than or equal to 2 microns, for example, it can be 2.5 microns, 2.85 microns, 3.1 microns, 3.6 microns, 4.25 microns, 4.7 microns, etc.

[0146] Of course, the above data may also be other values ​​depending on the accuracy of the product and process equipment.

[0147] Such a configuration enables the organic flat portion 61 to fill the first gap 54 between the source electrode 51 and the drain electrode 52, and the organic flat portion 61 to completely cover the sharp corners of the corners of the source electrode 51 and the drain electrode 52; so that the subsequently formed organic active layer 7 does not need to climb the side walls of the source electrode 51 and the drain electrode 52, thereby avoiding the appearance of gaps in the organic active layer 7 and not breaking due to the gaps; moreover, the requirements for process and equipment precision are low. Even if errors occur during the preparation process and the position of the organic flat portion 61 is shifted, the organic flat portion 61 will fill the first gap 54 between the source electrode 51 and the drain electrode 52, and the organic flat portion 61 will completely cover the sharp corners of the corners of the source electrode 51 and the drain electrode 52.

[0148] Furthermore, the distance H1 between the side of the organic planar portion 61 facing away from the base substrate 1 and the first conductive layer 5 can be less than the thickness H2 of the first conductive layer 5 in the third direction Z. That is, the height of the organic planar portion 61 protruding from the first conductive layer 5 is less than the thickness of the first conductive layer 5; the third direction Z is perpendicular to the side of the base substrate 1 adjacent to the first electrode layer 4. This allows the subsequently formed organic active layer 7 to slope along the sidewalls of the organic planar portion 61, but at a low slope height, thereby preventing gaps in the organic active layer 7 and preventing fractures due to gaps. Of course, in other exemplary embodiments of the present disclosure, the distance H1 between the side of the organic planar portion 61 facing away from the base substrate 1 and the first conductive layer 5 can also be equal to or greater than the thickness H2 of the first conductive layer 5 in the third direction Z.

[0149] Furthermore, the angle α between the side wall of the organic planarization layer 6 close to the first gap 54 and the side of the first conductive layer 5 close to the organic planarization layer 6 is smaller than the angle β between the side wall of the first conductive layer 5 close to the first gap 54 and the side of the first electrode layer 4 close to the first conductive layer 5; that is, the inclination angle of the side wall of the organic planarization layer 6 is smaller than the inclination angle of the side wall of the source 51 and the drain 52 of the first conductive layer 5; specifically, the angle α between the side wall of the organic flat portion 61 close to the first gap 54 and the side of the first conductive layer 5 facing away from the base substrate 1 is less than or equal to 70°, that is, although the organic flat portion 61 has a side wall, the slope of the side wall of the organic flat portion 61 is relatively gentle. Even if the subsequently formed organic active layer 7 climbs the side wall of the organic flat portion 61, no gap will appear and the layer will not break due to the gap.

[0150] In addition, the material of the organic flat portion 61 is an organic material, and the corners of the organic flat portion 61 are relatively smooth. The corners of the organic flat portion 61 can be curved, that is, the side of the organic flat portion 61 facing away from the base substrate 1 can be connected to the sidewall through a curved surface. No sharp corner structures are formed at the corners of the source 51 and the drain 52. Therefore, the subsequently formed organic active layer 7 has good coverage of the corners of the organic flat portion 61, and no fracture defects will occur at the corner bends. Of course, in some other exemplary embodiments of the present disclosure, the side of the organic flat portion 61 facing away from the base substrate 1 can also be directly connected to the sidewall, forming an obtuse angle.

[0151] Moreover, the angle between the sidewall of the organic planarization layer 6 near the first gap 54 and the surface of the first conductive layer 54 facing away from the base substrate 11 cannot be too small. If it is too small, the area of ​​the organic planarization portion 61 will be larger, thereby making the area of ​​the subsequently formed organic active layer 7 larger, resulting in a larger area of ​​the entire thin film transistor, which affects the aperture ratio of the display panel. Specifically, the angle between the sidewall of the organic planarization layer 6 near the first gap 54 and the surface of the first conductive layer 54 facing away from the base substrate 11 is greater than or equal to 30 degrees. For example, the angle between the sidewall of the organic planarization layer 6 near the first gap 54 and the surface of the first conductive layer 54 facing away from the base substrate 11 can be 32 degrees, 36 degrees, 42.5 degrees, 46.8 degrees, 51 degrees, 54.7 degrees, 58.4 degrees, 62 degrees, 65.3 degrees, 67.5 degrees, etc.

[0152] The thickness of the organic planarization layer 6 is greater than or equal to 300 nanometers and less than or equal to 800 nanometers. For example, the thickness of the organic planarization layer 6 can be 326 nanometers, 375 nanometers, 430 nanometers, 480 nanometers, 517 nanometers, 589 nanometers, 625 nanometers, 673 nanometers, 741 nanometers, 789 nanometers, etc.

[0153] In this exemplary embodiment, as shown in FIG1 , an organic active layer 7 may be provided on the side of the organic planarization layer 6 facing away from the base substrate 1. The organic active layer 7 is connected to the source electrode 51 and the drain electrode 52 on the side of the organic planar portion 61 facing away from the first gap 54. The organic active layer 7 may be made of an organic semiconductor (OSC) material.

[0154] Due to the planarization and protection of the organic planarization layer 6, the material selection space of the first conductive layer 5 is larger, so that the flexible array substrate can be mass-produced; moreover, since the organic semiconductor (OSC) material of the organic active layer 7 is a P-type material, the first conductive layer 5 needs to form an ohmic contact with the organic active layer 7, and the first conductive layer 5 needs to select a material with a larger work function. For example, the work function of the material of the first conductive layer 5 needs to be greater than 4.5eV; therefore, considering the work function, the material of the first conductive layer 5 can be Ag+SAM, whose work function is about 5.86eV, and Ag is closer to the base substrate 1; it can be ITO (indium tin oxide), whose work function is greater than or equal to 4.57 and less than or equal to 4.93eV; it can be Mo+surface oxidation (molybdenum oxide), whose work function is approximately 5.58eV, and Mo is closer to the substrate 1; it can be Mo alloy+surface oxidation (molybdenum oxide), whose work function is approximately 5.5eV, and the Mo alloy is closer to the substrate 1; it can also be TiN, whose work function is greater than or equal to 4.49 and less than or equal to 5.29eV; it can also be Au, whose work function is approximately 5.2eV; it can also be Pt, whose work function is approximately 5.6eV; it can also be Pd, whose work function is approximately 5.12eV, and so on.

[0155] While taking the conductive performance into consideration, the first conductive layer 5 can be stacked. For example, the first conductive layer 5 can include BF (Buffer Film), LRF (Low Resistance Film), and HWF (High Work Function Film) stacked in sequence; the buffer film is closer to the base substrate 1. The buffer film can be selected from: Mo, Mo alloy, Ti, ITO, IZO (indium zinc oxide), etc.; the low resistance film can be selected from: Cu, Al, Ag, etc.; the high work function film can be Ag+SAM, whose work function is approximately 5.86eV; it can be ITO (indium tin oxide), whose work function is greater than or equal to 4.57 and less than or equal to 4.93eV; it can be Mo+surface oxidation (molybdenum oxide), whose work function is approximately 5.58eV, and Mo is closer to the substrate 1; it can be Mo alloy + surface oxidation (molybdenum oxide), whose work function is approximately 5.5eV, and Mo alloy is closer to the substrate 1; it can also be TiN, whose work function is greater than or equal to 4.49 and less than or equal to 5.29eV; it can also be Au, whose work function is approximately 5.2eV; it can also be Pt, whose work function is approximately 5.6eV; it can also be Pd, whose work function is approximately 5.12eV, etc.

[0156] SAM is a self-assembled monolayer film that can form a monomolecular layer and modify the interface between the first conductive layer 4 and the organic active layer 7 to improve the work function.

[0157] In the prior art, the material of the first conductive layer 5 is a stacked structure of MoAlMo or a stacked structure of MoNd / Cu / MoNd. Because the surface is Mo or Mo alloy material, the work function is small (≤4.5eV), which does not meet the requirements; the present disclosure performs surface oxidation treatment, and the treatment methods include annealing, plasma, etc., so that the work function is increased to greater than or equal to 4.5eV, and the temperature of the surface oxidation treatment process is relatively low, generally not exceeding 100°C.

[0158] In this example embodiment, as shown in FIG1 , a gate insulating layer group 8 may be provided on a side of the organic active layer 7 facing away from the base substrate 1 , and the orthographic projection of the gate insulating layer group 8 on the base substrate 1 coincides with the orthographic projection of the organic active layer 7 on the base substrate 1 , that is, the orthographic projection of the gate insulating layer group 8 on the base substrate 1 coincides with the orthographic projection of the organic active layer 7 on the base substrate 1 , so that the gate insulating layer group 8 and the organic active layer 7 can be formed by the same patterning process, thereby reducing process steps and lowering costs.

[0159] As shown in Figure 1, the gate insulation layer group 8 may include a first gate insulation layer 81 and a second gate insulation layer 82. The first gate insulation layer 81 is arranged on the side of the organic active layer 7 away from the base substrate 1. The first gate insulation layer 81 needs to be a flexible film layer with insulating properties; and it is orthogonal to the solvent for etching the organic active layer 7 and has good matching performance, that is, the material of the first gate insulation layer 81 will not react with the material of the organic active layer 7, thereby ensuring the channel characteristics of the organic active layer 7; for example, the material of the first gate insulation layer 81 can be a material with a low dielectric constant.

[0160] It should be noted that an orthogonal solvent refers to a solvent with a large difference in polarity. An orthogonal solvent system is a solvent system used to apply a subsequent layer, in which the previously applied layer is insoluble.

[0161] The second gate insulating layer 82 is provided on the side of the first gate insulating layer 81 facing away from the base substrate 1. The second gate insulating layer 82 has a stronger barrier performance against the etching liquid of the gate layer 9 than the first gate insulating layer 81. The second gate insulating layer 82 needs to be a flexible film layer with insulating properties, good environmental stability, and can block water and oxygen. It can be a cross-linked material. Cross-linked materials are materials that undergo a cross-linking reaction. A cross-linking reaction refers to a reaction in which two or more molecules (generally linear molecules) are bonded and cross-linked to form a relatively stable molecule (bulk molecule) network structure. This reaction transforms linear or lightly branched macromolecules into a three-dimensional network structure, thereby improving properties such as strength, heat resistance, wear resistance, and solvent resistance. For example, the material of the second gate insulating layer 82 can be a cross-linkable dielectric material to improve electrical durability.

[0162] As shown in Figures 1, 5, and 6, a gate layer 9 can be provided on the side of the gate insulation layer group 8 facing away from the base substrate 1. The gate layer 9 can include a gate electrode 91. The orthographic projection of the gate layer 9 on the base substrate 1 coincides with the orthographic projection of the organic active layer 7 on the base substrate 1. In other words, the orthographic projection of the gate layer 9 on the base substrate 1 completely overlaps with the orthographic projection of the organic active layer 7 on the base substrate 1. This allows the gate layer 9 and the organic active layer 7 to be formed through the same patterning process, reducing process steps and costs. The orthographic projection of the gate layer 9 on the base substrate 1 can be located within the orthographic projection of the light shielding layer 3 on the base substrate 1.

[0163] Since the gate layer 9, the gate insulating layer group 8, and the organic active layer 7 are formed through the same patterning process, when only the first gate insulating layer 81 is provided, the first gate insulating layer 81 and the organic active layer 7 have poor barrier properties. Therefore, when etching the gate material layer 90, the etchant easily penetrates the first gate insulating layer 81 and the organic active layer 7 and corrodes the first conductive layer 5. When the gate insulating layer group 8 includes the first gate insulating layer 81 and the second gate insulating layer 82, the second gate insulating layer 82 has a stronger barrier property against the etchant of the gate layer 9 than the first gate insulating layer 81. During the etching process of the gate material layer 90, the second gate insulating material layer 820 can protect the first conductive layer 5, preventing the etchant of the gate layer 9 from corroding the first conductive layer 5, thereby ensuring the electrical properties of the first conductive layer 5 and thus ensuring the performance of the array substrate.

[0164] Therefore, in the process of etching to form the gate layer 9, the gate layer 9 can protect the gate insulating layer group 8 and the organic active layer 7 thereunder, preventing the etching solution of the gate layer 9 from corroding the first conductive layer 5. Therefore, the material selection space of the gate layer 9 is relatively large, so that the flexible array substrate can be mass-produced; for example, the material of the gate layer 9 can be Ag, Mo, Cu, Al, Ti, ITO, a stacked structure of ITO / Ag / ITO, a stacked structure of Mo / Al / Mo, a stacked structure of Mo / Cu / Mo, a stacked structure of Ti / Al / Ti, and the like.

[0165] In this example embodiment, as shown in Figure 1, a passivation layer 10 can be provided on the side of the gate layer 9 facing away from the base substrate 1. The passivation layer 10 needs to be a flexible film layer with insulating properties, good environmental stability, and the ability to block water and oxygen. Specifically, it can be a cross-linked material; the material of the passivation layer 10 can be the same as the material of the second gate insulating layer 82.

[0166] As shown in FIG. 9 , a first via hole 101 is provided on the passivation layer 10 , and the first via hole 101 is connected to the gate 91 .

[0167] 1 , 7 , 8 , and 9 , a second electrode layer 11 may be provided on a side of the passivation layer 10 facing away from the substrate 1 . The second electrode layer 11 may be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), or the like. The second electrode layer 11 includes spaced second electrodes 111 and gate line connectors 112 . The second electrodes 111 may be a common electrode, and therefore, multiple second electrodes 111 need to be connected together. The gate line connectors 112 need to be connected to the gate 91 , and therefore, the second electrodes 111 and the gate line connectors 112 need to be spaced apart. Specifically, the second electrodes 111 may be configured as strips extending along a first direction X, and the gate connectors 112 may be configured as strips extending along the first direction X. The second electrodes 111 and the gate connectors 112 may be alternately arranged in a second direction, i.e., a gate connector 112 is provided between two adjacent second electrodes 111, and a second electrode 111 is provided between two adjacent gate connectors 112. The plurality of second electrodes 111 may be connected in the peripheral region. Of course, the plurality of second electrodes 111 may also be bridged by other conductive film layers.

[0168] The gate connection portion 112 serves as a gate line alone. The gate connection portion 112 can extend along the first direction X. The gate connection portion 112 is connected to two adjacent gates 91 through the first via hole 101 on the passivation layer 10. Multiple gates 91 arranged along the first direction X are connected together through multiple gate connection portions 112. The gate connection portion 112 serves as a gate line to provide a scanning signal to each gate 91.

[0169] As shown in Figures 12 and 13, in some exemplary embodiments of the present disclosure, the gate layer 9 may include not only a gate 91 but also a gate extension 92. The gate extension 92 is connected to opposite sides of the gate 91 in the first direction X. However, because the gate extension 92, the gate 91, the gate insulation layer group 8, and the organic active layer 7 are formed through the same patterning process, to avoid interconnection between the organic active layers 7 of different thin-film transistors, the gate extension 92 is spaced apart from another adjacent gate 91. The gate extension 92 extends along the first direction X, which is parallel to the surface of the base substrate 1 adjacent to the first conductive layer 5. Of course, the gate extension 92 may be connected to one side of the gate 91 in the first direction X.

[0170] A portion of the orthographic projection of the gate extension portion 92 on the base substrate 1 may be located within the orthographic projection of the light-shielding layer 3 on the base substrate 1, and another portion of the orthographic projection of the gate extension portion 92 on the base substrate 1 may be located outside the orthographic projection of the light-shielding layer 3 on the base substrate 1, that is, the gate extension portion 92 protrudes beyond the light-shielding layer 3 in the first direction.

[0171] Since the gate layer 9 is made of metal with low resistance, such a configuration can reduce the resistance of the gate line and the power consumption of the array substrate.

[0172] In this case, a passivation layer 10 can be provided on the side of the gate layer 9 facing away from the base substrate 1. The passivation layer 10 needs to be a flexible film layer with insulation properties, good environmental stability, and the ability to block water and oxygen. Specifically, it can be a cross-linked material; the material of the passivation layer 10 can be the same as the material of the second gate insulation layer 82.

[0173] As shown in FIG. 9 , a first via hole 101 is provided on the passivation layer 10 , and the first via hole 101 is connected to the gate extension portion 92 .

[0174] 1 , 14 , 15 , and 9 , a second electrode layer 11 may be provided on a side of the passivation layer 10 facing away from the base substrate 1 . The second electrode layer 11 may be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), or the like. The second electrode layer 11 includes spaced second electrodes 111 and a gate connector 112 . The second electrodes 111 may be a common electrode, and therefore, multiple second electrodes 111 need to be connected together. The gate connector 112 needs to be connected to the gate extension 92 , and therefore, the second electrodes 111 and the gate connector 112 need to be spaced apart. Specifically, the second electrode layer 11 may be formed by providing multiple openings in the second electrode layer 11 , with the gate connector 112 disposed within the openings.

[0175] The gate connection portion 112 and the gate extension portion 92 together serve as a gate line. The gate connection portion 112 can extend along the first direction X. The gate connection portion 112 is connected to two adjacent gate extension portions 92 through the first via hole 101 on the passivation layer 10, that is, the gate connection portion 112 and the gate extension portion 92 are connected to form a gate line to connect multiple gates 91 arranged along the first direction X and provide a scanning signal to each gate 91.

[0176] Furthermore, as shown in FIG16 , the array substrate may further include a conductive reinforcement layer 15 . The conductive reinforcement layer 15 is disposed on the side of the second electrode layer 11 facing away from the base substrate 1 . The orthographic projection of the conductive reinforcement layer 15 on the base substrate 1 coincides with the orthographic projection of the gate connection portion 112 on the base substrate 1 , i.e., the conductive reinforcement layer 15 is not disposed on the side of the second electrode 111 facing away from the base substrate 1 , thereby ensuring the light-transmitting area of ​​the array substrate, i.e., ensuring the aperture ratio of the array substrate. The conductive reinforcement layer 15 is made of metal with low electrical resistance. The conductive reinforcement layer 15 can reduce the resistance of the gate connection portion 112, thereby reducing the resistance of the gate lines of the array substrate, reducing power consumption, and ensuring electric field uniformity of the second electrode 111 of the array substrate. Of course, in other exemplary embodiments of the present disclosure, as shown in FIG17 , the conductive reinforcement layer 15 can also be disposed on the side of the second electrode 111 facing away from the base substrate 1 . However, the conductive reinforcement layer 15 is only disposed in the area of ​​the second electrode 111 that is not the display area. For example, the conductive reinforcement layer 15 can be disposed in the portion where the second electrode 111 overlaps with the data line 53 .

[0177] Furthermore, as shown in FIG. 18 , the array substrate may further include a protective layer 14 . The protective layer 14 at least covers the sidewalls of the organic active layer 7 . The protective layer 14 may protect the organic active layer 7 .

[0178] In this exemplary embodiment, the protective layer 14 is disposed between the gate layer 9 and the organic planarization layer 6 and the passivation layer 10, and covers the organic active layer 7, the gate insulating layer group 8, and the sidewalls of the gate 91. That is, the protective layer 14 is formed after the gate layer 9 is formed.

[0179] The thickness of the protective layer 14 is greater than or equal to 1000 angstroms and less than or equal to 3000 angstroms. For example, the thickness of the protective layer 14 can be 1030 angstroms, 1085 angstroms, 1162 angstroms, 1238 angstroms, 1348 angstroms, 1586 angstroms, 1651 angstroms, 1752 angstroms, 1830 angstroms, 1985 angstroms, 2162 angstroms, 2338 angstroms, 2481 angstroms, 2568 angstroms, 2615 angstroms, 2725 angstroms, 2856 angstroms, 2965 angstroms, etc.

[0180] The material of the protective layer 14 can be the same as that of the first insulating layer 81 or the first planarization layer 21. The specific requirements of the material of the first insulating layer 81 and the material of the first planarization layer 21 have been described in detail above and will not be repeated here.

[0181] The matching of the protective layer 14 and the organic active layer 7 is stronger than the matching of the passivation layer 10 and the organic active layer 7. The protective layer 14 can prevent the organic active layer 7 from contacting the passivation layer 10. Due to the poor material matching between the organic active layer 7 and the passivation layer 10, for example, the organic active layer 7 and the passivation layer 10 will react, and additional by-products will be produced during the film formation process, or the organic active layer 7 and the passivation layer 10 will dissolve each other, resulting in damage to the organic active layer 7 and the passivation layer 10. However, the material matching between the protective layer 14 and the organic active layer 7 is better, that is, the material of the protective layer 14 is orthogonal to the material solvent of the organic active layer 7, that is, the material of the protective layer 14 and the material of the organic active layer 7 do not react with each other, so that the protective layer 14 and the organic active layer 7 can maintain integrity, and the stability of the thin film transistor is improved, ensuring the performance of the array substrate.

[0182] In this case, as shown in Figure 19, the gate connection portion 112 can be connected to the gate 91 through the first via 101 on the passivation layer 10 and the fourth via 141 on the protective layer 14, and the first via 101 on the passivation layer 10 and the fourth via 141 on the protective layer 14 can be formed by the same patterning process.

[0183] 20 , in some other example embodiments of the present disclosure, the light-shielding layer 3 may be configured as a strip extending along the first direction X, and one light-shielding layer 3 may correspond to a plurality of thin-film transistors arranged along the first direction X, that is, the orthographic projections of the plurality of organic active layers 7 arranged along the first direction X on the base substrate 1 are located within the orthographic projections of the light-shielding layer 3 on the base substrate 1.

[0184] In this case, a passivation layer 10 can be provided on the side of the gate layer 9 facing away from the base substrate 1. The passivation layer 10 needs to be a flexible film layer with insulation properties, good environmental stability, and the ability to block water and oxygen. Specifically, it can be a cross-linked material; the material of the passivation layer 10 can be the same as the material of the second gate insulation layer 82.

[0185] A first via hole 101 and a second via hole 102 are provided on the passivation layer 10. The first via hole 101 is connected to the gate 91. A third via hole 221 is provided on the second planarization layer 22. The second via hole 102 is connected to the third via hole 221 and is connected to the light shielding layer 3.

[0186] A second electrode layer 11 may be provided on the side of the passivation layer 10 facing away from the base substrate 1. The material of the second electrode layer 11 may be a transparent conductive material, for example, ITO (indium tin oxide), IZO (indium zinc oxide), etc. The second electrode layer 11 may include a second electrode 111 and a gate connection portion 112 that are spaced apart. The second electrode 111 may be a common electrode. The gate connection portion 112 is spaced apart from the second electrode 111. The gate connection portion 112 is connected to the gate 91 through the first via 101 and is connected to the light shielding layer 3 through the second via 102 and the third via 221. The light shielding layer 3 is multiplexed as a gate line and a second gate 91. The thin film transistor includes two gates 91, and the two gates 91 are respectively located on the upper and lower sides of the organic active layer 7 to ensure the performance of the thin film transistor.

[0187] Based on the same inventive concept, an exemplary embodiment of the present disclosure provides a method for preparing an array substrate. As shown in FIG. 21 , the method for preparing the array substrate may include the following steps:

[0188] Step S10: providing a base substrate.

[0189] In step S20, a first electrode layer and a first conductive layer are formed on one side of the base substrate, wherein the first electrode layer includes a first electrode, the first conductive layer includes a source and a drain, a first gap is provided between the source and the drain, and the orthographic projection of the drain on the base substrate overlaps with the orthographic projection of the first electrode layer on the base substrate.

[0190] Step S30 : forming an organic planarization layer, wherein the organic planarization layer includes a plurality of organic planar portions arranged at intervals, and the organic planar portions are at least arranged in the first gap.

[0191] In step S40 , an organic active layer is formed on a side of the organic planarization layer away from the base substrate, wherein the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planar portion away from the first gap.

[0192] Among them, the organic flat portion 61 at least does not cover the end portions of the source 51 and the drain 52 facing away from the first gap 54, and the angle between the side wall of the organic flat portion 61 close to the first gap 54 and the side of the first conductive layer 5 close to the organic planarization layer 6 is smaller than the angle between the side wall of the first conductive layer 5 close to the first gap 54 and the side of the first electrode layer 4 close to the first conductive layer 5.

[0193] The array substrate of the present disclosure can be formed by six patterning processes. The following describes in detail each step of the method for preparing the array substrate 100.

[0194] A base substrate 1 is provided, specifically, as shown in FIG22 , a glass substrate 13 is provided, and the base substrate 1 is bonded to the glass substrate 13 via an adhesive layer 12 (not shown in FIG22 to FIG40 ). A first planarization layer 21 is formed on the side of the base substrate 1 facing away from the glass substrate 13 .

[0195] As shown in Figures 23, 2, and 24, a light-shielding material layer is formed on the side of the first planarization layer 21 facing away from the base substrate 1, and the light-shielding material layer is patterned to form a light-shielding layer 3. This completes the first patterning process. The specific structure of the light-shielding layer 3 has been described in detail above and will not be repeated here.

[0196] 25 and 26 , a second planarization layer 22 , a first electrode material layer 40 and a first conductive material layer 50 are sequentially formed on the side of the light shielding layer 3 facing away from the base substrate 1 .

[0197] Then, a half-mask process is performed on the mask layer to form a mask pattern 16. Specifically, a mask layer is formed on the side of the first conductive material layer 50 facing away from the base substrate 1. A mask plate is placed on the side of the mask layer facing away from the base substrate 1. The mask plate may include a light-transmitting portion, a light-shielding portion 31, and a semi-transmitting portion. The semi-transmitting portion is arranged opposite to the second portion 162, that is, the orthographic projection of the semi-transmitting portion on the base substrate 1 coincides with the orthographic projection of the second portion 162 on the base substrate 1. The light-shielding portion 31 is arranged opposite to the first portion 161, that is, the orthographic projection of the light-shielding portion 31 on the base substrate 1 coincides with the orthographic projection of the first portion 161 on the base substrate 1. The light-transmitting portion is arranged opposite to other portions of the mask layer.

[0198] Then, referring to Figure 27, the mask layer is exposed and developed to form a mask pattern 16, which includes a first part 161 and a second part 162, that is, the mask layer arranged opposite to the light-transmitting part is removed; the mask layer arranged opposite to the semi-transmitting part is removed by a certain thickness to form the second part 162; the mask layer arranged opposite to the light-shielding part 31 is completely retained to form the first part 161, so that the thickness of the first part 161 is greater than the thickness of the second part 162, the first part 161 is arranged opposite to the first conductive layer 5 and a part of the first electrode layer 4, and the second part 162 is arranged opposite to another part of the first electrode layer 4.

[0199] As shown in Figure 28, the exposed first conductive material layer 50 is etched and removed for the first time, and the first electrode material layer 40 is etched and removed to form a first electrode layer 4, forming a first gap 54 between the source 51 and the drain 52 and a second gap 43 between the first electrode 41 and the resistance reduction connection part 42; the first electrode layer 4 covered by the mask pattern 16 and the remaining first conductive material layer 50 are retained.

[0200] As shown in FIG. 29 , mask pattern 16 is ashed to remove second portion 162, exposing first conductive material layer 50 covered by second portion 162. Gases used in the ashing process may include SF6 and O2. The ashing process removes second portion 162, exposing first conductive material layer 50 covered by second portion 162, and also reduces the thickness of first portion 161.

[0201] 30 and 31 , the remaining first conductive material layer 50 is patterned to form the first conductive layer 5. Specifically, the first conductive material layer 50 covered by the second portion 162 is etched away, while the first conductive material layer 50 covered by the first portion 161 remains to form the first conductive layer 5. Finally, the remaining first portion 161 is removed. This completes the second patterning process.

[0202] 32 and 33 , an organic planarization layer 6 is formed on the side of the first conductive layer 5 facing away from the base substrate 1 , and the organic planarization layer 6 is patterned to form a plurality of spaced organic planar portions 61 . This completes the third patterning process.

[0203] As shown in Figure 34 , an organic active material layer 70, a first gate insulating material layer 810, a second gate insulating material layer 820, and a gate material layer are sequentially formed on the side of the organic planar portion 61 facing away from the base substrate 1. A mask layer is then formed on the side of the gate material layer facing away from the base substrate 1 and exposed and developed to form a second mask pattern 17. As shown in Figure 35 , the gate material layer is etched using the second mask pattern 17 as a mask to form a gate layer 9. As shown in Figures 36 and 37 , the second mask pattern 17 is removed, and the first gate insulating material layer 810, the second gate insulating material layer 820, and the organic active material layer 70 are etched using the gate layer 9 as a mask to form a gate insulating layer group 8 (first gate insulating layer 81, second gate insulating layer 82) and an organic active layer 7. Alternatively, the mask pattern 16 can be removed after the gate insulating layer group 8 and the organic active layer 7 are formed. This completes the fourth patterning process.

[0204] As shown in FIG38 , a passivation layer 10 is formed on the side of the gate layer 9 facing away from the substrate 1 . As shown in FIG39 , the passivation layer 10 is patterned to form a first via 101 and a second via 102 , and a third via 221 is formed on the second planarization layer 22 . This completes the fifth patterning process. Furthermore, in some other exemplary embodiments of the present disclosure, as shown in FIG9 , the passivation layer 10 may be patterned to form only the first via 101 .

[0205] In other exemplary embodiments of the present disclosure, as shown in FIG. 17 , when the array substrate includes a protective layer 14, the protective layer 14 and the passivation layer 10 are sequentially formed on the side of the gate layer 9 facing away from the base substrate 1. The passivation layer 10 is patterned to form the first via hole 101, and the protective layer 14 is simultaneously patterned to form the fourth via hole 141, which is connected to the first via hole 101. Alternatively, the passivation layer 10 is patterned to form the first via hole 101 and the second via hole 102, and the third via hole 221 is formed on the second planarization layer 22. The protective layer 14 is simultaneously patterned to form the fourth via hole 141 and the fifth via hole, which is connected to the first via hole 101 and the fifth via hole, which is connected to the second via hole 102 and the third via hole 221. This completes the fifth patterning process.

[0206] 20 and 40 , a second electrode material layer is formed on the side of the passivation layer 10 facing away from the base substrate 1 , and the second electrode material layer is patterned to form a second electrode layer 11 and a gate connecting portion 112 . The sixth patterning process is now completed.

[0207] In other exemplary embodiments of the present disclosure, as shown in FIG16 and FIG17 , when the array substrate includes a conductive reinforcement layer 15, a second electrode material layer and a conductive reinforcement material layer are sequentially formed on the side of the passivation layer 10 facing away from the base substrate 1. The conductive reinforcement material layer is patterned to form the conductive reinforcement layer 15. Simultaneously, the second electrode material layer is patterned to form the second electrode layer 11 and the gate connection portion 112. Because the conductive reinforcement layer 15 and the second electrode layer 11 are formed over different areas, the formation process for the second electrode layer 11 and the conductive reinforcement layer 15 is the same as that for the gate layer 9 and the organic active layer 7, i.e., a half-mask process is first performed on the mask layer, followed by an ashing process. The specific steps are not further described herein. This completes the sixth patterning process.

[0208] It should be noted that although the steps of the array substrate manufacturing method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or a single step may be broken down into multiple steps.

[0209] Based on the same inventive concept, an example embodiment of the present disclosure provides a display panel, which is a liquid crystal display panel. The display panel may include an array substrate, a color filter substrate and a liquid crystal layer; the array substrate may be any one of the array substrates described above, and the specific structure of the array substrate has been described in detail above, so it will not be repeated here; the color filter substrate and the array substrate are arranged opposite to each other; the liquid crystal layer is arranged between the array substrate and the color filter substrate.

[0210] The color filter substrate may be a flexible color filter substrate, which may include a flexible substrate, a light shielding portion 31 and a filter portion provided on one side of the flexible substrate, and the filter portion may include a red filter portion, a green filter portion, a blue filter portion, and the like.

[0211] Based on the same inventive concept, an exemplary embodiment of the present disclosure provides a display device, which may be a sliding display device, a foldable display device, or a curved display device. The display device may include a display panel described in any one of the above. The specific structure of the display panel has been described in detail above, so it will not be repeated here.

[0212] The specific type of the display device is not particularly limited, and any type of display device commonly used in the field can be used, such as mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the display device, which will not be repeated here.

[0213] It should be noted that, in addition to the display panel, the display device also includes other necessary components and components, such as a housing, a circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0214] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. An array substrate, wherein: include: substrate; A first electrode layer is provided on one side of the base substrate, and the first electrode layer includes a first electrode; a first conductive layer, disposed on a side of the first electrode layer facing away from the base substrate, the first conductive layer comprising a source electrode and a drain electrode, a first gap being provided between the source electrode and the drain electrode, and an orthographic projection of the drain electrode on the base substrate overlapping with an orthographic projection of the first electrode layer on the base substrate; an organic planarization layer comprising a plurality of spaced-apart organic planar portions, the organic planar portions being disposed at least within the first gap and at least not covering ends of the source and drain electrodes facing away from the first gap, wherein an angle between a sidewall of the organic planar portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a sidewall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer; An organic active layer is provided on a side of the organic planarization layer away from the base substrate, and the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planar portion away from the first gap.

2. The array substrate according to claim 1, wherein: The distance between a surface of the organic flat portion facing away from the base substrate and the base substrate is greater than or equal to the distance between a surface of the first conductive layer facing away from the base substrate and the base substrate.

3. The array substrate according to claim 2, wherein: A portion of the organic flat portion is arranged on a side of the first conductive layer facing away from the base substrate. At a position close to the first gap, the orthographic projection of the organic flat portion on the base substrate overlaps with the orthographic projection of the source electrode on the base substrate, and the orthographic projection of the organic flat portion on the base substrate overlaps with the orthographic projection of the drain electrode on the base substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: An angle between a sidewall of the organic planar portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is less than or equal to 70°.

5. The array substrate according to claim 1, wherein: The distance between the first conductive layer and a surface of the organic flat portion facing away from the base substrate is smaller than the thickness of the first conductive layer in a third direction, and the third direction is perpendicular to a surface of the base substrate close to the first electrode layer.

6. The array substrate according to claim 1, wherein: A surface of the organic flat portion facing away from the base substrate is connected to a side wall of the organic flat portion via a curved surface.

7. The array substrate according to claim 1, wherein: The first conductive layer further includes a data line connected to the source electrode, and the first electrode layer further includes: The resistance-reducing connection portion is spaced apart from the first electrode, and the orthographic projections of the source electrode and the data line on the base substrate are located within the orthographic projection of the resistance-reducing connection portion on the base substrate.

8. The array substrate according to claim 1, wherein: The array substrate further includes: a gate insulating layer group, provided on a side of the organic active layer facing away from the base substrate, wherein an orthographic projection of the gate insulating layer group on the base substrate coincides with an orthographic projection of the organic active layer on the base substrate; The gate layer is provided on a side of the gate insulating layer group away from the base substrate. The gate layer includes a gate. The orthographic projection of the gate on the base substrate coincides with the orthographic projection of the organic active layer on the base substrate.

9. The array substrate according to claim 8, wherein: The gate insulation layer group includes: a first gate insulating layer, provided on a side of the organic active layer facing away from the base substrate; The second gate insulating layer is provided on a side of the first gate insulating layer away from the base substrate, and the second gate insulating layer has a stronger barrier performance to the etching liquid of the gate layer than the first gate insulating layer.

10. The array substrate according to claim 8, wherein: The array substrate further includes: a passivation layer, disposed on a side of the gate layer facing away from the substrate; The second electrode layer is provided on a side of the passivation layer away from the base substrate. The second electrode layer includes second electrodes and gate connecting portions that are spaced apart. The gate connecting portions are connected to two adjacent gates.

11. The array substrate according to claim 8, wherein: The gate layer further includes: A gate extension portion is connected to at least one side of the gate in a first direction, where the first direction is parallel to a surface of the array substrate close to the first electrode layer.

12. The array substrate according to claim 11, wherein: The array substrate further includes: a passivation layer, disposed on a side of the gate layer facing away from the substrate; The second electrode layer is provided on a side of the passivation layer away from the base substrate. The second electrode layer includes a second electrode and a gate connecting portion that are spaced apart. The gate connecting portion is connected to two adjacent gate extension portions.

13. The array substrate according to claim 10 or 12, wherein: The array substrate further includes: The conductive enhancement layer is provided on a side of the second electrode layer away from the base substrate, and the orthographic projection of the conductive enhancement layer on the base substrate is located within the orthographic projection of the gate connecting portion on the base substrate.

14. The array substrate according to claim 8, wherein: The array substrate further includes: a light shielding layer provided on one side of the base substrate, wherein the orthographic projection of the organic active layer on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate; a second planarization layer, disposed on a side of the light shielding layer away from the base substrate; the first electrode layer is disposed on a side of the second planarization layer away from the base substrate; and a third via hole is disposed on the second planarization layer; a passivation layer, disposed on a side of the gate layer facing away from the base substrate, the passivation layer being provided with a first via hole and a second via hole, the first via hole being connected to the gate, the second via hole being connected to the third via hole and connected to the light shielding layer; The second electrode layer is arranged on the side of the passivation layer away from the base substrate. The second electrode layer includes a second electrode and a gate connecting portion arranged at intervals. The gate connecting portion is connected to the gate through the first via hole, and is connected to the light-shielding layer through the second via hole and the third via hole. The light-shielding layer is multiplexed as a gate line and a second gate.

15. The array substrate according to claim 10 or 12, wherein: The array substrate further includes: The protective layer at least covers the sidewalls of the organic active layer.

16. The array substrate according to claim 15, wherein: The protective layer is arranged between the gate layer and the first electrode and the passivation layer, and covers the organic active layer, the gate insulation layer group and the side wall of the gate. The matching between the protective layer and the organic active layer is stronger than the matching between the passivation layer and the organic active layer.

17. The array substrate according to claim 1, wherein: The work function of the first conductive layer is greater than 4.5 eV.

18. The array substrate according to claim 1, wherein: The array substrate is a flexible array substrate.

19. A method for preparing an array substrate, wherein: include: providing a substrate; A first electrode layer and a first conductive layer are sequentially stacked on one side of the base substrate, wherein the first electrode layer includes a first electrode, and the first conductive layer includes a source electrode and a drain electrode, a first gap is provided between the source electrode and the drain electrode, and an orthographic projection of the drain electrode on the base substrate overlaps with an orthographic projection of the first electrode layer on the base substrate; forming an organic planarization layer, the organic planarization layer comprising a plurality of organic planar portions spaced apart from each other, the organic planar portions being at least disposed within the first gap; forming an organic active layer on a side of the organic planarization layer away from the base substrate, wherein the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planar portion away from the first gap; The organic flat portion at least does not cover the end portions of the source and the drain facing away from the first gap, and the angle between the side wall of the organic flat portion close to the first gap and the side of the first conductive layer close to the organic planarization layer is smaller than the angle between the side wall of the first conductive layer close to the first gap and the side of the first electrode layer close to the first conductive layer.

20. The method for preparing an array substrate according to claim 19, wherein: An organic active layer is formed on a side of the organic planarization layer facing away from the base substrate, and at the same time, a gate insulating layer group and a gate layer are formed.

21. The method for preparing an array substrate according to claim 20, wherein: The method comprises forming an organic active layer on a side of the organic planarization layer facing away from the base substrate and forming a gate insulating layer group and a gate layer at the same time, comprising: forming an organic active material layer, a gate insulating material layer group, and a gate material layer in sequence on a side of the organic planarization layer facing away from the base substrate; performing patterning on the gate material layer to form the gate layer; The gate insulating material layer group and the organic active material layer are patterned using the gate layer as a mask to form the gate insulating layer group and the organic active layer.

22. The method for preparing an array substrate according to claim 19, wherein: A first electrode layer and a first conductive layer are sequentially stacked on one side of the base substrate, comprising: A first electrode material layer and a first conductive material layer are sequentially formed on one side of the base substrate. forming a mask layer on a side of the first conductive material layer facing away from the base substrate, and performing a half-mask process on the mask layer to form a mask pattern, wherein the mask pattern includes a first portion and a second portion, the first portion is thicker than the second portion, the first portion is disposed opposite to the first conductive layer and a portion of the first electrode layer, and the second portion is disposed opposite to another portion of the first electrode layer; Etching and removing the exposed first conductive material layer, and etching and removing the first electrode material layer to form the first electrode layer; performing an ashing process on the mask pattern to remove the second portion, so as to expose the first conductive material layer covered by the second portion; The remaining first conductive material layer is patterned to form the first conductive layer.

23. The method for preparing an array substrate according to claim 20, wherein: The preparation method further comprises: A passivation layer is formed on a side of the gate layer facing away from the substrate, and the passivation layer is patterned to form a first via hole.

24. The method for preparing an array substrate according to claim 20, wherein: The preparation method further comprises: A protection layer and a passivation layer are sequentially formed on a side of the gate layer facing away from the base substrate, and the passivation layer is patterned to form a first via hole, and the protection layer is patterned to form a fourth via hole.

25. The method for preparing an array substrate according to claim 20, wherein: The preparation method further comprises: A protective layer and a passivation layer are sequentially formed on a side of the gate layer facing away from the base substrate, and the passivation layer is patterned to form a first via and a second via, and the protective layer is simultaneously patterned to form a fourth via and a fifth via, and the second planarization layer is simultaneously patterned to form a third via, the fourth via is connected to the first via, and the fifth via is connected to the second via and the third via.

26. The method for preparing an array substrate according to claim 23 or 24, wherein: The preparation method further comprises: A second electrode material layer is formed on a side of the passivation layer facing away from the substrate, and the second electrode material layer is patterned to form a second electrode layer.

27. The method for preparing an array substrate according to claim 23 or 24, wherein: The preparation method further comprises: A second electrode material layer and a conductive enhancement material layer are sequentially formed on a side of the passivation layer facing away from the substrate, and the conductive enhancement material layer and the second electrode material layer are patterned to form a conductive enhancement layer and a second electrode layer.

28. A display panel, wherein: include: An array substrate, comprising the array substrate according to any one of claims 1 to 18; a color filter substrate, arranged opposite to the array substrate; The liquid crystal layer is arranged between the array substrate and the color filter substrate.

29. The display panel according to claim 28, wherein: The array substrate is a flexible array substrate, and the color filter substrate is a flexible color filter substrate.

30. A display device, wherein: include: The display panel according to claim 28 or 29, wherein the display device is a roll-up display device, a foldable display device or a curved display device.

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