Quantum chips and related quantum computing devices

Abstract

The present invention discloses a quantum chip and related quantum computing equipment. The quantum chip comprises: a plurality of structural elements; among the plurality of structural elements, at least two structural elements with intersection regions are included; in the intersection region, a shielding structure is provided; the shielding structure is located between the two structural elements with intersection regions in the vertical direction. The present invention can well shield the two structural elements, avoid the coupling and signal crosstalk problems between the two structural elements with intersection regions, ensure the service life of the quantum bit, and improve the reliability of the quantum chip.

Description

Quantum chips and related quantum computing devices Technical Field

[0001] The present invention relates to the field of quantum information technology, and in particular to a quantum chip and related quantum computing equipment. Background Art

[0002] Superconducting quantum chips, due to their low noise, high speed, and low power consumption, are considered a powerful tool for quantum computing. Although research is still in its early stages, as scientists continue to optimize qubit design, improve error correction technology, and enhance control strategies, several leading institutions and companies have successfully created multi-qubit superconducting quantum systems in their laboratories.

[0003] Multi-bit superconducting quantum systems can solve complex problems that are difficult for classical computers, such as large-scale optimization problems and quantum simulations. Furthermore, these chips can also be used to implement quantum information technologies such as quantum communication and high-precision sensing, opening up new possibilities for scientific research and industrial applications.

[0004] The core component of a superconducting quantum chip is the superconducting qubit. More qubits mean greater computing power. Each qubit requires one or more signal lines for control or readout. As the number of qubits continues to increase, finding the best way to utilize the limited space for wiring becomes a challenge in scaling multi-qubit technology.

[0005] Summary of the Invention

[0006] In view of the above problems, the present invention is proposed to provide a quantum chip and related quantum computing devices that overcome the above problems or at least partially solve the above problems.

[0007] In a first aspect, an embodiment of the present invention provides a quantum chip, comprising: a plurality of structural elements;

[0008] The plurality of structural elements include at least two structural elements having an intersection area;

[0009] A shielding structure is provided in the intersection region; the shielding structure is located between the two structural elements having the intersection region in a vertical direction.

[0010] In one embodiment, the two structural elements having the intersection region include:

[0011] Two signal lines crossing each other; or

[0012] Two components crossing each other; or

[0013] Signal lines and components that have intersections with the signal lines.

[0014] In one embodiment, among the two structural elements having the intersection region, at least one structural element has structural subcomponents respectively provided on both sides of the intersection region; and the structural subcomponents are connected by connecting portions.

[0015] In one embodiment, the connection portion is implemented using a bridge structure.

[0016] In one embodiment, the connecting portion is an air bridge or a dielectric bridge.

[0017] In one embodiment, the two structural elements having the intersection region are respectively a first structural element and a second structural element; the first structural element is provided with two structural subcomponents on both sides of the intersection region, and the two structural subcomponents are connected by the connecting portion; the second structural element is an integral structure;

[0018] In a vertical direction, the shielding layer is located between the connecting portion of the first structural element and the second structural element.

[0019] In one embodiment, in the horizontal direction, the shielding structure is arranged on the inner side of the two structural subcomponents of the first structure and spans the second structural element; in the vertical direction, the shielding structure is located above the second structural element and below the connecting portion of the first structural element.

[0020] In one embodiment, in the horizontal direction, the shielding structure is arranged on the inner side of the two structural subcomponents of the first structural element and spans the connecting portion of the first structural element; in the vertical direction, the shielding structure is located below the second structural element and above the connecting portion of the first structural element.

[0021] In one embodiment, the width of the shielding structure is greater than or equal to the width of the second structural element it spans, or / and the width of the shielding structure is greater than or equal to the width of the connecting portion.

[0022] In one embodiment, the two structural elements having the intersection region are respectively a first structural element and a second structural element; the first structural element and the second structural element are respectively provided with two structural subcomponents on both sides of the intersection region, and the two structural subcomponents belonging to the same structural element are connected by respective connecting portions;

[0023] The shielding structure is located on the inner sides of the two structural subcomponents of the first structural element located on both sides of the intersection area; or the shielding structure is located on the inner sides of the two structural subcomponents of the second structural element located on both sides of the intersection area;

[0024] In the vertical direction, the shielding structure is located between the connecting portion of the first structural element and the connecting portion of the second structural element.

[0025] In one embodiment, the shielding structure is grounded or floating.

[0026] In one embodiment, the quantum chip further comprises: a chip substrate;

[0027] The ground is disposed on the substrate, and the plurality of structural elements are disposed on the chip substrate;

[0028] The shielding structure is disposed on the ground and is conductively connected to the ground.

[0029] In one embodiment, the ground is located on the same layer as the two structural subcomponents, and is located inside the two structural subcomponents.

[0030] In one embodiment, the ground is made of a superconducting metal film.

[0031] In one embodiment, the plurality of structural elements in the same layer include more than three structural elements with intersection areas; and the shielding structure is provided between every two structural elements with intersection areas.

[0032] In one embodiment, among the three or more structural elements having intersection regions, the intersection regions formed by every two structural elements are arranged in sequence in a vertical direction.

[0033] In one embodiment, a non-conductive filler is filled between the structural elements and the shielding structure that are in a vertically adjacent relationship, or a gap is formed between the structural elements and the shielding structure that are in a vertically adjacent relationship.

[0034] In one embodiment, the filler comprises:

[0035] Photoresist, SiOx and SiNx.

[0036] In one embodiment, the shielding structure is a shielding layer; the shielding layer has one or more layers.

[0037] In one embodiment, the cross-section of the shielding layer is arched or frame-shaped.

[0038] In one embodiment, the shielding structure is made of superconducting material, or non-superconducting metal material.

[0039] In one embodiment, the quantum chip is a single chip.

[0040] In one embodiment, the plurality of structural elements are all electrically conductive.

[0041] In one embodiment, the quantum chip is a superconducting quantum chip.

[0042] In one embodiment, two ends of the shielding structure are respectively connected to the ground, and the shielding structure is arranged in an arch shape and spans over one of the two structural elements having the intersection area.

[0043] In a second aspect, an embodiment of the present invention provides a quantum computing device, which includes the quantum chip as described above.

[0044] The beneficial effects of the above technical solutions provided by the embodiments of the present invention include at least:

[0045] The above-mentioned quantum chip and related quantum computing device provided by the embodiment of the present invention, on the same single-layer chip, by setting a shielding structure in two structural elements with an intersection area, and the shielding structure is located between the two structural elements with an intersection area in the vertical direction, can effectively shield the two structural elements, avoid the coupling and signal crosstalk problems between the two structural elements with an intersection area, ensure the service life of the quantum bit, and improve the reliability of the quantum chip.

[0046] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0047] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0049] FIG1 is a first implementation of a quantum bit expansion solution in the prior art;

[0050] FIG2 is a second implementation of the quantum bit expansion solution in the prior art;

[0051] FIG3 is a top view of the structural element 1, the structural element 2 and the shielding layer in the first structural form in an embodiment of the present invention;

[0052] FIG4 is a cross-sectional view of the structural element 1, the structural element 2 and the shielding layer 3 in the first structural form provided by an embodiment of the present invention;

[0053] FIG5 is a top view of the structural element 1, the structural element 2 and the shielding layer 3 in the second structural form provided by an embodiment of the present invention;

[0054] FIG6 is a top view of the structural element 1 , the structural element 2 and the shielding layer 3 in the third structural form provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0056] In the description of the invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the invention. In addition, the terms "first", "second" and "third" are only used for descriptive purposes and should not be understood as indicating or implying relative importance. In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be a communication between the internal parts of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] Regarding the solution to expand the existing quantum bits, the inventors of this application have found that there are two common approaches in the prior art to rationally utilize spatial wiring to achieve more quantum bits in a limited space:

[0058] In the first solution, all components and signal lines of the chip are set on a single chip (Die), and a large number of crosses occur between the signal lines. As shown in the enlarged schematic diagram in the lower right corner of Figure 1, in this case, the air bridge process is used to achieve cross-line and avoid line collision. This technical solution has a simple process and can be prepared without the use of complex multi-layer chip processes and expensive multi-layer process equipment.

[0059] However, this approach may lead to a drastic shortening of the lifetime of quantum bits due to the use of air bridges across components.

[0060] For example, if the air bridge connecting the signal line is placed directly above the qubit, that is, there is an intersection or overlap in the height direction of the air bridge and the qubit, a direct capacitive coupling will be generated between the air bridge and the qubit. The more air bridges there are, the more capacitive coupling between the qubit and the outside world will increase exponentially, and the energy of the qubit will leak to the outside world through this undesirable capacitive coupling. Among them, the qubit is one of the many components in the quantum chip.

[0061] As shown in Figure 2, the second solution is to prepare the various components and signal lines of the chip on multiple chips (die), such as the readout / interconnect tier, TSV tier, and Qubit tier in Figure 2, and then press-weld the multiple chips together to achieve multi-bit integration. The advantage of this solution is that different signal lines and components are set on different chips, without crossing, and the crosstalk and coupling between signal lines will also be very small. However, the disadvantage is that it requires a large number of complex multi-layer chip processes such as through silicon via technology (TSV) and flip chip technology. Because the process level is high and more complex and high-end equipment is required, the cost is relatively high.

[0062] In order to achieve the expansion of quantum bits and avoid the above-mentioned problems, the inventors of this application have implemented an extended architecture of quantum bits on a single chip through design concepts, which reduces the hardware requirements of the second solution in the prior art and solves the problem of short quantum bit lifespan on a single chip.

[0063] Based on this, an embodiment of the present application provides a quantum chip, comprising: a plurality of structural elements;

[0064] The plurality of structural elements include at least two structural elements having an intersection area;

[0065] In the intersection region, a shielding structure is provided; the shielding structure is located between the two structural elements in the intersection region in a vertical direction.

[0066] Wherein, the plurality of structural elements are all conductive.

[0067] The above-mentioned quantum chip is a single chip (Die) or simply a single chip. In the single chip, there are at least two structural elements that intersect with each other, that is, there is an intersection area.

[0068] The above-mentioned two structural elements have an intersection area. In the intersection area, one of the two structural elements is above and the other is below. In the intersection area, in the height direction, the shielding structure is arranged between the two structural elements, which can play a better shielding role, so that the two structural elements will not produce capacitive coupling or at least can reduce unnecessary capacitive coupling, thereby reducing crosstalk on the chip and ensuring the life of the quantum bit.

[0069] Referring to the examples shown in Figures 3 and 4, structural element 1 and structural element 2 are disposed on the chip substrate of the same quantum chip (die) and belong to the same chip. Figure 3 is a top view of structural element 1, structural element 2, and shielding layer 3; Figure 4 is a cross-sectional view of structural element 1, structural element 2, and shielding layer 3.

[0070] As can be seen from Figures 3 and 4, the structural element 1 and the structural element 2 intersect with each other, and there is an intersection area. In this intersection area, a shielding structure 3 exists between the structural element 1 and the structural element 2. In the vertical direction, that is, in the height direction, the shielding structure 3 is located between the structural element 1 and the structural element 2.

[0071] In the examples shown in Figures 3 and 4, structural element 2 is located above shielding structure 3, and structural element 1 is located below shielding structure 3. In embodiments of the present invention, the structural relationship between structural element 1 and structural element 2 can also be reversed, that is, structural element 1 is located above shielding structure 3, and structural element 2 is located below shielding structure 3.

[0072] In the embodiment of the present invention, the specific form and angle of intersection between the structural elements are not limited.

[0073] In one embodiment, the shielding structure 3 may be a layered structure, that is, a shielding layer; the number of layers of the shielding layer may be one or more layers.

[0074] When the shielding layer is multi-layer, the layers are stacked in the vertical direction, and adjacent layers are fully or partially combined together, or there are gaps between the layers, and interlayer insulation is achieved by air or vacuum.

[0075] In one embodiment, the cross-section of the shielding layer is arch-shaped or square-shaped.

[0076] As shown in FIG3 , the shielding layer adopts an arch shape.

[0077] In one embodiment, the two structural elements having the intersection region (such as structural element 1 and structural element 2 in FIG. 3 and FIG. 4 ) may include the following situations:

[0078] Two signal lines crossing each other; or

[0079] Two components crossing each other; or

[0080] Signal lines and components that cross signal lines.

[0081] The aforementioned components may be any components used in a quantum chip, including but not limited to electronic components such as quantum bits, resonators, and tunable couplers.

[0082] The signal lines include, for example, DC signal lines, microwave signal lines, and the like.

[0083] In one embodiment, the shielding structure 3 uses the same material as the structural elements 1 and 2, such as various superconducting materials, or can use non-superconducting metal materials, or other suitable types of materials with conductive functions, etc., and this application does not impose any restrictions on this.

[0084] Common superconducting materials include: some metals with superconducting properties (such as niobium, lead, etc.) or alloy materials (niobium-zirconium alloy, niobium-titanium alloy, etc.), or compounds (such as barium-yttrium-copper oxide, etc.).

[0085] The shielding structure 3 may also be made of non-superconducting metal materials, such as copper.

[0086] For the examples shown in FIG3 and FIG4, structural element 1 and structural element 2 may both be signal lines, or one of structural element 1 and structural element 2 may be a signal line and the other may be a component; or both structural element 1 and structural element 2 may be components.

[0087] In one embodiment, at least one of the two structural elements having an intersection region has a multi-component structure. For example, the structural element has structural subcomponents on either side of the intersection region; the structural subcomponents on either side of the intersection region are connected by a connecting portion. In the vertical direction, the shielding layer is located between the connecting portion of one structural element and the other structural element.

[0088] 3 and 4 , the structural element 2 has two structural subcomponents on both sides of the intersection area, namely, a structural subcomponent 21 and a structural subcomponent 22 provided on the left and right sides of the intersection area in FIG3 , respectively. The structural subcomponent 21 and the structural subcomponent 22 are connected by a connecting portion 23 .

[0089] The shielding layer 3 is disposed below the connecting portion 23 and above the structural element 1 .

[0090] Specifically, in the horizontal direction, the shielding structure 3 is arranged on the inner side of the two structural subcomponents (structural subcomponent 21 and structural subcomponent 22) of the structural element 2 and spans the entire structural element 1; in the vertical direction, the shielding structure 3 is located above the structural element 1 and below the connecting portion 23 of the structural element 2.

[0091] In another possible embodiment, which is not shown in the figure, the shielding structure 3 is located below the structural element 1 and above the connecting portion 23 of the structural element 2. In the horizontal direction, the shielding structure 3 is arranged on the inner side of the two structural subcomponents (structural subcomponent 21 and structural subcomponent 22) of the structural element 1 and spans the connecting portion 23 of the structural element 2.

[0092] Accordingly, in the above embodiment, the width of the shielding structure 3 is greater than or equal to the width of the structural element 1 it spans, or / and the width of the shielding structure 3 is greater than or equal to the width of the connecting portion 23 of the structural element 2 .

[0093] In one embodiment, as shown in FIG4 , the quantum chip further includes: a chip substrate;

[0094] The plurality of structural elements (such as structural element 1 and structural element 2 in FIG. 3 and FIG. 4 ) are disposed on the chip substrate;

[0095] The shielding structure 3 is disposed on the ground and is conductively connected to the ground.

[0096] In FIG. 4 , only a portion of the chip substrate, the structural subcomponent 22 , and a portion of the structural subcomponent 21 are shown.

[0097] 3 and 4 , the ground and the two structural subcomponents (structural subcomponent 22 and structural subcomponent 21 ) of the structural element 2 are located on the same layer, and the ground and the shielding structure 3 are located inside the structural subcomponents 21 and 22 of the structural element 2 .

[0098] The shielding structure 3 has two ends connected to the ground, and is arched across one of the two structural elements in the intersecting region. For example, as shown in FIG4 , the shielding structure 3 is arched across the structural element 1, with its two ends connected to the ground.

[0099] When the shielding structure 3 adopts an arched structure, its two ends are in contact with the ground and are conductive. Of course, the present application is not limited to the shielding structure 3 having only the two ends in contact with the ground and are conductive.

[0100] In one embodiment, the ground plane can be made of a superconducting metal film, for example, made of Al, Nb, Ta, etc. The ground plane is obtained by photolithography of the superconducting metal film. However, the ground plane can also be made of other suitable conductive materials, which is not limited in this application.

[0101] In one embodiment, in the quantum chip, the connection portion 23 can be implemented by, for example, a bridge structure.

[0102] Furthermore, the connecting portion 23 is an air bridge or a dielectric bridge.

[0103] An air bridge is a circuit structure that uses a three-dimensional bridge structure to achieve planar circuit bridging.

[0104] A dielectric bridge is a structure in microelectronic devices that consists of a thin film supported by one or more cantilever beams, where the thin film is called the "bridge".

[0105] The embodiments of the present invention are not limited to the above two bridge microstructures.

[0106] Referring to the example of another structure of a quantum chip shown in Figure 5, the structural element 1 is in the form of multiple components, and the structural sub-components 11 and 12 on both sides of the intersection area (the upper and lower sides of Figure 5) are connected by a connecting portion 13. The shielding structure 3 spans the structural element 2 and is located under the connecting portion 13 of the structural element 1.

[0107] In one embodiment, the width of the shielding structure 3 is greater than or equal to the width of the structural element 2 it spans, or / and the width of the shielding structure 3 is greater than or equal to the width of the connecting portion 13 of the structural element 1 .

[0108] For example, in FIG. 5 , the width of the shielding structure 3 may be comparable to the width of the structural element 2 it spans, or may be much larger than the width of the structural element 2 .

[0109] Alternatively, in other embodiments, the width of the shielding structure 3 is greater than or equal to the width of the connecting portion 13 .

[0110] For example, in FIG. 5 , the width of the shielding structure 3 may be comparable to the width of the connecting portion 13 , or may be much larger than the width of the connecting portion 13 .

[0111] In another case, two mutually intersecting structural elements both adopt a structural form composed of multiple structural sub-components.

[0112] For the case where both of the two mutually intersecting structures adopt a structure similar to the structural element 2 in Figure 1, in this case, the shielding structure 3 is provided between the connecting portions of the two structural elements.

[0113] 6 , both structural element 1 and structural element 2 are composed of two interconnected structural sub-components. In the intersection region, in the vertical direction, the shielding structure 3 is located between the connecting portions of the structural element 1 and the structural element 2 .

[0114] Structural element 1 and structural element 2 are each provided with two structural sub-components on both sides of the intersection area, and the two structural sub-components belonging to the same structural element are connected by respective connecting parts;

[0115] The shielding structure 3 is located inside the two structural subcomponents of the structural element 1 on both sides of the intersection area; or the shielding structure 3 is located inside the two structural subcomponents of the structural element 2 on both sides of the intersection area;

[0116] In the vertical direction, the shielding structure is located between the connecting portion of the structural element 1 and the connecting portion of the structural element 2 .

[0117] Figure 6 shows a situation where the connecting portion of the structural element 1 is located below the shielding layer 3, and the connecting portion of the structural element 2 is located above the shielding layer 3. Those skilled in the art can easily imagine that the structural relationship between the two can also be reversed, that is, the connecting portion of the structural element 2 is located below the shielding layer 3, and the connecting portion of the structural element 1 is located above the shielding layer 3. The embodiments of the present invention are not limited to this.

[0118] In one embodiment, the shielding structure 3 is grounded or floating.

[0119] The grounding of the shielding structure 3 can effectively suppress electromagnetic interference between various structural elements in the quantum chip.

[0120] Floating ground can also prevent electromagnetic interference to a certain extent.

[0121] In one embodiment, the plurality of structural elements in the same layer include more than three structural elements in an intersection region; and a shielding structure is provided between every two structural elements in an intersection region.

[0122] Furthermore, in one embodiment, among the three or more structural elements having intersection regions, the intersection regions formed by every two structural elements are arranged in sequence in the vertical direction.

[0123] In other words, if three or more structural elements have intersecting regions, and these intersecting regions overlap in height, for example, if there is an intersecting region between structural element 1 and structural element 2, and an intersecting region between structural element 2 and structural element 3, and the intersecting region between structural element 1 and structural element 2 is located above the intersecting region between structural element 2 and structural element 3, then corresponding shielding layers 3 can be provided in the intersecting regions of structural element 1 and structural element 2, and in the intersecting regions of structural element 2 and structural element 3, respectively. For example, a shielding layer can be provided between structural element 1 and structural element 2, and similarly, a shielding layer 3 can be provided between structural element 2 and structural element 3. In other words, a shielding layer can be provided between every two structural elements adjacent in height.

[0124] In one embodiment, a non-conductive filler is filled between the structural elements 1 and 2 and the shielding structure 3 that are in a vertically adjacent relationship, or a gap is formed between the structural elements 1 and 2 and the shielding structure 3 that are in a vertically adjacent relationship.

[0125] The non-conductive filler may be, for example, photoresist, SiOx, SiNx, etc.

[0126] During the actual operation of the quantum chip, the above-mentioned gap may be in a vacuum state, and in a non-operating state, it may also be filled with air or other gases (such as a pure gas), which is not limited in the embodiment of the present invention.

[0127] The quantum chip in each of the above embodiments is a superconducting quantum chip. However, the quantum chip may alternatively be another suitable type of chip, such as a semiconductor quantum chip. The present application does not impose any specific restrictions on the type of quantum chip. As long as a shielding structure 3 is provided in the intersection region between the structural element 1 and the structural element 2 in a single quantum chip, and the function of the shielding structure 3 is to reduce the capacitive coupling between the structural element 1 and the structural element 2, all technical solutions based on this core technical idea should fall within the scope of protection of the present application.

[0128] Based on the same inventive concept, an embodiment of the present invention further provides a quantum computing device, which includes the quantum chip as described above.

[0129] The aforementioned quantum computing devices may be, for example, quantum computers, various quantum communication devices, and the like. The aforementioned quantum chips and related quantum computing devices provided by embodiments of the present invention, on the same single-layer chip, utilize shielding structures disposed between two structural elements with an intersecting region. The shielding structures are located vertically between the two structural elements with the intersecting region. This effectively shields the two structural elements, preventing coupling and signal crosstalk between the two structural elements with the intersecting region, thereby ensuring the service life of the quantum bits and improving the reliability of the quantum chip.

[0130] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A quantum chip, characterized in that: include: multiple structural elements; The plurality of structural elements include at least two structural elements having intersection areas; A shielding structure is provided in the intersection region; the shielding structure is located between the two structural elements having the intersection region in a vertical direction.

2. The quantum chip according to claim 1, characterized in that: The two structural elements having an intersection area include: Two signal lines crossing each other; or Two components crossing each other; or A signal line and a component having an intersection area with the signal line.

3. The quantum chip according to claim 1, characterized in that: Among the two structural elements with the intersection area, at least one structural element has structural sub-components respectively arranged on both sides of the intersection area; and the structural sub-components are connected by connecting parts.

4. The quantum chip according to claim 3, characterized in that: The connecting portion is realized by a bridge structure.

5. The quantum chip according to claim 4, characterized in that: The connecting portion is an air bridge or a dielectric bridge.

6. The quantum chip according to claim 3, characterized in that: The two structural elements with the intersection area are respectively a first structural element and a second structural element; the first structural element is provided with two structural sub-components on both sides of the intersection area, and the two structural sub-components are connected by the connecting portion; the second structural element is an integral structure; In the vertical direction, the shielding layer is located between the connecting portion of the first structural element and the second structural element.

7. The quantum chip according to claim 6, characterized in that: In the horizontal direction, the shielding structure is arranged at the inner side of the two structural subcomponents of the first structural element and spans the second structural element; in the vertical direction, the shielding structure is located above the second structural element and below the connecting portion of the first structural element.

8. The quantum chip according to claim 6, characterized in that: In the horizontal direction, the shielding structure is arranged on the inner side of the two structural subcomponents of the first structural element and spans the connecting portion of the first structural element; in the vertical direction, the shielding structure is located below the second structural element and above the connecting portion of the first structural element.

9. The quantum chip according to claim 7 or 8, characterized in that: The width of the shielding structure is greater than or equal to the width of the second structural element it crosses, or / and the width of the shielding structure is greater than or equal to the width of the connecting portion.

10. The quantum chip according to claim 3, characterized in that: The two structural elements with the intersection area are respectively a first structural element and a second structural element; the first structural element and the second structural element are respectively provided with two structural sub-components on both sides of the intersection area, and the two structural sub-components belonging to the same structural element are connected by respective connecting parts; The shielding structure is located inside the two structural subcomponents of the first structural element located on both sides of the intersection area; or the shielding structure is located inside the two structural subcomponents of the second structural element located on both sides of the intersection area; In the vertical direction, the shielding structure is located between the connecting portion of the first structural element and the connecting portion of the second structural element.

11. The quantum chip according to any one of claims 1 to 8 and 10, characterized in that: The shielding structure is grounded or floating.

12. The quantum chip according to claim 11, characterized in that: Also includes: Chip substrate; The ground is disposed on the chip substrate, and the plurality of structural elements are disposed on the chip substrate; The shielding structure is disposed on the ground and is conductively connected to the ground.

13. The quantum chip according to claim 12, characterized in that: The ground is located at the same layer as the two structural subcomponents, and is located inside the two structural subcomponents.

14. The quantum chip according to claim 12, characterized in that: The ground is made of superconducting metal film.

15. The quantum chip according to any one of claims 1 to 8 and 10, characterized in that: The plurality of structural elements in the same layer include more than three structural elements in the intersection area; and the shielding structure is arranged between every two structural elements in the intersection area.

16. The quantum chip according to claim 15, characterized in that: Among the three or more structural elements having intersection regions, the intersection regions formed by every two structural elements are arranged in sequence in the vertical direction.

17. The quantum chip according to claim 16, characterized in that: A non-conductive filler is filled between the structural elements and the shielding structure that are adjacent to each other in an up-and-down relationship, or a gap is formed between the structural elements and the shielding structure that are adjacent to each other in an up-and-down relationship.

18. The quantum chip according to claim 17, characterized in that: The filler comprises: Photoresist, SiOx and SiNx.

19. The quantum chip according to any one of claims 1 to 8 and 10, characterized in that: The shielding structure is a shielding layer; the number of layers of the shielding layer is one or more.

20. The quantum chip according to claim 19, characterized in that: The cross-sectional shape of the shielding layer is an arch shape or a square frame shape.

21. The quantum chip according to any one of claims 1 to 8 and 10, characterized in that: The shielding structure is made of superconducting material or non-superconducting metal material.

22. The quantum chip according to any one of claims 1 to 8 and 10, characterized in that: The quantum chip is a single chip.

23. The quantum chip according to any one of claims 1 to 8 and 10, characterized in that: The plurality of structural elements are all conductive.

24. The quantum chip according to any one of claims 1 to 8 and 10, characterized in that: The quantum chip is a superconducting quantum chip.

25. The quantum chip according to claim 13, characterized in that: Two ends of the shielding structure are connected to the ground respectively, and the shielding structure is arranged in an arch shape and straddles one of the two structural elements having the intersection area.

26. A quantum computing device, characterized in that Comprising a quantum chip as described in any one of claims 1-25.

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