Demand response device interface detection circuit, method, electronic device and medium

Abstract

The present application provides a demand response device interface detection circuit, method, electronic device and medium, the circuit includes an interface controller, a multiplexer, a sampling circuit and an isolation amplifier; the interface controller sends multiple detection control signals to the multiplexer through multiple IO ports; the multiplexer selects the target level state collected by the sampling circuit according to the detection control signal, and obtains a first level state signal according to the target level state; the multiplexer inputs the first level state signal into the isolation amplifier for isolation amplification to obtain a second level state signal; the isolation amplifier inputs the second level state signal into the interface controller, so that the interface controller performs switch state detection according to the second level state signal. By adopting the above-mentioned demand response device interface detection circuit, method, electronic device and medium, the problem of AD port resource waste of the MCU chip is solved.

Description

Technical Field

[0001] The present application relates to the technical field of inverters, and in particular to a demand response device interface detection circuit, method, electronic device and medium. Background Art

[0002] DRED (Demand Response Enabling Device) is a power demand response enabling device, which is a grid dispatching device. In the power system, DRED is used to implement demand response (DR), which is a mechanism that responds to changes in power system demand by incentivizing or requiring users to change their electricity consumption behavior within a specific time. In the application of inverters, DRED can be used in conjunction with inverters to achieve control and management of power output. For example, the inverter can implement the DRM (Demand Response Modes) function by connecting to the DRED device to adjust its output power according to the needs of the power grid. This function is clearly required in the AS4777 standard. Specific to the operation of the inverter, the inverter needs to implement the DRM function by connecting to the data acquisition (data collector). When the main inverter is connected to the DRED device through the data acquisition, the DRM parameters can be set through the data acquisition Web management system or the smart photovoltaic App. This allows the grid dispatch center to remotely control the inverter through the DRED device to respond to changes in power grid demand.

[0003] In the prior art, the AD port of an MCU (Microcontroller Unit) chip is usually used to detect the voltage amplitude of each communication line of a DRED interface, and the switch state of a controlled switch is determined by the amplitude combination. However, using too many AD ports to detect the voltage amplitude of the communication line will cause a waste of AD port resources of the MCU chip. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a demand response device interface detection circuit, method, electronic device and medium to solve the problem of AD port resource waste of the MCU chip.

[0005] In a first aspect, an embodiment of the present application provides a demand response device interface detection circuit, including an interface controller, a multiplexer, a sampling circuit and an isolation amplifier, the interface controller including an AD port and a plurality of IO ports, and the sampling circuit is used to collect the level state of the demand response device interface;

[0006] The interface controller is connected to the multiplexer, and multiple detection control signals generated by the interface controller are sent to the multiplexer through multiple IO ports;

[0007] The multiplexer is connected to the sampling circuit, and the multiplexer selects the target level state collected by the sampling circuit according to the detection control signal, and obtains the first level state signal according to the target level state;

[0008] The multiplexer is connected to the isolation amplifier, and the first level state signal is input to the isolation amplifier for isolation amplification processing to obtain a second level state signal after isolation amplification;

[0009] The isolation amplifier is connected to the AD port of the interface controller, and inputs the second level state signal into the interface controller, so that the interface controller performs switch state detection according to the second level state signal.

[0010] Optionally, the demand response device interface detection circuit also includes an optocoupler circuit; one end of the optocoupler circuit is connected to the interface controller, and the other end of the optocoupler circuit is connected to the multiplexer; the optocoupler circuit receives multiple detection control signals sent by the interface controller, and electrically isolates the multiple detection control signals, and sends the isolated multiple detection control signals to the multiplexer.

[0011] Optionally, the multiple IO ports are three IO ports, the optocoupler circuit includes three optocoupler sub-circuits, and an input end of each optocoupler sub-circuit is connected to one IO port.

[0012] Optionally, the demand response device interface detection circuit also includes an op amp; one end of the op amp is connected to the isolation op amp, and the other end of the op amp is connected to the AD end of the interface controller; the op amp receives the second level state signal output by the isolation op amp, filters and amplifies the second level state signal to obtain a third level state signal, and sends the third level state signal to the AD end of the interface controller, so that the interface controller performs switch state detection according to the third level state signal.

[0013] Optionally, the demand response device interface detection circuit also includes a follower; one end of the follower is connected to the op amp, and the other end of the follower is connected to the AD end of the interface controller; the follower receives a third level state signal output by the op amp, isolates and buffers the third level state signal to obtain a fourth level state signal, and sends the fourth level state signal to the AD end of the interface controller, so that the interface controller performs switch state detection according to the fourth level state signal.

[0014] Optionally, the sampling circuit includes multiple level status collection terminals, which are connected to the intermediate nodes of the controlled switches of the demand response device interface as input terminals of the sampling circuit to collect the level status; the output terminal of the sampling circuit is connected to the input terminal of the multiplexer to input the filtered level status to the multiplexer.

[0015] Optionally, each optocoupler sub-circuit includes an optocoupler and a transistor.

[0016] In a second aspect, an embodiment of the present application further provides a demand response device interface detection method, which is applied to the above-mentioned demand response device interface detection circuit, the demand response device interface detection circuit includes a multiplexer, and the method includes:

[0017] Sending multiple groups of detection control signals to the multiplexer within a preset time range, and receiving multiple level status signals returned by the multiplexer;

[0018] For each level status signal, determining whether the level status signal meets the voltage value requirement;

[0019] If the multiple level state signals all meet the voltage value requirement, the switch states of the controlled switches corresponding to the multiple level state signals are queried in the preset logic state table.

[0020] In the third aspect, an embodiment of the present application also provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the demand response device interface detection method as described above are performed.

[0021] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the demand response device interface detection method as described above are executed.

[0022] The embodiments of the present application bring the following beneficial effects:

[0023] The demand response device interface detection circuit, method, electronic device and medium provided in the embodiment of the present application can collect the signal of the DRED interface by combining the controller IO port and AD port. The controller judges the switch state of the controlled switch under different working states according to the high and low level state of the detected IO port and the voltage amplitude of the AD port. At the same time, a multiplexer and an isolation amplifier are added to the detection circuit to strengthen the insulation isolation between the DRED interface and the MCU chip, improve the anti-interference and safety performance of the detection circuit, and compared with the demand response device interface detection method in the prior art, it solves the problem of waste of AD port resources of the MCU chip when detecting the voltage amplitude of each communication line of the DRED interface.

[0024] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of a demand response device interface detection circuit provided in an embodiment of the present application is shown;

[0027] Figure 2 A circuit diagram of a sampling circuit provided in an embodiment of the present application is shown;

[0028] Figure 3 A circuit diagram of a multiplexer provided in an embodiment of the present application is shown;

[0029] Figure 4 A circuit diagram of an optocoupler circuit provided in an embodiment of the present application is shown;

[0030] Figure 5 A circuit diagram of an operational amplifier circuit provided in an embodiment of the present application is shown;

[0031] Figure 6 A circuit diagram of a follower circuit provided in an embodiment of the present application is shown;

[0032] Figure 7 A flow chart of a demand response device interface detection method provided in an embodiment of the present application is shown;

[0033] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work belongs to the scope of protection of the present application.

[0035] It is worth noting that before this application was proposed, DRED (Demand Response Enabling Device) was a power demand response enabling device, which is a power grid dispatching device. In the power system, DRED is used to implement demand response (DR), which is a mechanism that responds to changes in power system demand by incentivizing or requiring users to change their electricity consumption behavior within a specific time. In the application of the inverter, DRED can be used in conjunction with the inverter to achieve control and management of power output. For example, the inverter can implement the DRM (Demand Response Modes) function by connecting the DRED device to adjust its output power according to the needs of the power grid. This function is clearly required in the AS4777 standard. Specifically for the operation of the inverter, the inverter needs to implement the DRM function by connecting to the data acquisition (data collector). When the main inverter is connected to the DRED device through the data acquisition, the DRM parameters can be set through the data acquisition Web management system or the smart photovoltaic App. This allows the power grid dispatching center to remotely control the inverter through the DRED device to respond to changes in power grid demand. In the prior art, the AD port of an MCU (Microcontroller Unit) chip is usually used to detect the voltage amplitude of each communication line of a DRED interface, and the switch state of a controlled switch is determined by the amplitude combination. However, using too many AD ports to detect the voltage amplitude of the communication line will cause a waste of AD port resources of the MCU chip.

[0036] Based on this, an embodiment of the present application provides a demand response device interface detection circuit to save waste of AD port resources of the MCU chip.

[0037] See also Figure 1 , Figure 1 This is a schematic diagram of a demand response device interface detection circuit provided by an embodiment of the present application. Figure 1 As shown, the demand response device interface detection circuit provided in the embodiment of the present application includes:

[0038] The interface controller 100, the multiplexer 200, the sampling circuit 300 and the isolation amplifier 400. The interface controller 100 includes an AD port and a plurality of IO ports, and the sampling circuit 300 includes a plurality of level state acquisition terminals.

[0039] The interface controller 100 is connected to the multiplexer 200 , and sends a plurality of detection control signals generated by the interface controller 100 to the multiplexer 200 through a plurality of IO ports.

[0040] The multiplexer 200 is connected to the sampling circuit 300, and the multiplexer 200 selects the target level state collected by the sampling circuit 300 according to the detection control signal, and obtains a first level state signal according to the target level state;

[0041] The multiplexer 200 is connected to the isolation amplifier 400, and the first level state signal is input to the isolation amplifier 400 for isolation amplification processing to obtain a second level state signal after isolation amplification;

[0042] The isolation amplifier 400 is connected to the AD port of the interface controller 100 and inputs the second level state signal to the interface controller 100 so that the interface controller 100 performs switch state detection according to the second level state signal.

[0043] In the embodiment of the present application, the demand response device may refer to DRED, and there are nine controlled switches in the DRED interface, namely switch S0, switch S1, switch S2, switch S3, switch S4, switch S5, switch S6, switch S7, and switch S8. There are six communication lines, namely communication line DRM1 / 5, communication line DRM2 / 6, communication line DRM3 / 7, communication line DRM4 / 8, communication line REF GE / 0, and communication line COM LOAD / 0.

[0044] The communication line drawn from the middle node of switch S1 and switch S5 is used as the level state acquisition terminal DRM1 / 5, and the level state acquisition terminal DRM1 / 5 detects the switch state of switch S1 and switch S5. The communication line drawn from the middle node of switch S2 and switch S6 is used as the level state acquisition terminal DRM2 / 6, and the level state acquisition terminal DRM2 / 6 detects the switch state of switch S2 and switch S6. The communication line drawn from the middle node of switch S3 and switch S7 is used as the level state acquisition terminal DRM3 / 7, and the level state acquisition terminal DRM3 / 7 detects the switch state of switch S3 and switch S7. The communication line drawn from the middle node of switch S4 and switch S8 is used as the level state acquisition terminal DRM4 / 8, and the level state acquisition terminal DRM4 / 8 detects the switch state of switch S4 and switch S8. REF GEN0 is directly connected to COM_5V, COM LOAD0 is connected to the level state acquisition terminal DRM0, and the level state acquisition terminal DRM0 detects the switch state of switch S0.

[0045] The sampling circuit 300 is used to collect the level state of the demand response device interface and filter the collected level state. The sampling circuit 300 includes multiple level state collection terminals, namely, the level state collection terminal DRM0, the level state collection terminal DRM1 / 5, the level state collection terminal DRM2 / 6, the level state collection terminal DRM3 / 7, and the level state collection terminal DRM4 / 8. The multiple level state collection terminals serve as the input terminals of the sampling circuit 300. Each level state collection terminal is connected to the demand response device interface to collect the level state at the intermediate node and COM LOAD0. The output terminal of the sampling circuit 300 is connected to the input terminal of the multiplexer 200. The sampling circuit 300 filters the collected level state and inputs it to the multiplexer 200. Among them, the signals input from the sampling circuit 300 to the multiplexer 200 are respectively recorded as: DRM0_U, DRM1 / 5_U, DRM2 / 6_U, DRM3 / 7_U, and DRM4 / 8_U.

[0046] Refer to the following Figure 2 Let's introduce the sampling circuit.

[0047] Figure 2 : shows a circuit diagram of a sampling circuit provided in an embodiment of the present application, such as Figure 2 As shown, the sampling circuit includes resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, capacitors C1, C2, C3, C4, and C5, and filtering is achieved by connecting resistors and capacitors in series and parallel. Among them, R4 and C1, R7 and C2, R10 and C3, R13 and C4, and R16 and C5 respectively form a group of RC filter circuits. The resistance value of R1 is 15KΩ, the resistance values ​​of R2, R3, R5, R6, R8, R9, R11, R12, R14, and R15 are all 10KΩ, the resistance values ​​of R4, R7, R10, R13, and R16 are all 1KΩ, and the capacitance values ​​of C1, C2, C3, C4, and C5 are all 0.1μF.

[0048] The multiple IO ports of the interface controller 100 are three IO ports, and the detection control signal is output to the multiplexer 200 through the three IO ports. The detection control signal is a high and low level signal, and the detection control signal includes three detection control signals, which are respectively recorded as: CS1, CS2, and CS3. The multiplexer 200 can refer to an analog switch-multiplexer, for example: the multiplexer 200 can be CD4051BPWR.

[0049] Refer to the following Figure 3 Let's introduce the multiplexer.

[0050] Figure 3 : shows a circuit diagram of a multiplexer provided in an embodiment of the present application, such as Figure 3 As shown, the multiplexer 200 includes three analog switch interfaces, i.e., control ports, which are A, B, and C, respectively. The three analog switch interfaces are respectively connected to the three IO ports of the interface controller 100 to receive detection control signals CS1, CS2, and CS3. The multiplexer 200 includes multiple signal input ports, which include X0, X1, X2, X3, X4, X5, X6, and X7. Among them, the signal input ports X0, X1, X2, X3, and X4 are connected to the output end of the sampling circuit 300 to receive the level state collected by the sampling circuit 300. For example, X0 is connected to DRM0 to receive the signal DRM0_U; X1 is connected to DRM1 / 5 to receive the signal DRM1 / 5_U; X2 is connected to DRM2 / 6 to receive the signal DRM2 / 6_U; X3 is connected to DRM3 / 7 to receive the signal DRM3 / 7_U; X4 is connected to DRM4 / to receive the signal DRM4 / 8_U. X is the output terminal of the multiplexer 200.

[0051] The multiplexer 200 searches the target chip select logic ports corresponding to the multiple detection control signals from the preset logic truth table, and screens the signal input to the multiplexer 200 by controlling the closing of the target chip select logic ports to select the target level state. The logic truth table is shown in Table 1.

[0052] Table 1: Logical truth table.

[0053]

[0054]

[0055] As shown in Table 1, when the detection control signal is CS1=1, CS2=1, CS3=1, the chip select logic port X0 is controlled to be closed, and the chip select logic port X0 is the target chip select logic port. At this time, the multiplexer 200 outputs DRM0_U, and DRM0_U is the target level state; when the detection control signal is CS1=1, CS2=1, CS3=0, the chip select logic port X1 is controlled to be closed, and the chip select logic port X0 is the target chip select logic port. At this time, the multiplexer 200 outputs DRM1 / 5_U, and DRM1 / 5_U is the target level state; when the detection control signal is CS1=1, CS2=0, CS3=1, the chip select logic port X2 is controlled to be closed, and the chip select logic port X0 is the target chip select logic port. It is the target chip select logic port. At this time, the multiplexer 200 outputs DRM2 / 6_U, and DRM2 / 6_U is the target level state; when the detection control signal is CS1=1, CS2=0, and CS3=0, the chip select logic port X3 is controlled to be closed, and the chip select logic port X0 is the target chip select logic port. At this time, the multiplexer 200 outputs DRM3 / 7_U, and DRM3 / 7_U is the target level state; when the detection control signal is CS1=0, CS2=0, and CS3=0, the chip select logic port X4 is controlled to be closed, and the chip select logic port X0 is the target chip select logic port. At this time, the multiplexer 200 outputs DRM4 / 8_U, and DRM4 / 8_U is the target level state.

[0056] The multiplexer 200 obtains a first level state signal according to the target level state, and the output end of the multiplexer 200 is connected to the input end of the isolation amplifier 400, and the input end of the isolation amplifier 400 is the INP pin, and the first level state signal is input to the isolation amplifier 400. The isolation amplifier 400 is used to isolate and amplify the first level state signal, and the isolation amplifier 400 may refer to NSI1300D25-DSWVR. The isolation amplifier 400 isolates the first level state signal and amplifies the first level state signal after isolation by 8.2 times to obtain a second level state signal, and the second level state signal is the first level state signal after isolation and amplification.

[0057] The output end of the isolation amplifier 400 is connected to the AD port of the interface controller 100. The isolation amplifier 400 inputs the second level state signal into the interface controller 100, and the interface controller 100 performs switch state detection according to the second level state signal. Among them, the output end of the isolation amplifier 400 is the OUTP pin and the OUTN pin, and the signal outputted from the output end of the isolation amplifier 400 is connected to the AD port of the interface controller 100 after filtering.

[0058] When the interface controller 100 performs switch state detection, it queries in the logic state table whether there is a voltage value corresponding to a group of second level state signals. If there is a corresponding voltage value, the switch state corresponding to the group of voltage values ​​is used as the switch state detection result of the nine controlled switches of the DRED interface. If there is no corresponding voltage value, it is determined that the controlled switch is closed abnormally and the detection ends. Among them, a group of second level state signals can refer to five level state signals within a preset time range, and the five level state signals include a second level state signal corresponding to each of DRM0_U, DRM1 / 5_U, DRM2 / 6_U, DRM3 / 7_U, and DRM4 / 8_U.

[0059] The demand response device interface detection circuit provided in the embodiment of the present application can collect the signal of the DRED interface by combining the controller IO port and the AD port. The controller determines the switch state of the controlled switch under different working states according to the high and low level states of the detected IO port and the voltage amplitude of the AD port. At the same time, a multiplexer and an isolation amplifier are added to the detection circuit to strengthen the insulation isolation between the DRED interface and the MCU chip, improve the anti-interference and safety performance of the detection circuit, and solve the problem of waste of AD port resources of the MCU chip when detecting the voltage amplitude of each communication line of the DRED interface.

[0060] In one example, the demand response device interface detection circuit further includes an optocoupler circuit 500. The input end of the optocoupler circuit 500 is connected to the output end of the interface controller 100, and the optocoupler circuit 500 includes three optocoupler sub-circuits, the circuits of the three optocoupler sub-circuits are the same, the input end of each optocoupler sub-circuit is connected to an IO port of the interface controller 100, and the input ends of different optocoupler sub-circuits are connected to different IO ports of the interface controller 100; the output end of each optocoupler sub-circuit is connected to a control port of the multiplexer 200, and the output ports of different optocoupler sub-circuits are connected to different control ports.

[0061] Refer to the following Figure 4 Let's introduce the optocoupler circuit.

[0062] Figure 4 : shows a circuit diagram of an optocoupler circuit provided in an embodiment of the present application, such as Figure 4 As shown, the first optocoupler sub-circuit includes: resistor R17, resistor R18, resistor R19, resistor R20, optocoupler O1, and transistor Q1; the second optocoupler sub-circuit includes: resistor R21, resistor R22, resistor R23, resistor R24, optocoupler O2, and transistor Q2; the third optocoupler sub-circuit includes: resistor R25, resistor R26, resistor R27, resistor R28, optocoupler O3, and transistor Q3.

[0063] One end of R18 is connected to the first IO port of the interface controller 100 as the input end of the first optocoupler sub-circuit, and the other end of R18 is connected to the base of the transistor Q1 in the first optocoupler sub-circuit, and the other end of R18 is also connected to one end of R19, and the other end of R19 is grounded. The emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the cathode of the optocoupler O1. The anode of the optocoupler O1 is connected to one end of R17, and the other end of R17 is connected to a 3.3V power supply. The collector of the optocoupler O1 serves as the output end of the first optocoupler sub-circuit, and the output end of the first optocoupler sub-circuit is connected to the control port A of the multiplexer 200. The emitter of the optocoupler O1 is grounded, and the collector of the optocoupler O1 is also connected to one end of R20, and the other end of R20 is connected to a 5V power supply.

[0064] One end of R22 is connected to the second IO port of the interface controller 100 as the input end of the second optocoupler subcircuit, and the other end of R22 is connected to the base of the transistor Q2 in the second optocoupler subcircuit. The other end of R22 is also connected to one end of R23, and the other end of R23 is grounded. The emitter of the transistor Q2 is grounded, and the collector of the transistor Q2 is connected to the cathode of the optocoupler O2. The anode of the optocoupler O2 is connected to one end of R21, and the other end of R21 is connected to a 3.3V power supply. The collector of the optocoupler O2 serves as the output end of the second optocoupler subcircuit, and the output end of the second optocoupler subcircuit is connected to the control port B of the multiplexer 200. The emitter of the optocoupler O2 is grounded, and the collector of the optocoupler O2 is also connected to one end of R24, and the other end of R24 is connected to a 5V power supply.

[0065] One end of R26 is connected to the third IO port of the interface controller 100 as the input end of the third optocoupler sub-circuit, and the other end of R26 is connected to the base of the transistor Q3 in the third optocoupler sub-circuit. The other end of R26 is also connected to one end of R27, and the other end of R27 is grounded. The emitter of the transistor Q3 is grounded, and the collector of the transistor Q3 is connected to the cathode of the optocoupler O3. The anode of the optocoupler O3 is connected to one end of R25, and the other end of R25 is connected to a 3.3V power supply. The collector of the optocoupler O3 serves as the output end of the third optocoupler sub-circuit, and the output end of the third optocoupler sub-circuit is connected to the control port C of the multiplexer 200. The emitter of the optocoupler O3 is grounded, and the collector of the optocoupler O3 is also connected to one end of R28, and the other end of R28 is connected to a 5V power supply.

[0066] Among them, R17, R21, and R25 are 510Ω, R18, R19, R22, R23, R26, and R27 are all 1KΩ, and R20, R24, and R28 are 4.7KΩ.

[0067] The output ends of the three optocoupler sub-circuits serve as the output ends of the optocoupler circuit 500, and the output end of the optocoupler circuit 500 is connected to the control port of the multiplexer 200. The optocoupler circuit 500 receives multiple detection control signals sent by the interface controller 100, and performs electrical isolation processing on the multiple detection control signals to prevent the high-voltage signal from interfering with and damaging the low-voltage part. At the same time, the multiple detection control signals after isolation are sent to the multiplexer 200. The control port of the multiplexer 200 receives the detection control signal to control the opening and closing of the signal input ports X0, X1, X2, X3, and X4 according to the detection control signal.

[0068] In one example, the demand response device interface detection circuit further includes an op amp circuit 600, the OUTP pin and the OUTN pin of the isolation op amp 400 serve as the output of the isolation op amp 400, the input of the op amp circuit 600 is connected to the output of the isolation op amp 400, the pin 7 of the op amp circuit 600 serves as the output of the op amp circuit 600, and the output of the op amp circuit 600 is connected to the AD terminal of the interface controller 100. The op amp circuit 600 receives the second level state signal output by the isolation op amp 400, filters and amplifies the second level state signal to obtain a third level state signal, and sends the third level state signal to the AD terminal of the interface controller 100, so that the interface controller 100 performs switch state detection according to the third level state signal.

[0069] Refer to the following Figure 5 Let's introduce the op amp circuit.

[0070] Figure 5 1 shows a circuit diagram of an operational amplifier circuit provided in an embodiment of the present application, such as Figure 5 As shown, the amplifier circuit 600 includes an amplifier U2, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a capacitor C6, and a capacitor C7. Among them, one end of the resistor R29 and the resistor R30 is connected to the output end of the isolation amplifier 400 as the input end of the amplifier circuit 600, and the other end of the resistor R29 and the resistor R30 is connected to the pin 5 and the pin 6 of the amplifier U2 respectively; the pin 5 of the amplifier U2 is also connected to one end of the resistor R31 and the capacitor C6, and the other end of the resistor R31 and the capacitor C6 is grounded; the pin 6 of the amplifier U2 is also connected to one end of the resistor R32 and the capacitor C7, and the other end of the resistor R32 and the capacitor C7 is connected to the output end (pin 7) of the amplifier U2; the resistor R31 and the capacitor C6 form a group of RC filter circuits, and the resistor R32 and the capacitor C7 form another group of RC filter circuits. The resistance values ​​of R29, R30, R30, and R31 are all 10KΩ, and the capacitance values ​​of C6 and C7 are all 100pF.

[0071] In one example, the demand response device interface detection circuit further includes a follower circuit 700, the input end of the follower circuit 700 is connected to the output end of the op amp circuit 600, and the output end of the follower circuit 700 is connected to the AD end of the interface controller 100. The follower circuit 700 receives the third level state signal output by the op amp circuit 600, performs isolation and buffering processing on the third level state signal to obtain a fourth level state signal, and sends the fourth level state signal to the AD end of the interface controller 100, so that the interface controller 100 performs switch state detection according to the fourth level state signal.

[0072] Refer to the following Figure 6 Let's introduce the follower circuit.

[0073] Figure 6 : shows a circuit diagram of a follower circuit provided in an embodiment of the present application, such as Figure 6 As shown, the follower circuit 700 includes a follower U3, a resistor R33, and a capacitor C8. Among them, the pin 3 of U3 is connected to the output end of the op amp circuit 600 as the input end of the follower circuit 700, the pin 1 of U3 is connected to one end of R33, and the other end of R33 is connected to the AD end of the interface controller 100 as the output end. The resistance value of R33 is 1KΩ, the capacitance value of C8 is 100pF, the pin 2 of the follower U3 is connected to the pin 1, the other end of R33 is also connected to one end of C8, and the other end of C8 is grounded.

[0074] Based on the same inventive concept, the embodiment of the present application also provides a demand response device interface detection method corresponding to the demand response device interface detection circuit. Since the principle of solving the problem by the method in the embodiment of the present application is similar to the above-mentioned demand response device interface detection circuit in the embodiment of the present application, the implementation of the method can refer to the implementation of the method, and the repeated parts will not be repeated.

[0075] See also Figure 7 , Figure 7 This is a flow chart of a demand response device interface detection method provided in an embodiment of the present application. Figure 7 As shown in , the demand response device interface detection method is applied to a demand response device interface detection circuit, the demand response device interface detection circuit includes a multiplexer, and the method includes:

[0076] Step S101, sending multiple groups of detection control signals to the multiplexer within a preset time range, and receiving multiple level status signals returned by the multiplexer;

[0077] Step S102, for each level status signal, determining whether the level status signal meets the voltage value requirement;

[0078] Step S103: if the multiple level state signals all meet the voltage value requirement, query the preset logic state table to obtain the switch states of the controlled switches corresponding to the multiple level state signals.

[0079] In step S101, the preset time range may refer to 2S, during which the interface controller will sequentially send five groups of detection control signals, each group of detection control signals including three detection control signals CS1, CS2, and CS3. The first group of detection control signals are CS1=1, CS2=1, and CS3=1; the second group of detection control signals are CS1=1, CS2=1, and CS3=0; the third group of detection control signals are CS1=1, CS2=0, and CS3=1; the fourth group of detection control signals are CS1=1, CS2=0, and CS3=0; and the fifth group of detection control signals are CS1=0, CS2=0, and CS3=0.

[0080] The multiplexer receives the five groups of detection control signals and selects the level state collected by the sampling circuit according to the five groups of detection control signals. For example, when the first group of detection control signals is CS1=1, CS2=1, and CS3=0, the multiplexer controls X1 to close to select DRM1 / 5_U as the target level state signal. The multiplexer sends the target level state signal to the isolation amplifier, and the target level state signal is input to the AD terminal of the interface controller after passing through the isolation amplifier, the amplifier, and the follower.

[0081] The interface controller receives five level status signals corresponding to five groups of detection control signals.

[0082] In step S102, for each level state signal, determine whether the level state signal meets the voltage value requirement, for example: compare the level state in the level state signal with multiple preset voltage ranges corresponding to the level state signal, determine which preset voltage range the level state is in, and make the preset voltage range in which the level state is located the target voltage range. The preset voltage range includes multiple, for example: the preset voltage range corresponding to the level state signal obtained by the DRM1 / 5 acquisition terminal is [0.85, 0.87], [1.35, 1.45], [1, 1.1]. If the level of the level state signal is 1, it is determined to be in the target voltage range of [1, 1.1]. Among them, the preset voltage range is determined based on the preset voltage.

[0083] If the level status signal is within a preset voltage range, it is determined that the level status signal meets the voltage value requirement; if the level status signal is not within any preset voltage range, it is determined that the level status signal does not meet the voltage value requirement.

[0084] If the five level state signals within the preset time range all meet the voltage value requirement, step S103 is executed; if any level state signal within the preset time range does not meet the voltage value requirement, it is determined that the switch closure is abnormal and the detection ends.

[0085] In step S103, the switch states of the controlled switches corresponding to the multiple level state signals are queried in the preset logic state table. The preset logic state table is as follows:

[0086] Table 2: Preset logic state table.

[0087]

[0088]

[0089]

[0090] As shown in Table 2, the switch state field records the switch states of each switch corresponding to the different level states collected by the five level state collection terminals. A switch state of 1 indicates that the controlled switch is closed, and a switch state of 0 indicates that the controlled switch is disconnected. For example, the levels collected by the five level state collection terminals DRM0, DRM1 / 5, DRM2 / 6, DRM3 / 7, and DRM4 / 8 are 2.198, 0, 0, 0, and 0, respectively. Then, the switch states of the controlled switches corresponding to the above five levels are queried in the preset logic state table as switch S0 is closed, and switches S1 to S8 are all disconnected.

[0091] See also Figure 8 , Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 8 As shown in , the electronic device 800 includes a processor 810 , a memory 820 and a bus 830 .

[0092] The memory 820 stores machine-readable instructions executable by the processor 810. When the electronic device 800 is running, the processor 810 communicates with the memory 820 via the bus 330. When the machine-readable instructions are executed by the processor 810, the above-mentioned Figure 7 The steps of the demand response device interface detection method in the method embodiment shown, the specific implementation method can be found in the method embodiment, and will not be repeated here.

[0093] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the computer program can execute the above-mentioned Figure 7 The steps of the demand response device interface detection method in the method embodiment shown, the specific implementation method can be found in the method embodiment, and will not be repeated here.

[0094] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0095] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0096] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0097] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0098] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application can essentially be embodied in the form of a software product, or in other words, the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0099] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A demand response device interface detection circuit, characterized in that: It includes an interface controller, a multiplexer, a sampling circuit and an isolation amplifier, wherein the interface controller includes an AD port and multiple IO ports, and the sampling circuit is used to collect the level state of the demand response device interface; The interface controller is connected to the multiplexer, and sends a plurality of detection control signals generated by the interface controller to the multiplexer through the plurality of IO ports; The multiplexer is connected to the sampling circuit, and the multiplexer selects the target level state collected by the sampling circuit according to the detection control signal, and obtains a first level state signal according to the target level state; The multiplexer is connected to the isolation amplifier, and inputs the first level state signal into the isolation amplifier for isolation amplification processing to obtain a second level state signal after isolation amplification; The isolation amplifier is connected to the AD port of the interface controller and inputs the second level state signal into the interface controller, so that the interface controller performs switch state detection according to the second level state signal.

2. The circuit according to claim 1, characterized in that The demand response device interface detection circuit also includes an optocoupler circuit; One end of the optocoupler circuit is connected to the interface controller, and the other end of the optocoupler circuit is connected to the multiplexer; The optocoupler circuit receives a plurality of detection control signals sent by the interface controller, electrically isolates the plurality of detection control signals, and sends the isolated plurality of detection control signals to the multiplexer.

3. The circuit according to claim 2, characterized in that The multiple IO ports are three IO ports, the optocoupler circuit includes three optocoupler sub-circuits, and the input end of each optocoupler sub-circuit is connected to one IO port.

4. The circuit according to claim 1, characterized in that The demand response device interface detection circuit also includes an operational amplifier; One end of the operational amplifier is connected to the isolation operational amplifier, and the other end of the operational amplifier is connected to the AD end of the interface controller; The operational amplifier receives the second level state signal output by the isolation operational amplifier, performs filtering and amplification processing on the second level state signal to obtain a third level state signal, and sends the third level state signal to the AD terminal of the interface controller, so that the interface controller performs switch state detection according to the third level state signal.

5. The circuit according to claim 4, characterized in that The demand response device interface detection circuit also includes a follower; One end of the follower is connected to the operational amplifier, and the other end of the follower is connected to the AD end of the interface controller; The follower receives the third level state signal output by the op amp, performs isolation and buffering processing on the third level state signal to obtain a fourth level state signal, and sends the fourth level state signal to the AD terminal of the interface controller so that the interface controller performs switch state detection according to the fourth level state signal.

6. The circuit according to claim 1, characterized in that The sampling circuit includes a plurality of level state acquisition terminals, which are connected to the intermediate nodes of the controlled switches of the demand response device interface as input terminals of the sampling circuit to acquire the level state; The output end of the sampling circuit is connected to the input end of the multiplexer to input the level state after filtering to the multiplexer.

7. The circuit according to claim 3, characterized in that Each optocoupler sub-circuit includes an optocoupler and a triode.

8. A method for detecting a demand response device interface, characterized in that: The demand response device interface detection circuit as claimed in any one of claims 1 to 7, wherein the demand response device interface detection circuit comprises a multiplexer, including: Sending multiple groups of detection control signals to the multiplexer within a preset time range, and receiving multiple level status signals returned by the multiplexer; For each level status signal, determining whether the level status signal meets the voltage value requirement; If the multiple level state signals all meet the voltage value requirement, the switch states of the controlled switches corresponding to the multiple level state signals are queried in a preset logic state table.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the steps of the demand response device interface detection method as described in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the demand response device interface detection method as claimed in claim 8 are executed.

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