Power semiconductor test circuit, method, device, equipment, medium and product

Abstract

The invention relates to the technical field of test circuits of power semiconductors, in particular to a test circuit, method, device, equipment, medium and product of a power semiconductor, the circuit comprises a direct current power supply and devices to be tested, and the devices to be tested comprise a first device to be tested and a second device to be tested; the first end of the first to-be-tested device is connected to the positive electrode of the DC power supply, and the second end of the first to-be-tested device is connected to the first end of the second to-be-tested device; the second end of the second to-be-tested device is connected to the cathode of the direct-current power supply; the switching loss of the power semiconductor device can be accurately measured.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor testing, and in particular to a power semiconductor testing circuit, method, device, equipment, medium and product. Background Art

[0002] The data sheets of power semiconductor devices provide the turn-on energy and turn-off energy of the devices, and these values ​​are obtained based on tests of specific electrical parameters. However, in actual applications, due to differences in application scenarios and specific design requirements, it is difficult for the switching voltage / current, drive resistance, and drive voltage of power semiconductor devices to be consistent with those in the data sheet. If the turn-on energy and turn-off energy in the data sheet are continued to be used for calculation, the calculated switching loss results will have a large deviation, and in severe cases, the power semiconductor device will burn out. There is a technical problem in this field that the switching loss of power semiconductor devices is difficult to measure. Summary of the invention

[0003] The present invention provides a power semiconductor test circuit, method, device, equipment, medium and product, which solve the technical problem that the switching loss of power semiconductor devices is difficult to measure.

[0004] In a first aspect, the present invention provides a test circuit for a power semiconductor, the circuit comprising: a DC power supply and a device under test, wherein the device under test comprises a first device under test and a second device under test; the first end of the first device under test is connected to the positive pole of the DC power supply, the second end of the first device under test is connected to the first end of the second device under test; the second end of the second device under test is connected to the negative pole of the DC power supply.

[0005] In some embodiments, the circuit further includes: an input capacitor, an inductor, and an output capacitor; the input capacitor is connected in parallel to both ends of a DC power supply; the first end of the inductor is connected to the second end of the first device under test, and the second end of the inductor is connected to the first end of the output capacitor; the second end of the output capacitor is connected to the negative pole of the DC power supply.

[0006] In some embodiments, the device under test includes a metal oxide semiconductor field effect transistor and an insulated gate bipolar transistor.

[0007] In a second aspect, the present invention provides a method for testing a power semiconductor based on a power semiconductor test circuit according to any one of the above aspects, the method comprising: obtaining an equivalent series resistance of the test circuit; driving the test circuit based on a preset drive signal so that the test circuit operates in a preset mode; collecting electrical parameters of the test circuit in the preset mode; and calculating the turn-off loss of the device under test based on the electrical parameters.

[0008] In some embodiments, the step of driving the test circuit based on a preset drive signal includes: turning on the first device under test of the test circuit at time zero based on the preset drive signal, and turning off the first device under test of the test circuit at time two based on the preset drive signal; turning on the second device under test of the test circuit at time two based on the preset drive signal, and turning off the second device under test of the test circuit at time four based on the preset drive signal.

[0009] In some embodiments, the step of calculating the turn-off loss of the device under test based on electrical parameters includes: calculating the input power of the test circuit based on the current and voltage of a DC power supply in the test circuit; calculating the line loss of the test circuit and the conduction loss of the device under test based on the current of the line in the test circuit, the current of the device under test, and the equivalent series resistance of the test circuit; subtracting the input power from the line loss of the test circuit and the conduction loss of the device under test to obtain the turn-off loss of the device under test.

[0010] In a third aspect, the present invention provides a power semiconductor testing device having a power semiconductor test circuit based on any one of the above aspects, the device comprising: an acquisition module for acquiring the equivalent series resistance of the test circuit; a driving module for driving the test circuit based on a preset driving signal so that the test circuit operates in a preset mode; an acquisition module for acquiring electrical parameters of the test circuit in the preset mode; and a calculation module for calculating the turn-off loss of the device under test based on the electrical parameters.

[0011] In a fourth aspect, the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any of the power semiconductor testing methods described above.

[0012] In a fifth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the power semiconductor testing methods described in the above aspects.

[0013] In a sixth aspect, the present invention provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of any of the power semiconductor testing methods described in the above aspects.

[0014] The present invention provides a test circuit, method, device, equipment, medium and product for power semiconductors, wherein the circuit includes: a DC power supply and a device under test, wherein the device under test includes a first device under test and a second device under test; the first end of the first device under test is connected to the positive pole of the DC power supply, and the second end of the first device under test is connected to the first end of the second device under test; the second end of the second device under test is connected to the negative pole of the DC power supply; and the switching loss of the power semiconductor device can be accurately measured. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be described in more detail below based on embodiments and with reference to the accompanying drawings:

[0016] Figure 1 is a schematic diagram of a power semiconductor test circuit provided by an embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of a power semiconductor testing method provided by an embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of a power semiconductor testing device provided by an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of a test waveform of a power semiconductor provided by an embodiment of the present invention;

[0020] Figure 5 is a schematic diagram of a circuit with ESR provided by an embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of a test circuit for a first mode of a power semiconductor provided by an embodiment of the present invention;

[0022] Figure 7 is a schematic diagram of a test circuit for a second mode of a power semiconductor provided by an embodiment of the present invention;

[0023] Figure 8 is a schematic diagram of a test circuit of a third mode of a power semiconductor provided by an embodiment of the present invention;

[0024] Fig. 9 is a schematic diagram of a fourth mode test circuit of a power semiconductor provided by an embodiment of the present invention;

[0025] Fig.10 is a schematic diagram of an IGBT test circuit provided by an embodiment of the present invention;

[0026] Fig.11 It is a schematic diagram of the IGBT test working waveform provided by an embodiment of the present invention.

[0027] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, and to fully understand and implement how the present invention applies technical means to solve technical problems and achieve the corresponding technical effects, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only an embodiment of a part of the present invention, not all of the embodiments. The embodiments of the present invention and the various features in the embodiments can be combined with each other without conflict, and the technical schemes formed are all within the scope of protection of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0031] The data sheets of power semiconductor devices provide the turn-on energy and turn-off energy of the devices, and these values ​​are obtained based on tests of specific electrical parameters. However, in actual applications, due to differences in application scenarios and specific design requirements, it is difficult for the switching voltage / current, drive resistance, and drive voltage of power semiconductor devices to be consistent with those in the data sheet. If the turn-on energy and turn-off energy in the data sheet are continued to be used for calculation, the calculated switching loss results will have a large deviation, and in severe cases, the power semiconductor device will burn out. There is a technical problem in this field that the switching loss of power semiconductor devices is difficult to measure.

[0032] Hereinafter, the technical solution of the present application will be described in conjunction with specific embodiments.

[0033] Embodiment 1

[0034] Figure 1 FIG. 1 is a schematic diagram of a test circuit for a power semiconductor provided by an embodiment of the present invention. Figure 1 As shown, in the technical solution of this embodiment, a test circuit for a power semiconductor is provided, the circuit comprising: a DC power supply and a device under test, wherein the device under test comprises a first device under test and a second device under test; the first end of the first device under test is connected to the positive pole of the DC power supply, and the second end of the first device under test is connected to the first end of the second device under test; the second end of the second device under test is connected to the negative pole of the DC power supply.

[0035] The technical problem to be solved by this embodiment is how to construct a test circuit body for measuring the switching loss of a power semiconductor device? In the field of switching loss testing of power semiconductor devices, a suitable test circuit body is required to carry out subsequent testing work, which is the basis for accurately measuring the switching loss.

[0036] The technical solution of this embodiment constructs the test circuit body by setting a DC power supply and a device under test. The device under test is divided into a first device under test and a second device under test, the first end of the first device under test is connected to the positive pole of the DC power supply, the second end is connected to the first end of the second device under test, and the second end of the second device under test is connected to the negative pole of the DC power supply. This connection method provides the basic framework for the subsequent construction of the complete test circuit and the switching loss test of the power semiconductor device, and is the core part of the entire test circuit.

[0037] The technical solution of this embodiment, first of all, clarifies the basic architecture of the test circuit body, so that there is a basic framework when other components are added to improve the test circuit later. For example, in a complete test circuit, the input capacitor, inductor, output capacitor and other components added later can be connected based on this main architecture. This main architecture makes it possible to accurately measure the switching loss of power semiconductor devices in the future. Without this basic circuit body, a complete test environment cannot be established. Moreover, this simple main architecture can be easily applied to different types of power semiconductor devices, whether it is a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor, etc., can be tested based on this main body. This is conducive to the construction of a unified infrastructure in the test scenarios of various power semiconductor devices, improves test efficiency, and provides a stable foundation for the subsequent application of more complex test circuit designs and test methods.

[0038] Embodiment 2

[0039] Based on the above embodiment, the circuit also includes: an input capacitor, an inductor, and an output capacitor; the input capacitor is connected in parallel to the two ends of the DC power supply; the first end of the inductor is connected to the second end of the first device under test, and the second end of the inductor is connected to the first end of the output capacitor; the second end of the output capacitor is connected to the negative electrode of the DC power supply.

[0040] The technical problem to be solved by this embodiment is how to construct a complete test circuit for measuring the switching loss of a power semiconductor device? After the main body of the test circuit is constructed, other components need to be added to form a complete test circuit to achieve a comprehensive test of the switching loss of the power semiconductor device.

[0041] The technical solution of this embodiment is to construct a complete test circuit by adding input capacitors, inductors, and output capacitors on the basis of the above embodiments. The input capacitor is connected in parallel to both ends of the DC power supply to stabilize the input voltage; the first end of the inductor is connected to the second end of the first device under test, and the second end is connected to the first end of the output capacitor; the second end of the output capacitor is connected to the negative electrode of the DC power supply to stabilize the output voltage. The addition of these components improves the test circuit, enabling it to better simulate actual working conditions and provide a complete circuit environment for accurately measuring the switching loss of power semiconductor devices.

[0042] The technical solution of this embodiment forms a complete test circuit by adding these components. The input capacitor can filter out high-frequency noise in the power supply and ensure the stability of the input voltage, which is crucial for accurately measuring the switching loss of power semiconductor devices. Because unstable input voltage may cause deviations in the measurement results. The inductor plays a role of filtering and energy storage in the circuit. It can be adjusted according to the required device shutdown current value, so that the test circuit can better simulate the current changes under actual working conditions. The output capacitor can stabilize the output voltage and ensure the stability of the test circuit output. In this way, the complete test circuit can more accurately simulate the working environment of the power semiconductor device in actual application, so as to more accurately measure its switching loss. Moreover, this complete test circuit structure has good versatility and can adapt to the testing requirements of different power semiconductor devices. By reasonably adjusting the parameters of each component, switching loss tests can be performed on various types of power semiconductor devices.

[0043] Embodiment 3

[0044] Based on the above embodiment, the device under test includes a metal oxide semiconductor field effect transistor and an insulated gate bipolar transistor.

[0045] The technical problem to be solved by this embodiment is how to construct a test circuit for measuring the switching loss of various power semiconductor devices? In the test of power semiconductor devices, a test circuit that can be applied to various types of devices is required to meet the needs of different application scenarios.

[0046] The technical solution of this embodiment is to construct a test circuit that can measure the switching loss of various power semiconductor devices by limiting the devices to be tested to include metal oxide semiconductor field effect transistors and insulated gate bipolar transistors. Based on the test circuit constructed above, both the main circuit structure and the various added components are compatible with these two common power semiconductor devices, thereby realizing the measurement of the switching loss of different types of devices.

[0047] The technical solution of this embodiment, first of all, the versatility of the test circuit is improved. In the application of power semiconductor devices, metal oxide semiconductor field effect transistors and insulated gate bipolar transistors are two very common devices, and the circuit that can perform switching loss tests on them has a high practical value. This test circuit can adapt to different device characteristics. For example, metal oxide semiconductor field effect transistors have bidirectional conductivity, and insulated gate bipolar transistors have unidirectional conductivity. The test circuit can perform corresponding tests according to their characteristics. Through such a test circuit, different types of power semiconductor devices can be compared and evaluated under the same test environment, providing a more accurate reference for the selection and application of devices.

[0048] Embodiment 4

[0049] Figure 2 Schematic diagram of a power semiconductor testing method provided by an embodiment of the present invention. Figure 2 As shown, in the technical solution of this embodiment, a method for testing a power semiconductor based on a power semiconductor test circuit of any one of the above embodiments is provided, the method comprising: obtaining an equivalent series resistance of the test circuit; driving the test circuit based on a preset drive signal so that the test circuit operates in a preset mode; collecting electrical parameters of the test circuit in the preset mode; and calculating the turn-off loss of the device under test based on the electrical parameters.

[0050] The technical problem to be solved by this embodiment is how to test the turn-off loss of power semiconductors based on the test circuit of the above embodiment? After having the test circuit, a complete set of test methods is needed to effectively test the turn-off loss of power semiconductors.

[0051] The technical solution of this embodiment is to obtain the equivalent series resistance of the test circuit, drive the test circuit based on a preset drive signal, make the test circuit work in a preset mode, collect the electrical parameters of the test circuit in the preset mode, and finally calculate the turn-off loss of the device under test based on these electrical parameters. Among them, the acquisition of the equivalent series resistance can be tested by the test equipment or queried from the technical specification provided by the supplier. The preset drive signal is used to control the opening and closing of the device in the test circuit. The preset mode is a different working state divided according to the working characteristics of the test circuit. The electrical parameters include voltage, current and other parameters. These parameters are the key to calculating the turn-off loss.

[0052] The technical solution of this embodiment can systematically test the turn-off loss of power semiconductor devices through this test method. Obtaining the equivalent series resistance can take into account the influence of the resistance characteristics of each component in the circuit on the turn-off loss, so that the test result is more accurate. Based on the preset drive signal and the preset mode of operation, the working process of the test circuit can be accurately controlled to simulate the switching process of the power semiconductor device under actual working conditions. The acquisition of electrical parameters provides a data basis for subsequent calculations. Through the reasonable calculation of these parameters, the turn-off loss of the device to be tested can be accurately obtained. This test method has high accuracy and can effectively avoid the turn-off loss calculation deviation caused by improper test methods. In practical applications, this helps to more accurately evaluate the performance of power semiconductor devices in specific application scenarios, and provide accurate data support for subsequent work such as thermal design, thereby avoiding over-design or under-design problems caused by inaccurate turn-off loss evaluation, and improving the reliability and economy of the entire power semiconductor device application system.

[0053] Embodiment 5

[0054] On the basis of the above embodiment, the step of driving the test circuit based on a preset drive signal includes: turning on the first device under test of the test circuit at time zero based on the preset drive signal, and turning off the first device under test of the test circuit at a second time based on the preset drive signal; turning on the second device under test of the test circuit at the second time based on the preset drive signal, and turning off the second device under test of the test circuit at a fourth time based on the preset drive signal.

[0055] The technical problem to be solved by this embodiment is how to drive the test circuit? In the switching loss test process of the power semiconductor device, it is necessary to clarify how to turn on and off the devices in the test circuit according to a specific time sequence to ensure the accuracy of the test.

[0056] The technical solution of this embodiment drives the test circuit by turning on the first device under test of the test circuit at time zero and turning off the first device under test at time two based on a preset driving signal; turning on the second device under test of the test circuit at time two and turning off the second device under test at time four. These specific time points control the turning on and off sequence of the two devices under test, so that the test circuit can work according to the predetermined working mode.

[0057] The technical solution of this embodiment, this precise driving method can ensure that the working state of the test circuit meets expectations and simulate the switching process of the power semiconductor device under actual working conditions. By turning on and off the device at a specific time, the current and voltage in the circuit can change according to the designed waveform, thereby providing an accurate working environment for subsequent electrical parameter collection and turn-off loss calculation.

[0058] Embodiment 6

[0059] On the basis of the above-mentioned embodiment, the step of calculating the turn-off loss of the device under test based on electrical parameters includes: calculating the input power of the test circuit based on the current and voltage of the DC power supply in the test circuit; calculating the line loss of the test circuit and the conduction loss of the device under test based on the current of the line in the test circuit, the current of the device under test and the equivalent series resistance of the test circuit; subtracting the input power from the line loss of the test circuit and the conduction loss of the device under test to obtain the turn-off loss of the device under test.

[0060] The technical problem to be solved by this embodiment is how to obtain the turn-off loss of the device under test? After driving the test circuit and collecting electrical parameters, an effective calculation method is needed to obtain the accurate turn-off loss of the device under test.

[0061] The technical solution of this embodiment calculates the input power of the test circuit based on the current and voltage of the DC power supply in the test circuit, calculates the line loss of the test circuit and the conduction loss of the device under test based on the current of the line in the test circuit, the current of the device under test and the equivalent series resistance of the test circuit, and then subtracts the input power from the line loss and the conduction loss to obtain the turn-off loss of the device under test. This embodiment takes into account various power loss factors in the circuit and accurately calculates the turn-off loss through the law of conservation of energy.

[0062] The calculation method of the technical solution of this embodiment can accurately obtain the turn-off loss of the device to be tested. By considering factors such as input power, line loss and conduction loss, the errors that may be caused by simple calculations are avoided. In practical applications, this accurate turn-off loss calculation result is crucial for the performance evaluation and application of power semiconductor devices. For example, in the design of power electronic converters, accurate turn-off losses can help engineers better perform thermal design and avoid over-design or under-design due to inaccurate turn-off loss assessment. This helps to improve the efficiency and reliability of the converter and extend the service life of power semiconductor devices. Moreover, this calculation method has high accuracy and strong versatility. It is suitable for different types of power semiconductor devices and different test circuit structures, and provides reliable technical support for the testing and application of power semiconductor devices.

[0063] Embodiment 7

[0064] Figure 3 is a schematic diagram of the structure of a power semiconductor testing device provided in an embodiment of the present application, such as Figure 3 As shown, in the technical solution of this embodiment, a power semiconductor testing device based on the power semiconductor testing circuit of any one of the above embodiments is provided, and the device includes: an acquisition module, used to obtain the equivalent series resistance of the test circuit; a driving module, used to drive the test circuit based on a preset driving signal, so that the test circuit works in a preset mode; an acquisition module, used to acquire the electrical parameters of the test circuit in the preset mode; and a calculation module, used to calculate the turn-off loss of the device under test based on the electrical parameters.

[0065] The technical problem to be solved by this embodiment is how to construct a test circuit body for measuring the switching loss of a power semiconductor device? In the field of switching loss testing of power semiconductor devices, a suitable test circuit body is required to carry out subsequent testing work, which is the basis for accurately measuring the switching loss.

[0066] The technical solution of this embodiment constructs the test circuit body by setting a DC power supply and a device under test. The device under test is divided into a first device under test and a second device under test, the first end of the first device under test is connected to the positive pole of the DC power supply, the second end is connected to the first end of the second device under test, and the second end of the second device under test is connected to the negative pole of the DC power supply. This connection method provides the basic framework for the subsequent construction of the complete test circuit and the switching loss test of the power semiconductor device, and is the core part of the entire test circuit.

[0067] The technical solution of this embodiment, first of all, clarifies the basic architecture of the test circuit body, so that there is a basic framework when other components are added to improve the test circuit later. For example, in a complete test circuit, the input capacitor, inductor, output capacitor and other components added later can be connected based on this main architecture. This main architecture makes it possible to accurately measure the switching loss of power semiconductor devices in the future. Without this basic circuit body, a complete test environment cannot be established. Moreover, this simple main architecture can be easily applied to different types of power semiconductor devices, whether it is a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor, etc., can be tested based on this main body. This is conducive to the construction of a unified infrastructure in the test scenarios of various power semiconductor devices, improves test efficiency, and provides a stable foundation for the subsequent application of more complex test circuit designs and test methods.

[0068] Embodiment 8

[0069] In the technical solution of this embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory, and the processor executes the computer program to implement the steps of any power semiconductor test method in the above-mentioned embodiments. In the technical solution of this embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by the processor, the steps of the power semiconductor test method in any of the above-mentioned embodiments are implemented. In the technical solution of this embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by the processor, the steps of the power semiconductor test method in any of the above-mentioned embodiments are implemented.

[0070] The processor may include, but is not limited to, for example, one or more processors or microprocessors. Each processor may be an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor or other electronic components to implement the method in the above embodiment. The computer readable storage medium may be implemented by any type of volatile or non-volatile storage device or a combination thereof, and the computer readable storage medium may include, but is not limited to, for example, a random access memory (RAM), a read-only memory (ROM), a flash memory, an EPROM memory, an EEPROM memory, a register, a computer storage medium (such as a hard disk, a floppy disk, a solid state drive, a removable disk, a CDROM, a DVDROM, a Blu-ray disc, etc.).

[0071] The computer-readable storage medium may also store at least one computer executable program / instruction, which may be, for example, a computer-readable instruction. The computer-readable storage medium includes, but is not limited to, for example, a volatile memory and / or a non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The computer-readable storage medium may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. For example, a non-transitory computer-readable storage medium may be connected to a computing device such as a computer, and then, when the computing device runs the computer-readable instructions stored on the computer-readable storage medium, the various methods described above may be performed.

[0072] In addition, the computer device may also include (but not limited to) a data bus, an input / output (I / O) bus, a display, and an input / output device (e.g., a keyboard, a mouse, a speaker, etc.). The processor may communicate with external devices via the I / O bus via a wired or wireless network. In one embodiment, the at least one computer executable instruction may also be compiled into or constitute a software product / computer program product, wherein one or more computer executable instructions are executed by the processor to perform the various functions and / or steps of the method in the embodiments described in the present technology.

[0073] Embodiment 9

[0074] Based on the above embodiments, this embodiment provides an application example.

[0075] This application example involves current conversion technology, specifically a power semiconductor device. As the basis of power electronics technology, power semiconductor devices are used in power electronic converters to achieve power conversion and control by controlling the opening and closing of semiconductor devices. With the development of power electronics technology and the promotion and application of third-generation wide-device semiconductor devices, the operating frequency of power semiconductor devices is getting higher and higher, the switching loss generated in the switching process is also higher, and the heating of the device is more serious. How to accurately evaluate the switching loss of power semiconductor devices has become a difficulty and hot spot in the current design of power electronic converters.

[0076] At present, the data sheets of power semiconductor devices such as MOS tubes and IGBTs all provide the device's turn-on energy E. on and the turn-off energy E off , these values ​​are based on specific switch voltage / current, drive resistance (on / off) and drive voltage (on / off) tests. However, in actual applications, due to differences in application scenarios and specific design requirements, it is difficult for the device's switch voltage / current, drive resistance and drive voltage to be consistent with the data sheet. For example, if we continue to use the E on and E off The calculated switching loss result will have a large deviation, which may cause the device to burn out in serious cases. The present invention proposes a method and circuit for testing the turn-off loss of power semiconductor devices. The switch voltage / current, drive resistance and drive voltage of the semiconductor device in the test circuit are configured according to specific design requirements to ensure that the switch conditions of the test are completely consistent with the actual switch conditions, thereby realizing the turn-off energy E generated during the device turn-off process. off Take precise measurements.

[0077] The actual off voltage / current, driving resistance and driving voltage of semiconductor devices are inconsistent with the device manual, resulting in the off energy E off The results of loss calculations vary greatly. This application example proposes a turn-off loss test method and circuit that fully simulates the actual switching conditions of the device. It can accurately measure the E of the device under actual conditions. off , thereby improving the accuracy of device turn-off energy calculation.

[0078] The test circuit of the present invention adopts a half-bridge structure, the circuit topology is a Buck circuit, the circuit output is open, the driving signals of Q1 and Q2 are complementary (ignoring the dead zone effect), and the duty cycle is 0.5, thereby the output voltage V o =V in / 2. See the circuit diagram Figure 1, the description of each device is shown in Table 1.

[0079] Table 1 Device Description

[0080]

[0081] The working waveform of the test circuit is shown in Figure 4 , the description and settings of each physical quantity are as follows:

[0082] ——V gs The preset driving signal of the device under test Q1 / Q2, whose driving voltage amplitude and driving resistance are consistent with the specific design parameters. The driving signals of Q1 and Q2 are complementary (ignoring the dead zone effect), with a duty ratio of D=50%.

[0083] ——V ds is the DS terminal voltage of Q1 / Q2, the switch is turned on, V ds Approximately equal to 0; the switch is turned off, V ds =V in . Where V in The DC input power supply voltage is adjusted to ensure that it is consistent with the specific designed working voltage.

[0084] ——i Q1 and i Q2 are the collector currents of Q1 and Q2 respectively.

[0085] ——i L is the inductor current.

[0086] ——T s is the switching period of the test circuit, f s is the switching frequency of the test circuit, f s =1 / T s When setting up specifically, minimize the influence of high-frequency skin effect and proximity effect of ESR (equivalent series resistance) in the circuit.

[0087] ——I m is the maximum inductor current, that is, the turn-off current of the semiconductor device. By changing the switching period T s and filter inductance L, ensuring that the value is consistent with the shutdown current of the specific design.

[0088] Depend on Figure 4It can be seen that at the turn-on time of the first device under test Q1 and the second device under test Q2 (the first device under test Q1 is turned on at the zeroth time t0 and the fifth time t5, and the second device under test Q2 is turned on at the second time t2), the device current is freewheeled by the body diode, so zero voltage turn-on can be achieved, that is, the turn-on loss of the two is zero; the turn-off of the first device under test Q1 and the second device under test Q2 are both hard turn-offs (the first device under test Q1 is turned off at the second time t2, and the second device under test Q2 is turned off at the fourth time t4), and the turn-off current is both within the maximum inductor current I m , that is, the turn-off losses of the two are equal and not zero; the turn-on time of the first device under test Q1 and the second device under test Q2 is equal, and the current passing through is equal to half of the inductor current, that is, the conduction losses of the two are equal.

[0089] In order to accurately evaluate the switching loss of the switching device, the equivalent series resistance ESR of the circuit connection parameters and the equivalent ESR of the device itself are evaluated. Figure 5 , the description of each resistor is as follows:

[0090] ——R DS : The on-resistance of the first device under test Q1 and the second device under test Q2, obtained by querying the technical specifications provided by the supplier;

[0091] ——R Cin : The ESR of the input capacitor can be obtained by testing with test equipment or by querying the technical specifications provided by the supplier;

[0092] ——R Co : The ESR of the output capacitor can be obtained by testing with test equipment or by querying the technical specifications provided by the supplier;

[0093] ——R L : The ESR of the filter inductor L can be obtained by testing with test equipment or by querying the technical specifications provided by the supplier;

[0094] ——R pcb1 : ESR of the cable connecting the input capacitor to the first device under test Q1 / the second device under test Q2. The connection form can be a printed circuit board (PCB), a composite busbar and a cable, which can be obtained by testing with a test equipment;

[0095] ——R pcb2 : ESR of the cable connecting the output capacitor to the first device under test Q1 / the second device under test Q2. The connection form can be PCB, composite busbar and cable, which can be obtained by testing with test equipment.

[0096] Combination Figure 4 The control waveform and Figure 5The circuit model is used to analyze the working mode of the circuit. According to the working characteristics of the circuit, a single cycle (t1~t5) can be divided into four working modes from the first mode to the fourth mode, such as Figure 6 , Figure 7 , Figure 8 , Fig. 9 As shown, where t0 = 0, t1 = T s / 4, t2 = T s / 2, t3 = 3T s / 4, t4 = T s , t5=5T s / 4.

[0097] First mode (t1-t2): The first device under test Q1 is turned on, the second device under test Q2 is turned off, and the voltage applied to the inductor is V in -V o =V in / 2, the inductor current increases linearly, and reaches its maximum value at time t2. The current loop is shown in Figure 6 .

[0098] Second mode (t2-t3): The first device under test Q1 is turned off at time t2. At this time, the turn-off current of the first device under test Q1 is I m , there is a turn-off loss P off ; The current is commutated from the first device under test Q1 to the body diode of the second device under test Q2. At this time, the second device under test Q2 is turned on. The second device under test Q2 is turned on at zero voltage, and the turn-on loss P on is zero. At this time, the voltage applied to the inductor is -V o =-V in / 2, the inductor current is I m Linearly decreases, the inductor current decreases to zero at t3, and the current loop is shown in Figure 7 .

[0099] The third mode (t3-t4): the first device under test Q1 is turned off, the second device under test Q2 is turned on, and the inductor is at -V in / 2, after the inductor current passes through zero, it continues to decrease. At t4, the inductor current reaches the maximum value in the reverse direction. The current loop is shown in Figure 8 .

[0100] The fourth mode (t4-t5): the second device under test Q2 is turned off at time t4. At this time, the turn-off current of the second device under test Q2 is I m , there is a turn-off loss, and it is related to the turn-off loss P of the first device under test Q1 in the second mode. offCompletely consistent; the current is commutated from the second device under test Q2 to the body diode of the first device under test Q1. At this time, the first device under test Q1 is turned on, and the first device under test Q1 is turned on with zero voltage, and the turn-on loss is zero. At this time, the voltage applied to the inductor is V in -V o =V in / 2, the inductor current is given by -I m The linear line increases, and the inductor current reaches zero at t5. The current loop is shown in Fig. 9 .

[0101] Measurement and design of device current.

[0102] The current value of each device can be obtained by measuring instruments or by calculation. Based on the above analysis, combined with the waveform, and according to D = 0.5, the current of each device is calculated as follows:

[0103] ——The effective current values ​​of the switch tube / first device under test Q1 and the second device under test Q2 are equal, and the calculation is as follows:

[0104]

[0105] ——Filter inductor L and output capacitor C o The effective value of the current is equal and is calculated as follows:

[0106]

[0107] ——Input capacitance C in The effective value of the current is calculated as follows:

[0108]

[0109] I in It is the output current of the power supply, which can be read directly from the power supply device or directly tested by current testing equipment.

[0110] Measurement and calculation of device losses.

[0111] The loss of each component can be measured by a measuring instrument or calculated. Based on the above analysis, combined with the waveform, and according to D = 0.5, the loss of each component is calculated as follows:

[0112] ——Input capacitor loss:

[0113] P Cin =i Cin_RMS 2 *R Cin (Formula 4)

[0114] ——Output capacitor loss:

[0115] PCo =i Co_RMS 2 *R Co (Formula 5)

[0116] ——The filter inductor is an air-core inductor with zero core loss. The only loss is the winding loss, which can be obtained through magnetic simulation software or by calculation:

[0117] P L =i L_RMS 2 *R L (Formula 6)

[0118] ——The connection loss is mainly caused by the connection cable (PCB, composite busbar or cable), mainly R pcb1 and R pcb2 The resulting loss is calculated as follows:

[0119] P pcb =i Q_RMS 2 *R pcb1 +i L_RMS 2 *R pcb2 (Formula 7)

[0120] ——The loss generated by semiconductor devices, consisting of conduction loss P con and P off Two parts, and the P con and P off Same. off It is difficult to calculate accurately the loss required. The loss P generated by a single device Q The calculation is as follows:

[0121] P Q =P con +P off (Formula 8)

[0122] P con =i Q_RMS 2 *R DS (Formula 9)

[0123] ——The power generated by the power supply P in It can be read directly from the power supply unit or calculated as follows:

[0124] P in =V in *I in (Formula 10)

[0125] According to the law of conservation of energy, the losses generated by all devices and connecting cables in the circuit are provided by the power supply, and we can get:

[0126] P in =P Cin +P Co +P L +P pcb +2P Q (Formula 11)

[0127] Substituting equation 8 into equation 11, we get:

[0128] P in =P Cin +P Co +P L +P pcb +2(P con +P off ) (Formula 12)

[0129] Then P off We can get:

[0130]

[0131] The calculation formula for the turn-off loss of semiconductor devices is:

[0132] P off =E off *f s (Formula 14)

[0133] Combining equations 13 and 14, we can finally obtain the turn-off energy of the semiconductor device:

[0134]

[0135] Equation 15 is the semiconductor device turn-off energy E off The final calculation formula is based on the shutdown energy of the specific application of the device. Its driving voltage amplitude, driving resistance size, voltage and current at the time of opening and closing, and other test conditions can be consistent with the actual working conditions to ensure the accuracy of the calculation. In subsequent applications, there is no need to query the device data sheet and directly use the E off By multiplying it by the actual switching frequency, the turn-off loss of the device can be accurately calculated, thus avoiding over-design and under-design in subsequent thermal design.

[0136] When the semiconductor device is replaced by MOS tubes and IGBTs, the basic test methods and principles are still applicable. The main changes are as follows:

[0137] 1) Test circuit changes: IGBT-based test circuits such as Fig.10 As shown, the first device under test Q1 / the second device under test Q2 is an IGBT, and VD1 / VD2 is a freewheeling diode.

[0138] 2) The working waveform has changed: IGBT passes Figure 4 The forward current of the first device under test Q1 / the second device under test Q2, the diode passes Figure 4 The reverse current of the first device under test Q1 / the second device under test Q2 in the example is changed as follows: Fig.11 shown.

[0139] 3) In working mode Figure 7 and Fig. 9 The circuit path has changed: the MOS tube has bidirectional conductivity, so after the current is reversed, it can still continue to pass through the MOS tube; IGBT is unidirectional conductivity, after the current direction is reversed, the current is continued through its anti-parallel diode.

[0140] 4) The current calculation has changed: the IGBT and anti-parallel diode circuit together constitute the current of the original MOS tube.

[0141] ——The calculation of IGBT current effective value is shown in formula 16, and the instantaneous value is set to i Q (t), can be found in reference Fig.11 The calculation is performed and will not be repeated here.

[0142]

[0143] ——The effective value of the diode current is calculated as shown in formula 17, and the instantaneous value is set to i VD (t), can be found in reference Fig.11 The calculation is performed and will not be repeated here.

[0144]

[0145] 5) The loss calculation of semiconductor switching devices has changed: the original single MOS tube loss has been changed to IGBT loss and diode loss.

[0146] ——The loss generated by IGBT is composed of conduction loss P con and P off Two parts, and the P con and P off Same. off It is difficult to calculate accurately the required loss. The loss P generated by a single IGBT Q The calculation is as follows, and P con The instantaneous value of the conduction current i Q (t) and its corresponding on-state voltage drop V ce The product is shown in formula 19, where the time from t1 to t2 is T s / 4.

[0147] P Q =P con +Poff (Formula 18)

[0148]

[0149] ——Diode loss: Reverse recovery loss is zero, only conduction loss. VD The instantaneous value of the conduction current i VD (t) and its corresponding on-state voltage drop V F The product is obtained, where the time from t0 to t1 is T s / 4.

[0150]

[0151] Finally, the turn-off energy of IGBT is obtained:

[0152]

[0153] This method can accurately test the turn-off energy E of semiconductor devices under specific applications. off , thereby enabling accurate calculation of the turn-off losses of semiconductor devices and avoiding over- or under-design of heat due to inaccurate loss assessment.

[0154] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0155] It should be noted that, in the present invention, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element limited by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0156] Although the embodiments disclosed in the present invention are as above, the above contents are only embodiments adopted for facilitating the understanding of the present invention and are not intended to limit the present invention. Any technician in the technical field to which the present invention belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A power semiconductor test circuit, characterized in that: The circuit comprises: a direct current power supply and a device under test, wherein the device under test comprises a first device under test and a second device under test; A first terminal of the first device under test is connected to the positive electrode of a DC power supply, and a second terminal of the first device under test is connected to a first terminal of a second device under test; The second terminal of the second device under test is connected to the negative electrode of the DC power supply.

2. The power semiconductor test circuit according to claim 1, characterized in that: The circuit also includes: an input capacitor, an inductor, and an output capacitor; The input capacitor is connected in parallel to both ends of the DC power supply; The first end of the inductor is connected to the second end of the first device under test, and the second end of the inductor is connected to the first end of the output capacitor; The second end of the output capacitor is connected to the negative electrode of the DC power supply.

3. The power semiconductor test circuit according to claim 1 or 2, characterized in that: The device under test includes a metal oxide semiconductor field effect transistor and an insulated gate bipolar transistor.

4. A method for testing a power semiconductor based on the power semiconductor test circuit according to any one of claims 1 to 3, characterized in that: The method comprises: Obtaining an equivalent series resistance of the test circuit; Driving the test circuit based on a preset drive signal so that the test circuit operates in a preset mode; Collecting electrical parameters of the test circuit in a preset mode; The turn-off loss of the device under test is calculated based on the electrical parameters.

5. The power semiconductor testing method according to claim 4, characterized in that: The step of driving the test circuit based on a preset driving signal includes: Turning on the first device under test of the test circuit at time zero based on a preset driving signal, and turning off the first device under test of the test circuit at time two based on the preset driving signal; The second device under test of the test circuit is turned on at a second moment based on the preset driving signal, and the second device under test of the test circuit is turned off at a fourth moment based on the preset driving signal.

6. The power semiconductor testing method according to claim 4, characterized in that: The step of calculating the turn-off loss of the device under test based on the electrical parameters comprises: calculating the input power of the test circuit based on the current and voltage of the DC power supply in the test circuit; Calculating the line loss of the test circuit and the conduction loss of the device under test based on the current of the line in the test circuit, the current of the device under test, and the equivalent series resistance of the test circuit; The input power is subtracted from the line loss of the test circuit and the conduction loss of the device under test to obtain the turn-off loss of the device under test.

7. A power semiconductor testing device based on the power semiconductor testing circuit according to any one of claims 1 to 3, characterized in that: The device comprises: An acquisition module, used to acquire the equivalent series resistance of the test circuit; A driving module, used for driving the test circuit based on a preset driving signal, so that the test circuit works in a preset mode; An acquisition module, used for acquiring electrical parameters of the test circuit in a preset mode; A calculation module is used to calculate the turn-off loss of the device under test based on the electrical parameters.

8. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the power semiconductor testing method according to any one of claims 4 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the power semiconductor testing method according to any one of claims 4 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the power semiconductor testing method according to any one of claims 4 to 6 are implemented.

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