Chip edge integrity detection circuit and chip

Abstract

This application relates to the field of chip design technology, disclosing a chip edge integrity detection circuit and a chip. The chip edge integrity detection circuit includes a metal loop, a detection circuit, and a protection circuit. The metal loop is disposed around the perimeter of the chip. The detection circuit is connected to the metal loop and configured to detect impedance changes in the metal loop to determine the integrity of the chip edge. The protection circuit is connected to both the metal loop and the detection circuit and configured to protect the circuit. In this application, the detection circuit provides an objective damage assessment method. By setting the parameters of the detection circuit, the impedance changes of the metal loop can be quantitatively analyzed, thereby quantitatively analyzing the degree of chip damage. This improves the accuracy of judging the degree of chip damage, reduces the situation where a minor chip damage is mistaken for complete chip failure, and improves chip yield.

Description

Technical Field

[0001] The present application relates to the technical field of chip design, for example, to a chip edge integrity detection circuit and a chip. Background Art

[0002] At present, with the continuous advancement of chip manufacturing technology, the requirements for chip edge integrity are getting higher and higher, and more accurate and reliable detection methods are needed to improve the yield of chips. For some chips working under harsh conditions, secondary damage may occur to the chips, and it is often difficult to re-detect the packaged chips. Therefore, a technology is needed to accurately detect and evaluate chip edge damage during chip manufacturing and use.

[0003] In the related art, a chip edge integrity detection system is disclosed. By adding a conductive loop around the chip, the loop port can be connected to a detection circuit. The detection circuit is used to determine whether the loop is disconnected to judge whether the chip is damaged.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The detection system in the related technology can only determine whether the chip is damaged, but cannot determine the degree of damage. It is easy to determine that the entire chip is damaged due to slight damage, thereby reducing the chip yield.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The disclosed embodiments provide a chip edge integrity detection circuit and a chip to accurately determine the damage degree of the chip.

[0009] In some embodiments, the chip edge integrity detection circuit includes: a metal loop, a detection circuit and a protection circuit; the metal loop is arranged around the chip; the detection circuit is connected to the metal loop and is configured to detect the impedance change of the metal loop to determine the integrity of the chip edge; the protection circuit is connected to the metal loop and the detection circuit and is configured to protect the circuit.

[0010] Optionally, the metal loop includes a plurality of topological structures connected in pairs in sequence; the plurality of topological structures are arranged around the chip in a circle, or are arranged at the chamfer and edge center of the chip.

[0011] Optionally, the topological structure includes, from bottom to top, a resistor layer and a top metal; or, the topological structure includes, from bottom to top, a resistor layer, an intermediate metal and a top metal, wherein the intermediate metal is one layer or multiple layers; the resistor layer, the intermediate metal and the top metal are separated from each other by oxide; the resistor layer, the intermediate metal and the top metal are interconnected through holes penetrating the oxide; the resistor layers of adjacent topological structures are interconnected; and the top metals of adjacent topological structures are interconnected.

[0012] Optionally, the detection circuit is connected to the metal loop through a first detection point and a second detection point; the first detection point is connected to an intermediate metal or resistance layer in a first topological structure; the second detection point is connected to an intermediate metal or resistance layer in a second topological structure; the first topological structure is the first topological structure in the metal loop, and the second topological structure is the last topological structure in the metal loop.

[0013] Optionally, the detection circuit also includes: a voltage detection circuit, a current compensation circuit, a voltage comparison circuit and a control circuit; the current compensation circuit is connected to the voltage detection circuit and the control circuit, and the current compensation circuit is configured to output a compensation current of the voltage detection circuit under the control of the control circuit; the voltage detection circuit is connected to the metal loop through a first detection point and a second detection point, and is connected to the current compensation circuit, and the voltage detection circuit is configured to output a detection voltage according to an impedance change of the metal loop, and output a reference voltage according to the compensation current; the voltage comparison circuit is connected to the voltage detection circuit, and is configured to compare the detection voltage with the reference voltage.

[0014] Optionally, the voltage detection circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first PMOS tube, a second PMOS tube, a third PMOS tube and a current source; the source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are all connected to the power supply; the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube and the drain of the third PMOS tube are all connected to the input end of the current source; the output end of the current source is grounded; the drain of the first PMOS tube is connected to the first end of the first resistor; the second end of the first resistor is connected to the first detection point; the first end of the second resistor is connected to the second detection point; the second end of the second resistor is grounded; the drain of the second PMOS tube is connected to the first end of the third resistor; the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is grounded; wherein the detection voltage is output at the first end of the first resistor; the first end of the third resistor is connected to the current compensation circuit, and the reference voltage is output at the first end of the third resistor according to the compensation current.

[0015] Optionally, the current compensation circuit includes: one or more current compensation branches; the current compensation branch includes a compensation PMOS tube and a switch; the source of the compensation PMOS tube is connected to the power supply, the gate is connected to the input end of the current source, and the drain is connected to the first end of the switch; the second end of the switch is connected to the first end of the third resistor; the control signal of the switch is generated by the control circuit; according to the control signal generated by the control circuit, the switch of each current compensation branch can be controlled separately to control the size of the compensation current.

[0016] Optionally, the resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the third resistor and the resistance value of the fourth resistor are the same.

[0017] Optionally, the protection circuit includes: a first capacitor, a second capacitor, a first NMOS tube, a second NMOS tube, a fifth resistor and a sixth resistor; the first end of the first capacitor is connected to the first detection point; the first end of the second capacitor is connected to the second detection point; the second end of the first capacitor and the second end of the second capacitor are both grounded; the drain of the first NMOS tube is connected to the first detection point; the drain of the second NMOS tube is connected to the second detection point; the gate of the first NMOS tube is connected to the first end of the fifth resistor; the gate of the second NMOS tube is connected to the first end of the sixth resistor; the source of the first NMOS tube, the source of the second NMOS tube, the second end of the fifth resistor, and the second end of the sixth resistor are all grounded.

[0018] In some embodiments, a chip includes: a chip edge integrity detection circuit as described above.

[0019] The chip edge integrity detection circuit and chip provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The chip edge integrity detection circuit provided by the embodiment of the present disclosure includes a metal loop, a detection circuit and a protection circuit. Since the metal loop is arranged around the chip, it can fully cover the edge of the chip. When the chip is damaged, the metal loop will also be damaged, thereby changing the impedance of the metal loop. The impedance change of the metal loop can be detected by the detection circuit, thereby accurately detecting the damage to the edge of the chip. The detection circuit provides an objective damage assessment method. By setting the parameters of the detection circuit, the impedance change of the metal loop can be quantitatively analyzed, thereby quantitatively analyzing the degree of damage to the chip, thereby improving the accuracy of the judgment of the degree of damage to the chip, reducing the situation where the entire chip is judged to be damaged due to slight damage to the chip, and improving the chip yield. In addition, the chip edge integrity detection circuit also includes a protection circuit, which can protect the metal loop and the detection circuit to prevent damage caused by external interference or internal abnormalities, thereby enhancing the stability and safety of the circuit.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a circuit block diagram of a chip edge integrity detection circuit provided by an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of a metal loop in a chip edge integrity detection circuit provided by an embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of setting a metal loop around a chip provided by an embodiment of the present disclosure;

[0026] Figure 4 It is a schematic diagram of damage to a metal loop in a chip edge integrity detection circuit provided by an embodiment of the present disclosure;

[0027] Figure 5 It is a schematic diagram of another metal loop damage in a chip edge integrity detection circuit provided by an embodiment of the present disclosure;

[0028] Figure 6 is a circuit block diagram of a detection circuit in a chip edge integrity detection circuit provided by an embodiment of the present disclosure;

[0029] Figure 7 is a circuit diagram of a detection circuit in a chip edge integrity detection circuit provided by an embodiment of the present disclosure;

[0030] Figure 8 It is a circuit diagram of a protection circuit in a chip edge integrity detection circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0032] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0033] Unless otherwise stated, the term "plurality" means two or more.

[0034] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0035] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0036] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0037] Combination Figure 1 As shown, an embodiment of the present disclosure provides a chip edge integrity detection circuit, including: a metal loop 10 , a detection circuit 20 and a protection circuit 30 .

[0038] The metal loop 10 is disposed around the chip 40. The detection circuit 20 is connected to the metal loop 10 and is configured to detect impedance changes of the metal loop 10 to determine the integrity of the edge of the chip 40. The protection circuit 30 is connected to both the metal loop 10 and the detection circuit 20 and is configured to protect the circuit.

[0039] In the disclosed embodiment, since the metal loop 10 is arranged around the chip 40, it can fully cover the edge of the chip 40. When the chip 40 is damaged, the metal loop 10 will also be damaged, thereby changing the impedance of the metal loop 10. The impedance change of the metal loop 10 can be detected by the detection circuit 20, so as to accurately detect the damage at the edge of the chip 40. The detection circuit 20 provides an objective damage assessment method. By setting the parameters of the detection circuit 20, the impedance change of the metal loop 10 can be quantitatively analyzed, thereby quantitatively analyzing the degree of damage to the chip 40, thereby improving the accuracy of the judgment of the degree of damage to the chip 40, reducing the situation where the entire chip 40 is judged to be damaged due to slight damage to the chip 40, and improving the chip yield. In addition, the chip edge integrity detection circuit also includes a protection circuit 30, which can protect the metal loop 10 and the detection circuit 20 to prevent damage caused by external interference or internal abnormalities, thereby enhancing the stability and safety of the circuit.

[0040] Optionally, combined Figure 2 As shown, the metal loop 10 includes a plurality of topological structures 11 connected in pairs in sequence; the plurality of topological structures 11 are arranged around the chip 40 in a circle, or are arranged at the chamfer and edge center of the chip 40 .

[0041] In this embodiment, the metal loop 10 is arranged into a plurality of topological structures 11 connected in pairs in sequence, and the plurality of topological structures 11 are arranged around the chip 40 in a circle, thereby ensuring full coverage of the edge of the chip 40, so that the detection circuit 20 can detect any part of the edge of the chip 40, thereby improving the comprehensiveness of the detection. Figure 3 As shown, according to the position indicated by the arrow in the figure, the topological structure 11 can also be selectively set at the chamfer and edge center of the chip 40 to detect the vulnerable parts in the chip 40. Due to the continuity and two-to-two connection characteristics of the topological structure 11, damage to any topological structure 11 may cause the impedance of the metal loop 10 to change, which can be captured by the detection circuit 20, thereby improving the sensitivity of damage detection.

[0042] Optionally, combined Figure 2 As shown, the topological structure 11 includes, from the bottom to the top, a resistance layer 12 and a top metal 14; or, the topological structure 11 includes, from the bottom to the top, a resistance layer 12, an intermediate metal 13 and a top metal 14, wherein the intermediate metal 13 is one layer or multiple layers; the resistance layer 12, the intermediate metal 13 and the top metal 14 are separated from each other by oxide; the resistance layer 12, the intermediate metal 13 and the top metal 14 are interconnected through holes penetrating the oxide; the resistance layers 12 of adjacent topological structures 11 are interconnected; and the top metals 14 of adjacent topological structures 11 are interconnected.

[0043] In this embodiment, the topological structure 11 realizes a hierarchical structure from the resistance layer 12 to the intermediate metal 13 and then to the top metal 14. The resistance layer 12, the intermediate metal 13 and the top metal 14 are separated by oxides to achieve electrical isolation, and the holes penetrating the oxides realize electrical connection between different layers, which not only ensures the isolation between the layers, but also realizes the necessary electrical connection. The resistance layer 12 and the top metal 14 of the adjacent topological structures 11 are connected to each other, ensuring the continuity and integrity of the metal loop 10. In addition, in order to simplify the structure of the metal loop 10, the intermediate metal 13 layer can also be discarded.

[0044] Optionally, the resistance layer 12 includes a Poly (Polysilicon) resistor.

[0045] In this embodiment, the Poly resistor is a resistor made of polysilicon material, which has good high temperature resistance and stable resistance characteristics. By adjusting the doping concentration and size of polysilicon, the resistance of the Poly resistor can be accurately controlled. When the edge of the chip 40 is damaged, it will affect the integrity of the metal loop 10 connected to the Poly resistor, thereby changing the impedance of the loop. The impedance change of the Poly resistor can be captured by the detection circuit 20 for judging damage.

[0046] Optionally, the resistance layer 12, the middle metal 13 and the top metal 14 are connected to each other through CT / VIA (Contact Via) holes penetrating the oxide.

[0047] Optionally, the detection circuit 20 is connected to the metal loop 10 through a first detection point A and a second detection point B; the first detection point A is connected to the intermediate metal 13 or the resistance layer 12 in the first topological structure; the second detection point B is connected to the intermediate metal 13 or the resistance layer 12 in the second topological structure; the first topological structure is the first topological structure in the metal loop 10, and the second topological structure is the last topological structure in the metal loop 10.

[0048] In this embodiment, the entire metal loop 10 is connected between the first detection point A and the second detection point B. In the case that the chip 40 is damaged, the metal loop 10 will also be damaged, thereby changing the impedance of the metal loop 10. The detection circuit 20 can detect the impedance change of the metal loop 10 through the first detection point A and the second detection point B, thereby determining the damage of the metal loop 10 and the chip 40. In addition, the first detection point A and the second detection point B can also be connected to the intermediate metal 13 or the resistance layer 12 in any topological structure 11 in the metal loop 10, so as to detect the impedance change of a specific part of the metal loop 10, and then locate the damage of the metal loop 10. Under normal circumstances, the first detection point A and the second detection point B are connected through holes and the top metal 14, the resistance layer 12 is short-circuited, and the current in the metal loop flows as follows. Figure 2 As shown by the arrow in , the metal loop 10 is in low impedance. When the chip 40 is damaged, the impedance of the metal loop 10 will change.

[0049] Combination Figure 4 As shown, when the edge of the chip 40 encounters lateral damage, the top metal 14 in the topological structure 11 is damaged and disconnected. At this time, the short circuit of the top metal 14 to the resistor layer 12 fails, and the current path passes through the hole and the resistor layer 12. The current in the metal loop flows as shown in FIG. Figure 4 As shown by the arrow in , the impedance between the first detection point A and the second detection point B becomes larger. If the damage is serious, until the resistance layer 12 is also disconnected, the metal loop 10 is completely disconnected at this time, and the impedance is nearly infinite.

[0050] Combination Figure 5 As shown, when the edge of the chip 40 encounters delamination damage, the top metal 14 in the topological structure 11 is damaged and disconnected from the hole. At this time, the short circuit of the top metal 14 to the resistance layer 12 also fails, which will also cause the impedance between the first detection point A and the second detection point B to increase. Considering that delamination damage is usually a large-area damage, a large-area top metal 14 will fail, and the loop impedance will increase significantly.

[0051] Optionally, combined Figure 6 As shown, the detection circuit 20 also includes: a voltage detection circuit 21, a current compensation circuit 22, a voltage comparison circuit 23 and a control circuit 24. The current compensation circuit 22 is connected to the voltage detection circuit 21 and the control circuit 24. The current compensation circuit 22 is configured to output the compensation current of the voltage detection circuit 21 under the control of the control circuit 24. The voltage detection circuit 21 is connected to the metal loop 10 through the first detection point A and the second detection point B, and is connected to the current compensation circuit 22. The voltage detection circuit 21 is configured to output the detection voltage Vdet according to the impedance change of the metal loop 10, and output the reference voltage Vapr according to the compensation current. The voltage comparison circuit 23 is connected to the voltage detection circuit 21, and is configured to compare the detection voltage Vdet with the reference voltage Vapr.

[0052] In this embodiment, the voltage detection circuit 21 can detect the impedance change of the metal loop 10 through the first detection point A and the second detection point B, and convert these changes into voltage signals, and output the detection voltage Vdet. The current compensation circuit 22 works under the control of the control circuit 24, and outputs a compensation current to adjust the reference voltage Vapr of the voltage detection circuit 21. The reference voltage Vapr can be changed by the compensation current, and then the damage of the chip 40 can be determined according to the comparison result between the detection voltage Vdet output by the voltage comparison circuit 23 and the reference voltage Vapr.

[0053] Optionally, combined Figure 7 As shown, the voltage detection circuit 21 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3 and a current source I.

[0054] The source of the first PMOS tube M1, the source of the second PMOS tube M2, and the source of the third PMOS tube M3 are all connected to the power supply; the gate of the first PMOS tube M1, the gate of the second PMOS tube M2, the gate of the third PMOS tube M3, and the drain of the third PMOS tube M3 are all connected to the input end of the current source I; the output end of the current source I is grounded; the drain of the first PMOS tube M1 is connected to the first end of the first resistor R1; the second end of the first resistor R1 is connected to the first detection point A; the first end of the second resistor R2 is connected to the second detection point B; the second end of the second resistor R2 is grounded; the drain of the second PMOS tube M2 is connected to the first end of the third resistor R3; the second end of the third resistor R3 is connected to the first end of the fourth resistor R4; the second end of the fourth resistor R4 is grounded. Wherein, the detection voltage Vdet is output at the first end of the first resistor R1; the first end of the third resistor R3 is connected to the current compensation circuit 22, and the reference voltage Vapr is output at the first end of the third resistor R3 according to the compensation current.

[0055] Optionally, the resistance value of the first resistor R1 , the resistance value of the second resistor R2 , the resistance value of the third resistor R3 and the resistance value of the fourth resistor R4 are the same.

[0056] In this embodiment, the current source I provides a reference current for the detection circuit 20, and the third PMOS tube M3 mirrors the reference current to the drain of the first PMOS tube M1 and the second PMOS tube M2 through a current mirror. The current at the first PMOS tube M1 flows into the metal loop 10 after passing through the first resistor R1 and the first detection point A, and then passes through the second detection point B and the second resistor R2. At this time, the detection voltage Vdet is output at the first end of the first resistor R1. The current at the second PMOS tube M2 and the compensation current pass through the third resistor R3 and the fourth resistor R4, and the reference voltage Vapr is output at the first end of the third resistor R3. When the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are all R0, the detection voltage Vdet = Ibias × (2R0 + Rt), and the reference voltage Vapr = (Ibias + Isw) × 2R0. Wherein, Ibias is the reference current, Rt is the metal loop resistance, and Isw is the compensation current.

[0057] Taking the case of Vdet<Vapr as an example, it can be obtained that Ibias×Rt<Isw×2R0. When the metal loop 10 is detected, Rt will increase when the metal loop 10 is damaged, and the more serious the damage, the larger Rt. Therefore, Isw is adjusted by the control circuit 24 to gradually increase Isw until the comparison result output by the voltage comparison circuit 23 is Vapr just greater than Vdet. According to the Isw at this time, the damage of the circuit can be analyzed. In order to reduce the situation where the entire chip 40 is judged to be damaged due to slight damage to the chip 40, a suitable compensation current threshold can be set. Only when the obtained Isw is greater than the compensation current threshold, the chip 40 is judged to be seriously damaged.

[0058] Optionally, combined Figure 7 As shown, the current compensation circuit 22 includes: one or more current compensation branches 221; the current compensation branch 221 includes compensation PMOS tubes (Ms1, Ms2, Ms3, Ms4) and switches (SW1, SW2, SW3, SW4).

[0059] The source of the compensation PMOS tube is connected to the power supply, the gate is connected to the input end of the current source I, and the drain is connected to the first end of the switch; the second end of the switch is connected to the first end of the third resistor R3; the control signal of the switch is generated by the control circuit 24. According to the control signal generated by the control circuit 24, the switch of each current compensation branch 221 can be controlled respectively to control the size of the compensation current.

[0060] In this embodiment, the current compensation circuit 22 includes one or more current compensation branches 221. By adjusting the switch of each current compensation branch 221, the size of the compensation current can be controlled. Take four current compensation branches 221 as an example, wherein the ratio of the current flowing through the first compensation PMOS tube, the second compensation PMOS tube, the third compensation PMOS tube and the fourth compensation PMOS tube is 1:2:4:8. Since the metal loop 10 is a plurality of topological structures 11 connected in sequence, assuming that the resistance of the resistance layer 12 of a single topological structure 11 is Rpo, the current flowing through the first compensation PMOS tube is I0, if at this time Ibias×Rpo<I0×2R0. The number of damages in the metal loop 10 can be estimated by controlling the switch. By controlling the switch, the size of the compensation current can be made N×I0, 1≤N≤15. If the metal loop resistance Rt satisfies Ibias×Rt<N×I0×2R0, it can be considered that Rt=N×Rpo, that is, there are N damage points in the metal loop 10.

[0061] Optionally, combined Figure 7As shown, the voltage comparison circuit 23 includes an error amplifier EA. The error amplifier EA has a negative input terminal connected to the detection voltage Vdet, a positive input terminal connected to the reference voltage Vapr, and an output terminal that outputs a comparison result between the detection voltage Vdet and the reference voltage Vapr.

[0062] Optionally, combined Figure 7 As shown, the control circuit 24 includes a config module. The config module includes a plurality of control signal output terminals for controlling switches in the current compensation circuit 22.

[0063] Optionally, combined Figure 8 As shown, the protection circuit 30 includes: a first capacitor C1, a second capacitor C2, a first NMOS transistor G1, a second NMOS transistor G2, a fifth resistor R5 and a sixth resistor R6.

[0064] The first end of the first capacitor C1 is connected to the first detection point A; the first end of the second capacitor C2 is connected to the second detection point B; the second end of the first capacitor C1 and the second end of the second capacitor C2 are both grounded; the drain of the first NMOS tube G1 is connected to the first detection point A; the drain of the second NMOS tube G2 is connected to the second detection point B; the gate of the first NMOS tube G1 is connected to the first end of the fifth resistor R5; the gate of the second NMOS tube G2 is connected to the first end of the sixth resistor R6; the source of the first NMOS tube G1, the source of the second NMOS tube G2, the second end of the fifth resistor R5, and the second end of the sixth resistor R6 are all grounded.

[0065] In this embodiment, since the metal loop 10 needs to surround the chip 40 for one circle, the circumference will reach several mm or even cm, therefore, it is necessary to set a protection circuit 30 for the detection circuit 20 and the metal loop 10. Among them, the first NMOS transistor G1 and the second NMOS transistor G2 are used to eliminate the antenna effect brought by the metal loop 10 or the induced electromotive force generated by the loop inductance in the magnetic field. The first capacitor C1 and the second capacitor C2 are used to stabilize the potential of the metal loop 10, avoid its rapid jitter, and improve the stability of the detection result of the detection circuit 20.

[0066] Optionally, the first NMOS transistor G1 and the second NMOS transistor G2 include: an antenna diode or a GGNMOS (Gate-Grounded NMOS).

[0067] An embodiment of the present disclosure provides a chip, comprising the chip edge integrity detection circuit as described above.

[0068] In the disclosed embodiment, when the chip is subjected to an edge integrity test, a chip integrating the above-mentioned chip edge integrity detection circuit is designed and prepared, and the chip port is configured to enable the edge integrity detection. In the config module, according to the tolerance for chip damage, a suitable compensation current is configured by controlling the switch. Then, a determination is made as to whether the chip damage exceeds the set tolerance based on the signal output by the voltage comparison circuit in the detection circuit. By adjusting the tolerance multiple times and performing repeated tests, the specific damage condition of the chip can be determined, and the number of transverse crack damages of the chip can be determined, or the chip can be determined as delamination damaged or severely damaged.

[0069] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A chip edge integrity detection circuit, characterized in that: include: Metal loops, detection circuits and protection circuits; The metal loop is set around the chip; The detection circuit is connected to the metal loop and is configured to detect impedance changes of the metal loop to determine the integrity of the chip edge; The protection circuit is connected to both the metal loop and the detection circuit and is configured to protect the circuit.

2. The chip edge integrity detection circuit according to claim 1, characterized in that: The metal loop includes a plurality of topological structures connected in pairs in sequence; the plurality of topological structures are arranged around the chip in a circle, or are arranged at the chamfer and edge center of the chip.

3. The chip edge integrity detection circuit according to claim 2, characterized in that: The topological structure includes, from the bottom to the top, a resistor layer and a top metal layer; or, the topological structure includes, from the bottom to the top, a resistor layer, an intermediate metal layer and a top metal layer, wherein the intermediate metal layer is one or more layers; The resistor layer, the middle metal and the top metal are separated by oxide. The resistor layer, the middle metal, and the top metal are interconnected via holes that penetrate the oxide; The resistance layers of adjacent topological structures are interconnected; The top metal layers of adjacent topologies are connected to each other.

4. The chip edge integrity detection circuit according to claim 3, characterized in that: The detection circuit is connected to the metal loop through the first detection point and the second detection point; The first detection point is connected to the middle metal or resistance layer in the first topological structure; The second detection point is connected to the middle metal or resistance layer in the second topological structure; The first topology structure is the first topology structure in the metal loop, and the second topology structure is the last topology structure in the metal loop.

5. The chip edge integrity detection circuit according to claim 4, characterized in that: The detection circuit also includes: a voltage detection circuit, a current compensation circuit, a voltage comparison circuit and a control circuit; The current compensation circuit is connected to the voltage detection circuit and the control circuit, and the current compensation circuit is configured to output a compensation current of the voltage detection circuit under the control of the control circuit; The voltage detection circuit is connected to the metal loop through the first detection point and the second detection point, and is connected to the current compensation circuit, and the voltage detection circuit is configured to output a detection voltage according to an impedance change of the metal loop, and output a reference voltage according to a compensation current; The voltage comparison circuit is connected to the voltage detection circuit and is configured to compare the detection voltage with a reference voltage.

6. The chip edge integrity detection circuit according to claim 5, characterized in that: The voltage detection circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a current source; The source of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube are all connected to the power supply; the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube, and the drain of the third PMOS tube are all connected to the input end of the current source; the output end of the current source is grounded; the drain of the first PMOS tube is connected to the first end of the first resistor; the second end of the first resistor is connected to the first detection point; the first end of the second resistor is connected to the second detection point; the second end of the second resistor is grounded; the drain of the second PMOS tube is connected to the first end of the third resistor; the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is grounded; The detection voltage is output at the first end of the first resistor; the first end of the third resistor is connected to the current compensation circuit, and the reference voltage is output at the first end of the third resistor according to the compensation current.

7. The chip edge integrity detection circuit according to claim 6, characterized in that: The current compensation circuit includes: one or more current compensation branches; the current compensation branches include a compensation PMOS tube and a switch; The source of the compensation PMOS tube is connected to the power supply, the gate is connected to the input end of the current source, and the drain is connected to the first end of the switch; the second end of the switch is connected to the first end of the third resistor; and the control signal of the switch is generated by the control circuit; According to the control signal generated by the control circuit, the switch of each current compensation branch can be controlled respectively to control the size of the compensation current.

8. The chip edge integrity detection circuit according to claim 6, characterized in that: The resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the third resistor and the resistance value of the fourth resistor are the same.

9. The chip edge integrity detection circuit according to any one of claims 4 to 8, characterized in that: The protection circuit includes: a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, a fifth resistor and a sixth resistor; The first end of the first capacitor is connected to the first detection point; the first end of the second capacitor is connected to the second detection point; the second end of the first capacitor and the second end of the second capacitor are both grounded; the drain of the first NMOS tube is connected to the first detection point; the drain of the second NMOS tube is connected to the second detection point; the gate of the first NMOS tube is connected to the first end of the fifth resistor; the gate of the second NMOS tube is connected to the first end of the sixth resistor; the source of the first NMOS tube, the source of the second NMOS tube, the second end of the fifth resistor, and the second end of the sixth resistor are all grounded.

10. A chip, characterized in that: include: A chip edge integrity detection circuit as claimed in any one of claims 1 to 9.

Images