A verification method, system and storage medium for RISC-V DSP chip ATE test module

Abstract

The present invention provides a verification method, system and storage medium for a RISC‑V DSP chip ATE test module. First, first frequency information is obtained according to first waveform information, and the relationship between the first frequency information and second frequency information is verified to set first flag information; secondly, first voltage information is obtained according to the first waveform information, and the relationship between the first voltage information and the second voltage information is verified to set second flag information; then, according to the configuration information of the functional module, the correct use of the output pin is verified to set third flag information; finally, according to the first flag information, the second flag information and the third flag information, the configuration of the core configuration module and the functional module is automatically adjusted for chip ATE retest, or a corresponding inspection instruction is generated and sent to a background, so as to improve the efficiency of module verification.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and more specifically, to a verification method, system and storage medium for a RISC-V DSP chip ATE test module. Background Art

[0002] When the RISC-V DSP chip is tested at the functional level ATE (Automatic Test Equipment), a specific test program is usually required for each function that needs to be tested. The test program is simulated in the RTL simulation environment to generate a test waveform passing through the JTAG / CJTAG pin of the chip. This waveform completes the function of loading the current test program into the RAM of the chip under test and controlling the chip to run this test program.

[0003] By checking the output waveform of the output pin, it is determined whether the ATE test of the chip functional module has passed. When the ATE test of the functional module fails, the tester is usually required to manually check the configuration parameters of each configuration module, which has the problems of low inspection efficiency and high trial and error time cost. Therefore, there is an urgent need for a verification technology for the RISC-V DSP chip ATE test module that automatically checks the core configuration module and the functional module. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a verification method, system and storage medium for a RISC-V DSP chip ATE test module. First, first frequency information is obtained according to first waveform information, and the correct configuration of the first configuration module is verified to set the first flag information; secondly, first voltage information is obtained according to the first waveform information, and the correct configuration of the second configuration module is verified to set the second flag information; then, according to the configuration information of the functional module, the correct use of the output pin is verified to set the third flag information; finally, according to the first flag information, the second flag information and the third flag information, the configuration of the core configuration module and the functional module is automatically adjusted for chip ATE retesting, or a corresponding inspection instruction is generated and sent to the background, so as to improve the efficiency of module verification.

[0005] A first aspect of the present invention provides a verification method for a RISC-V DSP chip ATE test module, the method comprising:

[0006] Acquire first waveform information;

[0007] Obtaining first frequency information according to the first waveform information;

[0008] Determining whether the first frequency information is higher than the set second frequency information;

[0009] If yes, set the first flag information;

[0010] Obtaining first voltage information according to the first waveform information;

[0011] Determining whether the first voltage information is equal to the set second voltage information;

[0012] If not, set the second flag information;

[0013] Acquire first configuration information of the first functional module and second configuration information of the second functional module;

[0014] Determining whether output pins overlap according to the first configuration information and the second configuration information;

[0015] If yes, set the third flag information;

[0016] The chip ATE test is modified according to the first flag information, the second flag information and the third flag information.

[0017] In this solution, the first frequency information is obtained according to the first waveform information, specifically:

[0018] Obtaining a first time series according to the first waveform information;

[0019] Calculate a first time interval sequence according to the first time series;

[0020] Obtaining first time information according to the first time interval sequence;

[0021] First frequency information is obtained according to the first time information.

[0022] This plan also includes:

[0023] Obtaining third configuration information of the first configuration module;

[0024] The second frequency information is obtained according to the third configuration information and the preset input frequency.

[0025] In this solution, the first voltage information is obtained according to the first waveform information, specifically:

[0026] Obtaining first level information and second level information according to the first waveform information;

[0027] Determining whether the first level information is within a preset first level range;

[0028] If so, the first voltage information is obtained according to the difference between the second level information and the first level information.

[0029] This plan also includes:

[0030] Obtaining fourth configuration information of the second configuration module;

[0031] The second voltage information is obtained according to the fourth configuration information and the preset input voltage.

[0032] In this solution, judging whether the output pins overlap according to the first configuration information and the second configuration information is specifically as follows:

[0033] Determine a first output pin of a first functional module according to the first configuration information;

[0034] Determining a second output pin of a second functional module according to the second configuration information;

[0035] Determining whether the first output pin is the same as the second output pin;

[0036] If yes, it means the output pins are overlapping.

[0037] A second aspect of the present invention provides a verification system for a RISC-V DSP chip ATE test module, including a verification method program for a RISC-V DSP chip ATE test module, wherein the verification method program for the RISC-V DSP chip ATE test module implements the following steps when executed by the processor:

[0038] Acquire first waveform information;

[0039] Obtaining first frequency information according to the first waveform information;

[0040] Determining whether the first frequency information is higher than the set second frequency information;

[0041] If yes, set the first flag information;

[0042] Obtaining first voltage information according to the first waveform information;

[0043] Determining whether the first voltage information is equal to the set second voltage information;

[0044] If not, set the second flag information;

[0045] Acquire first configuration information of the first functional module and second configuration information of the second functional module;

[0046] Determining whether output pins overlap according to the first configuration information and the second configuration information;

[0047] If yes, set the third flag information;

[0048] The chip ATE test is modified according to the first flag information, the second flag information and the third flag information.

[0049] In this solution, the first frequency information is obtained according to the first waveform information, specifically:

[0050] Obtaining a first time series according to the first waveform information;

[0051] Calculate a first time interval sequence according to the first time series;

[0052] Obtaining first time information according to the first time interval sequence;

[0053] First frequency information is obtained according to the first time information.

[0054] In this solution, the first voltage information is obtained according to the first waveform information, specifically:

[0055] Obtaining first level information and second level information according to the first waveform information;

[0056] Determining whether the first level information is within a preset first level range;

[0057] If so, the first voltage information is obtained according to the difference between the second level information and the first level information.

[0058] A third aspect of the present invention provides a computer-readable storage medium, which includes a verification method program for a RISC-V DSP chip ATE test module. When the verification method program for the RISC-V DSP chip ATE test module is executed by a processor, the steps of the verification method for the RISC-V DSP chip ATE test module as described in any one of the above items are implemented.

[0059] The present invention provides a verification method, system and storage medium for a RISC-V DSP chip ATE test module. First, first frequency information is obtained according to first waveform information, and the relationship between the first frequency information and second frequency information is verified to set first flag information; secondly, first voltage information is obtained according to the first waveform information, and the relationship between the first voltage information and the second voltage information is verified to set second flag information; then, according to the configuration information of the functional module, the correct use of the output pin is verified to set third flag information; finally, according to the first flag information, the second flag information and the third flag information, the configuration of the core configuration module and the functional module is automatically adjusted for chip ATE retest, or a corresponding inspection instruction is generated and sent to a background, so as to improve the efficiency of module verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope.

[0061] Figure 1 A flow chart of a verification method for a RISC-V DSP chip ATE test module of the present invention is shown;

[0062] Figure 2 A flowchart for confirming first frequency information provided by this embodiment is shown;

[0063] Figure 3 A flowchart for confirming first voltage information provided by this embodiment is shown;

[0064] Figure 4 A block diagram of a verification system for a RISC-V DSP chip ATE test module of the present invention is shown. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present invention have the same meanings as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present invention are clearly defined in this way.

[0067] The words "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The steps before or after the method of the embodiment of the present invention are not necessarily carried out in order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or a step or several steps can be removed from these processes.

[0068] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0069] Figure 1 A flow chart of a verification method for a RISC-V DSP chip ATE test module of the present invention is shown.

[0070] like Figure 1 As shown, the first aspect of the present invention discloses a verification method for a RISC-V DSP chip ATE test module, the method comprising:

[0071] S102, obtaining first waveform information;

[0072] S104, obtaining first frequency information according to the first waveform information;

[0073] S106, determining whether the first frequency information is higher than the set second frequency information;

[0074] S108, if yes, set the first flag information;

[0075] S110, obtaining first voltage information according to the first waveform information;

[0076] S112, determining whether the first voltage information is equal to the set second voltage information;

[0077] S114, if not, setting the second flag information;

[0078] S116, obtaining first configuration information of the first functional module and second configuration information of the second functional module;

[0079] S118, judging whether output pins overlap according to the first configuration information and the second configuration information;

[0080] S120, if yes, set the third flag information;

[0081] S122, modifying chip ATE testing according to the first flag information, the second flag information, and the third flag information.

[0082] It should be noted that the first waveform information is the output waveform of the output pin during ATE testing of the chip functional module; the first frequency information is the output waveform frequency obtained by analyzing the first waveform information; the second frequency information is the theoretical waveform frequency obtained by configuring parameters; the first flag information is the flag of the clock module verification status; the first voltage information is the high and low level difference of the output waveform obtained by analyzing the first waveform information; the second voltage information is the theoretical high and low level difference obtained by configuring parameters; the second flag information is the flag of the power supply module verification status; the first functional module is the functional module corresponding to the output waveform; the second functional module is the functional module configured for testing at the same time.

[0083] In this embodiment, when executing the verification of the chip ATE test module, the core configuration module is first verified, such as the clock module, the power supply module, etc.; then the configuration parameters of the functional module are verified, such as the output pins, etc.; when the configuration module or the functional module is verified abnormally, the corresponding flag information is set, and the configuration of the core configuration module and the functional module is automatically adjusted according to the flag information for chip ATE retest, or a corresponding inspection instruction is generated and sent to the background. First, the clock module, that is, the first configuration module, is verified; according to the first waveform information, the first frequency information is obtained by analysis; according to the configuration information of the clock module, the theoretical value of the frequency of the output waveform is calculated; since the theoretical value of the frequency is the minimum time interval of the output waveform, when the first frequency information is higher than the second frequency information, it means that the time interval of the actual output waveform is less than the theoretical minimum value, that is, there is an abnormality; at this time, the first flag information is set to the preset first flag threshold value to indicate that the clock module is abnormal. Secondly, check the power supply module, that is, the second configuration module; according to the first waveform information, analyze and obtain the first voltage information; according to the configuration information of the power supply module, analyze and calculate the theoretical high and low level difference of the output waveform, that is, the second voltage information; when the first voltage information is not equal to the second voltage information, it means that the power supply module has a configuration error or an output abnormality; at this time, the second flag information is set to the preset second flag threshold value to indicate that the power supply module is abnormal. Then, check the functional module, that is, the first functional module; in ATE testing, multiple functional modules are usually configured at the same time, and the output waveforms are collected in sequence according to the preset order. When multiple functional modules share the same output pin, there is a risk of mutual influence; therefore, according to the first configuration information of the first functional module and the second configuration information of the second functional module, the output pin of the first functional module and the output pin of the second functional module are obtained; when the output pins are the same, it means that the functional module may be abnormal; at this time, the third flag information is set to the preset third flag threshold value to indicate that the functional module is abnormal. Finally, according to the module abnormal flag bit, the configuration of the core configuration module and the functional module is automatically adjusted for chip ATE retest, or the corresponding inspection instruction is generated and sent to the background to improve the efficiency of module verification.

[0084] Figure 2 A flow chart for confirming the first frequency information provided by this embodiment is shown.

[0085] According to an embodiment of the present invention, Figure 2 As shown, the first frequency information is obtained according to the first waveform information, specifically:

[0086] S202, obtaining a first time series according to the first waveform information;

[0087] S204, calculating a first time interval sequence according to the first time series;

[0088] S206, obtaining first time information according to the first time interval sequence;

[0089] S208: Obtain first frequency information according to the first time information.

[0090] It should be noted that the first time series is a sequence composed of the time points of each rising edge and falling edge in the output waveform; the first time interval sequence is a sequence composed of the time intervals between adjacent rising edges and falling edges; the first time information is the minimum time interval value in the first time interval sequence. In this embodiment, the shortest time interval between adjacent rising edges and falling edges is found out according to the first waveform information, which is used as the first frequency information. First, the first time series is obtained by recording the time points of the rising edge and falling edge of the first waveform information. Secondly, the difference between the previous time point and the next time point in the first time series is calculated, that is, the time interval between adjacent rising edges and falling edges is calculated to form the first time interval sequence. Then, the minimum value in the first time interval sequence is found to obtain the first time information, which is used to represent the shortest rising edge and falling edge interval in the first waveform information, that is, the fastest switching time. Finally, the first frequency information is obtained according to the first time information.

[0091] According to an embodiment of the present invention, it also includes:

[0092] Obtaining third configuration information of the first configuration module;

[0093] The second frequency information is obtained according to the third configuration information and the preset input frequency.

[0094] It should be noted that the third configuration information is a configuration parameter of the clock module, which is used to determine information such as clock source, frequency division coefficient, etc. First, the clock source frequency and frequency division coefficient are obtained according to the third configuration information; then, the theoretical frequency information of the output waveform is obtained according to the clock source frequency and the frequency division coefficient.

[0095] Figure 3 A flow chart for confirming the first voltage information provided by this embodiment is shown.

[0096] According to an embodiment of the present invention, Figure 3 As shown, the first voltage information is obtained according to the first waveform information, specifically:

[0097] S302, obtaining first level information and second level information according to the first waveform information;

[0098] S304, determining whether the first level information is within a preset first level range;

[0099] S306: If yes, obtain first voltage information according to the difference between the second level information and the first level information.

[0100] It should be noted that the first level information is the voltage value when the output waveform is at a low level; the second level information is the voltage value when the output waveform is at a high level. In this embodiment, the first level information and the second level information are measured according to the first waveform information. When the first level information is within the preset first level range, it means that it is valid as a reference level. At this time, the difference between the second level information and the first level information is used as the first voltage information. When the first level information is not within the preset first level range, it means that its voltage value is too high and cannot be used as a reference voltage. At this time, the first voltage information is set to a preset voltage value.

[0101] According to an embodiment of the present invention, it also includes:

[0102] Obtaining fourth configuration information of the second configuration module;

[0103] The second voltage information is obtained according to the fourth configuration information and the preset input voltage.

[0104] It should be noted that the fourth configuration information is a configuration parameter of the power supply module, which is used to determine information such as the voltage input source and the voltage regulation coefficient. First, the voltage value and the voltage regulation coefficient of the voltage input source are obtained according to the fourth configuration information; then, the theoretical voltage value of the output waveform is obtained according to the voltage value and the voltage regulation coefficient of the voltage input source.

[0105] According to an embodiment of the present invention, judging whether output pins overlap according to the first configuration information and the second configuration information is specifically:

[0106] Determine a first output pin of a first functional module according to the first configuration information;

[0107] Determining a second output pin of a second functional module according to the second configuration information;

[0108] Determining whether the first output pin is the same as the second output pin;

[0109] If yes, it means the output pins are overlapping.

[0110] It should be noted that, first, according to the first configuration information of the first functional module, the first output pin of the first functional module is determined. Then, the second configuration information of all second functional modules is traversed to determine the second output pins of all second functional modules. Finally, it is determined whether the first output pin is the same as the second output pin; if so, it indicates that the output pins overlap; if not, it indicates that the output pins do not overlap.

[0111] It is worth mentioning that it also includes:

[0112] When it is determined that the first flag information is a preset first flag threshold;

[0113] Reading a first configuration parameter;

[0114] Obtaining third frequency information according to the first configuration parameter;

[0115] determining whether the third frequency information is the same as the second frequency information;

[0116] If yes, sending a first inspection instruction to the background according to the first flag information;

[0117] If not, the first configuration module is configured according to the third configuration information for chip ATE retesting.

[0118] It should be noted that, in the present embodiment, the first flag information is a preset first flag threshold, which indicates that the clock module is in an abnormal state. First, read the configuration parameters of the current clock module in the chip, that is, the first configuration parameters. According to the first configuration parameter, the configuration frequency of the output waveform is obtained. Determine whether the theoretical frequency of the output waveform is the same as the configuration frequency of the output waveform; if so, it means that the clock configuration parameters are configured according to the set configuration information, and a first check instruction is generated according to the first flag information and sent to the background, and the cause of the clock abnormality is checked by the background; if not, it means that the configuration parameters of the clock module of the chip are used incorrectly, and the configuration information of the clock module is adjusted according to the third configuration information for retesting of the chip ATE.

[0119] It is worth mentioning that it also includes:

[0120] When it is determined that the second flag information is a preset second flag threshold;

[0121] Reading a second configuration parameter;

[0122] Obtaining third voltage information according to the second configuration parameter;

[0123] determining whether the third voltage information is the same as the second voltage information;

[0124] If yes, send a second inspection instruction to the background according to the second flag information;

[0125] If not, the second configuration module is configured according to the fourth configuration information for chip ATE retesting.

[0126] It should be noted that, in the present embodiment, the second flag information is a preset second flag threshold, which indicates that the power supply module is in an abnormal state. First, read the configuration parameters of the current power supply module in the chip, that is, the second configuration parameters. According to the second configuration parameters, the configuration voltage of the output waveform is obtained. Determine whether the theoretical voltage of the output waveform is the same as the configuration voltage of the output waveform; if so, it means that the power supply configuration parameters are configured according to the set configuration information, and a second inspection instruction is generated according to the second flag information and sent to the background, and the cause of the power supply abnormality is checked through the background; if not, it means that the configuration parameters of the power supply module of the chip are used incorrectly, and the configuration information of the power supply module is adjusted according to the fourth configuration information for retesting of the chip ATE.

[0127] It is worth mentioning that it also includes:

[0128] When the third flag information is determined to be a preset third flag threshold

[0129] Sending a third inspection instruction to the background according to the third flag information;

[0130] Determining a second functional module according to the second output pin;

[0131] The second functional module is removed for chip ATE retest.

[0132] It should be noted that, in this embodiment, the third flag information is a preset third flag threshold, which indicates that the output pin of the functional module is in a reused state. A second inspection instruction is generated according to the third flag information and sent to the background, and the test work of the second functional module is arranged by the background. In addition, the second functional module with the same output pin is found through the output pin, the second functional module is removed from the current round of chip ATE test items, and then the chip ATE is retested.

[0133] Figure 4 A block diagram of a verification system for a RISC-V DSP chip ATE test module of the present invention is shown.

[0134] like Figure 4 As shown, the second aspect of the present invention discloses a verification system 4 for a RISC-V DSP chip ATE test module, comprising a memory 41 and a processor 42, wherein the memory comprises a verification method program for a RISC-V DSP chip ATE test module, and when the verification method program for a RISC-V DSP chip ATE test module is executed by the processor, the following steps are implemented:

[0135] Acquire first waveform information;

[0136] Obtaining first frequency information according to the first waveform information;

[0137] Determining whether the first frequency information is higher than the set second frequency information;

[0138] If yes, set the first flag information;

[0139] Obtaining first voltage information according to the first waveform information;

[0140] Determining whether the first voltage information is equal to the set second voltage information;

[0141] If not, set the second flag information;

[0142] Acquire first configuration information of the first functional module and second configuration information of the second functional module;

[0143] Determining whether output pins overlap according to the first configuration information and the second configuration information;

[0144] If yes, set the third flag information;

[0145] The chip ATE test is modified according to the first flag information, the second flag information and the third flag information.

[0146] It should be noted that the first waveform information is the output waveform of the output pin during ATE testing of the chip functional module; the first frequency information is the output waveform frequency obtained by analyzing the first waveform information; the second frequency information is the theoretical waveform frequency obtained by configuring parameters; the first flag information is the flag of the clock module verification status; the first voltage information is the high and low level difference of the output waveform obtained by analyzing the first waveform information; the second voltage information is the theoretical high and low level difference obtained by configuring parameters; the second flag information is the flag of the power supply module verification status; the first functional module is the functional module corresponding to the output waveform; the second functional module is the functional module configured for testing at the same time.

[0147] In this embodiment, when executing the verification of the chip ATE test module, the core configuration module is first verified, such as the clock module, the power supply module, etc.; then the configuration parameters of the functional module are verified, such as the output pins, etc.; when the configuration module or the functional module is verified abnormally, the corresponding flag information is set, and the configuration of the core configuration module and the functional module is automatically adjusted according to the flag information for chip ATE retest, or a corresponding inspection instruction is generated and sent to the background. First, the clock module, that is, the first configuration module, is verified; according to the first waveform information, the first frequency information is obtained by analysis; according to the configuration information of the clock module, the theoretical value of the frequency of the output waveform is calculated; since the theoretical value of the frequency is the minimum time interval of the output waveform, when the first frequency information is higher than the second frequency information, it means that the time interval of the actual output waveform is less than the theoretical minimum value, that is, there is an abnormality; at this time, the first flag information is set to the preset first flag threshold value to indicate that the clock module is abnormal. Secondly, check the power supply module, that is, the second configuration module; according to the first waveform information, analyze and obtain the first voltage information; according to the configuration information of the power supply module, analyze and calculate the theoretical high and low level difference of the output waveform, that is, the second voltage information; when the first voltage information is not equal to the second voltage information, it means that the power supply module has a configuration error or an output abnormality; at this time, the second flag information is set to the preset second flag threshold value to indicate that the power supply module is abnormal. Then, check the functional module, that is, the first functional module; in ATE testing, multiple functional modules are usually configured at the same time, and the output waveforms are collected in sequence according to the preset order. When multiple functional modules share the same output pin, there is a risk of mutual influence; therefore, according to the first configuration information of the first functional module and the second configuration information of the second functional module, the output pin of the first functional module and the output pin of the second functional module are obtained; when the output pins are the same, it means that the functional module may be abnormal; at this time, the third flag information is set to the preset third flag threshold value to indicate that the functional module is abnormal. Finally, according to the module abnormal flag bit, the configuration of the core configuration module and the functional module is automatically adjusted for chip ATE retest, or the corresponding inspection instruction is generated and sent to the background to improve the efficiency of module verification.

[0148] According to an embodiment of the present invention, obtaining the first frequency information according to the first waveform information is specifically:

[0149] Obtaining a first time series according to the first waveform information;

[0150] Calculate a first time interval sequence according to the first time series;

[0151] Obtaining first time information according to the first time interval sequence;

[0152] First frequency information is obtained according to the first time information.

[0153] It should be noted that the first time series is a sequence composed of the time points of each rising edge and falling edge in the output waveform; the first time interval sequence is a sequence composed of the time intervals between adjacent rising edges and falling edges; the first time information is the minimum time interval value in the first time interval sequence. In this embodiment, the shortest time interval between adjacent rising edges and falling edges is found out according to the first waveform information, which is used as the first frequency information. First, the first time series is obtained by recording the time points of the rising edge and falling edge of the first waveform information. Secondly, the difference between the previous time point and the next time point in the first time series is calculated, that is, the time interval between adjacent rising edges and falling edges is calculated to form the first time interval sequence. Then, the minimum value in the first time interval sequence is found to obtain the first time information, which is used to represent the shortest rising edge and falling edge interval in the first waveform information, that is, the fastest switching time. Finally, the first frequency information is obtained according to the first time information.

[0154] According to an embodiment of the present invention, it also includes:

[0155] Obtaining third configuration information of the first configuration module;

[0156] The second frequency information is obtained according to the third configuration information and the preset input frequency.

[0157] It should be noted that the third configuration information is a configuration parameter of the clock module, which is used to determine information such as clock source, frequency division coefficient, etc. First, the clock source frequency and frequency division coefficient are obtained according to the third configuration information; then, the theoretical frequency information of the output waveform is obtained according to the clock source frequency and the frequency division coefficient.

[0158] According to an embodiment of the present invention, obtaining the first voltage information according to the first waveform information is specifically:

[0159] Obtaining first level information and second level information according to the first waveform information;

[0160] Determining whether the first level information is within a preset first level range;

[0161] If so, the first voltage information is obtained according to the difference between the second level information and the first level information.

[0162] It should be noted that the first level information is the voltage value when the output waveform is at a low level; the second level information is the voltage value when the output waveform is at a high level. In this embodiment, the first level information and the second level information are measured according to the first waveform information. When the first level information is within the preset first level range, it means that it is valid as a reference level. At this time, the difference between the second level information and the first level information is used as the first voltage information. When the first level information is not within the preset first level range, it means that its voltage value is too high and cannot be used as a reference voltage. At this time, the first voltage information is set to a preset voltage value.

[0163] According to an embodiment of the present invention, it also includes:

[0164] Obtaining fourth configuration information of the second configuration module;

[0165] The second voltage information is obtained according to the fourth configuration information and the preset input voltage.

[0166] It should be noted that the fourth configuration information is a configuration parameter of the power supply module, which is used to determine information such as the voltage input source and the voltage regulation coefficient. First, the voltage value and the voltage regulation coefficient of the voltage input source are obtained according to the fourth configuration information; then, the theoretical voltage value of the output waveform is obtained according to the voltage value and the voltage regulation coefficient of the voltage input source.

[0167] According to an embodiment of the present invention, judging whether output pins overlap according to the first configuration information and the second configuration information is specifically:

[0168] Determine a first output pin of a first functional module according to the first configuration information;

[0169] Determining a second output pin of a second functional module according to the second configuration information;

[0170] Determining whether the first output pin is the same as the second output pin;

[0171] If yes, it means the output pins are overlapping.

[0172] It should be noted that, first, according to the first configuration information of the first functional module, the first output pin of the first functional module is determined. Then, the second configuration information of all second functional modules is traversed to determine the second output pins of all second functional modules. Finally, it is determined whether the first output pin is the same as the second output pin; if so, it indicates that the output pins overlap; if not, it indicates that the output pins do not overlap.

[0173] It is worth mentioning that it also includes:

[0174] When it is determined that the first flag information is a preset first flag threshold;

[0175] Reading a first configuration parameter;

[0176] Obtaining third frequency information according to the first configuration parameter;

[0177] determining whether the third frequency information is the same as the second frequency information;

[0178] If yes, sending a first inspection instruction to the background according to the first flag information;

[0179] If not, the first configuration module is configured according to the third configuration information for chip ATE retesting.

[0180] It should be noted that, in the present embodiment, the first flag information is a preset first flag threshold, which indicates that the clock module is in an abnormal state. First, read the configuration parameters of the current clock module in the chip, that is, the first configuration parameters. According to the first configuration parameter, the configuration frequency of the output waveform is obtained. Determine whether the theoretical frequency of the output waveform is the same as the configuration frequency of the output waveform; if so, it means that the clock configuration parameters are configured according to the set configuration information, and a first check instruction is generated according to the first flag information and sent to the background, and the cause of the clock abnormality is checked by the background; if not, it means that the configuration parameters of the clock module of the chip are used incorrectly, and the configuration information of the clock module is adjusted according to the third configuration information for retesting of the chip ATE.

[0181] It is worth mentioning that it also includes:

[0182] When it is determined that the second flag information is a preset second flag threshold;

[0183] Reading a second configuration parameter;

[0184] Obtaining third voltage information according to the second configuration parameter;

[0185] determining whether the third voltage information is the same as the second voltage information;

[0186] If yes, send a second inspection instruction to the background according to the second flag information;

[0187] If not, the second configuration module is configured according to the fourth configuration information for chip ATE retesting.

[0188] It should be noted that, in the present embodiment, the second flag information is a preset second flag threshold, which indicates that the power supply module is in an abnormal state. First, read the configuration parameters of the current power supply module in the chip, that is, the second configuration parameters. According to the second configuration parameters, the configuration voltage of the output waveform is obtained. Determine whether the theoretical voltage of the output waveform is the same as the configuration voltage of the output waveform; if so, it means that the power supply configuration parameters are configured according to the set configuration information, and a second inspection instruction is generated according to the second flag information and sent to the background, and the cause of the power supply abnormality is checked through the background; if not, it means that the configuration parameters of the power supply module of the chip are used incorrectly, and the configuration information of the power supply module is adjusted according to the fourth configuration information for retesting of the chip ATE.

[0189] It is worth mentioning that it also includes:

[0190] When the third flag information is determined to be a preset third flag threshold

[0191] Sending a third inspection instruction to the background according to the third flag information;

[0192] Determining a second functional module according to the second output pin;

[0193] The second functional module is removed for chip ATE retest.

[0194] It should be noted that, in this embodiment, the third flag information is a preset third flag threshold, which indicates that the output pin of the functional module is in a reused state. A second inspection instruction is generated according to the third flag information and sent to the background, and the test work of the second functional module is arranged by the background. In addition, the second functional module with the same output pin is found through the output pin, the second functional module is removed from the current round of chip ATE test items, and then the chip ATE is retested.

[0195] A third aspect of the present invention provides a computer-readable storage medium, which includes a verification method program for a RISC-V DSP chip ATE test module. When the verification method program for the RISC-V DSP chip ATE test module is executed by a processor, the steps of the verification method for the RISC-V DSP chip ATE test module as described in any one of the above items are implemented.

[0196] The present invention provides a verification method, system and storage medium for a RISC-V DSP chip ATE test module. First, first frequency information is obtained according to first waveform information, and the relationship between the first frequency information and second frequency information is verified to set first flag information; secondly, first voltage information is obtained according to the first waveform information, and the relationship between the first voltage information and the second voltage information is verified to set second flag information; then, according to the configuration information of the functional module, the correct use of the output pin is verified to set third flag information; finally, according to the first flag information, the second flag information and the third flag information, the configuration of the core configuration module and the functional module is automatically adjusted for chip ATE retest, or a corresponding inspection instruction is generated and sent to a background, so as to improve the efficiency of module verification.

[0197] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk, etc., which can store program codes.

[0198] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A verification method for a RISC-V DSP chip ATE test module, characterized in that: The method comprises: Acquire first waveform information; Obtaining first frequency information according to the first waveform information; Determining whether the first frequency information is higher than the set second frequency information; If yes, set the first flag information; Obtaining first voltage information according to the first waveform information; Determining whether the first voltage information is equal to the set second voltage information; If not, set the second flag information; Acquire first configuration information of the first functional module and second configuration information of the second functional module; Determining whether output pins overlap according to the first configuration information and the second configuration information; If yes, set the third flag information; The chip ATE test is modified according to the first flag information, the second flag information and the third flag information.

2. A verification method for a RISC-V DSP chip ATE test module according to claim 1, characterized in that: The obtaining of the first frequency information according to the first waveform information is specifically: Obtaining a first time series according to the first waveform information; Calculate a first time interval sequence according to the first time series; Obtaining first time information according to the first time interval sequence; First frequency information is obtained according to the first time information.

3. The verification method of a RISC-V DSP chip ATE test module according to claim 1, characterized in that: Also includes: Obtaining third configuration information of the first configuration module; The second frequency information is obtained according to the third configuration information and the preset input frequency.

4. The verification method of a RISC-V DSP chip ATE test module according to claim 1, characterized in that: The obtaining of the first voltage information according to the first waveform information is specifically: Obtaining first level information and second level information according to the first waveform information; Determining whether the first level information is within a preset first level range; If so, the first voltage information is obtained according to the difference between the second level information and the first level information.

5. The verification method of a RISC-V DSP chip ATE test module according to claim 1, characterized in that: Also includes: Obtaining fourth configuration information of the second configuration module; The second voltage information is obtained according to the fourth configuration information and the preset input voltage.

6. A verification method for a RISC-V DSP chip ATE test module according to claim 1, characterized in that: The determining whether the output pins overlap according to the first configuration information and the second configuration information is specifically: Determine a first output pin of a first functional module according to the first configuration information; Determining a second output pin of a second functional module according to the second configuration information; Determining whether the first output pin is the same as the second output pin; If yes, it means the output pins are overlapping.

7. A calibration system for a RISC-V DSP chip ATE test module, characterized in that: The system includes a memory and a processor, wherein the memory includes a verification method program for a RISC-V DSP chip ATE test module, and when the verification method program for the RISC-V DSP chip ATE test module is executed by the processor, the following steps are implemented: Acquire first waveform information; Obtaining first frequency information according to the first waveform information; Determining whether the first frequency information is higher than the set second frequency information; If yes, set the first flag information; Obtaining first voltage information according to the first waveform information; Determining whether the first voltage information is equal to the set second voltage information; If not, set the second flag information; Acquire first configuration information of the first functional module and second configuration information of the second functional module; Determining whether output pins overlap according to the first configuration information and the second configuration information; If yes, set the third flag information; The chip ATE test is modified according to the first flag information, the second flag information and the third flag information.

8. A calibration system for a RISC-V DSP chip ATE test module according to claim 7, characterized in that: The obtaining of the first frequency information according to the first waveform information is specifically: Obtaining a first time series according to the first waveform information; Calculate a first time interval sequence according to the first time series; Obtaining first time information according to the first time interval sequence; First frequency information is obtained according to the first time information.

9. A calibration system for a RISC-V DSP chip ATE test module according to claim 7, characterized in that: The obtaining of the first voltage information according to the first waveform information is specifically: Obtaining first level information and second level information according to the first waveform information; Determining whether the first level information is within a preset first level range; If so, the first voltage information is obtained according to the difference between the second level information and the first level information.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer-readable storage medium includes a verification method program for a RISC-V DSP chip ATE test module. When the verification method program for the RISC-V DSP chip ATE test module is executed by a processor, the steps of the verification method for the RISC-V DSP chip ATE test module as described in any one of claims 1 to 6 are implemented.

Images