Doppler radar echo signal processing method based on FPGA

Abstract

The invention discloses a Doppler radar echo signal processing method based on an FPGA (Field Programmable Gate Array), which mainly solves the problems of poor speed measurement real-time performance, long lock losing time and poorer reliability of the existing Doppler radar, and the implementation scheme is as follows: when the radar is locked, performing Hilbert transform and frequency mixing on a sampled signal to finish digital down-conversion processing; filtering, extracting and intercepting the Doppler frequency shift signals to form Doppler frequency shift signals and Doppler frequency shift difference signals of adjacent speed measurement periods, and outputting the Doppler frequency shift signals and the Doppler frequency shift difference signals to a DSP (Digital Signal Processor); the DSP performs automatic gain control and tracking threshold judgment according to the input signal; when the radar loses lock, FFT conversion of the sampling signal is added, and the sampling signal frequency is output and transmitted to the DSP for determining the accurate frequency sweeping range and reducing the radar lock losing time. According to the method, the real-time performance of digital signal processing is improved, the lock losing time of the Doppler radar is shortened, the requirements of a new platform for high real-time performance, short lock losing time and high reliability of Doppler radar data can be met, and the method can be used for Doppler radar speed measurement.

Description

Technical Field

[0001] The invention belongs to the field of digital signal processing, and in particular relates to a Doppler radar echo signal processing method, which can be used for Doppler radar speed measurement. Background Art

[0002] With the rapid development of Doppler radar platforms, the real-time requirements for Doppler radar data are becoming higher and higher, and the reliability requirements are becoming more and more stringent. The traditional Doppler radar digital signal processing technology based on DSP (digital signal processor) can no longer adapt to the rapid development of the platform.

[0003] Limited by the development of domestic integrated circuit technology, traditional Doppler radar digital signal processing is mostly based on the DSP platform, with a high signal sampling rate, resulting in a large amount of data to be processed in real time by the DSP, a long processing time, a large output delay, and poor real-time performance. However, with the rapid development of domestic integrated circuit technology, digital signal processing technology based on programmable logic arrays FPGAs has shown its characteristics of good real-time performance and high speed.

[0004] The existing Doppler radar platforms are faster and more maneuverable, and the electromagnetic environment they face is becoming more and more complex, requiring Doppler radars to have a wider speed measurement range, a stronger ability to filter out clutter signals, and the ability to quickly track after signal loss. Traditional DSP-based Doppler radar digital signal processing methods are no longer sufficient in the face of these usage environments.

[0005] Patent document with publication number CN110058221A discloses a Doppler radar low-speed speed measurement method, which adopts hardware changes such as wave absorption, improving antenna isolation, and improving the intermediate frequency filtering curve of the analog signal to improve the low-speed speed measurement signal tracking capability. However, it is easy to lose lock when the external environment changes, such as the junction of land and water or external interference, and when lost, the DSP re-scanning time is too long, resulting in a decrease in the time to output valid data. After the radar loses lock, the radar cannot be quickly and effectively tracked.

[0006] Therefore, under the new situation, there is an urgent need for a Doppler radar digital signal processing method with good real-time performance, high reliability and strong anti-interference ability. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a Doppler echo signal processing method based on FPGA to enhance the real-time performance of radar echo signal processing, improve the radar's ability to suppress interference signals, reduce the radar lock-out time, and improve the reliability of output data.

[0008] The technical idea of ​​the present invention is: based on FPGA integrated circuit technology, the sampled Doppler radar echo signal is processed by digital signal processing using FPGA, which has the characteristics of good real-time performance and fast response, thereby enhancing the real-time performance of radar digital signal processing. According to the maneuvering characteristics of different carrying platforms, by filtering the Doppler frequency shift difference signal between adjacent speed measurement cycles, the interference signal entering in the complex electromagnetic environment is filtered out, the anti-interference ability of the Doppler radar is enhanced, and the reliability of the output data is improved. After the radar loses lock, by adding FFT processing based on FPGA, the rough Doppler frequency shift signal is quickly calculated, the DSP frequency sweep range is reduced when the Doppler signal is lost, and the radar lock time is reduced.

[0009] According to the above ideas, the technical solutions of the present invention include the following:

[0010] Technical solution 1:

[0011] A method for processing echo signals when Doppler radar is locked based on FPGA, characterized by comprising:

[0012] S1) In a speed measurement cycle, when the radar is locked, the intermediate frequency sampling signal of the current speed measurement cycle is Hilbert transformed to output two orthogonal intermediate frequency signals containing Doppler frequency shift, and then the two orthogonal intermediate frequency signals containing Doppler frequency shift are low-pass filtered to retain the two orthogonal Doppler frequency shift signals, and after extraction and truncation, the amplitude of the Doppler frequency shift signal is calculated and transmitted to the DSP;

[0013] S2) DSP calculates the signal energy according to the Doppler frequency shift signal amplitude and performs automatic gain control of the radar intermediate frequency signal;

[0014] S3) In this speed measurement cycle, the frequency control word after calibration of the previous speed measurement cycle is received from the DSP, and the DDS signal generator inside the FPGA is controlled by the frequency control word to generate two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle; the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle are mixed with the intermediate frequency sampling signal of the current speed measurement cycle respectively to form two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signals of two adjacent speed measurement cycles; the two signals are subjected to low-pass filtering, data extraction and data truncation to form two orthogonal Doppler frequency shift difference signals of adjacent speed measurement cycles, which are transmitted to the DSP;

[0015] S4) In this speed measurement cycle, the DSP calculates the frequency of the Doppler frequency shift difference signal according to the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word of the next speed measurement cycle;

[0016] S5) In this speed measurement cycle, according to the Doppler frequency shift change characteristics between adjacent speed measurement cycles when the carrying platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals, the signals after secondary low-pass filtering are extracted and truncated, the amplitude of the main spectrum signal in the band is calculated, and transmitted to the DSP;

[0017] S6) During this speed measurement cycle, DSP uses the amplitude of the main spectrum signal in the band to calculate the main spectrum signal energy and make radar signal tracking threshold determination to ensure stable tracking;

[0018] S7) repeats the above steps S1)-S6) for each speed measurement cycle when the radar is locked, completing the processing of the echo signal when the Doppler radar is locked, wherein steps S1), S3), and S5) are all completed on the FPGA platform.

[0019] Technical solution 2:

[0020] A method for processing echo signals when a Doppler radar loses lock based on FPGA, characterized by comprising:

[0021] (1) When the radar loses lock within a speed measurement cycle, the FFT operation is performed on the intermediate frequency sampling signal within the speed measurement cycle, and the calculation result is transmitted to the DSP to determine the upper and lower limits of the frequency sweep, narrow the frequency sweep range, reduce the frequency sweep time, and enhance the rapid tracking capability of the radar after losing lock;

[0022] (2) During this speed measurement period, the intermediate frequency sampling signal of the radar is Hilbert transformed to output two orthogonal intermediate frequency signals containing Doppler frequency shift, and then the two orthogonal intermediate frequency signals containing Doppler frequency shift are low-pass filtered to retain the two orthogonal Doppler frequency shift signals. After extraction and truncation, the amplitude of the Doppler frequency shift signal is calculated and transmitted to the DSP;

[0023] (3) During this speed measurement cycle, the DSP calculates the signal energy based on the Doppler frequency shift signal amplitude and performs automatic gain control of the radar intermediate frequency signal;

[0024] (4) In this speed measurement cycle, the frequency control word after calibration of the previous speed measurement cycle is received from the DSP, and the DDS signal generator inside the FPGA is controlled by the frequency control word to generate two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle; the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle are then mixed with the intermediate frequency sampling signal of the current speed measurement cycle to form two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signals of two adjacent speed measurement cycles; the two signals are then subjected to low-pass filtering, data extraction and data truncation to form two orthogonal Doppler frequency shift difference signals of two adjacent speed measurement cycles, which are then transmitted to the DSP;

[0025] (5) In this speed measurement cycle, the DSP calculates the frequency of the Doppler frequency shift difference signal based on the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word of the next speed measurement cycle;

[0026] (6) During this speed measurement cycle, according to the Doppler frequency shift change characteristics between adjacent speed measurement cycles when the platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals, and the signals after secondary low-pass filtering are extracted and truncated to calculate the amplitude of the in-band main spectrum signal and transmit it to the DSP;

[0027] (7) During this speed measurement cycle, the DSP uses the amplitude of the main spectrum signal in the band to calculate the main spectrum signal energy and make radar signal tracking threshold determination to ensure stable tracking;

[0028] (8) Repeat the above steps (1) to (7) for each speed measurement cycle when the radar is lost, and complete the processing of the echo signal when the Doppler radar is lost, wherein steps (1), (2), (4), and (6) are all completed on the FPGA platform.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] Firstly, since the present invention completes the down-conversion, low-pass filtering and signal amplitude calculation of the intermediate frequency sampling signal on the FPGA platform, it can meet the requirements of the new platform for strong real-time digital signal processing.

[0031] Secondly, the present invention enhances the radar's adaptability to the motion characteristics of new platforms and complex electromagnetic environments by filtering the Doppler frequency shift difference signals of adjacent speed measurement cycles after digital down-conversion;

[0032] Thirdly, when the radar is unlocked, the present invention introduces an FPGA-based FFT processing method and utilizes the advantages of FPGA parallel processing to calculate the approximate signal frequency range, reduce the DSP sweep range, reduce the radar unlocking time, and enhance the reliability of the radar. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a flowchart of the implementation of Embodiment 1 of the present invention;

[0034] Figure 2 This is a flow chart of implementation of Embodiment 2 of the present invention;

[0035] Figure 3 is an amplitude-frequency response curve diagram of the first low-pass filter fir_1 in an embodiment of the present invention;

[0036] Figure 4 is an amplitude-frequency response curve diagram of the second low-pass filter fir_2 in an embodiment of the present invention;

[0037] Figure 5 is an amplitude-frequency response curve diagram of the third low-pass filter fir_3 in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to the embodiments.

[0039] The radar measures speed periodically, and each speed measurement cycle has the same duration;

[0040] During normal operation of the radar, the radar receives the echo signal, amplifies it through the intermediate frequency, performs AD sampling, and performs digital signal processing on the intermediate frequency sampling signal. The processing result is output to the DSP for calculation and output of speed information. At this time, the radar is locked.

[0041] When the echo information received by the radar is weak, or the Doppler frequency shift difference information between adjacent speed measurement cycles is too large and does not conform to the actual movement characteristics of the carrying platform, the amplitude of the output after digital signal processing will not meet the locking requirements and cause the radar to lose lock.

[0042] The present invention provides different embodiments of the echo signal processing method for the above two situations: radar locked and radar unlocked.

[0043] Embodiment 1: A method for processing Doppler radar echo signals when the radar is normally tracked and locked.

[0044] Reference Figure 1 The implementation steps of this example include the following:

[0045] Step 1: Perform Hilbert transform on the sampled signal, calculate the Doppler frequency shift signal amplitude and output it to DSP.

[0046] The sampling signal is an intermediate frequency analog signal that is converted into an intermediate frequency sampling signal after AD sampling, and its form is:

[0047] s(n)=Asin[2π(f0+f d )Δ t n+ω0],

[0048] Where A is the amplitude of the intermediate frequency sampling signal, f0 is the carrier frequency, f d is the Doppler shift signal frequency, is the sampling time, ω0 is the initial phase; n is the number of sampling points, and its value is a non-negative integer.

[0049] The implementation of this step includes:

[0050] 1.1) In a speed measurement cycle, the intermediate frequency sampling signal s(n) is Hilbert transformed to obtain two orthogonal intermediate frequency signals sI (n) and s Q (n):

[0051] s I (n) = Asin[2π(f0+f d )Δ t n+ω0]cos(2πf0Δ t n)

[0052] s Q (n) = Asin[2π(f0+f d )Δ t n+ω0]sin(2πf0Δ t n)

[0053] Among them, s I (n) is the intermediate frequency signal of channel I, s Q (n) is the Q-channel intermediate frequency signal;

[0054] According to the product-to-difference formula, the above two orthogonal intermediate frequency signals are transformed into the following form:

[0055]

[0056] 1.2) Use matlab to generate filter coefficients, and combine with the filter IP core of FPGA to form the first low-pass filter fir_1. Its amplitude-frequency response is shown in Figure 3 ,from Figure 3 It can be seen that the passband cutoff frequency of the low-pass filter is 8kHz;

[0057] 1.3) Use the low-pass filter fir_1 to low-pass filter the two orthogonal intermediate frequency signals to form two filtered orthogonal Doppler frequency shift signals s If (n) and s Qf (n):

[0058]

[0059] Among them, s If (n) is the Doppler frequency shift signal of path I, s Qf (n) is the Q-path Doppler frequency shift signal;

[0060] 1.4) The two filtered orthogonal Doppler frequency shift signals are decimated by 8 times to form two decimated orthogonal Doppler frequency shift signals as follows:

[0061]

[0062] 1.5) According to s Id (n) and s Qd (n) The two extracted orthogonal Doppler frequency shift signals are used to calculate the signal amplitude A:

[0063]

[0064] 1.6) Steps 1.1)-1.5) are completed on the FPGA platform, and then the signal amplitude A is output to the DSP, the signal energy is calculated on the DSP platform, and automatic gain control of the radar intermediate frequency signal is performed.

[0065] Step 2: low-pass filter the orthogonal Doppler frequency shift difference signal once, and output two orthogonal Doppler frequency shift difference signals to DSP.

[0066] 2.1) The DDS signal generator generates two orthogonal intermediate frequency signals p containing the Doppler frequency shift signal of the previous speed measurement cycle according to the frequency control word sent by the DSP. I (n) and p Q (n):

[0067] p I (n) = cos[2π(f0+f d )Δ t n]

[0068] p Q (n) = sin[2π(f0+f d )Δ t n].

[0069] Among them, p I (n) is the intermediate frequency signal of channel I, p Q (n) is the Q-channel intermediate frequency signal, f0 is the carrier frequency, f d is the Doppler shift signal frequency of the previous speed measurement cycle, is the sampling time, n is the number of sampling points, and its value is a non-negative integer;

[0070] 2.2) Assume that the difference of Doppler frequency shift signal between the current speed measurement cycle and the previous speed measurement cycle is Δ f , the intermediate frequency sampling signal of this speed measurement cycle is changed to: p(n) = Asin[2π(f0+f d +Δ f )Δ t n+ω1];

[0071] 2.3) Mix the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle with the intermediate frequency sampling signal p(n) of the current speed measurement cycle, and then convert them into two orthogonal intermediate frequency signals p containing the Doppler frequency shift difference signals of adjacent speed measurement cycles through the product-sum-difference formula. I1 (n) and p Q1 (n):

[0072]

[0073] Among them, p I1 (n) is the Doppler frequency shift difference signal of path I, p Q1 (n) is the Q-path Doppler frequency shift difference signal, A is the signal amplitude, and ω1 is the initial phase of the intermediate frequency sampling signal in this speed measurement period;

[0074] 2.4) Use matlab to generate filter coefficients, and combine with the filter IP core of FPGA to form the second low-pass filter fir_2. Its amplitude-frequency response is shown in Figure 4 ,from Figure 4 It can be seen that the passband cutoff frequency of the low-pass filter is 15kHz;

[0075] 2.5) Use the low-pass filter fir_2 to perform low-pass filtering on the two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signals to form two filtered orthogonal Doppler frequency shift difference signals p If1 (n) and p Qf1 (n):

[0076]

[0077] Among them, p If1 (n) is the Doppler frequency shift difference signal of path I after the first filtering, p Qf1 (n) is the Q-path Doppler frequency shift difference signal after the first filtering;

[0078] 2.6) The two-way filtered orthogonal Doppler frequency shift difference signal data is decimated and truncated by 8 times to form the two-way extracted orthogonal Doppler frequency shift difference signal difference signal p Id1 (n) and p Qd1 (n):

[0079]

[0080] Among them, p Id1 (n) is the Doppler frequency shift difference signal of path I after the first extraction, p Qd1 (n) is the Q-path Doppler frequency shift difference signal after the first extraction;

[0081] 2.7) The two-way decimated and truncated orthogonal Doppler frequency shift difference signals are respectively output to DSP and subsequent low-pass filter fir_3 for secondary low-pass filtering;

[0082] 2.8) Steps 2.1)-2.7) are completed on the FPGA platform, and then the two extracted and truncated orthogonal Doppler frequency shift difference signals are output to the DSP, and frequency and phase detection are performed on the DSP platform to calculate the frequency of the Doppler frequency shift difference signal for calibrating the frequency control word of the next speed measurement cycle.

[0083] Step 3, for p Id1 (n) and p Qd1 (n) Perform secondary low-pass filtering to narrow the filter bandwidth, filter out possible interference, and output the Doppler frequency shift difference signal amplitude to the DSP.

[0084] 3.1) Generate filter coefficients using matlab and import the FPGA's own IP core FIR filter to form the third low-pass filter fir_3. Its amplitude-frequency response is shown in Figure 5 ,from Figure 5 It can be seen that the passband cutoff frequency of the low-pass filter is 500Hz;

[0085] 3.2) For p Id1 (n) and p Qd1 (n) Whether there is an interference signal in the two signals, two low-pass filtering is performed respectively to form the orthogonal Doppler frequency shift difference signal p after two low-pass filtering. If2 (n) and p Qf2 (n):

[0086] If there is no interference signal, then p Id1 (n) and p Qd1 (n) After the two signals are subjected to secondary low-pass filtering, the change in the main spectrum amplitude can be ignored, forming the orthogonal Doppler frequency shift difference signal p after the two signals are subjected to secondary low-pass filtering. If2 (n) and p Qf2 (n):

[0087]

[0088] Among them, p If2 (n) is the Doppler frequency shift difference signal of path I after the second filtering, p Qf2 (n) is the Q-path Doppler frequency shift difference signal after the second filtering, A is the signal amplitude, Δ f is the difference of Doppler frequency shift signal between the current speed measurement cycle and the previous speed measurement cycle, is the sampling time, n is the number of sampling points, ω1 is the initial phase of the intermediate frequency sampling signal in this speed measurement period;

[0089] If there is an interference signal, add the interference signal to filter, extract and truncate the two orthogonal signals p Id1 (n) and p Qd1 (n) becomes the following orthogonal signal p with interference Idn1 (n) and p Qdn1 (n):

[0090]

[0091] Among them, p Idn1(n) is the Doppler frequency shift difference signal of path I after adding the interference signal, p Qdn1 (n) is the Q-path Doppler frequency shift difference signal after adding the interference signal, f noise is the interference signal frequency;

[0092] Then add the interference signal to the two orthogonal signals p Idn1 (n) and p Qdn1 (n) After the second low-pass filtering, the filtered frequency is f noise The interference signal forms two orthogonal Doppler frequency shift difference signals p after secondary filtering. If2 (n) and p Qf2 (n):

[0093]

[0094] Among them, p If2 (n) is the Doppler frequency shift difference signal of path I after the second filtering, p Qf2 (n) is the Q-path Doppler frequency shift difference signal after the second filtering;

[0095] 3.3) For p If2 (n) and p Qf2 (n) The two orthogonal signal data are decimated and truncated by 8 times to form two orthogonal signals p after secondary decimation and truncation. Id2 (n) and p Qd2 (n):

[0096]

[0097] Among them, p Id2 (n) is the Doppler frequency shift difference signal of path I after the second extraction and truncation, p Qd2 (n) is the Q-path Doppler frequency shift difference signal after the second extraction and truncation;

[0098] 3.4) Calculate the amplitude A of the two quadrature signals after secondary filtering:

[0099]

[0100] 3.5) Steps 3.1)-3.4) are completed on the FPGA platform, and the result A is output to the DSP. The main spectrum signal energy is calculated on the DSP platform, and the radar signal tracking threshold is determined to ensure stable tracking.

[0101] Step 4, repeat the above steps 1 to 3 for each speed measurement cycle when the radar is locked, and complete the processing of the echo signal when the Doppler radar is locked.

[0102] Embodiment 2: A method for processing Doppler radar echo signals when the radar is lost.

[0103] Reference Figure 2 The implementation steps of this example include the following:

[0104] Step 1: Calculate the intermediate frequency sampling signal frequency when the radar loses lock.

[0105] The sampling signal is an intermediate frequency analog signal that is converted into an intermediate frequency sampling signal after AD sampling, and its form is:

[0106] s(n)=Asin[2π(f0+f d )Δ t n+ω0],

[0107] Where A is the amplitude of the intermediate frequency sampling signal, f0 is the carrier frequency, f d is the Doppler shift signal frequency, is the sampling time, ω0 is the initial phase; n is the number of sampling points, and its value is a non-negative integer;

[0108] In a speed measurement cycle, when the radar loses lock, the frequency calculation of the intermediate frequency sampling signal in this speed measurement cycle is performed by DSP sending a "lost lock" signal to activate FFT transformation. FPGA uses its own IP core to complete FFT operation based on the received intermediate frequency sampling signal data and calculates the intermediate frequency sampling signal frequency f0+f d , where f0 is the carrier frequency, f d is the Doppler shift signal frequency;

[0109] The calculated results are then transmitted to the DSP to determine the upper and lower limits of the sweep frequency, narrow the sweep frequency range, reduce the radar lock-out time, and enhance the radar's rapid tracking capability after loss of lock.

[0110] Step 2: During this speed measurement cycle, perform Hilbert transform on the intermediate frequency sampling signal of the radar during this speed measurement cycle, output two orthogonal intermediate frequency signals containing Doppler frequency shift, and then perform low-pass filtering on the two orthogonal intermediate frequency signals containing Doppler frequency shift, retain the two orthogonal Doppler frequency shift signals, extract and truncate them, calculate the amplitude of the Doppler frequency shift signal, and transmit it to DSP.

[0111] The relevant implementation formula of this step is the same as step 1 of embodiment 1.

[0112] Step three, in this speed measurement cycle, receive the frequency control word calibrated from the previous speed measurement cycle from the DSP, and control the DDS signal generator inside the FPGA through the frequency control word to generate two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle; then mix the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle with the intermediate frequency sampling signal of the current speed measurement cycle respectively to form two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signals of two adjacent speed measurement cycles; then low-pass filter, data extraction and data truncation are performed on the two signals to form two orthogonal Doppler frequency shift difference signals of adjacent speed measurement cycles, which are transmitted to the DSP; the DSP calculates the frequency of the Doppler frequency shift difference signal according to the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word of the next speed measurement cycle;

[0113] The relevant implementation formula of this step is the same as step 2 of embodiment 1.

[0114] Step 4: During this speed measurement cycle, according to the Doppler frequency shift change characteristics between adjacent speed measurement cycles when the carrying platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals, and the signals after the secondary low-pass filtering are extracted and truncated to calculate the amplitude of the main spectrum signal in the band and transmit it to the DSP; the DSP uses the amplitude of the main spectrum signal in the band to calculate the energy of the main spectrum signal, perform radar signal tracking threshold judgment, and ensure stable tracking.

[0115] The relevant implementation formula of this step is the same as step 3 of embodiment 1.

[0116] Step 5: Repeat steps 1 to 4 for each speed measurement cycle when the radar is unlocked, and complete the processing of the echo signal when the Doppler radar is locked.

[0117] The above descriptions are only two specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention, such as increasing or decreasing the number of FFT transformation points according to the required range of frequency scanning, adjusting the Doppler frequency shift difference filtering characteristics for interference signals, and changing the decimation multiples to meet the data processing needs of the back-end DSP. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

[0118] It should be noted that the step numbers in the specification and claims of the present invention are only for a clear description of the implementation scheme of the present invention to facilitate understanding, and the order of the step numbers is not limited.

Claims

1. A method for processing echo signals when Doppler radar is locked based on FPGA, characterized in that: include: S1) In a speed measurement cycle, when the radar is locked, the intermediate frequency sampling signal of the current speed measurement cycle is Hilbert transformed to output two orthogonal intermediate frequency signals containing Doppler frequency shift, and then the two orthogonal intermediate frequency signals containing Doppler frequency shift are low-pass filtered to retain the two orthogonal Doppler frequency shift signals, and after extraction and truncation, the amplitude of the Doppler frequency shift signal is calculated and transmitted to the DSP; S2) DSP calculates the signal energy according to the Doppler frequency shift signal amplitude and performs automatic gain control of the radar intermediate frequency signal; S3) In this speed measurement cycle, the frequency control word after calibration of the previous speed measurement cycle is received from the DSP, and the DDS signal generator inside the FPGA is controlled by the frequency control word to generate two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle; the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle are mixed with the intermediate frequency sampling signal of the current speed measurement cycle respectively to form two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signals of two adjacent speed measurement cycles; the two signals are subjected to low-pass filtering, data extraction and data truncation to form two orthogonal Doppler frequency shift difference signals of adjacent speed measurement cycles, which are transmitted to the DSP; S4) In this speed measurement cycle, the DSP calculates the frequency of the Doppler frequency shift difference signal according to the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word of the next speed measurement cycle; S5) In this speed measurement cycle, according to the Doppler frequency shift change characteristics between adjacent speed measurement cycles when the carrying platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals, the signals after secondary low-pass filtering are extracted and truncated, the amplitude of the main spectrum signal in the band is calculated, and transmitted to the DSP; S6) During this speed measurement cycle, DSP uses the amplitude of the main spectrum signal in the band to calculate the main spectrum signal energy and make radar signal tracking threshold determination to ensure stable tracking; S7) repeats the above steps S1)-S6) for each speed measurement cycle when the radar is locked, completing the processing of the echo signal when the Doppler radar is locked, wherein steps S1), S3), and S5) are all completed on the FPGA platform.

2. The method according to claim 1, characterized in that In a speed measurement cycle, the Hilbert transform is performed on the intermediate frequency sampling signal, including the following: 2a) Let the intermediate frequency sampling signal be s(n)=Asin[2π(f0+f d )Δ t n+ω0], perform Hilbert transform on it, and obtain two orthogonal intermediate frequency signals s I (n) and s Q (n): s I (n)=Asin[2π(f0+f d )D t n+ω0]cos(2πf0Δ t n) s Q (n)=Asin[2π(f0+f d )D t n+ω0]sin(2πf0Δ t n) Among them, s I (n) is the intermediate frequency signal of channel I, s Q (n) is the Q-channel intermediate frequency signal, A is the intermediate frequency sampling signal amplitude, f0 is the carrier frequency, f d is the Doppler shift signal frequency, is the sampling time, n is the number of sampling points, ω0 is the initial phase; 2b) According to the product-to-difference formula, the above two orthogonal intermediate frequency signals are transformed into the following form:

3. The method according to claim 1, characterized in that After low-pass filtering, extraction and truncation of the two orthogonal intermediate frequency signals in the speed measurement period, the signal amplitude is calculated, including the following: 3a) Generate filter coefficients using matlab software, and combine with the filter IP core of FPGA to form the first low-pass filter fir_1; 3b) Using the first low-pass filter fir_1 to perform low-pass filtering on the two orthogonal intermediate frequency signals to form two filtered orthogonal Doppler frequency shift signals s If (n) and s Qf (n): Among them, s If (n) is the Doppler frequency shift signal of path I, s Qf (n) is the Q-path Doppler frequency shift signal, A is the intermediate frequency sampling signal amplitude, f d is the Doppler shift signal frequency, is the sampling time, n is the number of sampling points, ω0 is the initial phase; 3c) 8-fold decimation and truncation are performed on the two filtered orthogonal Doppler frequency shift signals to form two decimated and truncated orthogonal Doppler frequency shift signals s Id (n) and s Qd (n): Among them, s Id (n) is the Doppler frequency shift signal of path I after extraction and truncation, s Qd (n) is the Q-path Doppler frequency shift signal after decimation and truncation; 3d) According to s Id (n) and s Qd (n) The two extracted and truncated orthogonal Doppler frequency shift signals are used to calculate the signal amplitude A:

4. The method according to claim 1, characterized in that: In the present speed measurement cycle, the DDS generates two orthogonal intermediate frequency signals containing the Doppler frequency shift of the previous speed measurement cycle, and respectively mixes, low-pass filters, extracts data and truncates with the intermediate frequency sampling signal of the present speed measurement cycle, including the following: 4a) DDS generates two orthogonal intermediate frequency signals p containing the Doppler frequency shift signal of the previous speed measurement cycle according to the frequency control word sent by DSP. I (n) and p Q (n): p I (n)=cos[2π(f0+f d )D t [n] p Q (n)=sin[2π(f0+f d )D t [n] Among them, p I (n) is the intermediate frequency signal of channel I, p Q (n) is the Q-channel intermediate frequency signal, f0 is the carrier frequency, f d is the Doppler shift signal frequency of the previous speed measurement cycle, is the sampling time, n is the number of sampling points; 4b) Assume that the difference in Doppler frequency shift signal between the current speed measurement cycle and the previous speed measurement cycle is Δ f , then the intermediate frequency sampling signal of this speed measurement cycle becomes p(n)=Asin[2π(f0+f d +Δ f )Δ t n+ω1]; the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle are mixed with the intermediate frequency sampling signal p(n) of the current speed measurement cycle, and then converted into two orthogonal intermediate frequency signals p containing the Doppler frequency shift difference signal of adjacent speed measurement cycles through the product and difference formula I1 (n) and p Q1 (n): Among them, p I1 (n) is the Doppler frequency shift difference signal of path I, p Q1 (n) is the Q-path Doppler frequency shift difference signal, A is the signal amplitude, and ω1 is the initial phase of the intermediate frequency sampling signal in this speed measurement period; 4c) Generate filter coefficients using matlab software, and combine with the filter IP core of FPGA to form the second low-pass filter fir_2; 4d) Using the second low-pass filter fir_2 to perform low-pass filtering on the two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signals, to form two filtered orthogonal Doppler frequency shift difference signals p If1 (n) and p Qf1 (n): Among them, p If1 (n) is the Doppler frequency shift difference signal of path I after the first filtering, p Qf1 (n) is the Q-path Doppler frequency shift difference signal after the first filtering; 4e) 8-fold decimation and truncation are performed on the two-way filtered orthogonal Doppler frequency shift difference signal data to form two-way decimation and truncation orthogonal Doppler frequency shift difference signal p Id1 (n) and p Qd1 (n): Among them, p Id1 (n) is the Doppler frequency shift difference signal of path I after the first extraction, p Qd1 (n) is the Q-path Doppler frequency shift difference signal after the first extraction.

5. The method according to claim 1, characterized in that In the present speed measurement cycle, the two-way orthogonal Doppler frequency shift difference signal is subjected to secondary low-pass filtering, signal extraction and truncation, and the amplitude of the in-band main spectrum signal is calculated, including the following: 5a) Generate filter coefficients using matlab software and import them into the IP core FIR filter of FPGA to form the third low-pass filter fir_3; 5b) using a third low-pass filter fir_3 to perform low-pass filtering on the two-path orthogonal Doppler frequency shift difference signals to form two-path filtered orthogonal Doppler frequency shift difference signals; If there is no interference signal, then p Id1 (n) and p Qd1 (n) After the two signals are filtered twice, the change in the main spectrum amplitude can be ignored, forming the orthogonal Doppler frequency shift difference signal p after two secondary filtering. If2 (n) and p Qf2 (n): Among them, p If2 (n) is the Doppler frequency shift difference signal of path I after the second filtering, p Qf2 (n) is the Q-path Doppler frequency shift difference signal after the second filtering, A is the signal amplitude, Δ f is the difference of Doppler frequency shift signal between the current speed measurement cycle and the previous speed measurement cycle, is the sampling time, n is the number of sampling points, ω1 is the initial phase of the intermediate frequency sampling signal in this speed measurement period; If there is an interference signal, add the interference signal to filter, extract and truncate the two orthogonal signals p Id1 (n) and p Qd1 (n) becomes the following orthogonal signal p with interference Idn1 (n) and p Qdn1 (n): Among them, p Idn1 (n) is the Doppler frequency shift difference signal of path I after adding the interference signal, p Qdn1 (n) is the Q-path Doppler frequency shift difference signal after adding the interference signal, f noise is the interference signal frequency; After adding the interference signal, the two orthogonal signals are subjected to a second low-pass filter to filter out the frequency f noise The interference signal forms two orthogonal Doppler frequency shift difference signals p after secondary filtering. If2 (n) and p Qf2 (n): Among them, p If2 (n) is the Doppler frequency shift difference signal of path I after the second filtering, p Qf2 (n) is the Q-path Doppler frequency shift difference signal after the second filtering; 5c) For p If2 (n) and p Qf2 (n) The two orthogonal signal data are decimated and truncated by 8 times to form two orthogonal signals p after secondary decimation and truncation. Id2 (n) and p Qd2 (n): Among them, p Id2 (n) is the Doppler frequency shift difference signal of path I after the second extraction and truncation, p Qd2 (n) is the Q-path Doppler frequency shift difference signal after the second extraction and truncation; 5d) Calculate the amplitude A of the two quadrature signals after secondary filtering:

6. A method for processing echo signals when Doppler radar loses lock based on FPGA, characterized in that: include: (1) When the radar loses lock within a speed measurement cycle, the FFT operation is performed on the intermediate frequency sampling signal within the speed measurement cycle, and the calculation result is transmitted to the DSP to determine the upper and lower limits of the frequency sweep, narrow the frequency sweep range, reduce the frequency sweep time, and enhance the rapid tracking capability of the radar after losing lock; (2) During this speed measurement period, the intermediate frequency sampling signal of the radar is Hilbert transformed to output two orthogonal intermediate frequency signals containing Doppler frequency shift, and then the two orthogonal intermediate frequency signals containing Doppler frequency shift are low-pass filtered to retain the two orthogonal Doppler frequency shift signals. After extraction and truncation, the amplitude of the Doppler frequency shift signal is calculated and transmitted to the DSP; (3) During this speed measurement cycle, the DSP calculates the signal energy based on the Doppler frequency shift signal amplitude and performs automatic gain control of the radar intermediate frequency signal; (4) In this speed measurement cycle, the frequency control word after calibration of the previous speed measurement cycle is received from the DSP, and the DDS signal generator inside the FPGA is controlled by the frequency control word to generate two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle; the two orthogonal intermediate frequency signals containing the Doppler frequency shift signal of the previous speed measurement cycle are then mixed with the intermediate frequency sampling signal of the current speed measurement cycle to form two orthogonal intermediate frequency signals containing the Doppler frequency shift difference signals of two adjacent speed measurement cycles; the two signals are then subjected to low-pass filtering, data extraction and data truncation to form two orthogonal Doppler frequency shift difference signals of two adjacent speed measurement cycles, which are then transmitted to the DSP; (5) In this speed measurement cycle, the DSP calculates the frequency of the Doppler frequency shift difference signal based on the two orthogonal Doppler frequency shift difference signals, which is used to calibrate the frequency control word of the next speed measurement cycle; (6) During this speed measurement cycle, according to the Doppler frequency shift change characteristics between adjacent speed measurement cycles when the platform moves, the two orthogonal Doppler frequency shift difference signals are subjected to secondary low-pass filtering to filter out possible interference signals, and the signals after secondary low-pass filtering are extracted and truncated to calculate the amplitude of the in-band main spectrum signal and transmit it to the DSP; (7) During this speed measurement cycle, the DSP uses the amplitude of the main spectrum signal in the band to calculate the main spectrum signal energy and make radar signal tracking threshold determination to ensure stable tracking; (8) Repeat the above steps (1) to (7) for each speed measurement cycle when the radar is lost, so as to complete the processing of the echo signal when the Doppler radar is lost, wherein steps (1), (2), (4) and (6) are all completed on the FPGA platform.

7. The method according to claim 6, characterized in that In the speed measurement cycle, the FFT operation is performed on the intermediate frequency sampling signal when the radar is unlocked, including the following: 7a) When the Doppler signal is lost, the DSP sends a "lost lock" signal to activate the FFT transform; 7b) Receive the data of the intermediate frequency sampling signal. FPGA uses its own IP core to complete the FFT operation based on the data of the intermediate frequency sampling signal and calculates the frequency f0+f d , where f0 is the carrier frequency, f d is the Doppler shift signal frequency.

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