Method for outputting pulse per second signal, computer storage medium and terminal

Abstract

The invention discloses a method for outputting pulse per second (PPS) signals, a computer storage medium and a terminal, according to the embodiment of the invention, a CPU is configured to be in an awakening state only when periodically outputting the PPS signals, the CPU is in a standby state at other moments, two timers are kept to work, and the other timers are turned off, so that low power consumption of a global navigation satellite system (GNSS) module is realized; the actual clock cycle number of the output PSS signal is determined according to the clock drift of the GNSS module and the software consumption accumulative error, so that the clock cycle number correction is realized, and the output precision of the PSS signal is improved; under the condition that the GNSS module keeps an extremely low power consumption mode, precise, continuous and stable PPS signal output is provided, and application support is provided for application scenes requiring low power consumption, long-time operation and high precision.

Description

Technical Field

[0001] The present invention relates to satellite navigation technology, and in particular to a method for outputting a pulse signal per second, a computer storage medium and a terminal. Background Art

[0002] In the field of global navigation satellite system (GNSS) applications, for devices with limited power supply and requiring continuous and precise time synchronization, the GNSS module is required to provide a high-precision pulse per second (PPS) signal while maintaining extremely low power consumption.

[0003] The related technologies provide PPS signals in three ways: Method 1: In the low-power mode of the GNSS module, the power supply of the core modules such as the CPU main control, memory, radio frequency unit and GNSS baseband is maintained to ensure the real-time output of accurate PPS pulses; Method 2: In order to maintain low power consumption, many GNSS modules will stop or reduce the output of the time synchronization signal of the PPS signal, or directly use the local clock as the reference output signal to output the PPS signal in real time; Method 3: In the normal working mode, the external board uses the PPS signal of the GNSS module to synchronize and correct the clock, and obtain the deviation between the PPS signal and the local clock. When entering the low-power mode, the GNSS module is turned off, and the external board uses the obtained fixed deviation to correct the local clock and then perform other work. In the above methods, Method 1 keeps most of the core of the GNSS module powered on, which will increase power consumption. Method 2, due to the errors of the crystal oscillator itself and the software implementation, continuous operation will cause the drift or decrease of the time reference, and the accuracy of the output PPS signal is usually poor. Method 3 requires the combination of the GNSS module and the external board to achieve, which will cause jitter and discontinuity in the output of the PPS signal.

[0004] In summary, how to obtain a PPS signal that meets the accuracy requirements while maintaining low power consumption has become a problem to be solved. Summary of the invention

[0005] The present application provides a method for outputting a pulse per second signal, comprising:

[0006] After the GNSS module enters the low power consumption mode, the central processing unit CPU is configured to be in the awake state only when the PPS signal is periodically output, and in the standby state at other times. In addition to the CPU, only the first timer and the second timer are kept in the working state, wherein the first timer is used to periodically trigger the output of the PPS signal, and the second timer is used to provide a time reference for calculating the accumulated error consumed by the software;

[0007] Calculate the software consumption accumulated error based on the time base of the second timer;

[0008] Perform error correction on the preset initial clock cycle number of the output PPS signal according to the clock drift of the GNSS module and the calculated software consumption cumulative error, and determine the actual clock cycle number of the output PPS signal;

[0009] The first timer is used to periodically trigger the output of the PPS signal according to the determined actual clock cycle number.

[0010] On the other hand, an embodiment of the present application further provides a computer storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of outputting a pulse signal per second is implemented.

[0011] On the other hand, an embodiment of the present application further provides a terminal, comprising: a memory and a processor, wherein the memory stores a computer program; wherein:

[0012] The processor is configured to execute the computer program in the memory;

[0013] When the computer program is executed by the processor, the method of outputting a pulse signal per second as described above is implemented.

[0014] The disclosed embodiment configures the CPU to be awakened during the process of outputting the PPS signal, keeps two timers in working state, and shuts down the coprocessor, memory, baseband and other peripherals, thereby realizing low power consumption of the GNSS module; according to the clock drift of the GNSS module and the accumulated error of software consumption, the actual number of clock cycles of the output PPS signal is determined, the clock cycle number correction is realized, and the output accuracy of the PSS signal is improved; when the GNSS module maintains an extremely low power consumption mode, accurate, continuous and stable PPS signal output is provided, thereby providing application support for application scenarios requiring low power consumption, long-term operation and high precision.

[0015] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0017] Figure 1 A flow chart of a method for outputting a pulse per second signal according to an embodiment of the present disclosure;

[0018] Figure 2 A schematic diagram of the related art entering a low power consumption mode at random moments;

[0019] Figure 3 A schematic diagram of the embodiment of the present disclosure when entering a low power consumption mode;

[0020] Figure 4 A structural block diagram of a device for outputting a pulse signal per second according to an embodiment of the present disclosure;

[0021] Figure 5 is a schematic diagram of a GNSS module according to an embodiment of the present disclosure;

[0022] Figure 6 This is a schematic diagram of the GNSS module workflow of the embodiment of the present disclosure;

[0023] Figure 7 A pulse diagram of an embodiment of the present disclosure when entering a low power consumption mode;

[0024] Figure 8 It is a schematic diagram of the divergence accuracy of the PPS signal according to the embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0026] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0027] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0028] Figure 1 Flow chart of the method for outputting a pulse signal per second according to an embodiment of the present disclosure, as shown in FIG. Figure 1 As shown, including:

[0029] Step 101, after the global navigation satellite system (GNSS) module enters the low power consumption mode, the central processing unit (CPU) is configured to be in the awake state only when the pulse per second (PPS) signal is periodically output, and in the standby state at other times. In addition to the CPU, only the first timer and the second timer are kept in the working state, wherein the first timer is used to periodically trigger the output of the PPS signal, and the second timer is used to provide a time reference for calculating the accumulated error consumed by the software;

[0030] Step 102, calculating the software consumption cumulative error based on the time base of the second timer;

[0031] Step 103: performing error correction on the preset initial clock cycle number of the output PPS signal according to the clock drift of the GNSS module and the calculated software consumption cumulative error, and determining the actual clock cycle number of the output PPS signal;

[0032] Step 104: Periodically trigger output of a PPS signal according to the determined actual clock cycle number through a first timer.

[0033] The disclosed embodiment configures the CPU to be awakened during the process of outputting the PPS signal, keeps two timers in working state, and shuts down the coprocessor, memory, baseband and other peripherals, thereby realizing low power consumption of the GNSS module; according to the clock drift of the GNSS module and the accumulated error of software consumption, the actual number of clock cycles of the output PPS signal is determined, the clock cycle number correction is realized, and the output accuracy of the PSS signal is improved; when the GNSS module maintains an extremely low power consumption mode, accurate, continuous and stable PPS signal output is provided, thereby providing application support for application scenarios requiring low power consumption, long-term operation and high precision.

[0034] In an exemplary embodiment, before step 101 of the embodiment of the present disclosure, the process further includes:

[0035] After receiving the command to enter low power consumption, according to the level state of the pulse per second (PPS) signal at the current moment when the command to enter low power consumption is received and the time information of the PPS signal latched by the hardware, the global navigation satellite system (GNSS) module is controlled to enter the low power consumption mode at the low level moment of the PPS signal at the current moment that meets the preset conditions, wherein the low level moment that meets the preset conditions includes: the time length from the low level moment to the next rising edge moment is greater than the processing time length for entering the low power consumption mode.

[0036] In the disclosed embodiment, when the global navigation satellite system (GNSS) outputs a pulse per second (PPS) signal, in order to avoid randomly entering a low power consumption mode causing a certain probability of discontinuity in the output PPS signal, it is determined to enter the low power consumption mode at a low level moment that meets preset conditions, thereby ensuring the stability and continuity of the PPS signal.

[0037] In an exemplary embodiment, the embodiment of the present disclosure determines the low level moment of the PPS signal at the current moment through a pulse edge detection algorithm.

[0038] The time when the related technology enters the low power mode is random, see Figure 2 , there is a certain probability that the output PPS signal will be discontinuous, for example, Figure 2 Before moment t1, the PPS model output is in normal mode. If a command is sent at moment t1 to enter low power mode, the GNSS module will be powered off gradually. Since the PPS signal is in the high level pulse period at this time, the power off after moment t1 causes the pulse output of the PPS signal to be cut off. Ideally, the low power mode should be entered during the low level idle period of the pulse to reserve time for the low power process and subsequent pulse cycle configuration. The disclosed embodiment combines hardware time latching technology to control the GNSS module to enter low power mode at the current moment when the PPS signal meets the preset low level conditions. The low level moments that meet the preset conditions include: the duration from the low level moment to the next rising edge moment, which is greater than the processing time to enter the low power mode, and the state of the output PPS signal is accurately controlled, see Figure 3 , the embodiments of the present disclosure mainly consider two situations:

[0039] for Figure 3 In the case marked in ①, the PPS signal receives a low power command at the high level moment, and the remaining high level duration needs to be calculated according to the cycle, that is, the high level moment to the next falling edge moment in the figure is t1. To ensure the integrity of the high level pulse, the low power time needs to be delayed by t1. Figure 3In the case marked by ②, when the PPS receives the command to enter low power consumption at the low level moment, the duration of the remaining low level moment is still calculated according to the cycle, that is, the duration t2 from the low level moment to the next rising edge moment in the figure. If the calculated t2 time is greater than the processing time Nms for entering the low power consumption mode (assuming that the maximum processing time for low power consumption is N ms), the low power consumption mode can be entered directly; if the calculated t2 time is less than N ms, in order to ensure the integrity of the PPS cycle and low power consumption processing, t2 needs to be delayed to the next high level pulse falling edge moment, that is, enter the low power consumption mode at time ③.

[0040] In an exemplary instance, the command configuration actions of the external user on the GNSS module in the embodiment of the present disclosure include entering low power consumption and outputting PPS signals, the period and pulse width of the output PPS signals, etc.; after the configuration is completed, the PPS output pulse edge detection and error correction for entering low power consumption are completed inside the GNSS module, and when the external user issues a command to exit low power consumption, the exit process is initiated.

[0041] In an exemplary embodiment, the embodiment of the present disclosure configures the central processing unit (CPU) to be in an awake state only when a pulse per second PPS signal is periodically output, including:

[0042] The CPU is configured to be in a wake-up state when the PPS signal is periodically output by using a preset interrupt drive.

[0043] The disclosed embodiment only interrupts and wakes up the CPU during the process of outputting the PPS signal. After the PPS signal is output, the CPU immediately enters the standby mode, thereby achieving extremely low standby power consumption.

[0044] In an exemplary instance, after the GNSS module enters low power consumption, the first timer and the second timer including the GNSS module baseband are in a power-off state, and the PPS signal output to the sky is turned off. At this time, the local crystal oscillator inside the board of the GNSS module outputs the PPS signal, but the board clock based on the local crystal oscillator may have drift (clock drift), that is, as time goes by, the time of the board clock continues to deviate from the actual time, resulting in the clock drift of the GNSS module; in order to ensure accuracy, the drift of the board clock of the local crystal oscillator must be corrected; after the GNSS module is powered on, the embodiment of the present disclosure calculates the time and position information and synchronizes the satellite time, and at the same time fits the clock drift of the local crystal oscillator, that is, the clock drift of the GNSS module through the algorithm in the relevant technology.

[0045] In an exemplary embodiment, the embodiment of the present disclosure may adopt a clock drift fitting algorithm to perform fitting based on the difference between the synchronized satellite time and the time of the local crystal oscillator to obtain an accurate clock drift of the GNSS module.

[0046] After the clock drift of the GNSS module is determined in the above manner, the embodiment of the present disclosure calculates the PPS error of the output PPS signal based on the clock drift of the GNSS module.

[0047] The disclosed embodiment assumes that the clock drift of the GNSS module is Δt (ns / s), the clock drift value can be positive or negative, the number of initial clock cycles is t, the clock frequency is m Hz, and the duration of each clock cycle is seconds; then, the error time caused by clock drift Δt (ns / s) in each clock cycle is The total error duration of t clock cycles is Divide the total error duration by the duration of each clock cycle Get the number of error clock cycles caused by clock drift after t clock cycles are executed. The expression is:

[0048]

[0049] In order to ensure the continuity of the output PPS signal and the accuracy of the cycle, it is necessary to consider the clock consumption during the software execution process, and compensate for the number of clock cycles consumed by the software in the low-power process and the number of software delay cycles configured for the cycle of the PPS signal output, so as to avoid the cumulative error of the software; in order to avoid the timer overflow rollover error, the disclosed embodiment can use a 64-bit hardware timer (timer) to calculate the number of clock cycles consumed by the software execution. The disclosed embodiment outputs the PPS signal with low power consumption, and will reconfigure the interrupt of the first timer according to the number of clock cycles of the output PPS signal, and dynamically adjust the configuration value of the first timer to ensure the accuracy of the PPS information cycle output; the software configuration of the first timer, interrupt callback, and function stack entry and exit operations will cause clock consumption, affecting the accuracy of the output PPS signal.

[0050] In an exemplary embodiment, the embodiment of the present disclosure keeps the first timer and the second timer turned on, and calculates the number of clock cycles τ consumed by the accumulated error consumed by the software based on the time base of the second timer.

[0051] The disclosed embodiment comprehensively considers the error clock cycle number ε caused by clock drift and the clock cycle number τ consumed by the accumulated error consumption of software, corrects the initial clock cycle number, and calculates the actual clock cycle number c executed under the corrected t clock cycles as: c=t±|ε|-τ(cycle).

[0052] In low-power mode, in the process of periodically triggering the output of the PPS signal through interrupts, the delay difference of the dynamic interrupt callback and the instruction execution jitter of different instructions may cause a certain periodic error. If it is not eliminated in time, it will cause cumulative errors during long-term operation.

[0053] In an exemplary embodiment, the method of the present disclosure further includes:

[0054] Determine the accumulated error caused by instruction execution jitter during the output of the PPS signal;

[0055] According to the determined accumulated error caused by instruction execution jitter in the process of outputting the PPS signal, error correction is performed on the actual clock cycle number of the output PPS signal.

[0056] In an exemplary embodiment, the embodiment of the present disclosure determines the accumulated error caused by instruction execution jitter during the process of outputting the PPS signal, including:

[0057] Get the time difference between two consecutive output PPS signals as the actual cycle length, and subtract the actual cycle length from the expected clock cycle length to get a cycle error. The cycle error is X m -X m-1 -X T , where X m is the timestamp of the PPS signal output at time m between two consecutive PPS signal outputs, X m-1 is the timestamp of the PPS signal output at time m-1 between two consecutive PPS signals, X T is the clock cycle length of the desired output PPS signal;

[0058] After obtaining the periodic error, the exponential moving average method is used to calculate the cumulative error A at time m ′ tm , A ′ m The expression is A ′ m =α·A m-1 +(1-α)·A ′ m-1 , where A m-1 is the periodic error at time m-1, A ′ m-1 is the smoothed difference estimate at time m, and α is the smoothing coefficient.

[0059] The embodiment of the present disclosure uses an exponential sliding average method for calculation, thereby ensuring the smoothness of dynamic adjustment, performing error correction on the actual number of clock cycles of the output PPS signal, and further improving the accuracy of the output PPS signal.

[0060] Taking into account the differences in the characteristics of single crystal oscillators, different crystal oscillators have different smoothing coefficients α. In order to adaptively find an optimal α value for each single crystal oscillator, the smoothed difference A ′ t Ability to maintain smoothness while being as close to the target value as possible to reduce cumulative error.

[0061] In an exemplary embodiment, the method of the present disclosure further includes:

[0062] The least square method is used to solve the smoothing coefficient α.

[0063] The embodiment of the present disclosure defines the sum of squared errors (SSE) to measure the difference between the estimated value of α and the actual value, and the error is defined as:

[0064]

[0065] Among them, A m is the expected error, A ′ m is the error of the current estimate, starting from m=1, obtain n groups of SSE;

[0066] In practical applications, it is expected that m =0, simplifying to:

[0067]

[0068] Use the gradient descent method to minimize SSE(α); the embodiment of the present disclosure calculates the derivative of SSE(α) with respect to α, and the goal of the gradient descent is to adjust α in the negative gradient direction so that SSE(α) is minimized:

[0069]

[0070] Select an initial α, use the gradient descent method to iteratively update α, and finally adaptively obtain the optimal α:

[0071]

[0072] Among them, μ is the learning rate, which can take a minimum value, and a ranges from [0, 1].

[0073] In an exemplary embodiment, the method of the present disclosure further includes:

[0074] When the GNSS module exits low power mode, the clock drift is updated.

[0075] When a wake-up command is received in the embodiment of the present disclosure, the high priority interrupt immediately switches from the low power consumption mode to the normal working mode, and the real-time nature of the clock drift is ensured by updating the clock drift, so as to quickly restore the operation of the GNSS module.

[0076] The embodiment of the present disclosure also provides a computer storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of outputting a pulse signal per second is implemented.

[0077] The embodiment of the present disclosure also provides a terminal, including: a memory and a processor, wherein a computer program is stored in the memory;

[0078] in,

[0079] The processor is configured to execute the computer program in the memory;

[0080] When the computer program is executed by the processor, the method of outputting a pulse signal per second as described above is implemented.

[0081] Figure 4 The structure block diagram of the device for outputting a pulse signal per second according to the embodiment of the present disclosure is as follows: Figure 4 As shown, it includes: a configuration unit, a calculation unit, a correction unit and an output unit; wherein,

[0082] The configuration unit is set to: after the GNSS module enters the low power consumption mode, the central processing unit CPU is configured to be in the awake state only when the PPS signal is periodically output, and is in the standby state at other times. In addition to the CPU, only the first timer and the second timer are kept in the working state, wherein the first timer is used to periodically trigger the output of the PPS signal, and the second timer is used to provide a time reference for calculating the accumulated error consumed by the software;

[0083] The calculation unit is configured to: calculate the software consumption cumulative error based on the time reference of the second timer;

[0084] The correction unit is configured to: perform error correction on a preset initial clock cycle number of the output PPS signal according to the clock drift of the GNSS module and the calculated software consumption cumulative error, and determine the actual clock cycle number of the output PPS signal;

[0085] The output unit is configured to periodically trigger the output of the PPS signal according to the determined actual clock cycle number through a first timer.

[0086] In an exemplary embodiment, the device of the embodiment of the present disclosure further includes entering a low power consumption unit, which is configured as follows:

[0087] After receiving the command to enter low power consumption, according to the level state of the pulse per second PPS signal at the current moment when the command to enter low power consumption is received and the time information of the PPS signal latched by the hardware, the global navigation satellite system GNSS module is controlled to enter the low power consumption mode at the low level moment of the PPS signal at the current moment that meets the preset conditions, wherein the low level moment that meets the preset conditions includes: the time length from the low level moment to the next rising edge moment is greater than the processing time length for entering the low power consumption mode.

[0088] In an exemplary embodiment, the embodiment of the present disclosure enters the low power consumption unit by: determining the low level moment of the PPS signal at the current moment that meets the preset condition through a pulse edge detection algorithm.

[0089] In an exemplary embodiment, the configuration unit of the embodiment of the present disclosure is configured to configure the CPU to be in an awake state only when the PPS signal is periodically output, including:

[0090] The CPU is configured to be in wake-up state only when the PPS signal is output periodically using a preset interrupt drive.

[0091] In an exemplary embodiment, the clock drift of the GNSS module of the embodiment of the present disclosure is Δt, in nanoseconds per second, and can be positive or negative. The number of initial clock cycles is t, the clock frequency is m Hz, and the duration of each clock cycle is seconds. The expression for the number of error clock cycles caused by clock drift after t clock cycles is:

[0092]

[0093] In an exemplary embodiment, the computing unit of the embodiment of the present disclosure is further configured to:

[0094] Determine the accumulated error caused by instruction execution jitter during the output of the PPS signal;

[0095] According to the determined accumulated error caused by instruction execution jitter in the process of outputting the PPS signal, error correction is performed on the actual clock cycle number of the output PPS signal.

[0096] In an exemplary embodiment, the calculation unit of the embodiment of the present disclosure is configured to determine the cumulative error caused by instruction execution jitter during the output of the PPS signal, including:

[0097] The time difference between two consecutive output PPS signals is obtained as the actual cycle length, and the actual cycle length is subtracted from the expected clock cycle length to obtain a cycle error.

[0098] According to the periodic error, the exponential moving average method is used to calculate the cumulative error A at time m. ′ tm , A ′ m The expression is: A ′ m =α·A m-1 +(1-α)·A ′ m-1 ;

[0099] Among them, A m-1 is the periodic error at time m-1, A ′ m-1 is the smoothed difference estimate at time m, and α is the smoothing coefficient.

[0100] In an exemplary embodiment, the apparatus of the embodiment of the present disclosure further includes an updating unit, which is configured to:

[0101] Update the clock drift when the GNSS module exits low power mode.

[0102] The following briefly describes the embodiments of the present disclosure through application examples. The application examples are only used to illustrate the embodiments of the present disclosure and are not used to limit the protection scope of the embodiments of the present disclosure.

[0103] In the GNSS module of the disclosed embodiment, the user sends a STANBDY ON command through the serial port and continuously outputs the PPS signal in the low power consumption mode, and sends a STANBDY OFF command through the serial port to exit the low power consumption mode and restore the function of the GNSS module. Figure 5 is a schematic diagram of a GNSS module according to an embodiment of the present disclosure, Figure 5 As shown, the GNSS module is a high-precision positioning processor that integrates RF, baseband and CPU. It can be divided into CPU, GNSS baseband, memory, peripherals and RF components. Among them, peripherals include timers and UART devices. UART is used for command interaction. Figure 6 As shown, including:

[0104] Table 1 shows some technical indicators of the GNSS module of the embodiment of the present disclosure:

[0105] index parameter Voltage +3.0V~+3.6V DC Time accuracy (RMS) 20 nanoseconds Power consumption 450mW (typical) Initialization time <5s (typical) Data update rate 20Hz

[0106] Table 1

[0107] System power on: Calculate and synchronize sky time and position information;

[0108] Clock drift fitting: Fit the clock drift Δt of the crystal oscillator through an algorithm;

[0109] Receive low power command: UART receives the command to enter low power mode and prepares to enter low power mode. It pre-processes the level of the PPS signal according to the pulse edge detection algorithm to eliminate jitter and achieve a smooth transition from normal mode to low power mode.

[0110] Enter low power mode: turn off the off-chip memory, RF, GNSS BB, auxiliary CPU processor, other peripherals except UART and TIMER, and 1.8V DCDC, adjust DCDC to PFM mode, wake up the standby mode through the periodic interrupt of the timer during the pulse of the PPS signal, and remain in sleep mode for the rest of the time to minimize power consumption;

[0111] Timer configuration: Calculate the clock cycle count value of the first timer according to the clock drift of the GNSS module and the accumulated error of software consumption;

[0112] Entering standby mode: The main CPU enters standby mode, waiting for an interrupt trigger, and periodically outputs an accurate PPS signal.

[0113] This paper tries to enter the low power mode by inputting commands from the test serial port in normal mode. It can enter the low power mode as expected and generate stable and accurate PPS signal pulses in the low power state. Figure 7 The pulses are smooth and jitter-free before and after entering low power mode.

[0114] The accuracy of the PPS signal in the low power consumption mode of the embodiment of the present disclosure is shown in Figure 8 The horizontal axis of the figure is the time axis, and the vertical axis is the PPS error. The line segment from top to bottom in the figure is the error generated once an hour. After the board is dormant for 1 hour, the divergence accuracy of the PPS signal is about 226.4us; the power consumption of the GNSS model in low power consumption mode can be an average of 0.075W, achieving extremely low power consumption.

[0115] The disclosed embodiment was tested with different boards, RTK positioning modules, GNSS SoC chips and other devices, and the sleep wake-up success rate was 100%. The disclosed embodiment switches from normal mode to low power mode, and the PPS signal is stable, continuously output, and has no jitter; compared with the normal working mode, the power consumption is reduced from 0.42w to 0.07w on average, and the power consumption is reduced by 93%; in terms of PPS accuracy, under the premise of clock drift Δt=400ns / s and PPS period of 1Hz frequency, the test 1h divergence accuracy is 226.4us, while the current industry has not passed the calibration algorithm or the correction algorithm is insufficient in accuracy, and the output PPS accuracy is 1h error is usually 1.5~20ms, and the accuracy of the solution provided by the disclosed embodiment is at least 6 times higher.

[0116] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A method for outputting a pulse signal per second, characterized in that: include: After the GNSS module enters the low power consumption mode, the central processing unit CPU is configured to be in the awake state only when the PPS signal is periodically output, and in the standby state at other times. In addition to the CPU, only the first timer and the second timer are kept in the working state, wherein the first timer is used to periodically trigger the output of the PPS signal, and the second timer is used to provide a time reference for calculating the accumulated error consumed by the software; Calculate the software consumption accumulated error based on the time base of the second timer; Perform error correction on the preset initial clock cycle number of the output PPS signal according to the clock drift of the GNSS module and the calculated software consumption cumulative error, and determine the actual clock cycle number of the output PPS signal; The first timer is used to periodically trigger the output of the PPS signal according to the determined actual clock cycle number.

2. The method according to claim 1, characterized in that Before the GNSS module enters the low power consumption mode, the method further includes: After receiving the low power command, according to the level state of the PPS signal at the current moment when the low power command is received and the time information of the PPS signal latched by the hardware, control the GNSS module to enter the low power mode at the low level moment of the PPS signal at the current moment that meets the preset conditions; The low-level moment that meets the preset condition includes: the duration from the low-level moment to the next rising edge is greater than the processing duration for entering the low power consumption mode.

3. The method according to claim 2, characterized in that The low level moment of the PPS signal at the current moment that meets the preset conditions is determined by a pulse edge detection algorithm.

4. The method according to claim 1, characterized in that: The configuration of the central processing unit CPU is in the awake state only when the PPS signal is periodically outputted, including: The CPU is in a wake-up state when periodically outputting the PPS signal using a preset interrupt drive configuration.

5. The method according to claim 1, characterized in that: The clock drift of the GNSS module is Δt, in nanoseconds per second, which can be positive or negative. The number of initial clock cycles is t, the clock frequency is m Hz, and the duration of each clock cycle is seconds. The expression for the number of error clock cycles caused by clock drift after t clock cycles is: cycle.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: Determine the accumulated error caused by instruction execution jitter during the process of outputting the PPS signal; According to the determined accumulated error caused by instruction execution jitter during the process of outputting the PPS signal, error correction is performed on the actual clock cycle number of outputting the PPS signal.

7. The method according to claim 6, characterized in that The determining of the accumulated error caused by instruction execution jitter during the process of outputting the PPS signal includes: Obtain a set of time differences between two consecutive outputs of the PPS signal as the actual cycle duration, and subtract the actual cycle duration from the expected clock cycle duration to obtain a cycle error; According to the periodic error, the cumulative error A at time m is calculated using the exponential sliding average method. ′ tm , A ′ m The expression is: ′ m =α·A m-1 +(1-α)·A ′ m-1 ; Among them, A m-1 is the periodic error at time m-1, A ′ m-1 is the smoothed difference estimate at time m, and α is the smoothing coefficient.

8. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: Update the clock drift when the GNSS module exits low power mode.

9. A computer storage medium, wherein a computer program is stored in the computer storage medium, and when the computer program is executed by a processor, the method for outputting a pulse per second signal according to any one of claims 1 to 8 is implemented.

10. A terminal, comprising: A memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute the computer program in the memory; When the computer program is executed by the processor, the method for outputting a pulse-per-second signal according to any one of claims 1 to 8 is implemented.

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