Array substrate, display panel and display device

Abstract

The invention provides an array substrate. The array substrate comprises a substrate body; a plurality of scanning lines and a plurality of scanning lines; each sub-pixel comprises a first active layer, a second active layer and a pixel electrode; wherein the sub-pixel further comprises a first connecting part, a second connecting part and a pixel electrode connecting part, the data line is electrically connected with the first area of the first active layer through the first connecting part, the second area of the second active layer is electrically connected with the pixel electrode connecting part through the second connecting part, and the pixel electrode connecting part is directly connected with the pixel electrode; the total extension length of the first connecting part is a first length, the average width of the first connecting part in the direction perpendicular to the extension direction of the first connecting part is a first width, the total extension length of the second connecting part is a second length, and the average width of the second connecting part in the direction perpendicular to the extension direction of the second connecting part is a second width. The deviation ratio of the first length to the second length is less than or equal to 10%, and the deviation ratio of the first width to the second width is less than or equal to 10%.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Electronic Paper Display (EPD) is a display technology that mimics traditional printed paper, with high contrast, low power consumption, and clear display even in direct sunlight. EPD technology is based on the phenomenon of electrophoresis, that is, charged particles move under the action of an electric field. In EPD, tiny white and black particles are suspended in a liquid. When an electric field is applied, these particles move according to the direction of the electric field to form an image on the display. EPD display technology has been widely used in e-book readers, smart tags and other fields due to its unique display characteristics and low power consumption. With the continuous advancement of technology, EPD is expected to play an important role in more fields. In EPD display products, how to ensure the best display effect is one of the topics that display product developers are concerned about.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, an array substrate is provided, the array substrate comprising:

[0005] substrate substrate;

[0006] A plurality of scanning lines are located on the substrate, and the plurality of scanning lines extend along a first direction and are arranged along a second direction;

[0007] a plurality of data lines, located on the base substrate, the plurality of data lines extending along the second direction and arranged along the first direction; and

[0008] A plurality of sub-pixels are located on the base substrate, the plurality of sub-pixels are arranged in an array along the first direction and the second direction, the sub-pixels include a first active layer, a second active layer and a pixel electrode, a first area of ​​the first active layer is electrically connected to one of the data lines, a second area of ​​the first active layer is electrically connected to a first area of ​​the second active layer, and a second area of ​​the second active layer is electrically connected to the pixel electrode;

[0009] The sub-pixel further comprises a first connection portion, a second connection portion and a pixel electrode connection portion, the first connection portion electrically connects the data line and the first area of ​​the first active layer, the second connection portion electrically connects the second area of ​​the second active layer and the pixel electrode connection portion, and the pixel electrode connection portion is directly connected to the pixel electrode; and

[0010] The total extended length of the first connecting portion is a first length, the average width of the first connecting portion in a direction perpendicular to its extending direction is a first width, the total extended length of the second connecting portion is a second length, the average width of the second connecting portion in a direction perpendicular to its extending direction is a second width, the deviation ratio of the first length compared to the second length is less than or equal to 10%, and the deviation ratio of the first width compared to the second width is less than or equal to 10%.

[0011] According to some exemplary embodiments, the first active layer and the second active layer are symmetrically arranged with respect to a first virtual straight line axis, and the first portion of the first connecting portion and at least the second portion of the first connecting portion are symmetrically arranged with respect to the first virtual straight line axis.

[0012] According to some exemplary embodiments, the first portion of the first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line, or,

[0013] The second parts of the first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line, or,

[0014] The first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line.

[0015] According to some exemplary embodiments, the sub-pixel further includes a third connection portion, the third connection portion electrically connecting the second region of the first active layer and the first region of the second active layer, the third connection portion being axially symmetrically arranged with respect to the first virtual straight line.

[0016] According to some exemplary embodiments, the first connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is directly connected to the first region of the first active layer, and the second sub-portion is located on a side of the first sub-portion close to the data line and is directly connected to the data line;

[0017] The second connecting portion includes a third sub-portion and a fourth sub-portion, the third sub-portion is directly connected to the second area of ​​the second active layer, and the fourth sub-portion is located on a side of the third sub-portion close to the pixel electrode connecting portion and is directly connected to the pixel electrode connecting portion;

[0018] The third connecting portion includes a fifth sub-portion, a sixth sub-portion and a seventh sub-portion, the fifth sub-portion and the seventh sub-portion are respectively connected to both sides of the sixth sub-portion, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and the orthographic projection of the sixth sub-portion on the base substrate does not overlap with the orthographic projections of the first active layer and the second active layer on the base substrate; and

[0019] A minimum dimension of at least one of the second sub-section, the fourth sub-section and the sixth sub-section along the extension direction of the first virtual linear axis is smaller than a minimum dimension of at least one of the first sub-section, the third sub-section, the fifth sub-section and the seventh sub-section along the extension direction of the first virtual linear axis.

[0020] According to some exemplary embodiments, the first active layer and the second active layer are arranged at intervals along the first direction, a size of the first active layer along the first direction is larger than a size along the second direction, and a size of the second active layer along the first direction is larger than a size along the second direction; and

[0021] The first area and the second area of ​​the first active layer are arranged at intervals along the second direction, the first area and the second area of ​​the second active layer are arranged at intervals along the second direction, the first area of ​​the second active layer is located on one side of the second area of ​​the first active layer along the first direction, the second area of ​​the second active layer is located on one side of the first area of ​​the first active layer along the first direction, and the pixel electrode connection portion is located on a side of the second area of ​​the second active layer away from the first area of ​​the second active layer along the second direction.

[0022] According to some exemplary embodiments, the first connection portion is in a strip shape extending along the first direction, and the second portion of the second connection portion and the first connection portion are axially symmetrically arranged with respect to the first virtual straight line; and

[0023] The second connecting portion further includes a third portion, the third portion is located at one side of the second portion along the second direction, and the third portion connects the second portion and the pixel electrode connecting portion.

[0024] According to some exemplary embodiments, the second connection portion is in an L-shape rotated 90° counterclockwise, and the first portion of the first connection portion and the second connection portion are symmetrically arranged relative to the first virtual straight line axis; and

[0025] The first connection portion further includes a fourth portion connected to a side of the first portion away from the second connection portion along the first direction, and the fourth portion electrically connects the first portion and the data line.

[0026] According to some exemplary embodiments, the sub-pixel further includes a gate electrically connected to the scan line, an orthographic projection of the gate on the base substrate and an orthographic projection of the first active layer on the base substrate at least partially overlap, and an orthographic projection of the gate on the base substrate and an orthographic projection of the second active layer on the base substrate at least partially overlap;

[0027] The gate has at least one notch, which is partially recessed into the gate along the second direction, and the orthographic projection of the notch on the base substrate is located between the orthographic projection of the first active layer on the base substrate and the orthographic projection of the second active layer on the base substrate.

[0028] According to some exemplary embodiments, the sub-pixel further includes a gate electrically connected to the scan line, an orthographic projection of the gate on the base substrate and an orthographic projection of the first active layer on the base substrate at least partially overlap, and an orthographic projection of the gate on the base substrate and an orthographic projection of the second active layer on the base substrate at least partially overlap; and

[0029] The gate includes a first edge and a second edge located at both sides of the second direction, the first edge continuously extends along the first direction, and the second edge continuously extends along the first direction.

[0030] According to some exemplary embodiments, the third connecting portion includes a fifth sub-portion, a sixth sub-portion, and a seventh sub-portion, the fifth sub-portion and the seventh sub-portion are respectively connected to both sides of the sixth sub-portion along the first direction, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and the orthographic projection of the sixth sub-portion on the base substrate does not overlap with the orthographic projections of the first active layer and the second active layer on the base substrate;

[0031] The fifth sub-section and the seventh sub-section are both in the shape of strips extending along the first direction, the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the fifth sub-section along the second direction, and the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the seventh sub-section along the second direction

[0032] According to some exemplary embodiments, the first active layer and the second active layer are arranged at intervals along the first direction, a size of the first active layer along the first direction is smaller than a size along the second direction, and a size of the second active layer along the first direction is smaller than a size along the second direction; and

[0033] The first area and the second area of ​​the first active layer are arranged at intervals along the first direction, the first area and the second area of ​​the second active layer are arranged at intervals along the first direction, the first area of ​​the second active layer is located on a side of the second area of ​​the first active layer away from the first area of ​​the first active layer, and the pixel electrode connecting portion is located on a side of the second area of ​​the second active layer away from the first area of ​​the second active layer along the first direction.

[0034] According to some exemplary embodiments, the first sub-portion is in the shape of a long strip extending along the second direction, the second sub-portion is connected to a side of the first sub-portion along the first direction and away from the second active layer, and the minimum size of the second sub-portion along the second direction is smaller than the minimum size of the first sub-portion along the second direction; and / or,

[0035] The third sub-portion is in the shape of a long strip extending along the second direction, the fourth sub-portion is connected to a side of the second sub-portion along the first direction and away from the first active layer, and the minimum size of the fourth sub-portion along the second direction is smaller than the minimum size of the third sub-portion along the second direction; and / or,

[0036] The fifth sub-section and the seventh sub-section are both in the shape of long strips extending along the second direction, the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the fifth sub-section along the second direction, and the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the seventh sub-section along the second direction.

[0037] According to some exemplary embodiments, the first active layer and the second active layer are respectively symmetrical with respect to a second virtual straight line axis, and the second virtual straight line axis passes through at least one of the second sub-portion, the fourth sub-portion, and the sixth sub-portion.

[0038] According to some exemplary embodiments, the first subsection and the third subsection are symmetrically arranged with respect to the first virtual straight line axis, and at least a portion of the second subsection and at least a portion of the fourth subsection are symmetrically arranged with respect to the first virtual straight line axis.

[0039] In another aspect, an array substrate is provided, the array substrate comprising:

[0040] substrate substrate;

[0041] A plurality of scanning lines are located on the substrate, and the plurality of scanning lines extend along a first direction and are arranged along a second direction;

[0042] a plurality of data lines, located on the base substrate, the plurality of data lines extending along the second direction and arranged along the first direction; and

[0043] A plurality of sub-pixels are located on the base substrate, the plurality of sub-pixels are arranged in an array along the first direction and the second direction, the sub-pixels include a first active layer, a second active layer and a pixel electrode, a first area of ​​the first active layer is electrically connected to one of the data lines, a second area of ​​the first active layer is electrically connected to a first area of ​​the second active layer, and a second area of ​​the second active layer is electrically connected to the pixel electrode;

[0044] The sub-pixel further comprises a first connection portion, a second connection portion and a pixel electrode connection portion, the first connection portion electrically connects the data line and the first area of ​​the first active layer, the second connection portion electrically connects the second area of ​​the second active layer and the pixel electrode connection portion, and the pixel electrode connection portion is directly connected to the pixel electrode;

[0045] The first connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is directly connected to the first region of the first active layer, and the second sub-portion is located at a side of the first sub-portion close to the data line and is directly connected to the data line;

[0046] The second connecting portion includes a third sub-portion and a fourth sub-portion, the third sub-portion is directly connected to the second area of ​​the second active layer, and the fourth sub-portion is located on a side of the third sub-portion close to the pixel electrode connecting portion and is directly connected to the pixel electrode connecting portion;

[0047] The third connecting portion includes a fifth sub-portion, a sixth sub-portion and a seventh sub-portion, the fifth sub-portion and the seventh sub-portion are respectively connected to both sides of the sixth sub-portion, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and the orthographic projection of the sixth sub-portion on the base substrate does not overlap with the orthographic projections of the first active layer and the second active layer on the base substrate; and

[0048] A minimum dimension of at least one of the second sub-section, the fourth sub-section and the sixth sub-section along the extension direction of the first virtual linear axis is smaller than a minimum dimension of at least one of the first sub-section, the third sub-section, the fifth sub-section and the seventh sub-section along the extension direction of the first virtual linear axis.

[0049] In another aspect, a display panel is provided, comprising the array substrate as described in any one of the above items.

[0050] In another aspect, a display device is provided, wherein the display device is the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0052] Figure 1 A schematic plan view of an array substrate in the related art is shown schematically.

[0053] Figure 2 A schematic plan view of another array substrate in the related art is shown.

[0054] Figure 3A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0055] Figure 3B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown.

[0056] Figure 4 The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0057] Figure 5 The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0058] Figure 6 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein: Figure 6 Indicated Figure 3A A cross-sectional view taken along line AA'.

[0059] Figure 7 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein: Figure 7 Indicated Figure 5 A cross-sectional view taken along line BB'.

[0060] Fig. 8A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0061] Figure 8B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown.

[0062] Fig. 9 The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0063] Fig.10 The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0064] Fig.11A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0065] Fig. 11B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown.

[0066] Fig. 12A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0067] Fig. 12B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown.

[0068] Fig.13A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0069] Fig. 13B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown.

[0070] Fig.14 The plan view of the array substrate according to some embodiments of the present disclosure is schematically shown, wherein Fig.14 Indicated along Fig.11A Cross-section taken along center line CC'.

[0071] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0072] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0073] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0074] When an element is described as "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on another element, directly connected to another element or directly coupled to another element, or there may be an intermediate element. However, when an element is described as "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to physical connection, electrical connection, communication connection and / or fluid connection. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0075] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, a first element may be named a second element, and similarly, a second element may be named a first element.

[0076] Figure 1 A schematic plan view of an array substrate in the related art is shown schematically. Figure 2 A schematic plan view of another array substrate in the related art is shown.

[0077] Reference Figure 1 or Figure 2 The array substrate includes two transistors connected in series. Compared with a substrate including only one transistor, the dual-transistor structure has a lower off-state leakage current and is particularly suitable for bistable driven products, such as Electronic Shelf Label (ESL) products.

[0078] In such an array substrate having dual series transistors, the two transistors have an asymmetric structure, for example Figure 1 and Figure 2The inventors have found that this asymmetric structure will cause resistance differences, resulting in differences in the hysteresis characteristics of the two transistors, which will in turn cause increased display power consumption, white point defects, crosstalk, and afterimages.

[0079] Figure 3A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 3B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown. Figure 4 The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 5 The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 6 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein: Figure 6 Indicated Figure 3A A cross-sectional view taken along line AA'. Figure 7 A cross-sectional view of an array substrate according to some embodiments of the present disclosure is schematically shown, wherein: Figure 7 Indicated Figure 5 A cross-sectional view taken along line BB'.

[0080] Combined with reference Figure 3A and Figure 3B , the display substrate includes a plurality of scan lines SL, a plurality of data lines DL, and a plurality of sub-pixels SP. The plurality of scan lines SL extend along a first direction X and are arranged along a second direction Y, and the plurality of data lines DL extend along a second direction Y and are arranged along the first direction X. The plurality of sub-pixels SP are arranged in an array along the first direction X and the second direction Y, and the sub-pixels SP include a first active layer 310, a second active layer 320, and a pixel electrode 510. The first active layer 310 includes a channel region 311 and a first region 312 and a second region 313 located on both sides of the channel region 311, and the second active layer 320 includes a channel region 321 and a first region 322 and a second region 323 located on both sides of the channel region 321. The first region 312 of the first active layer 310 is electrically connected to a data line DL, the second region 313 of the first active layer 310 is electrically connected to the first region 322 of the second active layer 320, and the second region 323 of the second active layer 320 is electrically connected to the pixel electrode 510.

[0081] The sub-pixel SP further includes a first connection portion 410, a second connection portion 420, a third connection portion 430, a gate electrode 210, and a pixel electrode connection portion 440. The first connection portion 410 electrically connects the data line DL and the first area 312 of the first active layer 310, the second connection portion 420 electrically connects the second area 323 of the second active layer 320 and the pixel electrode connection portion 440, the pixel electrode connection portion 440 is directly connected to the pixel electrode 510, and the third connection portion 430 electrically connects the second area 313 of the first active layer 310 and the first area 322 of the second active layer 320. The gate electrode 210 is electrically connected to a scanning line SL, and the orthographic projection of the gate electrode 210 on the substrate overlaps with the orthographic projection of the channel area 311 of the first active layer 310 on the substrate, and the orthographic projection of the gate electrode 210 on the substrate overlaps with the orthographic projection of the channel area 321 of the second active layer 320 on the substrate. A portion of the scan line SL may be thickened as the gate electrode 210 of the first active layer 310 and the second active layer 320 .

[0082] The first active layer 310, the first connecting portion 410, a portion of the third connecting portion 430 and a portion of the gate 210 constitute a first transistor T1, the second active layer 320, another portion of the third connecting portion 430, the second connecting portion 420 and another portion of the gate 210 constitute a second transistor T2, and the third connecting portion 430 realizes a series connection between the first transistor T1 and the second transistor T2.

[0083] Continue to refer to Figure 3A and Figure 3B , the total extension length of the first connection portion 410 is the first length, the average width of the first connection portion 410 in a direction perpendicular to the extension direction thereof is the first width, the total extension length of the second connection portion 420 is the second length, the average width of the second connection portion 420 in a direction perpendicular to the extension direction thereof is the second width, the deviation ratio of the first length to the second length is less than or equal to 10%, and the deviation ratio of the first width to the second width is less than or equal to 10%. By setting the difference between the total extension length and the average width of the first connection portion 410 and the second connection portion 420 to be relatively small, the difference between the resistance of the first connection portion 410 and the resistance of the second connection portion 420 can be made small, thereby effectively avoiding display defects caused by the difference in hysteresis characteristics between the first transistor T1 and the second transistor T2.

[0084] It should be noted that the shape of the connecting portion is a straight strip or a broken line strip, and the total extension length of the connecting portion should be understood as the distance extending from one end along its edge contour to the other end. Figure 3B The total extended length of the first connection portion 410 is L1, and the total extended length of the second connection portion 420 is the sum of L2 and L3, wherein 90%*(L2+L3)≤L1≤110%*(L2+L3).

[0085] The connecting portion can be designed with equal width or unequal width. When the connecting portion is designed with equal width, the average width of the connecting portion is the width at any position. When the connecting portion is designed with unequal width, the average width of the connecting portion can be calculated based on the actual shape of the connecting portion (for example, it can be calculated by the ratio of the total area of ​​the connecting portion to the total extension length).

[0086] For example, refer to Figure 3B The first connection portion 410 and the second connection portion 420 are both designed with equal width, the average width of the first connection portion 410 is W1, and the average width of the second connection portion 420 is W2, wherein 90%*W2≤W1≤110%*W2.

[0087] According to some exemplary embodiments, in combination with reference Figure 3A and Figure 6 The array substrate may include a base substrate 100, a gate metal layer 200 located on the base substrate 100, a gate insulating layer GI located on the side of the gate metal layer 200 away from the base substrate 100, a semiconductor layer 300 located on the side of the gate insulating layer GI away from the base substrate 100, a source-drain metal layer 400 located on the side of the semiconductor layer 300 away from the base substrate 100, a passivation layer PVX located on the side of the source-drain metal layer 400 away from the base substrate 100, and a pixel electrode layer 500 located on the side of the passivation layer PVX away from the base substrate 100.

[0088] The gate electrode 210 and the scan line SL are located in the gate metal layer 200, the first active layer 310 and the second active layer 320 are located in the semiconductor layer 300, the data line DL, the first connection part 410, the second connection part 420, the third connection part 430 and the pixel electrode connection part 440 are located in the source-drain metal layer 400, and the pixel electrode 510 is located in the pixel electrode layer 500. The passivation layer PVX includes a first via hole V01, and the pixel electrode 510 is electrically connected to the pixel electrode connection part 440 through the first via hole V01.

[0089] It should be noted that the first connection portion 410 and the data line DL are connected into an integrated structure, and there is no obvious dividing line between the first connection portion 410 and the data line DL. The linear structure extending along the second direction Y is the data line DL, and the structure protruding toward the first direction X compared to the data line DL is the first connection portion 410.

[0090] The second connection portion 420 and the pixel electrode connection portion 440 are connected to form an integral structure, and there is no obvious dividing line between the second connection portion 420 and the pixel electrode connection portion 440. The shape of the pixel electrode connection portion 440 is, for example, a square. The width of one end of the second connection portion 420 connected to the pixel electrode 510 may be significantly smaller than the size of the pixel electrode connection portion 440. The position where the edge shape and size suddenly change should be considered as the dividing line between the pixel electrode connection portion 440 and the second connection portion 420.

[0091] When the width of the end of the second connection portion 420 connected to the pixel electrode 510 is substantially equal to the size of the pixel electrode connection portion 440, the edge of the pixel electrode connection portion 440 can be determined in conjunction with the position of the first via hole V01. Figure 3A The orthographic projection of the first via hole V01 on the base substrate is approximately located at the center of the pixel electrode connecting portion 440 on the base substrate.

[0092] It should be noted that the source-drain metal layer 400 and the semiconductor layer 300 can be formed in the same patterning process using a halftone mask, so there is a semiconductor layer 300 under the source-drain metal layer 400, and the excess portion of the semiconductor layer 300 compared to the source-drain metal layer 400 is the channel region of the active layer.

[0093] According to some exemplary embodiments, in combination with reference Figure 3A and Figure 6 , the sub-pixel SP also includes a storage capacitor Cst, the storage capacitor Cst includes a first capacitor plate 220 and a second capacitor plate 450, the first capacitor plate 220 can be located in the gate metal layer 200, and the second capacitor plate 450 can be located in the source-drain metal layer 400. The passivation layer PVX and the gate insulating layer GI include a second via hole V02, the pixel electrode 510 is electrically connected to the first capacitor plate 220 through the second via hole V02, and the pixel electrode 510 connects the pixel voltage signal to the first capacitor plate 220. A plurality of second capacitor plates 450 arranged at intervals along the second direction Y are connected in a row through a plurality of capacitor connecting portions 460 and connected to a voltage signal different from the pixel voltage signal in the peripheral area.

[0094] According to some exemplary embodiments, in combination with reference Figure 3A and Figure 3BThe first active layer 310 and the second active layer 320 are symmetrically arranged compared to the first virtual linear axis A1, and the first part of the first connecting part 410 and the second part of the first connecting part 410 are symmetrically arranged compared to the first virtual linear axis A1. By arranging at least a part of the first connecting part 410 and at least a part of the second connecting part 420 to be symmetrical compared to the first virtual linear axis A1, the difference in extension length and average width of the first connecting part 410 and the second connecting part 420 can be reduced, thereby making the difference in resistance of the first connecting part 410 and the second connecting part 420 smaller.

[0095] According to some exemplary embodiments, in combination with reference Figure 3A and Figure 3B The third connection portion 430 is symmetrically arranged compared to the first virtual straight axis A1, that is, a part of the third connection portion 430 connected to the second area 313 of the first active layer 310 and another part of the third connection portion 430 connected to the first area 322 of the second active layer 320 are symmetrical compared to the first virtual straight axis A1, which is beneficial to further avoid poor display caused by the difference in hysteresis characteristics between the first transistor T1 and the second transistor T2.

[0096] According to some exemplary embodiments, referring to Figure 3A , the first active layer 310 and the second active layer 320 are arranged at intervals along the first direction X, and the first virtual linear axis A1 extends along the second direction Y. The size of the first active layer 310 along the first direction X is greater than the size along the second direction Y, and the first area 312 and the second area 313 of the first active layer 310 are arranged at intervals along the second direction Y; the size of the second active layer 320 along the first direction X is greater than the size along the second direction Y, and the first area 322 and the second area 323 of the second active layer 320 are arranged at intervals along the second direction Y.

[0097] The first area 322 of the second active layer 320 is located on one side of the second area 313 of the first active layer 310 along the first direction X, the second area 323 of the second active layer 320 is located on one side of the first area 312 of the first active layer 310 along the first direction X, and the pixel electrode connection portion 440 is located on a side of the second area 323 of the second active layer 320 away from the first area 322 of the second active layer 320 along the second direction Y.

[0098] According to some exemplary embodiments, in combination with reference Figure 3A and Figure 3BThe first connection portion 410 is in a strip shape extending along the first direction X. One end of the first connection portion 410 extends along the first direction X to connect with the data line DL, and the other end of the first connection portion 410 extends along the first direction X to connect with the first region 312 of the first active layer 310. The second portion 420A of the second connection portion 420 is symmetrically arranged with the first connection portion 410 relative to the first virtual linear axis A1. The second connection portion 420 further includes a third portion 420B, which is located at one side of the second portion 420A along the second direction Y. The third portion 420B connects the second portion 420A and the pixel electrode connection portion 440.

[0099] According to some exemplary embodiments, referring to Figure 3B The extension width of the third portion 420B is equal to the extension width of the second portion 420A, the shape of the orthographic projection of the third portion 420B on the substrate plate is a rectangle, the edge of the third portion 420B away from the first connection portion 410 along the first direction X is flush with the edge of the second portion 420A away from the first connection portion 410 along the first direction X, and the shape of the orthographic projection of the second connection portion 420 on the substrate substrate is an L-shape rotated 90° counterclockwise.

[0100] Fig. 8A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Figure 8B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown. Fig. 9 The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Fig.10 The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0101] According to some exemplary embodiments, in combination with reference Fig. 8A and Figure 8B , the second connection portion 420 is L-shaped rotated 90° counterclockwise, and the first portion 410A of the first connection portion 410 and the second connection portion 420 are symmetrically arranged relative to the first virtual linear axis A1. The first connection portion 410 also includes a fourth portion 410B, which is connected to a side of the first portion 410A away from the second connection portion 420 along the first direction X, and the fourth portion 410B electrically connects the first portion 410A and the data line DL.

[0102] According to some exemplary embodiments, referring to Fig. 8A The first connection portion 410 is designed to have an equal width at all locations, and the second connection portion 420 is designed to have an equal width at all locations.

[0103] According to some exemplary embodiments, referring to Figure 8BThe edge of the fourth portion 410B away from the third connection portion 430 along the second direction Y is flush with the edge of the first portion 410A away from the third connection portion 430 along the second direction Y, and the orthographic projection of the first connection portion 410 on the substrate is roughly Z-shaped.

[0104] According to some exemplary embodiments, referring to Figure 4 and Fig. 9 The gate 210 has at least one notch 211, and the notch 211 is partially recessed into the gate 210 along the second direction Y. The orthographic projection of the notch 211 on the substrate is located between the orthographic projection of the first active layer 310 on the substrate and the orthographic projection of the second active layer 320 on the substrate. The notch 211 is provided at the portion of the gate 210 between the first active layer 310 and the second active layer 320. At the location of the notch 211, the size of the gate 210 along the second direction Y is narrowed, which is beneficial to reducing the leakage current of the transistor.

[0105] It should be noted that in Figure 4 and Fig. 9 In the illustrated structure, the notch 211 is only provided on one side of the gate 210 along the second direction Y. The notch 211 may also be provided on both sides of the gate 210 along the second direction Y according to actual process requirements.

[0106] According to some exemplary embodiments, referring to Figure 5 and Fig.10 , the gate 210 includes a first edge 212 and a second edge 213 located on both sides of the second direction Y, the first edge 212 extends continuously along the first direction X, and the second edge 213 extends continuously along the first direction X. That is, compared to Figure 4 and Fig. 9 In the structure, the gate 210 is not provided with the notch 211, so that the resistance of the gate 210 can be reduced.

[0107] Combined with reference Figure 6 and Figure 7 , Figure 6 The schematic diagram is a cross-sectional view of a notch 211 provided in the gate 210. Figure 7 The diagram shows a cross-sectional view of the gate 210 with and without the notch 211 .

[0108] According to some exemplary embodiments, referring to Figure 4 and Fig. 9The third connection portion 430 includes a fifth sub-portion 431, a sixth sub-portion 432 and a seventh sub-portion 433. The fifth sub-portion 431 and the seventh sub-portion 433 are respectively connected to the two sides of the sixth sub-portion 432 along the first direction X. The fifth sub-portion 431 is directly connected to the second area 313 of the first active layer 310. The seventh sub-portion 433 is directly connected to the first area 322 of the second active layer 320. The orthographic projection of the sixth sub-portion 432 on the substrate substrate does not overlap with the orthographic projections of the first active layer 310 and the second active layer 320 on the substrate substrate. The fifth sub-portion 431 and the seventh sub-portion 433 are both in the shape of strips extending along the first direction X. The minimum dimension of the sixth sub-portion 432 along the second direction Y is smaller than the minimum dimension of the fifth sub-portion 431 along the second direction Y. The minimum dimension of the sixth sub-portion 432 along the second direction Y is smaller than the minimum dimension of the seventh sub-portion 433 along the second direction Y. By narrowing the size of the fifth sub-portion 431 of the third connection portion 430 located between the first active layer 310 and the second active layer 320 along the second direction Y, the leakage current of the transistor can be effectively reduced.

[0109] For example, the fifth sub-section 431 and the seventh sub-section 433 are both equal-width strip structures, and the widths of the fifth sub-section 431 and the seventh sub-section 433 are equal, the shape of the sixth sub-section 432 is rectangular, the width W3 of the sixth sub-section 432 is smaller than the width W4 of the fifth sub-section 431, the width W3 of the sixth sub-section 432 is smaller than the width W5 of the seventh sub-section 433, and the width W4 of the fifth sub-section 431 is equal to the width W5 of the seventh sub-section 433.

[0110] Fig.11A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Fig. 11B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown. Fig. 12A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Fig. 12B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown. Fig.13A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown. Fig. 13B The plan view of the source-drain metal layer of the array substrate according to some embodiments of the present disclosure is schematically shown. Fig.14 The plan view of the array substrate according to some embodiments of the present disclosure is schematically shown, wherein Fig.14 Indicated along Fig.11A Cross-section taken along center line CC'.

[0111] According to some exemplary embodiments, referring to Fig.11AThe first active layer 310 and the second active layer 320 are arranged at intervals along the second direction Y, the size of the first active layer 310 along the first direction X is smaller than the size along the second direction Y, and the first area 312 and the second area 313 of the first active layer 310 are arranged at intervals along the first direction X; the size of the second active layer 320 along the first direction X is smaller than the size along the second direction Y, and the first area 322 and the second area 323 of the second active layer 320 are arranged at intervals along the first direction X. The first area 322 of the second active layer 320 is located on a side of the second area 313 of the first active layer 310 away from the first area 312 of the first active layer 310, and the pixel electrode connecting portion 440 is located on a side of the second area 323 of the second active layer 320 away from the first area 322 of the second active layer 320 along the first direction X, that is, the first area 312 of the first active layer 310, the second area 313 of the first active layer 310, the first area 322 of the second active layer 320, and the second area 323 of the second active layer 320 are arranged in sequence along the first direction X.

[0112] According to some exemplary embodiments, in combination with reference Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B The first connection portion 410 includes a first sub-portion 411 and a second sub-portion 412. The first sub-portion 411 is directly connected to the first area 312 of the first active layer 310. The second sub-portion 412 is located on a side of the first sub-portion 411 close to the data line DL and is directly connected to the data line DL. The second connection portion 420 includes a third sub-portion 421 and a fourth sub-portion 422. The third sub-portion 421 is directly connected to the second area 323 of the second active layer 320. The fourth sub-portion 422 is located on a side of the third sub-portion 421 close to the pixel electrode connection portion 440 and is directly connected to the pixel electrode connection portion 440. The third connecting portion 430 includes a fifth sub-portion 431, a sixth sub-portion 432 and a seventh sub-portion 433, the fifth sub-portion 431 and the seventh sub-portion 433 are respectively connected to the two sides of the sixth sub-portion 432, the fifth sub-portion 431 is directly connected to the second area 313 of the first active layer 310, the seventh sub-portion 433 is directly connected to the first area 322 of the second active layer 320, and the orthographic projection of the sixth sub-portion 432 on the substrate does not overlap with the orthographic projections of the first active layer 310 and the second active layer 320 on the substrate.

[0113] The minimum size of at least one of the second sub-portion 412, the fourth sub-portion 422 and the sixth sub-portion 432 along the extension direction of the first virtual linear axis A1 is smaller than the minimum size of at least one of the first sub-portion 411, the third sub-portion 421, the fifth sub-portion 431 and the seventh sub-portion 433 along the extension direction of the first virtual linear axis A1. That is, the leakage current of the transistor can be effectively reduced by narrowing the size of at least one of the second sub-portion 412 (the end where the first connecting portion 410 is connected to the data line DL), the fourth sub-portion 422 (the end where the second connecting portion 420 is connected to the pixel electrode connecting portion 440) and the sixth sub-portion 432 (the portion of the third connecting portion 430 located between the first active layer 310 and the second active layer 320) along the extension direction of the first virtual linear axis A1, as described in detail below with reference to the accompanying drawings. The dimension of at least one of the second sub-portion 412 , the fourth sub-portion 422 , and the sixth sub-portion 432 along the extension direction of the first virtual linear axis A1 may be set to be smaller according to the process capability, for example, the dimension is 3-5 μm.

[0114] According to some exemplary embodiments, in combination with reference Fig. 12A and Fig. 12B The first sub-portion 411 is in the shape of a long strip extending along the second direction Y, the shape of the orthographic projection of the second sub-portion 412 on the substrate includes a rectangle, the second sub-portion 412 is connected to the first sub-portion 411 along the first direction X and away from the side of the second connecting portion 420 and connected to the data line DL, and the dimension W6 of the second sub-portion 412 along the second direction Y is smaller than the dimension W7 of the first sub-portion 411 along the second direction Y.

[0115] According to some exemplary embodiments, in combination with reference Fig.13A and Fig. 13B The third sub-portion 421 is in the shape of a long strip extending along the second direction Y, the shape of the positive projection of the fourth sub-portion 422 on the substrate includes a rectangle, the fourth sub-portion 422 is connected to the third sub-portion 421 along the first direction X and away from the side of the first active layer 310, and the dimension W8 of the fourth sub-portion 422 along the second direction Y is smaller than the dimension W9 of the third sub-portion 421 along the second direction Y.

[0116] According to some exemplary embodiments, in combination with reference Fig.11A Fig. 11BThe fifth sub-portion 431 and the seventh sub-portion 433 are both in the shape of long strips extending along the second direction Y, the shape of the orthographic projection of the sixth sub-portion 432 on the substrate includes a rectangle, the dimension W10 of the sixth sub-portion 432 along the second direction Y is smaller than the dimension W11 of the fifth sub-portion 431 along the second direction Y, the dimension W10 of the sixth sub-portion 432 along the second direction Y is smaller than the dimension W12 of the seventh sub-portion 433 along the second direction Y, the dimension W11 of the fifth sub-portion 431 along the second direction Y is equal to the dimension W12 of the seventh sub-portion 433 along the second direction Y, and the orthographic projection of the third connecting portion 430 on the substrate is H-shaped.

[0117] According to some exemplary embodiments, in combination with reference Fig.13A and Fig. 13B The total extended length of the first connection portion 410 is the first length, the average width of the first connection portion 410 in a direction perpendicular to its extending direction is the first width, the total extended length of the second connection portion 420 is the second length, the average width of the second connection portion 420 in a direction perpendicular to its extending direction is the second width, the deviation ratio of the first length to the second length is less than or equal to 10%, and the deviation ratio of the first width to the second width is less than or equal to 10%.

[0118] It should be noted that when the connecting portion is not a continuously extending strip structure, the connecting portion should include a plurality of connected sub-portions that extend independently, and the total extension length of the connecting portion should be the sum of the lengths of the respective extensions of the sub-portions. For example, the first connecting portion 410 is not a continuously extending strip structure, and the total extension length of the first connecting portion 410 should be understood as the sum of the extension length L4 of the first sub-portion 411 (that is, the dimension W7 of the first sub-portion 411 along the second direction Y) and the extension length L5 of the second sub-portion 412. Similarly, the total extension length of the second connecting portion 420 should be understood as the sum of the extension length L6 of the third sub-portion 421 (that is, the dimension W9 of the third sub-portion 421 along the second direction Y) and the extension length L7 of the fourth sub-portion 422.

[0119] According to some exemplary embodiments, in combination with reference Fig.13A and Fig. 13B At least a portion of the first connecting portion 410 and at least a portion of the second connecting portion 420 are symmetrically arranged relative to the first virtual linear axis A1. For example, the first sub-portion 411 and the third sub-portion 421 are symmetrically arranged relative to the first virtual linear axis A1, and at least a portion of the second sub-portion 412 and at least a portion of the fourth sub-portion 422 are symmetrically arranged relative to the first virtual linear axis A1.

[0120] According to some exemplary embodiments, in combination with reference Fig.13A and Fig. 13BThe first connecting portion 410 and the second connecting portion 420 are symmetrically arranged compared to the first virtual linear axis A1, the first sub-portion 411 and the third sub-portion 421 are symmetrically arranged compared to the first virtual linear axis A1, and the second sub-portion 412 and the fourth sub-portion 422 are symmetrically arranged compared to the first virtual linear axis A1 (the pixel electrode connecting portion 440 can be adjusted so that the size of the second sub-portion 412 along the first direction X is equal to the size of the fourth sub-portion 422 along the first direction X).

[0121] According to some exemplary embodiments, in combination with reference Fig.13A and Fig. 13B The first active layer 310 and the second active layer 320 are symmetrical with respect to a second virtual linear axis A2, and the second virtual linear axis A2 passes through at least one of the second sub-portion 412, the fourth sub-portion 422 and the sixth sub-portion 432, that is, the second sub-portion 412, the fourth sub-portion 422 or the sixth sub-portion 432 with a narrower width is arranged at a relatively central position of the first active layer 310 and the second active layer 320 along the second direction Y, which can make the electric field and the carrier distribution in the first active layer 310 and the second active layer 320 more symmetrical and uniform, so that it is easier to be controlled by the gate 210, the leakage current is smaller, and at the same time, the current crowding can be reduced, thereby reducing power consumption and heat.

[0122] For example, the first connection portion 410 is symmetrical with respect to the second virtual linear axis A2, and / or the second connection portion 420 is symmetrical with respect to the second virtual linear axis A2, and / or the third connection portion 430 is symmetrical with respect to the second virtual linear axis A2.

[0123] According to some exemplary embodiments, in combination with reference Fig.11A and Fig.14 The array substrate may further include an organic insulating layer ORG, the organic insulating layer ORG is located between the passivation layer PVX and the pixel electrode layer 500, the organic insulating layer ORG includes a third via hole V03, the orthographic projection of the first via hole V01 on the base substrate is located within the orthographic projection of the third via hole V03 on the base substrate, and the orthographic projection of the second via hole V02 on the base substrate is located within the orthographic projection of the third via hole V03 on the base substrate. The pixel electrode 510 is electrically connected to the pixel electrode connecting portion 440 through the first via hole V01 and the third via hole V03, and the pixel electrode 510 is electrically connected to the first capacitor plate 220 through the second via hole V02 and the third via hole V03.

[0124] At least some embodiments of the present disclosure also provide a display panel, which includes the array substrate as described above.

[0125] For example, the display panel may further include an electronic ink layer located on the array substrate, an opposing electrode located on a side of the electronic ink layer away from the base substrate, and an opposing substrate located on a side of the opposing electrode away from the base substrate.

[0126] At least some embodiments of the present disclosure also provide a display device, which includes the display substrate described above. The display device may include any device or product with a display function. For example, the display device may be an e-book reader, a smart tag, a smart watch, a digital sign, etc.

[0127] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate, and these features and advantages can be referred to the above description of the display substrate, which will not be repeated here.

[0128] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0129] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, wherein: The array substrate comprises: substrate substrate; A plurality of scanning lines are located on the substrate, and the plurality of scanning lines extend along a first direction and are arranged along a second direction; a plurality of data lines, located on the base substrate, the plurality of data lines extending along the second direction and arranged along the first direction; and A plurality of sub-pixels are located on the base substrate, the plurality of sub-pixels are arranged in an array along the first direction and the second direction, the sub-pixels include a first active layer, a second active layer and a pixel electrode, a first area of ​​the first active layer is electrically connected to one of the data lines, a second area of ​​the first active layer is electrically connected to a first area of ​​the second active layer, and a second area of ​​the second active layer is electrically connected to the pixel electrode; The sub-pixel further comprises a first connection portion, a second connection portion and a pixel electrode connection portion, the first connection portion electrically connects the data line and the first area of ​​the first active layer, the second connection portion electrically connects the second area of ​​the second active layer and the pixel electrode connection portion, and the pixel electrode connection portion is directly connected to the pixel electrode; and The total extended length of the first connecting portion is a first length, the average width of the first connecting portion in a direction perpendicular to its extending direction is a first width, the total extended length of the second connecting portion is a second length, the average width of the second connecting portion in a direction perpendicular to its extending direction is a second width, the deviation ratio of the first length compared to the second length is less than or equal to 10%, and the deviation ratio of the first width compared to the second width is less than or equal to 10%.

2. The array substrate according to claim 1, wherein: The first active layer and the second active layer are arranged symmetrically with respect to a first virtual straight line, and the first portion of the first connecting portion and at least the second portion of the first connecting portion are arranged symmetrically with respect to the first virtual straight line.

3. The array substrate according to claim 1 or 2, wherein: The first part of the first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line, or, The second parts of the first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line, or, The first connecting portion and the second connecting portion are arranged symmetrically with respect to the first virtual straight line.

4. The array substrate according to claim 2 or 3, wherein: The sub-pixel further includes a third connection portion, which electrically connects the second region of the first active layer and the first region of the second active layer, and the third connection portion is arranged axially symmetrically with respect to the first virtual straight line.

5. The array substrate according to claim 4, wherein: The first connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is directly connected to the first region of the first active layer, and the second sub-portion is located at a side of the first sub-portion close to the data line and is directly connected to the data line; The second connecting portion includes a third sub-portion and a fourth sub-portion, the third sub-portion is directly connected to the second area of ​​the second active layer, and the fourth sub-portion is located on a side of the third sub-portion close to the pixel electrode connecting portion and is directly connected to the pixel electrode connecting portion; The third connecting portion includes a fifth sub-portion, a sixth sub-portion and a seventh sub-portion, wherein the fifth sub-portion and the seventh sub-portion are respectively connected to two sides of the sixth sub-portion, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and the orthographic projection of the sixth sub-portion on the base substrate does not overlap with the orthographic projections of the first active layer and the second active layer on the base substrate; as well as A minimum dimension of at least one of the second sub-section, the fourth sub-section and the sixth sub-section along the extension direction of the first virtual linear axis is smaller than a minimum dimension of at least one of the first sub-section, the third sub-section, the fifth sub-section and the seventh sub-section along the extension direction of the first virtual linear axis.

6. The array substrate according to any one of claims 2 to 5, wherein: The first active layer and the second active layer are arranged at intervals along the first direction, the size of the first active layer along the first direction is larger than the size along the second direction, and the size of the second active layer along the first direction is larger than the size along the second direction; and The first area and the second area of ​​the first active layer are arranged at intervals along the second direction, the first area and the second area of ​​the second active layer are arranged at intervals along the second direction, the first area of ​​the second active layer is located on one side of the second area of ​​the first active layer along the first direction, the second area of ​​the second active layer is located on one side of the first area of ​​the first active layer along the first direction, and the pixel electrode connection portion is located on a side of the second area of ​​the second active layer away from the first area of ​​the second active layer along the second direction.

7. The array substrate according to claim 6, wherein: The first connecting portion is in a strip shape extending along the first direction, and the second portion of the second connecting portion and the first connecting portion are symmetrically arranged with respect to the first virtual straight line; and The second connecting portion further includes a third portion, the third portion is located at one side of the second portion along the second direction, and the third portion connects the second portion and the pixel electrode connecting portion.

8. The array substrate according to claim 6, wherein: The second connecting portion is in an L-shape rotated 90° counterclockwise, and the first portion of the first connecting portion and the second connecting portion are symmetrically arranged with respect to the first virtual straight line axis; and The first connection portion further includes a fourth portion connected to a side of the first portion away from the second connection portion along the first direction, and the fourth portion electrically connects the first portion and the data line.

9. The array substrate according to any one of claims 6 to 8, wherein: The sub-pixel further includes a gate electrically connected to the scan line, an orthographic projection of the gate on the base substrate and an orthographic projection of the first active layer on the base substrate at least partially overlap, and an orthographic projection of the gate on the base substrate and an orthographic projection of the second active layer on the base substrate at least partially overlap; The gate has at least one notch, which is partially recessed into the gate along the second direction, and the orthographic projection of the notch on the base substrate is located between the orthographic projection of the first active layer on the base substrate and the orthographic projection of the second active layer on the base substrate.

10. The array substrate according to any one of claims 6 to 8, wherein: The sub-pixel further includes a gate electrically connected to the scan line, an orthographic projection of the gate on the base substrate and an orthographic projection of the first active layer on the base substrate at least partially overlap, and an orthographic projection of the gate on the base substrate and an orthographic projection of the second active layer on the base substrate at least partially overlap; as well as The gate includes a first edge and a second edge located at both sides of the second direction, the first edge continuously extends along the first direction, and the second edge continuously extends along the first direction.

11. The array substrate according to any one of claims 6 to 10, wherein: The third connecting portion includes a fifth sub-portion, a sixth sub-portion and a seventh sub-portion, wherein the fifth sub-portion and the seventh sub-portion are respectively connected to two sides of the sixth sub-portion along the first direction, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and the orthographic projection of the sixth sub-portion on the base substrate does not overlap with the orthographic projections of the first active layer and the second active layer on the base substrate; as well as The fifth sub-section and the seventh sub-section are both in the shape of strips extending along the first direction, the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the fifth sub-section along the second direction, and the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the seventh sub-section along the second direction.

12. The array substrate according to claim 5, wherein: The first active layer and the second active layer are arranged at intervals along the first direction, a size of the first active layer along the first direction is smaller than a size along the second direction, and a size of the second active layer along the first direction is smaller than a size along the second direction; and The first area and the second area of ​​the first active layer are arranged at intervals along the first direction, the first area and the second area of ​​the second active layer are arranged at intervals along the first direction, the first area of ​​the second active layer is located on a side of the second area of ​​the first active layer away from the first area of ​​the first active layer, and the pixel electrode connecting portion is located on a side of the second area of ​​the second active layer away from the first area of ​​the second active layer along the first direction.

13. The array substrate according to claim 12, wherein: The first sub-portion is in the shape of a long strip extending along the second direction, the second sub-portion is connected to a side of the first sub-portion along the first direction and away from the second active layer, and the minimum size of the second sub-portion along the second direction is smaller than the minimum size of the first sub-portion along the second direction; and / or, The third sub-portion is in the shape of a long strip extending along the second direction, the fourth sub-portion is connected to a side of the second sub-portion along the first direction and away from the first active layer, and the minimum size of the fourth sub-portion along the second direction is smaller than the minimum size of the third sub-portion along the second direction; and / or, The fifth sub-section and the seventh sub-section are both in the shape of long strips extending along the second direction, the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the fifth sub-section along the second direction, and the minimum dimension of the sixth sub-section along the second direction is smaller than the minimum dimension of the seventh sub-section along the second direction.

14. The array substrate according to claim 13, wherein: The first active layer and the second active layer are respectively symmetrical with respect to a second virtual straight line axis, and the second virtual straight line axis passes through at least one of the second sub-portion, the fourth sub-portion, and the sixth sub-portion.

15. The array substrate according to any one of claims 13 or 14, wherein: The first sub-section and the third sub-section are arranged symmetrically with respect to the first virtual straight line axis, and at least a portion of the second sub-section and at least a portion of the fourth sub-section are arranged symmetrically with respect to the first virtual straight line axis.

16. An array substrate, wherein: The array substrate comprises: substrate substrate; A plurality of scanning lines are located on the substrate, and the plurality of scanning lines extend along a first direction and are arranged along a second direction; a plurality of data lines, located on the base substrate, the plurality of data lines extending along the second direction and arranged along the first direction; and A plurality of sub-pixels are located on the base substrate, the plurality of sub-pixels are arranged in an array along the first direction and the second direction, the sub-pixels include a first active layer, a second active layer and a pixel electrode, a first area of ​​the first active layer is electrically connected to one of the data lines, a second area of ​​the first active layer is electrically connected to a first area of ​​the second active layer, and a second area of ​​the second active layer is electrically connected to the pixel electrode; The sub-pixel further comprises a first connection portion, a second connection portion and a pixel electrode connection portion, the first connection portion electrically connects the data line and the first area of ​​the first active layer, the second connection portion electrically connects the second area of ​​the second active layer and the pixel electrode connection portion, and the pixel electrode connection portion is directly connected to the pixel electrode; The first connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is directly connected to the first region of the first active layer, and the second sub-portion is located at a side of the first sub-portion close to the data line and is directly connected to the data line; The second connecting portion includes a third sub-portion and a fourth sub-portion, the third sub-portion is directly connected to the second area of ​​the second active layer, and the fourth sub-portion is located on a side of the third sub-portion close to the pixel electrode connecting portion and is directly connected to the pixel electrode connecting portion; The third connecting portion includes a fifth sub-portion, a sixth sub-portion and a seventh sub-portion, the fifth sub-portion and the seventh sub-portion are respectively connected to both sides of the sixth sub-portion, the fifth sub-portion is directly connected to the second region of the first active layer, the seventh sub-portion is directly connected to the first region of the second active layer, and the orthographic projection of the sixth sub-portion on the base substrate does not overlap with the orthographic projections of the first active layer and the second active layer on the base substrate; and A minimum dimension of at least one of the second sub-section, the fourth sub-section and the sixth sub-section along the extension direction of the first virtual linear axis is smaller than a minimum dimension of at least one of the first sub-section, the third sub-section, the fifth sub-section and the seventh sub-section along the extension direction of the first virtual linear axis.

17. A display panel, wherein: The display panel comprises an array substrate according to any one of claims 1-16.

18. A display device, wherein: The display device comprises the display panel according to claim 17.

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