Row and Column Scanning Control System Based on Sleep and Wake-up Function Chip

Abstract

The present invention provides a row-column scanning control system based on a chip with sleep and wake-up functions, which consists of a linear Hall chip matrix and a main control unit. The chip matrix is arranged in an N×M structure, and each chip is provided with a sleep pin, a wake-up pin, and a signal output pin. The main control unit is provided with N groups of sleep ports, wake-up ports, and M groups of acquisition input ports. The sleep and wake-up pins of each row of chips are short-circuited to the corresponding ports, and the signal output pins of each column of chips are short-circuited to the acquisition input ports. The main control unit realizes matrix management by logically controlling the sleep and wake-up pins. The system supports high-speed progressive scanning, high-speed interlaced scanning, and medium-speed scanning modes to meet the requirements for real-time performance and power consumption optimization in different application scenarios. When a magnetic field change is detected in the sleep state, the chip can send an interrupt signal to the main control unit through the wake-up pin to achieve a fast response of the system. The present invention supports three scanning modes and has the characteristic of low power consumption, and is particularly suitable for application scenarios such as three-mode keyboards.

Description

Technical Field

[0001] The present invention relates to the field of electronic devices, and particularly to a row-column scanning control system based on a sleep and wake-up function chip. Background Art

[0002] Linear Hall chips are sensor chips widely used in the fields of industrial control and automotive electronics, which are used to detect magnetic field changes and output corresponding electrical signals. Traditional linear Hall chip control systems usually adopt a simple row-column scanning architecture, but in large-scale chip matrices, the following technical problems exist:

[0003] (1) High resource occupancy: When the number of MCU pins is limited, directly controlling the row and column signals of a large-scale chip matrix will cause the pin resources to be exhausted, restricting the scalability of the system;

[0004] (2) Insufficient real-time performance: In high-speed signal acquisition scenarios, there is a delay in row-column switching in traditional systems, making it difficult to meet the requirements of high-precision and high-speed data acquisition;

[0005] (3) Weak anti-interference ability: In a complex environment, high-frequency noise is easily superimposed on the signal, affecting the sampling accuracy of the ADC signal. Summary of the Invention

[0006] This application provides a row-column scanning control system based on a sleep and wake-up function chip, which can meet the high-speed response requirements while minimizing the overall system power consumption.

[0007] This application provides a row-column scanning control system based on a sleep and wake-up function chip, wherein the control system includes:

[0008] A linear Hall chip matrix, which is arranged in an n×m matrix structure by a plurality of the linear Hall chips, and each linear Hall chip includes:

[0009] A sleep pin, which is used to receive a sleep signal to control the working state of the chip and switch the chip to the sleep state;

[0010] A wake-up pin, which is used to receive a logic control signal to manage the output state of the chip, or output an interrupt signal to trigger system wake-up;

[0011] A main control unit, which is connected to the linear Hall chip matrix, and controls the working state switching, row-column signal switching, target row activation and signal acquisition of the chip matrix by configuring the logical combination of the sleep pin and / or the wake-up pin;

[0012] The system supports a signal output mode and an interrupt wake-up mode, and the signal output mode includes a high-speed progressive scanning mode, a high-speed interleaved row scanning mode and a medium-speed scanning mode.

[0013] Optionally, the high-speed progressive scanning mode includes:

[0014] The master control unit configures the sleep pins of all the linear Hall chips to make them in the normal working state, configures the wake-up pins according to the preset scanning logic to activate the output signal of the target row, and simultaneously controls the output states of other rows, so as to realize the row-column progressive high-speed scanning and signal acquisition of the linear Hall chip matrix.

[0015] Optionally, the high-speed interlaced scanning mode includes:

[0016] The master control unit configures the sleep pins to make the linear Hall chips in the adjacent n rows of the linear Hall chip matrix in the normal working state, and the linear Hall chips in the remaining rows remain in the sleep state; the master control unit activates the output signal of the current target row according to the preset scanning order, and at the same time the next row of the chips is already in the ready state; by dynamically adjusting the working and output states of the chip matrix, while realizing high-speed scanning and data acquisition, the system power consumption is reduced.

[0017] Optionally, the medium-speed scanning mode is applicable to power-sensitive scenarios and includes:

[0018] The master control unit only configures the sleep pins of the target row chips to make them in the working state, and the chips in the remaining rows remain in the sleep state; the master control unit configures the wake-up pins of the target row by direct control or serial communication to realize the output acquisition of the target row signal.

[0019] Optionally, in the interrupt wake-up mode, the following process is included:

[0020] The master control unit configures all the sleep pins in the linear Hall chip matrix to the low-power mode, makes all the linear Hall chips enter the low-frequency signal acquisition state, and at the same time the master control unit switches to the sleep state, only retaining the interrupt wake-up function;

[0021] All the linear Hall chips detect the change of the external magnetic field at a preset time interval;

[0022] When the change of the external magnetic field detected by any one of the linear Hall chips exceeds the set threshold, the linear Hall chip outputs the interrupt signal to the master control unit

[0023] After receiving the interrupt signal, the master control unit switches from the sleep state to the working state, reconfigures the working logic of the linear Hall chip matrix, activates the target row chips, and completes signal acquisition.

[0024] Optionally, the master control unit includes multiple groups of ports, and each group of ports includes:

[0025] Sleep ports, respectively connected to the sleep pins of each row of the linear Hall chips;

[0026] Wake-up ports, respectively connected to the wake-up pins of each row of the linear Hall chips.

[0027] Optionally, the control system further includes a shift register for achieving row-by-row dynamic control through serial communication, characterized in that:

[0028] The shift register receives the control signal from the main control unit and switches the working state of the chips row by row, activates the chips in the target row, and controls the chips in other rows to remain in the sleep state;

[0029] The main control unit activates the target row signal output or receives an interrupt signal through the wake-up port.

[0030] Optionally, the output signal supports analog voltage output or digital signal output to meet the requirements of different data acquisition devices.

[0031] Optionally, the logic control signal includes but is not limited to level signals, level inversion signals, pulse signals, timing control signals, data carrier signals, etc.

[0032] Optionally, the linear Hall chip matrix can be arranged in a dynamic n×m pattern, where n and m are any positive integers, to adapt to different signal acquisition requirements.

[0033] Optionally, make the linear Hall chips in n adjacent rows in the linear Hall chip matrix be in the normal working state, where n is any positive integer greater than or equal to 2.

[0034] Optionally, the main control unit realizes synchronous signal acquisition of multiple linear Hall chip matrices through a clock signal to meet the application requirements across matrices.

[0035] The present invention provides a row-column scanning control system based on a chip with sleep and wake-up functions, including a linear Hall chip matrix and a main control unit. The linear Hall chip matrix adopts an n×m arrangement structure, and each chip is provided with a sleep pin and a wake-up pin, which are respectively used to control the working state and signal output state of the chip, or trigger system wake-up through an interrupt signal. The main control unit realizes the switching of the working state of the chip matrix, the switching of row-column signals, the activation of the target row, and the signal acquisition system supports high-speed row-by-row scanning mode, high-speed intermittent row scanning mode, and medium-speed scanning mode to meet the requirements of real-time performance and power consumption optimization in different application scenarios. In addition, the system supports the interrupt wake-up mode, which can trigger the wake-up of the main control unit when the chip detects a magnetic field change in the standby state, realizing the combination of low-power operation and high response speed. The present invention is applicable to application scenarios such as three-mode keyboards.

[0036] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and should not limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The figure shows a schematic structural diagram of a row-column scanning control system based on a sleep and wake-up function chip provided by this application.

[0038] Figure 2 The figure shows a schematic structural diagram of a row-column scanning control system based on a sleep and wake-up function chip according to an embodiment provided by this application.

[0039] Figure 3 The figure shows a waveform diagram of a row-column scanning control system based on a sleep and wake-up function chip according to an embodiment provided by this application in a high-speed progressive scanning mode.

[0040] Figure 4 The figure shows a waveform diagram of a row-column scanning control system based on a sleep and wake-up function chip according to an embodiment provided by this application in a high-speed interlaced scanning mode.

[0041] Figure 5 The figure shows a waveform diagram of a row-column scanning control system based on a sleep and wake-up function chip according to an embodiment provided by this application in a medium-speed scanning mode.

[0042] Figure 6 The figure shows a waveform diagram of a row-column scanning control system based on a sleep and wake-up function chip according to an embodiment provided by this application in an interrupt wake-up mode.

[0043] Figure 7 The figure shows a schematic structural diagram of a row-column scanning control system based on a sleep and wake-up function chip according to another embodiment provided by this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. On the contrary, they are merely examples of devices consistent with some aspects of this application as detailed in the appended claims.

[0045] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should have the ordinary meaning understood by those of ordinary skill in the field to which this invention belongs. The terms "first", "second" and similar words used in the specification and claims of this application do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not denote a quantity limitation, but mean that there is at least one. If only referring to "one", it will be separately stated. "Plurality" or "several" means two or more. Unless otherwise indicated, words such as "front", "rear", "lower" and / or "upper" are for convenience of description only and are not limited to a position or a spatial orientation. Words such as "comprising" or "including" mean that the elements or objects appearing before "comprising" or "including" cover the elements or objects listed after "comprising" or "including" and their equivalents, and do not exclude other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. The singular forms "a", "the" and "said" used in the specification and appended claims of this application are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0046] As Figure 1 shown, this application provides a row-column scanning control system based on a sleep and wake-up function chip. The control system includes:

[0047] A linear Hall chip matrix 1, which is arranged by a plurality of the linear Hall chips 2 in an n×m matrix structure, where each linear Hall chip 2 includes:

[0048] A sleep pin SLEEP, which is used to receive a sleep signal to control the working state of the chip and switch the chip to the sleep state;

[0049] An awake pin AWAKE, which is used to receive a logic control signal to manage the output state of the chip, or output an interrupt signal to trigger system wake-up;

[0050] A main control unit MCU, which is connected to the linear Hall chip matrix, and controls the working state switching, row-column signal switching, target row activation and signal acquisition of the linear Hall chip matrix by configuring the logical combination of the sleep pin and / or the awake pin.

[0051] The control system supports a signal output mode and an interrupt wake-up mode. Among them, the signal output mode includes a high-speed progressive scanning mode, a high-speed interlaced scanning mode, and a medium-speed scanning mode.

[0052] In this embodiment, the control system includes a linear Hall chip matrix and a main control unit. The linear Hall chip matrix is composed of multiple linear Hall chips arranged in an n×m structure. Each chip is provided with a sleep pin and a wake-up pin. Among them, the sleep pin is used to receive the sleep signal output by the main control chip, so that the main control chip controls the working state of the chip through this sleep pin. The wake-up pin is used to receive a logic control signal, so that the main control chip controls the signal output state of the chip through this wake-up pin. Alternatively, the wake-up pin can also output an interrupt signal to trigger system wake-up. The main control unit realizes the switching of the working state of the chip matrix, the switching of row and column signals, the activation of the target row, and signal acquisition by dynamically configuring the logical combination of the sleep pin and the wake-up pin. This logical combination includes, but is not limited to, high and low levels, and the specific situation will be described in detail below. The system of the present invention supports a high-speed progressive scanning mode, a high-speed interlaced scanning mode, and a medium-speed scanning mode to meet the requirements for real-time performance and power consumption optimization in different application scenarios. In addition, the system supports an interrupt wake-up mode, which can trigger the wake-up of the main control unit when the chip detects a magnetic field change in the standby state, realizing the combination of low-power operation and high response speed. The present invention is applicable to application scenarios such as a three-mode keyboard. In some embodiments, the main control unit MCU includes multiple groups of ports, and each group of ports includes:

[0053] A sleep port SLEEP`, which is respectively connected to the sleep pin SLEEP of each row of the linear Hall chips;

[0054] An awake port AWAKE`, which is respectively connected to the wake-up pin AWAKE of each row of the linear Hall chips.

[0055] The main control unit is respectively connected to each row of the linear Hall chips through their respective sleep ports SLEEP` and sleep pins SLEEP, so that the main control unit transmits a sleep signal to each row of the linear Hall chips to control the switching of the chips between the normal working state and the sleep state, and through their respective awake ports AWAKE` and wake-up pins AWAKE, so that the main control unit transmits a logic control signal to each row of the linear Hall chips to manage the switching of the chips between the normal output state and the high-impedance state.

[0056] In addition, it should be noted that the number of multiple groups of ports of the main control unit matches the chip matrix structure.

[0057] In some embodiments, the linear Hall chip matrix can adopt a dynamic n×m arrangement, where n and m are any positive integers to adapt to different signal acquisition requirements.

[0058] In some embodiments, the high-speed progressive scanning mode includes:

[0059] The main control unit configures the sleep pins of all the linear Hall chips to make them in the normal working state, configures the wake-up pins according to the preset scanning logic to activate the output signals of the linear Hall chips in the target row, and simultaneously controls the output states of the linear Hall chips in other rows, so as to realize the row-by-row high-speed scanning and signal acquisition of the linear Hall chip matrix.

[0060] Specifically, in the high-speed progressive scanning mode, the main control unit configures the sleep pins of all the chips to be at a low level, so that all the chips are in the normal working state, and acquires the chip data of the target row as needed. The wake-up pins are configured to be at a high level according to the preset scanning logic, so that the chips in the target row can normally output signals. For example, as shown in Figure 2 、 Figure 3 Taking an 8×8 linear Hall chip matrix as an example, the ports of the main control unit MCU can be set to 8 groups. When it is necessary to acquire the data of the chips in the first row, the wake-up port AWAKE`0 of the main control unit MCU is at a high level, and the remaining wake-up ports AWAKE`1~AWAKE`7 are at a low level. Correspondingly, the wake-up pins of the chips in the first row are at a high level, and the wake-up pins of the chips in the remaining rows are at a low level. When it is necessary to acquire the data of the chips in the second row, the wake-up port AWAKE`1 of the main control unit is at a high level, and the remaining wake-up ports AWAKE`0, AWAKE`2~AWAKE`7 are at a low level. Correspondingly, the wake-up pins of the chips in the second row are at a high level, and the wake-up pins of the chips in the remaining rows are at a low level. In this way, the main control unit can selectively control the output signals of the chips in the target row, while the chips in the remaining non-target rows enter the sleep mode, only retaining the necessary working modules, greatly reducing unnecessary power consumption. At the same time, the main control unit reduces unnecessary data reading and processing, thereby reducing the overall system power consumption.

[0061] In some embodiments, the high-speed interlaced scanning mode includes:

[0062] The main control unit configures the sleep pins to make the linear Hall chips in n adjacent rows in the linear Hall chip matrix in the normal working state, and the linear Hall chips in the remaining rows remain in the sleep state; the main control unit activates the output signals of the linear Hall chips in the current target row according to the preset scanning order, and at the same time the linear Hall chips in the next row are already in the ready state; by dynamically adjusting the working state and output state of the linear Hall chip matrix, the system power consumption is reduced while realizing high-speed scanning and data acquisition.

[0063] In the high-speed progressive scanning mode of the previous embodiment, when the main control unit needs to collect data of the target row chips, it only controls the chips of the current target row to be in the normal working state, rather than also controlling the chips of the n adjacent rows of the current target row to be in the normal working state. However, in this embodiment, in the high-speed interlaced scanning mode, the main control unit can control multiple rows of chips to be in the normal working state at the same time. When it is necessary to collect data of the target row chips, the chips of the current target row are correspondingly activated to normally output signals, and at the same time, the chips of the next target row are controlled to be in the preparation state.

[0064] Specifically, in combination with Figure 2 、 Figure 4 shown, continue to take an 8×8 linear Hall chip matrix and two-row interlaced scanning as an example for illustration. In the high-speed interlaced scanning mode, the main control unit MCU controls the sleep ports SLEEP`0 - SLEEP`7 to achieve two-row interlaced scanning, where two rows of chips are controlled to be in the normal working state, while the chips of other rows are in the sleep state, and the outputs of the chips of each row are controlled through the wake-up ports AWAEK`0 - AWAKE`7. For example, when the main control unit needs to collect data of the first row, the sleep ports SLEEP`0 and SLEEP`1 are configured to be at a low level, the wake-up port AWAKE`0 outputs a high level, and the remaining AWAKE`1 - AWAKE`7 outputs remain at a low level. At this time, since the sleep port SLEEP`1 is at a low level, the chips of the corresponding row are in the preparation state. When the main control unit needs to collect data of the second row, the sleep ports SLEEP`1 and SLEEP`2 are configured to be at a low level, the wake-up port AWAKE`1 outputs a high level, and the outputs of the chips of the remaining rows remain at a low level. Similarly, at this time, since the sleep port SLEEP`2 is at a low level, the chips of the corresponding row are in the preparation state.

[0065] Since when the main control unit collects data of the chips of the current row, the chips of the next row are in the normal working state, at this time, only by controlling the wake-up pin AWAKE of the chips of the next row, the output of the chips of this row can be directly switched on and off. Therefore, sampling can be performed without waiting after the row scanning is switched, thus greatly improving the scanning speed of the system. In this way, compared with the high-speed progressive scanning mode, the system scanning speed in the high-speed interlaced scanning mode of this embodiment is faster and the power consumption is lower. In this way, compared with the high-speed progressive scanning mode, the system scanning speed in the high-speed interlaced scanning mode of this embodiment is faster.

[0066] In some embodiments, the main control unit configures the sleep pins to make the linear Hall chips of n adjacent rows in the linear Hall chip matrix be in the normal working state, where n is any positive integer greater than or equal to 2.

[0067] In some embodiments, the master control unit realizes synchronous signal acquisition of multiple linear Hall chip matrices through a clock signal to meet the application requirements across matrices.

[0068] In some embodiments, the medium-speed scanning mode is applicable to power-sensitive scenarios, including:

[0069] The master control unit only configures the sleep pins of the linear Hall chips in the target row to make them in the working state, and the linear Hall chips in the remaining rows remain in the sleep state; the master control unit configures the wake-up pins of the linear Hall chips in the target row through direct control or serial communication to realize the output signal acquisition of the linear Hall chips d in the target row.

[0070] In this embodiment, in the medium-speed scanning mode, the master control unit controls the output states of the chips in each row by controlling all sleep ports. Combining Figure 2 、 Figure 5 As shown, when the chip in the target row of the data collected by the master control unit is the chip in the first row, the sleep port SLEEP`0 is configured to be at a low level, and SLEEP`1~SLEEP`7 are at high levels; or, when the chip in the target row of the data collected by the master control unit is the chip in the second row, the sleep port SLEEP`1 is configured to be at a low level, and the sleep port SLEEP`0 and the sleep ports SLEEP`2~SLEEP`7 are at high levels. In this way, all rows of chip data can be collected by sequential switching. The medium-speed scanning mode has lower power consumption compared to the above-mentioned high-speed row-by-row scanning mode and high-speed interlaced row scanning mode.

[0071] In some embodiments, in the interrupt wake-up mode, the following process is included:

[0072] The master control unit configures all sleep pins in the linear Hall chip matrix to the low-power mode, enabling all the linear Hall chips to enter the low-frequency signal acquisition state. At the same time, the master control unit switches to the sleep state, only retaining the interrupt wake-up function;

[0073] All the linear Hall chips detect the external magnetic field change at a preset time interval;

[0074] When the external magnetic field change detected by any one of the linear Hall chips exceeds the set threshold, the linear Hall chip outputs the interrupt signal to the master control unit;

[0075] After receiving the interrupt signal, the master control unit switches from the sleep state to the working state, reconfigures the working logic of the linear Hall chip matrix, activates the linear Hall chips in the target row, and completes signal acquisition.

[0076] Specifically, as Figure 6As shown, in the interrupt wake-up mode, before all the linear Hall chips enter the low-frequency signal acquisition state, the main control unit first configures all the sleep ports to output high level, and at the same time configures all the wake-up ports to the interrupt wake-up input state, and itself enters the sleep state. At this time, all the chips enter the low-frequency signal acquisition state and detect the external magnetic field change at a preset time interval. For example, the external magnetic field change is detected once every 12.5 ms. Further, if any chip detects that the external magnetic field changes beyond the set threshold, the chip switches its wake-up pin from high level to low level and outputs it to the main control unit, and this low-level output is the interrupt signal output. When the main control unit receives this interrupt signal, the main control unit is woken up, that is, it switches from the sleep state to the working state, and wakes up the overall system to resume work. In this way, the overall power consumption of the system is reduced, the response speed of the system is improved, and the user experience is enhanced.

[0077] In some embodiments, as Figure 7 shown, the control system further includes a shift register 3 for realizing row-by-row dynamic control through serial communication.

[0078] The shift register receives the control signal of the main control unit and switches the working state of the linear Hall chips row by row, activates the linear Hall chips in the target row, and controls the chips in other rows to remain in the sleep state;

[0079] The main control unit includes a plurality of wake-up ports; the main control unit activates the signal output or receives the interrupt signal of the linear Hall chips in the target row through the wake-up ports.

[0080] In this embodiment, in order to save the ports of the main control unit, a shift register is provided. Specifically, the shift register is provided with a plurality of serial communication input ports and a plurality of register output ports. The main control unit MCU includes a plurality of serial communication output ports and a plurality of wake-up ports. The plurality of serial communication output ports are connected to the plurality of serial communication input ports in one-to-one correspondence. The plurality of wake-up ports are connected to the wake-up pins of each row of the linear Hall chips in one-to-one correspondence. The plurality of register output ports are connected to the sleep pins of each row of the linear Hall chips in one-to-one correspondence.

[0081] Continuing to take an 8×8 linear Hall chip matrix as an example, the plurality of serial communication input ports include a data input port DS, a clock input port SHCP, and a latch input port STCP, and the plurality of register output ports include 8 register output ports Q0~Q7. Correspondingly, the plurality of serial communication output ports include 3 serial communication ports GPIO_0~GPIO_2, and the plurality of wake-up ports include 8 wake-up ports AWAKE`0~AWAKE`7.

[0082] The data input port DS of the shift register is used to receive the serial sleep signal from the main control unit. The clock input port SHCP is used to receive the clock signal provided by the main control unit. The latch input port STCP is used to receive the latch signal from the main control unit. The main control unit sends the sleep signal bit by bit through the data input port DS into the shift register, and shifts it into the register under the control of the clock signal. When the shift of the sleep signal is completed, the latch input port STCP latches the sleep signal to the register output port according to the latch signal.

[0083] In this embodiment, by setting the shift register to communicate with the main control unit, only a small number of ports are required to control multiple outputs, thus saving the port resources of the main control unit. At the same time, the shift register supports high-speed serial data transmission, effectively improving the data transmission efficiency between the main control unit and the linear Hall chip matrix.

[0084] In some embodiments, the output signal supports analog voltage output or digital signal output to meet the requirements of different data acquisition devices.

[0085] In some embodiments, the logic control signal includes but is not limited to level signal, level inversion signal, pulse signal, timing control signal, data carrier signal.

[0086] In some embodiments, continue to refer to Figure 7 As shown, the main control unit further includes a plurality of sampling ports, and the number of the plurality of sampling ports matches the structure of the linear Hall chip matrix, that is, ADC0~ADC7 in the figure; in occasions where the noise requirement is relatively high and the sampling speed is relatively low, the control system further includes an RC low-pass filter module 4. The RC low-pass filter module is connected between the output end of each linear Hall chip and the plurality of sampling ports, and is used to filter out high-frequency noise in the signal to improve the sampling accuracy of the sampling ports of the main control unit.

[0087] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A row-column scanning control system based on a sleep and wake-up function chip, characterized in that The system includes: A linear Hall chip matrix, which is arranged in an N-row × M-column matrix structure by a plurality of linear Hall chips. Each of the linear Hall chips includes: A sleep pin, which is used to receive a sleep signal to control the working state of the linear Hall chip and switch the linear Hall chip to the sleep state; A wake-up pin, which is used to receive a logic control signal to manage the output state of the linear Hall chip or output an interrupt signal in the sleep mode to trigger system wake-up; A signal output pin, which is used to output a detection signal; A main control unit, which is connected to the sleep pins and wake-up pins of each row of the linear Hall chips; The main control unit at least includes: M groups of acquisition input ports, which respectively correspond to M columns of the linear Hall chip matrix; The signal output pins of each column of the linear Hall chips are shorted to each other and correspondingly connected to a group of acquisition input ports of the main control unit; The main control unit controls the system to enter a high-speed progressive scanning mode or a high-speed interlaced scanning mode or a medium-speed scanning mode by configuring the signal combinations of the sleep pins and / or wake-up pins, and receives the detection signals output by the linear Hall chip matrix; The system can operate in different scanning modes, and the working state of the linear Hall matrix is controlled by the main control unit, including: In the high-speed interlaced scanning mode, the main control unit simultaneously activates multiple rows of the linear Hall chips according to a preset logic to make them enter the working state synchronously; the main control unit sequentially acquires the detection signals of the current target row, and at the same time, the linear Hall chips of the next target row are in a state to be acquired. In this way, interlaced high-speed scanning is realized, and the time delay of row switching is reduced; The high-speed interlaced scanning mode specifically includes: The main control unit configures the sleep pins of the linear Hall chips in n adjacent rows in the row of the linear Hall chip matrix to be at a low level to make them in the working state, and at the same time configures the sleep pins of the linear Hall chips in the remaining rows to be at a high level to keep them in the sleep state; According to the preset scanning order, the main control unit sequentially configures the wake-up pins of the current target row to be at a high level, so that the linear Hall chips of the current target row output the detection signals to the main control unit through the corresponding signal output pins; When the linear Hall chips of the current target row complete scanning and are about to switch to the next row for scanning, the main control unit controls to configure the sleep pins of the linear Hall chips of the current target row to be at a high level to switch them to the sleep state, and at the same time controls to configure the sleep pins of the next row of linear Hall chips adjacent to the current n rows to be at a low level to switch them to the working state; In the sleep mode, if any linear Hall chip detects a change in the external magnetic field, it outputs an interrupt signal to the main control unit through the wake-up pin to trigger system wake-up.

2. The row-column scanning control system according to claim 1, characterized in that, The working state of the linear Hall chip is controlled by the main control unit, and the state is switched through the sleep pin and the wake-up pin to manage the signal output of the chip, specifically including: Sleep mode: When the main control unit sends a sleep signal to the linear Hall chip of the target row, the linear Hall chip of the target row enters the sleep state, stops normal signal output, and at the same time its signal output pin is in a high-impedance state; Working mode: When the main control unit sends a wake-up signal to the linear Hall chip of the target row, the linear Hall chip of the target row exits the sleep state and enters the working mode, starts detecting external magnetic field changes, and sends detection signals through the corresponding signal output pins; The main control unit realizes row-by-row scanning by dynamically controlling the sleep pins and wake-up pins of each row of linear Hall chips, so that the linear Hall chips of the target row are in the working mode, while the linear Hall chips of the remaining rows remain in the sleep mode or high-impedance state.

3. The row-column scanning control system according to claim 1, wherein: The main control unit sends a sleep signal to all the chips and enters the sleep mode itself, only retaining the interrupt wake-up function; at the same time, all the chips switch to the low-power mode and independently detect external magnetic field changes; When any one of the chips detects that the external magnetic field change exceeds the set threshold, the chip outputs the interrupt signal to the main control unit; after receiving the interrupt signal, the main control unit switches from the sleep mode to the normal working mode.

4. The row-column scanning control system according to claim 1, characterized in that, The system can operate in different scanning modes, and the working state of the linear Hall matrix is controlled by the main control unit. Specifically, it further includes: In the high-speed row-by-row scanning mode, the main control unit sequentially activates the linear Hall chips of the target row to make them enter the working state for magnetic field detection, and the chips of the remaining rows remain in the sleep state; after the chips of the target row complete the detection, they re-enter the sleep state, and at the same time activate the chips of the next target row, and so on, to achieve efficient row-by-row scanning; In the medium-speed scanning mode, the main control unit controls the linear Hall chips of the target row to remain in the working state, and the linear Hall chips of the remaining rows remain in the sleep state, and so on, to achieve medium-speed scanning.

5. The system according to claim 4, wherein The high-speed row-by-row scanning mode specifically includes: The main control unit makes all the linear Hall chips enter the working state by controlling the states of all the sleep pins; The main control unit sequentially configures the logic control signals for the wake-up pins of the target row, so that the linear Hall chips of the target row output the detection signals to the main control unit through the corresponding signal output pins; After the linear Hall chips of the target row complete the scanning, the linear Hall chips of the next target row are sequentially activated, and so on, to achieve row-by-row high-speed scanning and signal acquisition of the linear Hall chip matrix.

6. The system according to claim 4, characterized in that, The medium-speed scanning mode is applicable to power-sensitive scenarios, and specifically includes: The main control unit makes the linear Hall chips of the target row be in the working state by controlling the states of the sleep pins of the target row, and the linear Hall chips of the remaining rows remain in the sleep state; The linear Hall chips of the target row detect external magnetic field changes and transmit the detection signals to the main control unit through the corresponding signal output pins; After the data acquisition of the linear Hall chip in the target row is completed, the main control unit selects to keep the linear Hall chip in the target row working according to system requirements, or to make the linear Hall chip in the target row re-enter the sleep state.

7. The system according to claim 1, characterized in that, The main control unit includes multiple groups of ports, and each group of ports includes: Sleep ports, which are respectively connected to the sleep pins of each row of the linear Hall chips; Wake-up ports, which are respectively connected to the wake-up pins of each row of the linear Hall chips.

8. The system according to claim 1, wherein The control system further includes a shift register, which realizes row-by-row dynamic control through serial communication; The shift register has multiple serial communication input ports and register output ports; The main control unit is provided with multiple serial communication output ports and wake-up ports; Each of the serial communication input ports is correspondingly connected to each of the serial communication output ports of the main control unit; each of the register output ports is correspondingly connected to the sleep pins of each row of the linear Hall chips; each of the wake-up ports is correspondingly connected to the wake-up pins of each row of the linear Hall chips.

9. The system according to claim 1, wherein The detection signal of the linear Hall chip supports analog voltage output or digital signal output to meet the requirements of different data acquisition devices.

10. The system according to claim 1, wherein The logic control signal includes one of a level signal, a level inversion signal, a pulse signal, a timing control signal, or a data carrier signal.

11. The system according to claim 1, wherein The linear Hall chip matrix adopts a dynamic N×M arrangement, where N and M are any positive integers, to adapt to different signal acquisition requirements.

12. The system according to claim 1, wherein The main control unit makes the linear Hall chips in adjacent n rows in the linear Hall chip matrix be in the working mode by configuring the sleep pins, where n is any positive integer greater than or equal to 2.

13. The system according to claim 3, characterized in that, The main control unit controls multiple linear Hall chip matrices through a clock signal to achieve synchronous signal acquisition.

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