An LDO circuit with optimized power supply rejection

Abstract

The present invention discloses an LDO circuit capable of optimizing power supply rejection, belonging to the technical field of high power supply rejection LDO circuits. It mainly includes a power transistor substrate control module, an error amplifier module, a power transistor module, and a feedback resistor module. The power transistor module outputs a stabilized voltage Vout. The feedback resistor module divides the voltage Vout for detection and provides a feedback signal to the error amplifier. The substrate potential of the power transistor module is electrically connected to the power transistor substrate control module. The power transistor substrate control module controls the substrate potential of the power transistor module to change the on-resistance of the power transistor module. The power transistor substrate control module controls the bias voltage of the power transistor at different high-frequency bands through capacitors with different capacitance values, specifically improving the PSR performance in the high-frequency band, solving the problem of deteriorated PSR of the LDO in the high-frequency band, and meeting the requirements for high power supply stability in frontier fields such as autonomous driving systems and medical electronic devices.

Description

Technical Field

[0001] The present invention relates to the technical field of high power supply rejection LDO circuits, and specifically to an LDO circuit capable of optimizing power supply rejection. Background Art

[0002] As a core device for precision power regulation, the low dropout regulator (LDO) plays an important role in low-noise power supply scenarios. With the intelligent evolution of autonomous driving systems, medical electronic devices, and industrial control units, the limitations of traditional linear regulators, such as low efficiency and severe temperature drift, have gradually emerged. The LDO, with its ultra-low dropout voltage, ultra-high power supply rejection ratio, and microvolt-level output accuracy characteristics, demonstrates irreplaceable advantages in multi-stage power supply architectures. Especially in cutting-edge fields such as precision measurement systems (such as bioelectrical signal acquisition, quantum computing control units), almost extreme performance requirements are imposed on the transient response speed and long-term stability of the LDO.

[0003] However, due to the limitation of the error amplifier in the LDO, the PSR in the high-frequency band generally deteriorates. When the PSR in the high-frequency band deteriorates, the high-frequency noise in the input power supply is difficult to be effectively suppressed. These noises will be transmitted to the output terminal, resulting in the mixing of high-frequency noise components in the output voltage. Moreover, in some circuits with high requirements for power quality, such as sensor circuits in autonomous driving systems and signal processing circuits in medical electronic devices, the instability of the output voltage and the introduction of noise will lead to a decline in circuit performance. For example, sensors may generate measurement errors due to power supply noise, affecting the accurate perception of environmental information by autonomous driving systems; the signal processing circuits of medical electronic devices may not be able to accurately process and analyze physiological signals due to power supply problems.

[0004] Therefore, it is necessary to provide an LDO circuit capable of optimizing power supply rejection to solve the above problems.

[0005] It should be noted that the above information disclosed in this background art section is only used to understand the background art of the inventive concept of the present invention, and therefore, it may include information that does not constitute the prior art. Summary of the Invention

[0006] The purpose of the present invention is to provide an LDO circuit capable of optimizing power supply rejection to solve the problems raised in the above background art.

[0007] The technical solution adopted by the present invention to solve its technical problems is:

[0008] An LDO circuit that can optimize power supply rejection, including a power transistor substrate control module, an error amplifier module, a power transistor module, and a feedback resistor module. The power transistor module outputs the stabilized voltage Vout. The feedback resistor module divides the voltage Vout for detection and provides a feedback signal to the error amplifier, forming a feedback loop with the error amplifier. The error amplifier module compares the feedback signal provided by the feedback resistor module with the reference signal Vref and then outputs a control signal to the power transistor module to change the gate voltage of the power transistor module, adjust the conduction degree, and thus adjust the voltage Vout.

[0009] Among them, the substrate potential of the power transistor module is electrically connected to the power transistor substrate control module. The power transistor substrate control module controls the substrate potential of the power transistor module to change the conduction impedance of the power transistor module.

[0010] Preferably, the power transistor module includes PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3. The gates of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are respectively electrically connected to the output control terminals of the error amplifier module. The drains of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are respectively electrically connected to one end of the feedback resistor module, and the drains of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are the output voltage Vout. The sources of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are respectively electrically connected to the input voltage Vin. The substrate potentials B1 of PMOS transistor M1, B2 of PMOS transistor M2, and B3 of PMOS transistor M3 are respectively electrically connected to the output terminals of the power transistor substrate control module. The input terminal of the power transistor substrate control module is electrically connected to the input voltage Vin.

[0011] Preferably, the error amplifier module includes error amplifier EA. The negative input terminal of error amplifier EA is connected to the reference voltage Vref. The positive input terminal of error amplifier EA is electrically connected to the feedback resistor module after voltage division. The output terminal of error amplifier EA is respectively connected to the gates of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3.

[0012] Preferably, the feedback resistor module includes resistor R1 and resistor R2. Resistor R1 and resistor R2 are connected in series. The end portions of the series-connected resistor R1 are respectively connected to the drains of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3. The end portion of the series-connected resistor R2 is grounded. The positive input terminal of error amplifier EA is connected to the common connection end of resistor R1 and resistor R2.

[0013] Preferably, the power transistor substrate control module includes a power transistor substrate control circuit BC1, a power transistor substrate control circuit BC2, and a power transistor substrate control circuit BC3. The input ends of the power transistor substrate control circuit BC1, the power transistor substrate control circuit BC2, and the power transistor substrate control circuit BC3 are all electrically connected to the input voltage Vin. The output ends of the power transistor substrate control circuit BC1, the power transistor substrate control circuit BC2, and the power transistor substrate control circuit BC3 are respectively connected to the substrate potential B1 of the PMOS transistor M1, the substrate potential B2 of the PMOS transistor M2, and the substrate potential B3 of the PMOS transistor M3.

[0014] Preferably, the power transistor substrate control module further includes a voltage dividing circuit. The voltage dividing circuit includes a resistor R41, a resistor R42, a resistor R43, and a resistor R44. The resistor R41, the resistor R42, the resistor R43, and the resistor R44 are connected in series. The access end of the series-connected resistor R44 is connected to the input voltage Vin. The series-connected resistor R41 is grounded. Bias voltages Vbias1, Vbias2, and Vbias3 are respectively generated between every two of the resistor R41, the resistor R42, the resistor R43, and the resistor R44. The bias voltages Vbias1, Vbias2, and Vbias3 respectively provide reference potentials for the power transistor substrate control circuit BC1, the power transistor substrate control circuit BC2, and the power transistor substrate control circuit BC3.

[0015] Preferably, the power transistor substrate control circuit BC1, the power transistor substrate control circuit BC2, and the power transistor substrate control circuit BC3 are the same control circuits. The power transistor substrate control circuit BC1 includes an amplifier opa1. The negative input end of the amplifier opa1 is connected to the bias voltage Vbias1. The positive input end of the amplifier opa1 is connected to one end of a resistor R11. A capacitor C1 is connected in parallel across both ends of the resistor R11. A resistor R12 is connected in parallel between the positive input end and the output end of the amplifier opa1. One end of the resistor R12 is connected to the capacitor C1. The output end of the amplifier opa1 is connected to the substrate potential B1 of the PMOS transistor M1 after being connected in series with a resistor R13.

[0016] Preferably, the amplifier opa1 includes an input stage, an active load, and an output stage. The input stage includes an NMOS transistor NM1 and an NMOS transistor NM2. The gate of the NMOS transistor NM1 is connected to the input signal Vinp+, and the gate of the NMOS transistor NM2 is connected to the input signal Vinn-. The sources of the NMOS transistor NM1 and the NMOS transistor NM2 are connected together and connected to a current source Ib1 that provides a stable bias current for the NMOS transistor NM1 and the NMOS transistor NM2 through a resistor R21. The drains of the NMOS transistor NM1 and the NMOS transistor NM2 are respectively connected to a current source Ib3 and a current source Ib4;

[0017] The active load includes a PMOS transistor PM3 and a PMOS transistor PM4. The gates of the PMOS transistor PM3 and the PMOS transistor PM4 are connected together and receive a bias voltage Vbias. The current source Ib3 and the current source Ib4 are also respectively connected to the drains of the PMOS transistor PM3 and the PMOS transistor PM4;

[0018] The output stage includes an NMOS transistor NM3, an NMOS transistor NM4, an NMOS transistor NM5, and an NMOS transistor NM6. The gate of the NMOS transistor NM3 is connected to the gate of the NMOS transistor NM4. The drain of the NMOS transistor NM3 is also connected to the gate of the NMOS transistor NM4. The drain of the NMOS transistor NM3 is further connected to the source of the PMOS transistor PM3. The source of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM5. The source of the NMOS transistor NM4 is connected to the drain of the NMOS transistor NM6. The sources of the NMOS transistor NM5 and the NMOS transistor NM6 are commonly grounded. The gates of the NMOS transistor NM5 and the NMOS transistor NM6 are connected. The drain of the NMOS transistor NM4 and the source of the PMOS transistor PM4 are commonly used as the output terminal Vout.

[0019] Preferably, the feedback resistor module further includes a capacitor CL and a resistor RL. One end of the capacitor CL and the resistor RL is connected to the end of the series resistor R1, and the other end of the capacitor CL and the resistor RL is grounded.

[0020] The beneficial effects of the present invention are:

[0021] The feedback regulation mechanism composed of a feedback resistor module, an error amplifier module, and a power transistor module. The feedback resistor accurately detects the output voltage, the error amplifier precisely compares and amplifies the difference, and the power transistor accurately adjusts the conduction degree according to the control signal, making the output voltage stably approach the set value of the reference signal, meeting the application scenarios with high requirements for the accuracy of the supply voltage.

[0022] The power transistor substrate control module controls the bias voltage of the power transistor at different high-frequency bands through capacitors with different capacitance values, exactly showing an improvement at three frequency points on the PSR, specifically improving the PSR performance in the high-frequency band, solving the problem of the deterioration of the PSR of the LDO in the high-frequency band, meeting the requirements for high power supply stability in cutting-edge fields such as autonomous driving systems and medical electronic devices. The power transistor substrate control module generates a bias voltage according to the input voltage to provide a reference potential for the control circuit. The control circuit cleverly controls the substrate potential of the power transistor according to different input signal frequencies, changing the on-resistance. The structural design of the input stage, active load, and output stage of the amplifier opa1 is reasonable, and they cooperate to achieve functions such as signal amplification, ensuring the stable and efficient operation of the entire LDO circuit.

[0023] In addition to the purposes, features, and advantages described above, the present invention has other purposes, features, and advantages. The present invention will be further described in detail below with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The specification drawings forming a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0025] Figure 1 is a system block diagram of an LDO circuit capable of optimizing power supply rejection of the present invention;

[0026] Figure 2 is a circuit diagram of an LDO circuit capable of optimizing power supply rejection of the present invention;

[0027] Figure 3 is a circuit diagram of the power transistor substrate control module of the present invention;

[0028] Figure 4 is a circuit diagram of the amplifier of the present invention;

[0029] Figure 5 is a comparison diagram of the new architecture PSR waveform (dashed line) and the traditional architecture PSR waveform (solid line) of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0031] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0032] Please refer to Figures 1-5 , the embodiments provided by the present invention:

[0033] As Figure 1 shown, an LDO circuit that can optimize power supply rejection includes a power transistor substrate control module, an error amplifier module, a power transistor module, and a feedback resistor module. The power transistor module outputs the stabilized voltage Vout. The feedback resistor module divides the voltage Vout for detection and provides a feedback signal to the error amplifier, and forms a feedback loop with the error amplifier. The error amplifier module compares the feedback signal provided by the feedback resistor module with the reference signal Vref and outputs a control signal to the power transistor module, changes the gate voltage of the power transistor module, adjusts the conduction degree, and thus adjusts the voltage Vout.

[0034] Specifically, as Figure 2 shown, the power transistor module includes PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3. The gates of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are respectively electrically connected to the output control terminals of the error amplifier module. The drains of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are respectively electrically connected to one end of the feedback resistor module, and the drains of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are the output voltage Vout. The sources of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are respectively electrically connected to the input voltage Vin. The substrate potentials B1 of PMOS transistor M1, B2 of PMOS transistor M2, and B3 of PMOS transistor M3 are respectively electrically connected to the output terminals of the power transistor substrate potential control module. The input terminal of the power transistor substrate control module is electrically connected to the input voltage Vin.

[0035] The error amplifier module includes an error amplifier EA. The negative input terminal of the error amplifier EA is connected to the reference voltage Vref. The reference signal Vref is a stable reference voltage value, providing a voltage reference standard for the entire voltage regulator.

[0036] The positive input terminal of the error amplifier EA is electrically connected to the voltage-divided feedback resistor module. The feedback resistor module includes resistor R1, resistor R2, capacitor CL, and resistor RL. Resistor R1 and resistor R2 are connected in series. The end of the series-connected resistor R1 is respectively connected to the drains of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3. The end of the series-connected resistor R2 is grounded. The positive input terminal of the error amplifier EA is connected to the common connection end of resistor R1 and resistor R2. One end of the capacitor CL and resistor RL is connected to the end of the series-connected resistor R1, and the other end of the capacitor CL and resistor RL is grounded.

[0037] Resistor R1 and resistor R2 perform voltage division detection on the output voltage Vout of the LDO. The voltage after voltage division is input into the error amplifier EA as a feedback signal. The feedback signal input into the error amplifier EA is compared with the reference signal Vref. If there is a difference between the feedback signal and the reference signal, the error amplifier will amplify this difference and output a corresponding control signal. The magnitude and direction of this control signal depend on the difference between the feedback signal and the reference signal. Its purpose is to adjust the output voltage Vout to make it as close as possible to the voltage value set by the reference signal Vref.

[0038] Among them, capacitor CL is the output capacitor. Its main function is to store and release charges to stabilize the output voltage Vout. When the load current changes, capacitor CL can quickly provide or absorb current to avoid large fluctuations in the output voltage and improve the stability of the output voltage. At the same time, it also has a certain filtering effect on the high-frequency noise of the output voltage, reducing the ripple of the output voltage. Resistor RL is the load resistor, which represents the load driven by the LDO circuit.

[0039] The output terminal of the error amplifier EA is respectively connected to the gates of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3. PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are respectively controlled by the control signal output by the error amplifier. By changing the gate voltage of the PMOS transistor through the control signal, the conduction degree of the PMOS transistor is changed, so as to adjust the output voltage Vout.

[0040] In order to be able to further accurately adjust the working state of the power transistor and improve the performance and stability of the voltage regulator, the substrate potential of the power transistor module is electrically connected to the power transistor substrate control module. The power transistor substrate control module controls the substrate of the power transistor module to change the conduction impedance of the power transistor module.

[0041] Specifically, the power transistor substrate control module includes a power transistor substrate control circuit BC1, a power transistor substrate control circuit BC2, and a power transistor substrate control circuit BC3. The input ends of the power transistor substrate control circuit BC1, the power transistor substrate control circuit BC2, and the power transistor substrate control circuit BC3 are all electrically connected to the input voltage Vin. The output ends of the power transistor substrate control circuit BC1, the power transistor substrate control circuit BC2, and the power transistor substrate control circuit BC3 are respectively connected to the substrate potential B1 of the PMOS transistor M1, the substrate potential B2 of the PMOS transistor M2, and the substrate potential B3 of the PMOS transistor M3.

[0042] As Figure 3 shown, the power transistor substrate control module further includes a voltage dividing circuit. The voltage dividing circuit includes a resistor R41, a resistor R42, a resistor R43, and a resistor R44. The resistor R41, the resistor R42, the resistor R43, and the resistor R44 are connected in series. The access end of the series-connected resistor R44 is connected to the input voltage Vin. The series-connected resistor R41 is grounded. Bias voltages Vbias1, Vbias2, and Vbias3 are respectively generated between every two of the resistor R41, the resistor R42, the resistor R43, and the resistor R44. The bias voltages Vbias1, Vbias2, and Vbias3 respectively provide reference potentials for the power transistor substrate control circuit BC1, the power transistor substrate control circuit BC2, and the power transistor substrate control circuit BC3.

[0043] The input voltage Vin generates bias voltages Vbias1, Vbias2, and Vbias3 through the resistor R41, the resistor R42, the resistor R43, and the resistor R44, and supplies them to the negative input ends of opa1, opa2, and opa3 of the amplifier.

[0044] The power transistor substrate control circuit BC1, the power transistor substrate control circuit BC2, and the power transistor substrate control circuit BC3 are the same control circuits. Taking the power transistor substrate control circuit BC1 as an example, the power transistor substrate control circuit BC1 includes an amplifier opa1. The negative input end of the amplifier opa1 is connected to the bias voltage Vbias1. The positive input end of the amplifier opa1 is connected to one end of a resistor R11. A capacitor C1 is connected in parallel across both ends of the resistor R11. A resistor R12 is connected in parallel between the positive input end and the output end of the amplifier opa1. One end of the resistor R12 is connected to the capacitor C1. The output end of the amplifier opa1 is connected to the substrate potential B1 of the PMOS transistor M1 after being connected in series with a resistor R13.

[0045] In the low-frequency range: the capacitor C1 cannot be short-circuited. Mainly through the clamping action of the amplifier opa1 resistor, the potential of the substrate potential B1 point of the PMOS transistor M1 is equal to the bias voltage Vbias1.

[0046] When in the high-frequency range: Capacitor C1 is short-circuited, and the positive input terminal of amplifier opa1 is equal to the input voltage VIN. Since the input voltage VIN > the bias voltage Vbias1, the potential at the output terminal of amplifier opa1 increases, causing the potential at point B1, the substrate potential of PMOS transistor M1, to increase and approach the input voltage VIN.

[0047] Since the power transistor substrate control circuits BC2 and BC3 have the same circuit design as the power transistor substrate control circuit BC1, except for the different capacitance values of capacitors C1, C2, and C3, they can control the bias voltage of the power transistor module in different high-frequency bands, and there is an improvement at three frequency points reflected on the PSR, as Figure 5 shown. Figure 5 in is the error amplifier gain. At DC, .

[0048] As Figure 4 shown, amplifier opa1 includes an input stage, an active load, and an output stage. The input stage includes NMOS transistors NM1 and NM2. The gate of NMOS transistor NM1 is connected to the input signal Vinp+, and the gate of NMOS transistor NM2 is connected to the input signal Vinn-. The sources of NMOS transistors NM1 and NM2 are connected together and connected to the current source Ib1 that provides a stable bias current for NMOS transistors NM1 and NM2 through resistor R21. The drains of NMOS transistors NM1 and NM2 are respectively connected to current source Ib3 and current source Ib4;

[0049] When there is a difference between the input signals Vinp+ and Vinn-, it will cause different conduction degrees of NM1 and NM2, and thus cause a difference in their drain currents. This current difference is processed by the subsequent circuit to achieve the amplification of the input signal difference. For the common-mode signal, due to the symmetric structure of NM1 and NM2, their conduction degree changes are the same, and the changes in drain currents are also the same, so they are cancelled out in the subsequent circuit, achieving the purpose of suppressing the common-mode signal, realizing differential input, amplifying the difference of the input signal, and at the same time suppressing the common-mode signal (i.e., the same part of the two input signals), thereby improving the sensitivity of the amplifier to the change of the input signal and the anti-interference ability.

[0050] The active load includes PMOS transistor PM3 and PMOS transistor PM4. The gates of PMOS transistor PM3 and PMOS transistor PM4 are connected together and receive a bias voltage Vbias. Current sources Ib3 and Ib4 are also respectively connected to the drains of PMOS transistor PM3 and PMOS transistor PM4. Compared with traditional resistive loads, the active load can provide higher gain and better frequency characteristics, improve the performance of the amplifier, and at the same time provide a suitable load impedance for the input stage, enabling the input stage to effectively convert the change of the input signal into a voltage change;

[0051] The output stage includes NMOS transistors NM3, NMOS transistor NM4, NMOS transistor NM5, and NMOS transistor NM6. The gate of NMOS transistor NM3 is connected to the gate of NMOS transistor NM4. The drain of NMOS transistor NM3 is also connected to the gate of NMOS transistor NM4. The drain of NMOS transistor NM3 is further connected to the source of PMOS transistor PM3. The source of NMOS transistor NM3 is connected to the drain of NMOS transistor NM5. The source of NMOS transistor NM4 is connected to the drain of NMOS transistor NM6. The sources of NMOS transistor NM5 and NMOS transistor NM6 are commonly grounded. The gates of NMOS transistor NM5 and NMOS transistor NM6 are connected. The drain of NMOS transistor NM4 and the source of PMOS transistor PM4 are commonly used as the output terminal Vout.

[0052] Further processing and output of the signal processed by the input stage and the active load can provide a suitable output impedance to drive the subsequent circuit and achieve accurate transmission and processing of the signal.

[0053] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A LDO circuit capable of optimizing power supply suppression, characterized in that: It includes a power tube substrate control module, an error amplifier module, a power tube module and a feedback resistor module. The power tube module outputs a stabilized voltage Vout. The feedback resistor module detects the voltage Vout by voltage division and provides a feedback signal to the error amplifier, and forms a feedback loop with the error amplifier. The error amplifier module compares the feedback signal provided by the feedback resistor module with a reference signal Vref and outputs a control signal to the power tube module, thereby changing the gate voltage of the power tube module, adjusting the conduction degree, and adjusting the voltage Vout. The substrate potential of the power tube module is electrically connected to the power tube substrate control module, and the power tube substrate control module controls the substrate potential of the power tube module to change the on-resistance of the power tube module; The power tube module includes a PMOS tube M1, a PMOS tube M2 and a PMOS tube M3, the gates of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 are respectively electrically connected to the output control end of the error amplifier module, the drains of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 are respectively electrically connected to one end of the feedback resistor module, and the drains of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 are the output voltage Vout, the sources of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 are respectively electrically connected to the input voltage Vin, the substrate potential B1 of the PMOS tube M1, the substrate potential B2 of the PMOS tube M2 and the substrate potential B3 of the PMOS tube M3 are respectively electrically connected to the output end of the power tube substrate control module, and the input end of the power tube substrate control module is electrically connected to the input voltage Vin; The power tube substrate control module includes a power tube substrate control circuit BC1, a power tube substrate control circuit BC2 and a power tube substrate control circuit BC3, the input ends of the power tube substrate control circuit BC1, the power tube substrate control circuit BC2 and the power tube substrate control circuit BC3 are all electrically connected to the input voltage Vin, and the output ends of the power tube substrate control circuit BC1, the power tube substrate control circuit BC2 and the power tube substrate control circuit BC3 are respectively connected to the substrate potential B1 of the PMOS tube M1, the substrate potential B2 of the PMOS tube M2 and the substrate potential B3 of the PMOS tube M3; The power tube substrate control module also includes a voltage divider circuit, which includes a resistor R41, a resistor R42, a resistor R43 and a resistor R44. The resistors R41, R42, R43 and R44 are connected in series, and the access end of the series-connected resistor R44 is connected to the input voltage Vin. The series-connected resistor R41 is grounded. A bias voltage Vbias1, a bias voltage Vbias2 and a bias voltage Vbias3 are generated between each of the resistors R41, R42, R43 and R44, respectively. The bias voltage Vbias1, the bias voltage Vbias2 and the bias voltage Vbias3 provide reference potentials for the power tube substrate control circuit BC1, the power tube substrate control circuit BC2 and the power tube substrate control circuit BC3, respectively. The power tube substrate control circuit BC1, the power tube substrate control circuit BC2 and the power tube substrate control circuit BC3 are the same control circuits. The power tube substrate control circuit BC1 includes an amplifier opa1, the negative input end of the amplifier opa1 is connected to the bias voltage Vbias1, the positive input end of the amplifier opa1 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to the input voltage Vin, the two ends of the resistor R11 are connected in parallel with a capacitor C1, the positive input end and the output end of the amplifier opa1 are connected in parallel with a resistor R12, one end of the resistor R12 is connected to the capacitor C1, and the output end of the amplifier opa1 is connected in series with a resistor R13 and then connected to the substrate potential B1 of the PMOS tube M1; The power tube substrate control circuit BC2 and the power tube substrate control circuit BC3 have the same circuit design as the power tube substrate control circuit BC1, and the capacitors C1, C2 and C3 have different capacitances so as to control the bias voltage of the power tube module in different high frequency bands.

2. The LDO circuit with optimized power supply rejection according to claim 1, characterized in that: The error amplifier module includes an error amplifier EA, a negative input terminal of the error amplifier EA is connected to a reference voltage Vref, a positive input terminal of the error amplifier EA is electrically connected to a divided feedback resistor module, and an output terminal of the error amplifier EA is respectively connected to the gates of PMOS tubes M1, M2 and M3.

3. The LDO circuit with optimized power supply suppression according to claim 2, characterized in that: The feedback resistor module includes a resistor R1 and a resistor R2, the resistor R1 and the resistor R2 are connected in series, the ends of the series-connected resistor R1 are respectively connected to the drains of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3, the ends of the series-connected resistor R2 are grounded, and the positive input end of the error amplifier EA is connected to the common end of the resistor R1 and the resistor R2.

4. The LDO circuit capable of optimizing power supply suppression according to claim 1, characterized in that: The amplifier opa1 includes an input stage, an active load and an output stage, the input stage includes an NMOS transistor NM1 and an NMOS transistor NM2, the gate of the NMOS transistor NM1 is connected to the input signal Vinp+, the gate of the NMOS transistor NM2 is connected to the input signal Vinn-, the sources of the NMOS transistor NM1 and the NMOS transistor NM2 are connected together, and connected to a current source Ib1 that provides a stable bias current for the NMOS transistor NM1 and the NMOS transistor NM2 through a resistor R21, and the drains of the NMOS transistor NM1 and the NMOS transistor NM2 are connected to a current source Ib3 and a current source Ib4 respectively; The active load includes a PMOS transistor PM3 and a PMOS transistor PM4, the gates of the PMOS transistor PM3 and the PMOS transistor PM4 are connected together and receive a bias voltage Vbias, and the current source Ib3 and the current source Ib4 are also connected to the drains of the PMOS transistor PM3 and the PMOS transistor PM4 respectively; The output stage includes NMOS transistor NM3, NMOS transistor NM4, NMOS transistor NM5 and NMOS transistor NM6, the gate of the NMOS transistor NM3 is connected to the gate of the NMOS transistor NM4, the drain of the NMOS transistor NM3 is also connected to the gate of the NMOS transistor NM4, the drain of the NMOS transistor NM3 is also connected to the source of the PMOS transistor PM3, the source of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM5, the source of the NMOS transistor NM4 is connected to the drain of the NMOS transistor NM6, the source of the NMOS transistor NM5 and the source of the NMOS transistor NM6 are commonly grounded, the gate of the NMOS transistor NM5 is connected to the gate of the NMOS transistor NM6, and the drain of the NMOS transistor NM4 and the source of the PMOS transistor PM4 are commonly the output terminal Vout.

5. The LDO circuit capable of optimizing power supply suppression according to claim 3, characterized in that: The feedback resistor module further includes a capacitor CL and a resistor RL. One end of the capacitor CL and the resistor RL is connected to the end of the series-connected resistor R1 , and the other end of the capacitor CL and the resistor RL is grounded.

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