Single power rail overcurrent protection circuit, LDO chip and overcurrent protection method

Abstract

The embodiment of the invention relates to the technical field of overcurrent protection, in particular to a single-power-rail overcurrent protection circuit, an LDO chip and an overcurrent protection method. The overcurrent protection circuit comprises a primary mirror image module composed of a power tube, a sampling tube and a clamping module; grid electrodes of the sampling tube and the power tube are short-circuited and then connected to the output end of the error amplifier; source electrodes of the sampling tube and the power tube are respectively connected to two input ends of the clamping module for clamping, so that the voltage of the source end of the sampling tube is equal to the output voltage of the LDO; drain electrodes of the sampling tube and the power tube are both connected to the LDO input end, and the LDO input voltage is used for supplying power to the clamping module on the basis that the source end voltage of the sampling tube and the LDO output voltage are both smaller than the LDO input voltage. According to the scheme, power is supplied to the single power rail, the complexity of a peripheral application circuit of the chip can be reduced, and the application range of the LDO chip can be expanded.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of overcurrent protection, and in particular to a single power rail overcurrent protection circuit, an LDO chip and an overcurrent protection method. Background Art

[0002] During the use of LDO linear regulator chips, the current limiting circuit generally clamps the first-stage mirror circuit in order to accurately sample the load current. Since the voltage difference between the gate and source of the MOS tube has a greater impact on the current than the drain-source voltage, the power tube and the sampling tube source are usually connected to ensure that the gate-source voltage is the same and the drain voltage is clamped. However, this mode has obvious limitations. When the power tube is an NMOS tube, the source of the power tube and the sampling tube are both connected to the LDO output voltage, and the drain voltage of the sampling tube needs to be clamped to the LDO input voltage. Therefore, in order to ensure that the clamping module can work properly, it is necessary to ensure that the clamping module power supply voltage is higher than the LDO input voltage VIN. Therefore, the clamping module circuit needs to add an additional power rail to supply power, which not only increases the complexity of the chip's peripheral application circuit, but also compresses the application scope of the chip.

[0003] Therefore, a single power rail overcurrent protection circuit is urgently needed. Summary of the invention

[0004] In order to solve the problem that the current limiting circuit of the traditional LDO chip needs to clamp the drain voltage of the sampling tube to the LDO input voltage, and in order to ensure that the clamping module can work normally, the power supply voltage of the clamping module needs to be higher than the LDO input voltage, so an additional power rail needs to be added to the periphery of the chip, the embodiment of the present invention provides a single power rail overcurrent protection circuit, an LDO chip and an overcurrent protection method.

[0005] In a first aspect, an embodiment of the present invention provides a single power rail overcurrent protection circuit, which is applied to an LDO chip. The overcurrent protection circuit at least includes: a primary mirror module that uses a sampling tube to perform mirror sampling on a load current flowing through a power tube; the primary mirror module includes a power tube, a sampling tube and a clamping module;

[0006] The gates of the sampling tube and the power tube are short-circuited and connected to the output end of the error amplifier inside the LDO chip;

[0007] The source electrodes of the sampling tube and the power tube are respectively connected to the two input terminals of the clamping module for clamping, so that the voltage at the source terminal of the sampling tube is equal to the output voltage of the LDO; wherein the source electrode of the power tube is connected to the output terminal of the LDO;

[0008] The drains of the sampling tube and the power tube are both connected to the LDO input terminal, the load current flows through the power tube, and based on the fact that the sampling tube source voltage and the LDO output voltage are both lower than the LDO input voltage, the LDO input voltage is used to power the clamping module.

[0009] In a second aspect, an embodiment of the present invention further provides an LDO chip, comprising: a reference source, an error amplifier, a power tube, and an overcurrent protection circuit as described in any embodiment of this specification; a feedback network and a load are connected to the output end of the LDO;

[0010] The non-inverting input terminal of the error amplifier is connected to the reference voltage terminal output by the reference source, the inverting input terminal is connected to the feedback network, and the output terminal of the error amplifier is respectively connected to the overcurrent protection circuit and the power tube gate;

[0011] The source of the power tube is connected to the LDO output terminal, and the drain is connected to the LDO input terminal;

[0012] The other end of the overcurrent protection circuit is connected to the LDO input end.

[0013] In a third aspect, an embodiment of the present invention further provides an overcurrent protection method based on the overcurrent protection circuit described in any embodiment of this specification, the method comprising:

[0014] Connect the drains of the sampling tube and the power tube to the LDO input terminal;

[0015] The source electrodes of the sampling tube and the power tube are clamped by using a clamping module so that the voltage at the source end of the sampling tube is equal to the LDO output voltage. Based on the fact that the voltage at the source end of the sampling tube and the LDO output voltage are both less than the LDO input voltage, the LDO input voltage is used to power the clamping module; wherein the source electrode of the power tube is connected to the LDO output end;

[0016] The sampling tube and the clamping module are used to perform accurate mirror sampling on the load current of the power tube.

[0017] The embodiment of the present invention provides a single power rail overcurrent protection circuit, an LDO chip and an overcurrent protection method. The drain end of the sampling tube and the power tube are connected to the LDO input voltage. The source end of the sampling tube and the power tube is clamped by a clamping module. Since the source end of the power tube is connected to the LDO output voltage, the voltage at the source end of the sampling tube is equal to the LDO output voltage. It can be seen that the LDO output voltage is less than the LDO input voltage. Therefore, the clamping module can directly use the LDO input voltage for power supply without adding an additional power rail for power supply. Therefore, this solution is powered by a single power rail, which can not only reduce the complexity of the chip peripheral application circuit, but also expand the application range of the LDO chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A single power rail overcurrent protection circuit diagram provided by an embodiment of the present invention;

[0020] Figure 2 This is a transient simulation diagram of a single power rail adaptive overcurrent protection provided by an embodiment of the present invention;

[0021] Figure 3 This is a general architecture diagram of an LDO chip provided by an embodiment of the present invention;

[0022] Figure 4 is a flow chart of an overcurrent protection method provided by an embodiment of the present invention;

[0023] Among them, M SENSE - Sampling tube; M POWER -power tube; 10-secondary mirror module; 20-tertiary mirror module. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] The specific implementation of the above concept is described below.

[0026] Please refer to Figure 1 The embodiment of the present invention provides a single power rail overcurrent protection circuit, which is applied to an LDO chip. The circuit at least includes: a circuit for using a sampling tube M SENSE Convection into the power tube M POWER The load current I LOAD A first-level mirror module for performing mirror sampling; the first-level mirror module includes a power tube, a sampling tube and a clamp module;

[0027] The gates of the sampling tube and the power tube are short-circuited and connected to the output of the error amplifier inside the LDO;

[0028] The source electrodes of the sampling tube and the power tube are respectively connected to the two input terminals of the clamping module for clamping, so that the voltage at the source terminal of the sampling tube is equal to the output voltage of the LDO; wherein the source electrode of the power tube is connected to the output terminal of the LDO;

[0029] The drains of the sampling tube and the power tube are connected to the LDO input terminal. Since the sampling tube source voltage and the LDO output voltage are both lower than the LDO input voltage, the LDO input voltage is used to power the clamping module.

[0030] In the embodiment of the present invention, the drain end of the sampling tube and the power tube are connected to the LDO input voltage, and the source end of the sampling tube and the power tube are clamped by the clamping module. Since the source end of the power tube is connected to the LDO output voltage, the voltage at the source end of the sampling tube will be equal to the LDO output voltage. It can be seen that the LDO output voltage is less than the LDO input voltage, so the clamping module can directly use the LDO input voltage for power supply without adding an additional power rail for power supply. Therefore, this solution is powered by a single power rail, which can reduce the complexity of the chip peripheral application circuit and expand the application range of the LDO chip.

[0031] It should be noted that there are many implementation methods for the clamping module. Figure 1 A clamping operational amplifier is used to implement clamping. The implementation methods of other clamping modules are also within the scope of protection required by this solution.

[0032] According to the following Figure 1 The circuit diagram shown is explained.

[0033] In some embodiments, reference may be made to Figure 1 , the single power rail overcurrent protection circuit also includes: a secondary mirror module, a tertiary mirror module and a switch tube M0;

[0034] The secondary mirror module is connected between the primary mirror module and the tertiary mirror module, and the secondary mirror module is used to map the sampling current of the primary mirror module to the tertiary mirror module;

[0035] The tertiary mirror module is connected between the secondary mirror module and the switch tube M0, and the switch tube M0 is connected to the primary mirror module. The tertiary mirror module is used to form a current mirror to scale down the mapping current of the secondary mirror module, and output a target current that reflects the load current size. The target current is compared with the reference current connected to the gate of the switch tube M0 to control the working state of the switch tube M0, and then control the working state of the power tube.

[0036] In this embodiment, reference can be made to Figure 1 , Figure 1The sampled current is scaled down twice by the secondary mirror module 10 and the tertiary mirror module 20 in sequence. The circuit power consumption is reduced as much as possible by scaling down the sampled current in proportion, and a target current is finally obtained for comparison with the reference current. The target current reflects the magnitude of the actual load current. The comparison result between the target current and the reference current determines the working state of the switch tube M0, thereby realizing the control of the power tube M0. POWER Gate voltage control.

[0037] In the embodiment of the present invention, when the load current is less than the current limit point, the sampling current is less than the reference current after being reduced by the secondary mirror module and the tertiary mirror module, and the gate of the switch tube M0 is a low voltage, so that the switch tube M0 is in a closed state, and the overcurrent protection circuit does not work;

[0038] When the load current exceeds the current limit point, the sampling current is greater than the reference current after being reduced by the secondary mirror module and the tertiary mirror module. The gate of the switch tube M0 is a high voltage, which makes the switch tube M0 in the on state. At the same time, the gate of the power tube is pulled down, the overcurrent protection circuit starts to work, and the LDO enters the current limiting state.

[0039] In this embodiment, a sampling tube M is used. SENSE The load current is sampled and proportionally reduced through three mirror modules. The load current is judged whether it exceeds the current limit point set by the LDO by comparing the reduced target current with the reference current. If it does not exceed the current limit point, the overcurrent protection circuit does not work; if it exceeds the current limit point, the power tube gate potential is lowered to enter the current limiting state.

[0040] However, in the process of using LDO linear regulator chips, sometimes there will be an error operation of directly shorting the output end to the ground or the load is too large to enter the current limiting state. At this time, the voltage difference between the two ends of the power tube of the chip is very large, approximately equal to the input voltage, and the current limit point of the power tube in the traditional overcurrent protection circuit will not change adaptively and is set above the maximum load current. Therefore, even if the load current is limited to the current limit point, it will generate huge power consumption, and a large amount of heat will burn the chip and cause permanent failure. This kind of misoperation will not only bring danger during the use of the chip, but also increase the additional cost of chip application, resulting in certain economic losses.

[0041] Therefore, in the embodiment of the present invention, when the LDO output end is hard short-circuited or overloaded, the LDO output voltage VOUT is pulled down, the secondary mirror module 10 generates an over-mirror image, triggering the LDO current limit point adaptive adjustment mechanism to reduce the current limit point.

[0042] In this embodiment, when the LDO output end is hard short-circuited or overloaded, the secondary mirror module 10 generates over-mirroring, which can adaptively and significantly reduce the current limit point, alleviate the heating of the chip under a large voltage difference, reduce the risk of damage, and improve the safety of chip application.

[0043] In some embodiments, the secondary mirror module 10 contains two MOS tubes. When the LDO output end is hard short-circuited or overloaded, the two MOS tubes in the secondary mirror module work in different states, one works in the linear region and the other works in the saturation region, resulting in over-mirroring.

[0044] When the chip output is hard shorted to ground, the two MOS tubes in the internal secondary mirror module 10 work in different states. One enters the linear region due to insufficient voltage margin, and the other works in the saturation region. This difference causes the mirror ratio to increase, achieving over-mirroring. POWER A smaller load current will trigger the overcurrent protection, that is, the lower the output voltage value, the higher the over-image ratio, and the current limit point decreases as the output voltage VOUT decreases. POWER The current flowing through is limited to a smaller value, which alleviates the heating of the chip under large voltage difference and protects the chip.

[0045] In the embodiment of the present invention, continue to refer to Figure 1 , the secondary mirror module 10 includes: a MOS tube M3 and a MOS tube M4;

[0046] The gates of the M3 tube and the M4 tube are connected to the output end of the clamping module, the drain of the M3 tube is connected to the source of the sampling tube, and the source of the M3 tube is grounded;

[0047] The drain of the M4 tube is connected to the three-stage mirror module, and the source of the M4 tube is grounded.

[0048] In this embodiment, the precise sampling current flows through the M3 tube, the M4 tube has the same gate-source voltage as the M3 tube, and the sampling current is mapped to the branch where the M4 and M1 tubes are located, and flows into the three-stage mirror module 20.

[0049] In some embodiments, when the LDO output terminal is hard short-circuited or overloaded, the source terminal voltage of the sampling tube follows the LDO output voltage and is extremely low, and the drain terminal voltage of the M3 tube is extremely low, so that the drain-source voltage difference of the M3 tube is less than the difference between the gate-source voltage difference of the M3 tube and the threshold voltage of the M3 tube, so that the M3 tube is in a non-saturated state and operates in a linear region; at the same time, the drain-source voltage difference of the M4 tube is greater than the difference between the gate-source voltage difference of the M4 tube and the threshold voltage of the M4 tube, so that the M4 tube operates in a saturated region.

[0050] In this embodiment, from Figure 1As can be seen from the circuit schematic, as long as the LDO input voltage VIN is powered normally, the clamping module can work normally regardless of the state of the output voltage VOUT, and the sampling tube source voltage VSENSE voltage changes with the output voltage VOUT. The sampling tube source voltage VSENSE voltage will affect the working state of the M3 tube. When the output is hard short-circuited, the VSENSE voltage is very low, that is, the drain voltage of the M3 tube is very low, making the M3 tube drain-source voltage difference less than the difference between the M3 tube gate-source voltage difference and the M3 tube threshold voltage, that is, VDS3<VGS3-VTH3, and the M3 tube is in a non-saturated state, working in the linear region or even the deep linear region.

[0051] At this time, the drain voltage of the M4 tube is VIN-VSG1. Correspondingly, the drain-source voltage difference of the M4 tube is greater than the difference between the gate-source voltage difference of the M4 tube and the threshold voltage of the M4 tube, that is, VDS4>VGS4-VTH4, and the M4 tube operates in the saturation region.

[0052] According to the drain current formula of MOS tube in saturation region: ID = μCoxW / L (VGS-VTH) 2 / 2 and the drain current formula of the MOS tube in the linear region: ID = μCoxW / L[(VGS-VTH)VDS-VDS 2 / 2], where μ is the electron mobility, Cox is the gate oxide capacitance per unit area, and W / L is the width-to-length ratio.

[0053] It can be seen from the above formula that under the same gate-source voltage conditions, the saturation region MOS tube leakage current is greater than the linear region, so M4 produces an over-image to the secondary mirror of M3, that is, under the same width-to-length ratio of the two MOS tubes, the current of M4 will be larger than that of M3, and then the target current output by M2 compared with the reference current will also be larger, which ultimately makes the load current I LOAD The overcurrent protection can be triggered under this condition to reduce the load current I LOAD current, and the lower the hard short resistance, the lower the hard short current limiting clamp I LOAD The lower the current is, the more the current limit point is adaptively lowered.

[0054] In the embodiment of the present invention, continue to refer to Figure 1 , the three-stage mirror module 20 includes: a MOS tube M1 and a MOS tube M2;

[0055] The gates of the M1 tube and the M2 tube are connected, the drain of the M1 tube is connected to the gate connection line of the M1 tube and the M2 tube and the drain of the M4 tube respectively, and the source of the M1 tube is connected to the LDO input terminal;

[0056] The drain of the M2 tube is connected to the gate of the switch tube M0 and the reference current terminal respectively, and the source of the M2 tube is connected to the LDO input terminal.

[0057] In this embodiment, the current mirror composed of M1 and M2 scales down the current mapped by the secondary mirror module to minimize the circuit power consumption, and finally obtains the target current for comparison with the reference current. It can be seen that the M1 and M2 tubes of the three-stage mirror circuit can also be directly powered by the LDO input voltage VIN to avoid introducing an additional power rail.

[0058] Finally, a transient simulation is performed on the single power rail overcurrent protection circuit proposed in this scheme to verify the adaptive adjustment capability of the current limit point to the output voltage change. The simulation results are shown in the figure. Figure 2 As shown. The simulation takes the normal output of 1V voltage by LDO as an example. The first 4ms is the normal output of the chip under zero load conditions. Then the load current increases linearly with a slope of 2A / ms. After the load current reaches 7.6A, the overcurrent protection is triggered, the output voltage is pulled down and the power tube current IPOWER is limited to no longer increase with the load. Then the load current decreases, and after the overcurrent protection state is released, the chip is allowed to work stably for a period of time under a 4A load. At 15ms, the NMOS tube connected in series between the LDO output and the ground is turned on instantly to simulate the situation where the chip is hard short-circuited. At the moment of short circuit, the LDO output voltage drops to zero, and the sampling voltage is almost zero. The power tube instantaneous current rushes to 22A and is limited to around 1.13A. This value is much lower than the conventional current limit value of 7.6A. The adaptive overcurrent protection circuit plays the expected protection role, dynamically controls the power consumption of the power tube, greatly reduces the power consumption of the chip during hard short circuit, and improves the reliability of chip application.

[0059] like Figure 3 As shown, this embodiment also provides an LDO chip, including: a reference source, an error amplifier, a power tube and an overcurrent protection circuit as in any embodiment in the specification; a feedback network and a load are connected to the output end of the LDO;

[0060] The non-inverting input terminal of the error amplifier is connected to the reference voltage terminal output by the reference source, the inverting input terminal is connected to the feedback network, and the output terminal of the error amplifier is connected to the overcurrent protection circuit and the gate of the power tube respectively;

[0061] The source of the power tube is connected to the LDO output terminal, and the drain is connected to the LDO input terminal;

[0062] The other end of the overcurrent protection circuit is connected to the LDO input end.

[0063] It should be noted that the above LDO chip embodiment and the overcurrent protection circuit embodiment belong to the same concept, and the specific implementation process thereof is detailed in the overcurrent protection circuit embodiment, which will not be repeated here.

[0064] like Figure 4 As shown, this embodiment also provides an overcurrent protection method based on the overcurrent protection circuit of this specification, the method comprising:

[0065] Step 400, connecting the drains of the sampling tube and the power tube to the LDO input terminal;

[0066] Step 402, using a clamping module to clamp the source of the sampling tube and the power tube, so that the voltage at the source end of the sampling tube is equal to the LDO output voltage, based on the fact that the voltage at the source end of the sampling tube and the LDO output voltage are both less than the LDO input voltage, the LDO input voltage is used to power the clamping module; wherein the source of the power tube is connected to the LDO output end;

[0067] Step 404, using the sampling tube and the clamping module, accurately mirror-sample the load current of the power tube.

[0068] It should be noted that the above method embodiment and the overcurrent protection circuit embodiment belong to the same concept, and the specific implementation process thereof is detailed in the overcurrent protection circuit embodiment, which will not be repeated here.

[0069] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical factors in the process, method, article or device including the elements.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single power rail overcurrent protection circuit, characterized in that: Applied to the LDO chip, the overcurrent protection circuit at least includes: a primary mirror module that uses a sampling tube to perform mirror sampling on the load current flowing into the power tube; the primary mirror module includes a power tube, a sampling tube and a clamping module; The gates of the sampling tube and the power tube are short-circuited and connected to the output end of the error amplifier inside the LDO chip; The source electrodes of the sampling tube and the power tube are respectively connected to the two input terminals of the clamping module for clamping, so that the voltage at the source terminal of the sampling tube is equal to the output voltage of the LDO; wherein the source electrode of the power tube is connected to the output terminal of the LDO; The drains of the sampling tube and the power tube are both connected to the LDO input terminal, the load current flows through the power tube, and based on the fact that the sampling tube source voltage and the LDO output voltage are both lower than the LDO input voltage, the LDO input voltage is used to power the clamping module.

2. The overcurrent protection circuit according to claim 1, characterized in that: Also includes: Secondary mirror module, tertiary mirror module and switch tube M0; The secondary mirror module is connected between the primary mirror module and the tertiary mirror module, and the secondary mirror module is used to map the sampled current of the primary mirror module to the tertiary mirror module; The three-stage mirror module is connected between the two-stage mirror module and the switch tube M0, and the switch tube M0 is connected to the one-stage mirror module. The three-stage mirror module is used to form a current mirror to scale down the mapping current of the two-stage mirror module, and output a target current that reflects the size of the load current. The target current is compared with a reference current connected to the gate of the switch tube M0 to control the working state of the switch tube M0, and then control the working state of the power tube.

3. The overcurrent protection circuit according to claim 2, characterized in that: When the load current is less than the current limit point, the sampling current is less than the reference current after being reduced by the secondary mirror module and the tertiary mirror module, and the gate of the switch tube M0 is at a low voltage, so that the switch tube M0 is in a closed state, and the overcurrent protection circuit does not work; When the load current exceeds the current limiting point, the sampling current is greater than the reference current after being reduced by the secondary mirror module and the tertiary mirror module, and the gate of the switch tube M0 is a high voltage, so that the switch tube M0 is in the on state, and the gate of the power tube is pulled down at the same time, the overcurrent protection circuit starts to work, and the LDO enters the current limiting state.

4. The overcurrent protection circuit according to claim 2, characterized in that: When the LDO output terminal is hard short-circuited or overloaded, the LDO output voltage is pulled down, and the secondary mirror module generates an over-mirror image, triggering the power tube current limit point adaptive adjustment mechanism to reduce the current limit point.

5. The overcurrent protection circuit according to claim 4, characterized in that: The secondary mirror module contains two MOS tubes. When the LDO output end is hard short-circuited or overloaded, the two MOS tubes in the secondary mirror module work in different states, one works in the linear region and the other works in the saturation region, resulting in over-mirroring.

6. The overcurrent protection circuit according to claim 5, characterized in that: The secondary mirror module includes: MOS tube M3 and MOS tube M4; The gates of the M3 tube and the M4 tube are connected to each other and then connected to the output end of the clamping module, the drain of the M3 tube is connected to the source of the sampling tube, and the source of the M3 tube is grounded; The drain of the M4 tube is connected to the three-stage mirror module, and the source of the M4 tube is grounded.

7. The overcurrent protection circuit according to claim 6, characterized in that: When the LDO output end is hard short-circuited or overloaded, the source voltage of the sampling tube follows the LDO output voltage and is extremely low, and the drain voltage of the M3 tube is extremely low, so that the drain-source voltage difference of the M3 tube is smaller than the difference between the gate-source voltage difference of the M3 tube and the threshold voltage of the M3 tube, so that the M3 tube is in a non-saturated state and works in a linear region; at the same time, the drain-source voltage difference of the M4 tube is greater than the difference between the gate-source voltage difference of the M4 tube and the threshold voltage of the M4 tube, so that the M4 tube works in a saturated region.

8. The overcurrent protection circuit according to claim 6, characterized in that: The three-stage mirror module includes: a MOS tube M1 and a MOS tube M2; The gates of the M1 tube and the M2 tube are connected, the drain of the M1 tube is respectively connected to the gate connection line of the M1 tube and the M2 tube and the drain of the M4 tube, and the source of the M1 tube is connected to the LDO input terminal; The drain of the M2 tube is connected to the gate of the switch tube M0 and the reference current terminal respectively, and the source of the M2 tube is connected to the LDO input terminal.

9. An LDO chip, characterized in that: include: A reference source, an error amplifier, a power tube and an overcurrent protection circuit as claimed in any one of claims 1 to 8; The output end of the LDO is connected to a feedback network and a load; The non-inverting input terminal of the error amplifier is connected to the reference voltage terminal output by the reference source, the inverting input terminal is connected to the feedback network, and the output terminal of the error amplifier is respectively connected to the overcurrent protection circuit and the power tube gate; The source of the power tube is connected to the LDO output terminal, and the drain is connected to the LDO input terminal; The other end of the overcurrent protection circuit is connected to the LDO input end.

10. An overcurrent protection method based on the overcurrent protection circuit according to any one of claims 1 to 8, characterized in that: Methods include: Connect the drains of the sampling tube and the power tube to the LDO input terminal; The source electrodes of the sampling tube and the power tube are clamped by using a clamping module so that the voltage at the source end of the sampling tube is equal to the LDO output voltage. Based on the fact that the voltage at the source end of the sampling tube and the LDO output voltage are both less than the LDO input voltage, the LDO input voltage is used to power the clamping module; wherein the source electrode of the power tube is connected to the LDO output end; The sampling tube and the clamping module are used to perform accurate mirror sampling on the load current of the power tube.

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