A method for realizing low-order crossover between multiple VC4 and arbitrary VC12

Abstract

The present invention relates to the field of communication technology, and in particular to a method for realizing low-order crossover of arbitrary VC12 of multiple VC4s, comprising adopting two-level data cache and two-level data polling readout operation to write data into a pipeline; adopting two-level data distribution operation to read data out of the pipeline and then distribute it to different FIFOs. The method adopts two-level data cache, the first level is each VC12 data cache of each VC4, the second level is all VC12 data cache of each VC4, adopts two-level data polling readout, the first level is each VC12 data polling readout of each VC4, the second level is all VC12 data polling readout of each VC4, by separately forming data frames of VC12 data of all VC4s, and then writing the data frames into pipelines; at the receiving end, the data is read out from the pipeline, and distributed to different VC12 caches according to labels, so as to realize low-order crossover of arbitrary VC12 of multiple VC4s.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method for realizing low-order crossover of multiple VC4s and arbitrary VC12s. Background Art

[0002] SDH (Synchronous Digital Hierarchy) is a signal transmission system with high-speed, large-capacity optical fiber transmission technology and intelligent network technology. Due to its unique high flexibility and manageability, it has long become an important development direction of optical fiber communication. SDH supports multiple speed modes. Low-speed SDH signals are formed into high-speed SDH signals through interleaving multiplexing, and the position of low-speed SDH signals in high-speed SDH is fixed and predictable. In this way, low-speed SDH signals can be directly extracted / inserted from high-speed SDH signals, simplifying the signal multiplexing and demultiplexing process, which makes the SDH system particularly suitable for high-speed, large-capacity optical fiber communication systems.

[0003] The most basic transmission rate level of SDH is synchronous transmission module STM1, which is encapsulated by one VC4, and this VC4 data is multiplexed by 63 VC12 data. Therefore, the smallest data unit of SDH transmission is VC12. Each VC12 is mapped from one E1 (electrical interface signal) signal. When there is a need for data exchange with E1 granularity during data transmission, E1 exchange can be avoided and VC12 exchange can be used to implement E1 data exchange.

[0004] The commonly used processing method for SDH signal transmission in the packet transport network is to separate the VC4 data from the SDH, and then encapsulate the VC4 data into Ethernet. At the receiving end, the VC4 data is decrypted from the received Ethernet data packet containing VC4 data, and finally the SDH signal is restored through the VC4 data. Therefore, the data exchange of each VC12 of the SDH signal becomes the data exchange of each VC12 of the VC4.

[0005] At present, SDH data processing is mainly completed through FPGA. When using FPGA to realize low-order cross-connection of multiple VC4 and arbitrary VC12, there are the following deficiencies, such as: when VC12 data in one VC4 is cross-connected arbitrarily, all VC12 have thousands of possibilities, such as Figure 1As shown, if the number of VC4s that need to exchange VC12 is large (such as 16), there are more than one million possibilities for all VC12s. It is impossible for the current FPGA to implement such a complex logic through a multiplexer. In order to solve the difficulty of implementing VC12 crossover through a multiplexer in the existing FPGA, it is urgent to propose a method for implementing low-order crossover of multiple VC4s and arbitrary VC12s. Summary of the invention

[0006] The purpose of the present invention is to provide a method for realizing low-order crossover of multiple VC4 and arbitrary VC12, aiming to solve the problem that it is difficult to realize VC12 crossover through a multiplexer in existing FPGA.

[0007] To achieve the above object, the present invention provides a method for realizing low-order crossover of multiple VC4 and arbitrary VC12, comprising the following steps:

[0008] Use two-level data cache and two-level data polling read operation to write data into the pipeline;

[0009] A two-level data distribution operation is adopted to distribute the data to different FIFOs after reading the data out of the pipeline.

[0010] The two-level data cache includes a first-level cache and a second-level cache, the first-level cache is used to store each VC12 data of each VC4, and the second-level cache is used to store all VC12 data of each VC4, and the two-level data polling includes a first-level polling and a second-level polling, the first-level polling is used to read each VC12 data of each VC4, and the second-level polling is used to read all VC12 data of each VC4.

[0011] The two-level data allocation includes first-level data allocation and second-level data allocation. The first-level data allocation allocates the received VC12 data of the same VC4 to a specified VC4 channel, and the second-level data allocation allocates VC12 of VC4 to different VC12 channels.

[0012] The specific method of using two-level data cache and two-level data polling read operation to write data into the pipeline is as follows:

[0013] When there is no data write request, it is in idle state. When there is a data write request, the discrete data is written into FIFO after data bit width expansion, and the counter is started at the same time;

[0014] A VC12 polling state machine, which starts polling the VC12 buffer FIFO of each VC4 after power-on reset;

[0015] Add a label field at the beginning of the read data and write the corresponding VC12 label at the low position;

[0016] The 63 channels of VC12 data of each VC4 are written into a FIFO for buffering. When a complete frame of VC12 data is written, the VC4 frame counter starts to increase by 1.

[0017] VC4 polls the state machine, and the state machine starts to poll each VC4 cache FIFO after power-on reset. When the FIFO counters of all VC4 are 0, the state machine polls one by one in sequence;

[0018] The corresponding VC4 label is written into the high byte of the label field, and finally the VC12 data with the label is sent into the transmission pipeline.

[0019] The specific method of using a two-level data allocation operation to allocate data to different FIFOs after reading the data out of the pipeline is as follows:

[0020] When no data frame is received, the receiving state machine is in an idle state. When a complete data frame is received, the state machine starts to jump and judge the length of the data frame. If the length of the data frame is inconsistent with the set length, the data frame is discarded and the state machine returns to the starting state. If the length of the data frame meets the requirements, the data is split into bit widths.

[0021] The split data enters the first-level state machine, where the VC4 tag is judged. If the VC4 tag is within the set range, the VC4 data is allocated.

[0022] When the VC4 label is allocated, the VC12 label is judged. If the VC12 label is within the set range, the cache switch corresponding to VC12 is turned on and the VC12 data is written into the corresponding FIFO.

[0023] The invention discloses a method for realizing low-order crossover of arbitrary VC12 in multiple VC4s. The method adopts two-level data cache and two-level data polling readout operation to write data into a pipeline; adopts two-level data distribution operation to read data out of the pipeline and distribute it to different FIFOs. The method adopts two-level data cache, the first level is each VC12 data cache of each VC4, the second level is all VC12 data cache of each VC4, adopts two-level data polling readout, the first level is each VC12 data polling readout of each VC4, the second level is all VC12 data polling readout of each VC4, and adopts two-level label determination to realize data distribution operation, the first level is each VC4 data label, the second level is each VC12 data label of each VC4, by forming VC12 data of all VC4s into data frames separately, and then writing the data frames into the pipeline; at the receiving end, the data is read out from the pipeline and distributed to different VC12 caches according to the labels, so as to realize low-order crossover of arbitrary VC12 in multiple VC4s. The method solves the problem that it is difficult to realize VC12 crossover through a multiplexer in the existing FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 This is a schematic diagram of how any VC12 in a VC4 can be crossed through a multiplexer.

[0026] Figure 2 It is a block diagram of the process of writing data into the pipeline.

[0027] Figure 3 It is a block diagram of the process of allocating data to different FIFOs after reading out of the pipeline.

[0028] Figure 4 The present invention provides a flowchart of a method for realizing low-order crossover of multiple VC4 and arbitrary VC12.

[0029] Figure 5 It is a flow chart of a specific method of writing data into a pipeline by using two-level data caching and two-level data polling read operations.

[0030] Figure 6 It is a flow chart of a specific method of using a two-level data distribution operation to distribute data to different FIFOs after reading the data out of the pipeline. DETAILED DESCRIPTION

[0031] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0032] See also Figures 1 to 6 The present invention provides a method for realizing low-order crossover of multiple VC4 and arbitrary VC12, comprising the following steps:

[0033] S1 uses two-level data caching and two-level data polling read operations to write data into the pipeline;

[0034] In an embodiment of the present invention, the two-level data cache includes a first-level cache and a second-level cache, the first-level cache is used to store each VC12 data of each VC4, and the second-level cache is used to store all VC12 data of each VC4, and the two-level data polling includes a first-level polling and a second-level polling, the first-level polling is used to read each VC12 data of each VC4, and the second-level polling is used to read all VC12 data of each VC4.

[0035] Specific method:

[0036] S11 is in an idle state when there is no data write request. When there is a data write request, the discrete data is written into the FIFO after the data bits are widened, and the counter is started at the same time;

[0037] In the embodiment of the present invention, when there is no data write request, the system is in an idle state. When there is a data write request, in order to improve data processing efficiency, the VC12 discrete data separated from VC4 is firstly widened by the data bit number (this solution widens 2 8-bit input data into 16-bit data, which can actually be changed according to the amount of data) and then written into the FIFO and the counter counting is started at the same time. When the number of discrete data written reaches the set number, a flag bit that is aligned with the last data of a frame of data and maintains a periodic pulse is generated as the data end flag bit. The data end flag bit and the frame data are written into the cache FIFO together, and then the data counter is cleared to 0, and the frame counter is incremented by 1 at the same time, indicating that the storage of a frame of data has been completed, and step S12 is executed.

[0038] S12VC12 polling state machine, which starts polling the VC12 buffer FIFO of each VC4 after power-on reset;

[0039] In the embodiment of the present invention, the VC12 polling state machine starts to poll the VC12 buffer FIFO of each VC4 after power-on reset. When the frame counters of the 63 buffer FIFOs are all 0, the state machine polls one by one in order. When the frame counter of a certain VC12 is not 0, the state machine starts to read data from the FIFO. When the frame end flag of the read data is 1, the FIFO is closed, indicating that the data of the specified length of the VC12 has been read from the FIFO. The polling state machine performs a delay operation, and after the delay is completed, the next FIFO is polled, and step S13 is executed.

[0040] S13 adds a label field at the beginning of the read data and writes the corresponding VC12 label at the low position;

[0041] In the embodiment of the present invention, a 16-bit label field is added at the beginning of the read data, and the corresponding VC12 label is written at the lower 8-bit position, and S14 is executed.

[0042] S14 writes the 63 channels of VC12 data of each VC4 into a FIFO for buffering. When a complete frame of VC12 data is written, the VC4 frame counter starts to increase by 1.

[0043] In the embodiment of the present invention, 63 channels of VC12 data of each VC4 are written into a FIFO for buffering. When a complete frame of VC12 data is written, the VC4 frame counter starts to add 1 and executes S15.

[0044] S15VC4 polls the state machine. After the state machine is powered on and reset, it starts to poll each VC4 cache FIFO. When the FIFO counters of all VC4 are 0, the state machine polls one by one in sequence.

[0045] In the embodiment of the present invention, the VC4 polling state machine starts to poll each VC4 buffer FIFO after power-on reset. When the FIFO counters of all VC4 are 0, the state machine polls one by one in sequence. When a VC4 frame counter is not 0, the state machine starts to read data from the FIFO, closes the FIFO when a complete frame of VC12 data is read, and performs a subtraction operation on the VC4 frame counter. The polling state machine performs a delay operation, and after the delay is completed, the next FIFO is polled, and S16 is executed.

[0046] S16 writes the corresponding VC4 label into the high byte of the label field, and finally sends the VC12 data with the label into the transmission pipeline.

[0047] In the embodiment of the present invention, the corresponding VC4 label is written into the high byte of the 16-bit label field. Finally, the VC12 data with the label is sent into the transmission pipeline.

[0048] S2 uses a two-level data distribution operation to distribute data to different FIFOs after reading the data out of the pipeline.

[0049] In the embodiment of the present invention, the two-level data allocation includes first-level data allocation and second-level data allocation. The first-level data allocation allocates the received VC12 data of the same VC4 to a specified VC4 channel, and the second-level data allocation allocates VC12 of VC4 to different VC12 channels.

[0050] Specific method:

[0051] S21: When no data frame is received, the receiving state machine is in an idle state. When a complete data frame is received, the state machine starts to jump and judges the length of the data frame. If the length of the data frame is inconsistent with the set length, the data frame is discarded and the state machine returns to the starting state. If the length of the data frame meets the requirements, the data is split into bit widths.

[0052] In the embodiment of the present invention, when no data frame is received, the receiving state machine is in an idle state. When a complete data frame is received, the state machine starts to jump, firstly judging the length of the data frame. If the length of the data frame is inconsistent with the set length, the data frame is discarded and the state machine returns to the start state. If the length of the data frame meets the requirements, the data is split into 8-bit data by bit width (this solution splits the 16-bit input data into 8-bit data, which can actually be changed according to the amount of data), and S22 is executed.

[0053] S22: The split data enters the first level state machine, and the VC4 label is judged. If the VC4 label is within the set range, the VC4 data is allocated and S23 is executed;

[0054] S23: After the VC4 label is allocated, the VC12 label is judged. If the VC12 label is within the set range, the cache switch corresponding to VC12 is turned on to write the VC12 data into the corresponding FIFO.

[0055] The above disclosure is only a preferred embodiment of a method for realizing low-order crossover of multiple VC4 and arbitrary VC12 of the present invention, which certainly cannot be used to limit the scope of the present invention. A person skilled in the art can understand that all or part of the processes of the above embodiment can be realized, and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.

Claims

1. A method for realizing low-order crossover of multiple VC4 and arbitrary VC12, characterized in that: The steps include: Use two-level data cache and two-level data polling read operation to write data into the pipeline; A two-level data distribution operation is adopted to distribute the data to different FIFOs after reading the data out of the pipeline.

2. The method for realizing low-order crossover of multiple VC4 and arbitrary VC12 as claimed in claim 1, characterized in that: The two-level data cache includes a first-level cache and a second-level cache, the first-level cache is used to store each VC12 data of each VC4, and the second-level cache is used to store all VC12 data of each VC4. The two-level data polling includes a first-level polling and a second-level polling, the first-level polling is used to read each VC12 data of each VC4, and the second-level polling is used to read all VC12 data of each VC4.

3. The method for realizing low-order crossover of multiple VC4 and arbitrary VC12 as claimed in claim 1, characterized in that: The two-level data allocation includes a first-level data allocation and a second-level data allocation. The first-level data allocation allocates the received VC12 data of the same VC4 to a designated VC4 channel, and the second-level data allocation allocates the VC12 of the VC4 to different VC12 channels.

4. The method for realizing low-order crossover of multiple VC4 and arbitrary VC12 as claimed in claim 1, It is characterized by: The specific method of using two-level data cache and two-level data polling read operation to write data into the pipeline is as follows: When there is no data write request, it is in idle state. When there is a data write request, the discrete data is written into FIFO after data bit width expansion, and the counter is started at the same time; A VC12 polling state machine, which starts polling the VC12 buffer FIFO of each VC4 after power-on reset; Add a label field at the beginning of the read data and write the corresponding VC12 label at the low position; The 63 channels of VC12 data of each VC4 are written into a FIFO for buffering. When a complete frame of VC12 data is written, the VC4 frame counter starts to increase by 1. VC4 polls the state machine, and the state machine starts to poll each VC4 cache FIFO after power-on reset. When the FIFO counters of all VC4 are 0, the state machine polls one by one in sequence; The corresponding VC4 label is written into the high byte of the label field, and finally the VC12 data with the label is sent into the transmission pipeline.

5. The method for realizing low-order crossover of multiple VC4 and arbitrary VC12 as claimed in claim 1, It is characterized by: The specific method of using two-level data allocation operation to allocate data to different FIFOs after reading data out of the pipeline is as follows: When no data frame is received, the receiving state machine is in an idle state. When a complete data frame is received, the state machine starts to jump and judge the length of the data frame. If the length of the data frame is inconsistent with the set length, the data frame is discarded and the state machine returns to the starting state. If the length of the data frame meets the requirements, the data is split into bit widths. The split data enters the first-level state machine, where the VC4 tag is judged. If the VC4 tag is within the set range, the VC4 data is allocated. When the VC4 label is allocated, the VC12 label is judged. If the VC12 label is within the set range, the cache switch corresponding to VC12 is turned on and the VC12 data is written into the corresponding FIFO.

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