Memory management method and memory controller

Abstract

The present disclosure provides a memory management method and a memory controller. The method comprises: obtaining the block usage of a plurality of physical blocks of a rewritable non-volatile memory module and the working state of a storage device; when the working state is a busy state, determining whether to perform a garbage collection operation according to the block usage and the host write demand; and when the garbage collection operation is performed during the host write operation, dynamically adjusting the write speed of the host write operation according to the number of remaining blocks. The method significantly improves the execution efficiency of the garbage collection operation by real-time monitoring of the physical block usage and the host write behavior, and effectively improves the write performance of the storage device under high load conditions.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of memory technology, and in particular, to a memory management method and a memory controller. BACKGROUND

[0002] Non-volatile memory refers to computer storage that does not lose stored data when the current is interrupted. It has the advantages of data non-volatility, power saving, small size, and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is a memory configured with NAND flash memory (such as a solid state disk), which has the characteristics of high read-write speed and does not require mechanical structures for data access.

[0004] In existing storage devices, the total number of available physical blocks of a rewritable non-volatile memory module (e.g., NAND flash memory) is determined. As the host system continues to perform write operations, the physical blocks in the storage device will be continuously consumed. When the physical blocks are about to be exhausted, the firmware of the storage device must start a garbage collection operation to release the physical blocks occupied by invalid data. However, in order to ensure that the release speed of the physical blocks is faster than the consumption speed of the physical blocks, the storage device must limit the write speed of the host write operation. In the prior art, if the garbage collection operation releases the physical blocks at a slow speed, the storage device will suddenly limit the host write operation to a lower speed range, and the sudden drop in write speed may cause the host system to have performance stalls. SUMMARY

[0005] The present disclosure provides a memory controller and a control method thereof for dynamically adjusting the write speed according to the working condition of the storage device, the usage of the data blocks, and the host behavior, which can solve the technical problem of performance stalls of the host system caused by the sudden reduction of the write speed of the storage device in the prior art.

[0006] One or more embodiments of the present disclosure provide a memory management method suitable for a storage device configured with a rewritable non-volatile memory module. The method comprises: obtaining the block usage of a plurality of physical blocks of the rewritable non-volatile memory module; obtaining the working state of the storage device; when the working state of the storage device is a busy state, then: determining whether to perform a garbage collection operation according to the block usage of the plurality of physical blocks and the host write demand of the storage device; and when the garbage collection operation is performed during the host write operation, dynamically adjusting the write speed of the host write operation according to the number of the plurality of remaining blocks in the plurality of physical blocks.

[0007] In one or more embodiments of the present disclosure, the method further comprises: when the working state of the storage device is an idle state, obtaining a first total valid data amount of a plurality of first written physical blocks in the plurality of physical blocks, and determining whether to perform a pre-garbage collection operation according to the first total valid data amount; and when a host write instruction is received during the execution of the pre-garbage collection operation, suspending the pre-garbage collection operation.

[0008] In one or more embodiments of the present disclosure, the step of determining whether to perform the pre-garbage collection operation according to the first total valid data amount comprises: obtaining a first valid data ratio between the first total valid data amount and a total storage space of the plurality of first written physical blocks; and when the first valid data ratio is less than a first valid data ratio threshold, determining to perform the pre-garbage collection operation, wherein the step of suspending the pre-garbage collection operation comprises: not limiting a write speed of another host write operation corresponding to the host write instruction.

[0009] In one or more embodiments of the present disclosure, the step of determining whether to perform the garbage collection operation according to the block usage of the plurality of physical blocks and the host write demand of the storage device comprises: obtaining a first total number of a plurality of remaining blocks in the plurality of physical blocks that have not been written; recording a second total number of a plurality of second written physical blocks in the plurality of remaining blocks; when a ratio of the second total number to the first total number exceeds a usage threshold, determining the host write demand; and when the determined host write demand is a high demand, determining to perform the garbage collection operation; and when the determined host write demand is not the high demand, determining not to perform the garbage collection operation.

[0010] In one or more embodiments of the present disclosure, the step of determining the host write demand comprises: obtaining a second total valid data amount of the plurality of second written physical blocks; obtaining a second valid data ratio between the second total valid data amount and a total storage space of the plurality of second written physical blocks; and when the second valid data ratio exceeds a second valid data ratio threshold, determining that the host write demand is a high demand.

[0011] In one or more embodiments of the present disclosure, the step of performing the garbage collection operation comprises: selecting one or more target collection physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target collection physical blocks, wherein an effective data ratio of each target collection physical block is less than a collection effective data ratio threshold.

[0012] In one or more embodiments of the present disclosure, wherein the step of dynamically adjusting the write speed of the host write operation according to the number of the remaining blocks in the plurality of physical blocks comprises: obtaining a reclaim write speed of the garbage collection operation; and adjusting the write speed of the current host write operation according to the first total number of the remaining blocks in the plurality of physical blocks that have not been written and the reclaim write speed.

[0013] In one or more embodiments of the present disclosure, wherein the step of adjusting the write speed of the current host write operation according to the first total number of the remaining blocks in the plurality of physical blocks that have not been written and the reclaim write speed comprises: obtaining a first remaining ratio between the first total number and a total number of the plurality of physical blocks; and adjusting the write speed using the reclaim write speed according to the first remaining ratio.

[0014] In one or more embodiments of the present disclosure, wherein the step of adjusting the write speed using the reclaim write speed according to the first remaining ratio comprises: obtaining a current remaining ratio interval corresponding to the first remaining ratio; determining a corresponding speed adjustment multiple according to the remaining ratio interval, wherein a lower remaining ratio interval corresponds to a lower speed adjustment multiple; and adjusting the write speed using the reclaim write speed of the garbage collection operation and the speed adjustment multiple, wherein if the remaining ratio interval is a highest remaining ratio interval, the write speed of the host write operation is not adjusted.

[0015] In one or more embodiments of the present disclosure, wherein the step of dynamically adjusting the write speed of the host write operation according to the number of the remaining blocks in the plurality of physical blocks further comprises: when the first total number of the remaining blocks in the plurality of physical blocks that have not been written reaches a critical remaining number, determining that the remaining ratio interval is a lowest remaining ratio interval, and performing the following steps: selecting one or more target reclaim physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target reclaim physical blocks; obtaining an effective data ratio of each target reclaim physical block; and adjusting the write speed of the host write operation according to the effective data ratio of the target reclaim physical block and a target reclaim write speed corresponding to the target reclaim physical block.

[0016] In one or more embodiments of the present disclosure, wherein the step of adjusting the write speed of the host write operation according to the valid data proportion of the target reclaimed physical block and the target reclaimed write speed corresponding to the target reclaimed physical block comprises: determining an emergency speed adjustment multiple based on a comparison result of the valid data proportion and another reclaimed valid data proportion threshold; and adjusting the write speed of the host write operation using the target reclaimed write speed and the emergency speed adjustment multiple.

[0017] In one or more embodiments of the present disclosure, wherein the step of suspending the pre-garbage collection operation further comprises: obtaining a current execution progress of the pre-garbage collection operation; recording breakpoint information corresponding to the current execution progress; and setting a recovery identifier based on the breakpoint information, wherein when the host write instruction execution is completed, it is judged whether to resume execution of the pre-garbage collection operation according to the recovery identifier.

[0018] In one or more embodiments of the present disclosure, wherein the step of determining the host write demand comprises: setting a sliding time window; within the sliding time window, calculating a cumulative write data amount according to the logical address range of the received host write instruction; and when the cumulative write data amount exceeds a preset data amount threshold, determining that the host write demand is the high demand.

[0019] In one or more embodiments of the present disclosure, wherein the step of adjusting the write speed using the reclaimed write speed of the garbage collection operation and the speed adjustment multiple comprises: obtaining a last write speed; calculating a speed difference value between a current target write speed and the last write speed; judging whether a smooth transition is needed according to the speed difference value; and if it is judged that the smooth transition is needed, gradually adjusting the write speed to the target write speed within a preset transition period.

[0020] Based on the above, the memory management method and the memory controller provided by the embodiments of the present disclosure effectively reduce the concentrated reclaim overhead when the physical block is about to be exhausted by performing garbage collection in advance according to the valid data amount when the storage device is idle; the write demand is pre-judged using a host write behavior analysis mechanism, and a hierarchical speed limiting strategy is implemented according to the number of remaining physical blocks, so that the adjustment of the write speed is more smooth; the speed limiting multiple is dynamically adjusted based on the valid data proportion of the target reclaimed physical block in the critical state, which avoids the sudden drop of the write speed caused by the too low garbage collection efficiency, and significantly improves the performance stability of the storage device under high load. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0022] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present application;

[0023] Figure 2 is a flowchart of a memory management method according to an embodiment of the present application;

[0024] Figure 3 is a flowchart of determining a host write demand according to an embodiment of the present application;

[0025] Figure 4 is a flowchart of dynamically adjusting a write speed according to an embodiment of the present application;

[0026] Figure 5 is a flowchart of dynamically adjusting a write speed in a critical state according to an embodiment of the present application;

[0027] Figure 6 is a diagram of a relationship between a speed adjustment ratio and a remaining ratio according to an embodiment of the present application;

[0028] Figure 7 is a diagram of a relationship between an emergency speed adjustment ratio and an effective data ratio according to an embodiment of the present application.

[0029] BRIEF DESCRIPTION OF DRAWINGS

[0030] 10: host system

[0031] 20: storage device

[0032] 211: first processor

[0033] 110: second processor

[0034] 120: host memory

[0035] 130: data transfer interface circuit

[0036] 210: memory controller

[0037] 212: data management circuit

[0038] 213: memory interface control circuit

[0039] 214: buffer memory

[0040] 220: rewritable non-volatile memory module

[0041] 230: connection interface circuit

[0042] S210-S240: Steps of the memory management method

[0043] S310-S390: Steps of determining the host write demand

[0044] S410-S450: Steps of dynamically adjusting the write speed

[0045] S510-S540: Steps of dynamically adjusting the write speed in the critical state

[0046] CT61: Chart of the speed adjustment ratio and the total number of remaining blocks

[0047] CT71: Chart of the emergency speed adjustment ratio and the effective data proportion

[0048] RS61: Lowest remaining proportion interval

[0049] RS62: Medium remaining proportion interval

[0050] RS63: High remaining proportion interval

[0051] RS64: Highest remaining proportion interval

[0052] RS71: Low effective data proportion area

[0053] RS72: High effective data proportion area

[0054] SL1, SL2: Slope DETAILED DESCRIPTION

[0055] Reference will now be made to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used throughout the drawings and the description to refer to the same or like parts.

[0056] Figure 1 The block schematic diagram of the host system and the storage device illustrated according to the embodiments of the present disclosure. Please refer to Figure 1The host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor) and a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled to (also referred to as electrically connected to) the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other by a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 can be disposed on a host board of the host system 10.

[0057] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0058] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transfer interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

[0059] In the present embodiment, the number of data transfer interface circuits 130 can be one or more. Through the data transfer interface circuits 130, the host board can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. In addition, the host board can also be electrically connected to various I / O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. via a system bus.

[0060] In the present embodiment, the data transfer interface circuits 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, data transfer between the data transfer interface circuits 130 and the connection interface circuit 230 is performed using the Non-Volatile Memory express (NVMe) communication protocol.

[0061] In another embodiment, the connection interface circuit 230 can be packaged in a chip with the memory controller 210, or the connection interface circuit 230 can be disposed outside a chip containing the memory controller 210.

[0062] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 can be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), etc. However, it must be understood that the present disclosure is not limited thereto, and the host memory 120 can also be other suitable memories.

[0063] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10.

[0064] In more detail, the processor 211 in the memory controller 210 is a hardware with computing capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is in operation, the control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in the present embodiment, the control instructions / program codes can also be executed to implement the memory management method provided by the present disclosure. The control instructions / program codes corresponding to the memory management can also be implemented as a circuit unit in hardware form to implement the memory management method provided by the present disclosure.

[0065] It is worth mentioning that, in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and the present disclosure is not limited thereto.

[0066] In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the memory controller 210 can also be considered as operations performed by the memory controller 210.

[0067] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to accept the indication of the processor 211 to perform data transmission. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation (also referred to as a host write operation) is performed according to a write instruction (also referred to as a host write instruction) from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 (the data can be read from one or more storage units of the one or more physical units) via the memory interface control circuit 213, and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0068] The memory interface control circuit 213 is used to accept the indication of the processor 211 to perform a write (also referred to as programming) operation, a read operation, or an erase operation (also referred to as an erasure operation) on the rewritable non-volatile memory module 220 in cooperation with the data management circuit 212.

[0069] In addition, data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 transmits a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the command sequence can include a write instruction sequence to instruct writing data, a read instruction sequence to instruct reading data, an erase instruction sequence to instruct erasing data, and corresponding instruction sequences to instruct various memory operations. The command sequence can include one or more signals, or data on a bus. The signals or data can include instruction codes or program codes. For example, in the read instruction sequence, identification codes, memory addresses, physical addresses, and the like are included.

[0070] In the present disclosure, the memory controller 210 establishes a logical to physical address mapping table (also referred to as an L2P mapping table) and a physical to logical address mapping table (also referred to as a P2L mapping table) to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages, or logical columns) configured to the rewritable non-volatile memory module 220 and the physical addresses of physical units (e.g., physical erase units / physical blocks, physical pages, or physical columns). In other words, the memory controller 210 can look up the physical unit mapped by a logical unit (e.g., look up the physical page mapped by a logical page; look up the physical address mapped by a logical address) through the logical to physical address mapping table (also referred to as a logical to physical mapping table), and the memory controller 210 can look up the logical unit mapped by a physical unit (e.g., look up the logical page mapped by a physical page; look up the logical address mapped by a physical address) through the physical to logical address mapping table (also referred to as a physical to logical mapping table).

[0071] In an embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data (e.g., various mapping tables, index tables, block usage information of physical blocks, various total valid data amounts, various valid data proportions, various remaining proportions, speed adjustment multiples of various remaining proportion intervals, cumulative write data amount statistics within a sliding time window, breakpoint information, and its recovery identifier, and other system data associated with the present memory management method) used to manage the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214.

[0072] In an embodiment, the memory controller 210 reserves specific regions in the buffer memory 214 for storing various mapping tables and index information. The memory controller 210 classifies and caches these data according to access frequency and importance: frequently accessed mapping table information is saved in a fast access region, while less frequently used information is stored in a normal region. When the buffer memory 214 is insufficient in space, the memory controller 210 preferentially writes the less frequently used information back to the rewritable non-volatile memory module 220. In order to improve data reliability, the memory controller 210 also periodically synchronizes important mapping information in the buffer memory 214 to the rewritable non-volatile memory module 220 and records the synchronization timestamp, so that the system can be restored to the most recent valid state in the event of a system anomaly.

[0073] In another embodiment, the memory controller 210 stores these data structures in a pre-set area in the buffer memory and periodically synchronizes their updated status to the rewritable non-volatile memory module to ensure data persistence and consistency. In some embodiments, when the memory controller 210 is restarted, the latest status of these data structures can be recovered from the rewritable non-volatile memory module, ensuring that the system can continue the previous storage management operation.

[0074] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store the data written by the host system 10.

[0075] In the present embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, each of which is electrically connected to a plurality of storage units, also known as columns (also known as physical columns). The plurality of columns on the same word line will form a physical programming unit (also known as a physical page or a physical page). Each physical page will correspond to a physical address to record the location of the data stored in the physical page. In addition, a plurality of physical pages can form a physical block (also known as a physical erase unit or a physical block). Each memory die (chip) of the rewritable non-volatile memory module has a plurality of planes, and each plane has a plurality of physical blocks. It should be noted that the present disclosure is not limited to the size of each physical page and logical page.

[0076] The storage unit type (also known as storage mode) can be used to represent the number of bits that each storage unit (Memory Cell, also known as storage unit) can store. Common types include SLC (Single Layer Storage Unit, each storage unit stores 1 bit), MLC (Multi-Layer Storage Unit, each storage unit stores 2 bits), TLC (Three-Layer Storage Unit, each storage unit stores 3 bits), etc. Different storage modes differ in storage density, read / write speed, and durability, etc., affecting the overall performance and characteristics of the flash memory.

[0077] Figure 2 is a flowchart of a memory management method according to an embodiment of the present application;

[0078] Referring to Figure 2In one embodiment, the memory controller 210 performs a memory management method. Specifically, in step S210, the memory controller 210 acquires the block usage of a plurality of physical blocks of the rewritable non-volatile memory module 220. The memory controller 210 communicates with the rewritable non-volatile memory module 220 through the memory interface control circuit 213 to acquire the usage status information of each physical block, including the used space, the remaining space, the valid data amount of each data block (written block), and the like. These information are buffered in the buffer memory 214 for subsequent analysis by the processor 211.

[0079] Next, in step S220, the memory controller 210 acquires the working status of the storage device 20.

[0080] In one embodiment, the processor 211 monitors whether there is a write request from the host system 10 through the data management circuit 212. If no write request from the host system 10 is received within a predetermined time window, it is determined that the storage device 20 is in an idle state; otherwise, if it is detected that the host system 10 is performing a write operation or waiting to perform a write operation, it is determined that the storage device 20 is in a busy state.

[0081] In another embodiment, the processor 211 can also consider other factors to determine the working status, such as the system load degree, the current write queue length, and the usage rate of the buffer memory 214.

[0082] Next, in step S230, when the working status of the storage device 20 is in a busy state, the memory controller 210 determines whether to perform a garbage collection operation according to the block usage of the plurality of physical blocks and the host write demand.

[0083] Figure 3 is a flowchart of determining the host write demand according to one embodiment of the present application.

[0084] Referring to Figure 3 In one embodiment, the memory controller 210 performs a method for determining the host write demand. When the working status of the storage device 20 is in a busy state, the memory controller 210 determines the host write demand according to the following steps to decide whether to perform a garbage collection operation.

[0085] In step S310, the processor 211 acquires, through the memory interface control circuit 213, a first total number of a plurality of remaining blocks that have not been written in the plurality of physical blocks of the rewritable non-volatile memory module 220. The processor 211 temporarily stores the first total number in the buffer memory 214 for subsequent calculation and determination.

[0086] Next, in step S320, the processor 211 obtains a second total number of the plurality of second written physical blocks in a predetermined period. Specifically, the processor 211 continuously monitors and records the number of physical blocks actually consumed in the remaining blocks when the host system 10 performs a write operation in the predetermined period (e.g., the last 100 milliseconds or other time, which is not limited in the present disclosure). The second total number is also temporarily stored in the buffer memory 214.

[0087] Next, in step S330, the processor 211 determines whether the host write demand needs to be determined according to the first total number and the second total number. Specifically, the processor 211 calculates the ratio of the second total number to the first total number. When the ratio exceeds a preset usage threshold (e.g., 10% or other predetermined ratio, which is not limited in the present disclosure), it indicates that the consumption speed of the physical blocks in the recent period is relatively fast, and the processor 211 determines that the host write demand needs to be further determined (e.g., starts to perform the operation of determining the host write demand). Conversely, if the ratio does not exceed the usage threshold, the processor 211 returns to step S310 to continue monitoring the usage of the physical blocks.

[0088] If it is determined in step S330 that the host write demand needs to be determined, the processor 211 obtains the total valid data amount of the plurality of second written physical blocks in step S340.

[0089] In an embodiment, the processor 211 can obtain the second total valid data amount by a real-time counter mechanism. Specifically, when the host system 10 performs a write operation, the processor 211 maintains a valid data counter for each second written physical block. When new data is written, the counter of the corresponding physical block is incremented by one; when data is overwritten or deleted, the counter of the source physical block is decremented by one, and the counter of the target physical block is incremented by one. The processor 211 can obtain the second total valid data amount by accumulating the values of these counters.

[0090] In another embodiment, the processor 211 can obtain the second total valid data amount by a mapping table scanning method. Specifically, the processor 211 maintains a logical-to-physical mapping table in the buffer memory 214, which records whether each physical address stores valid data. By scanning the mapping table, the processor 211 can count the number of mapped addresses in each second written physical block, thereby calculating the second total valid data amount.

[0091] In yet another embodiment, the processor 211 can use a hybrid acquisition method. Specifically, the counter is used for real-time statistics during normal writing, and the mapping table scanning is used periodically to correct the counter value, thereby improving the accuracy of the second total valid data amount statistics.

[0092] Next, in step S350, the processor 211 obtains a second valid data ratio between the second total valid data amount and the total storage space of the plurality of second written physical blocks. Specifically, the processor 211 first calculates the total storage space of the second written physical blocks, and then divides the second total valid data amount by the total storage space to obtain the second valid data ratio.

[0093] Next, in step S360, the processor 211 determines whether the second valid data ratio exceeds a second valid data ratio threshold. When the second valid data ratio exceeds a predetermined threshold (e.g., 90% or other predetermined proportion, which is not limited in the present disclosure), it indicates that the recently written data blocks contain a large amount of valid data, and the processor 211 determines in step S370 that the current host write demand is high demand, and performs a garbage collection operation in step S380 (even if the host write operation is currently being performed, the garbage collection operation will be performed).

[0094] Conversely, if the second valid data ratio does not exceed the threshold, the processor 211 determines in step S390 that the host write demand is not high demand. In this case, the processor 211 can perform the following operations: first, the processor 211 maintains the current host write speed at a high level without starting the write speed limiting mechanism. Second, the processor 211 can allocate system resources to the host write operation first, and postpone the garbage collection operation until the storage device 20 is idle. In this way, the memory controller 210 ensures the host write performance.

[0095] In an embodiment, when it is determined that the garbage collection operation needs to be performed, the processor 211 selects one or more target collection physical blocks from the plurality of physical blocks. Specifically, the processor 211 obtains the valid data ratio of each physical block, and selects a physical block with a valid data ratio less than a collection valid data ratio threshold (e.g., 30% or other predetermined proportion, which is not limited in the present disclosure) as a target collection physical block. By selecting physical blocks with less valid data for garbage collection, the overhead of data migration can be reduced, and the efficiency of garbage collection can be improved.

[0096] Through the above-mentioned multiple judgment mechanism based on the usage of the physical blocks, the memory controller 210 can timely identify the high-intensity write behavior of the host system 10, and start the garbage collection operation in advance, thereby avoiding passive execution of garbage collection when the physical block resources are tight. This pre-judgment management method significantly improves the performance of the storage device 20 under high load conditions.

[0097] In some embodiments, the processor 211 can dynamically adjust the above-mentioned thresholds according to the actual application scenario of the storage device 20, for example:

[0098] (1) In high performance mode, the second valid data ratio threshold can be lowered. The advantage of lowering the second valid data ratio threshold in high performance mode is that high performance mode usually has higher requirements on write speed and response time. Lowering the threshold means that even if the proportion of valid data in the data block is relatively low, it will be determined as high write demand. In this way, lowering the second valid data ratio threshold in high performance mode can trigger the garbage collection operation earlier to release the physical block resources in advance to avoid being forced to perform garbage collection when the physical block resources are tight, thereby reducing the write delay.

[0099] (2) In low power mode, the usage threshold can be increased: the advantage of increasing the usage threshold in low power mode is that low power mode prioritizes reducing system resource consumption. Increasing the usage threshold means that a higher proportion of physical block consumption is required to trigger garbage collection judgment. In this way, increasing the usage threshold in low power mode can reduce unnecessary garbage collection operations and reduce power consumption. In addition, since low power mode has lower performance requirements, it can tolerate higher write delay.

[0100] In an embodiment, if the processor 211 determines that the host write demand is high demand, it is decided to perform the garbage collection operation. On the contrary, if it is determined that the host write demand is not high demand, the garbage collection operation is not performed. Through this judgment mechanism based on the analysis of host write behavior, the memory controller 210 can start the garbage collection operation at the appropriate time, effectively balancing the storage performance and resource utilization efficiency.

[0101] In another embodiment, the processor 211 can use a sliding time window mechanism to determine the host write demand. Specifically, the processor 211 sets a sliding time window of a fixed size (such as 100 milliseconds or other predetermined time, the present disclosure is not limited thereto), which continuously moves forward over time. Within this time window, the processor 211 records and accumulates the logical address range of each write instruction sent by the host system 10, and calculates the cumulative write data amount. When the cumulative write data amount exceeds the preset data amount threshold, the processor 211 determines that the current host write demand is high demand. This judgment method based on the sliding time window can accurately reflect the write pressure of the host system 10 in a certain time period.

[0102] Back to Figure 2Then, in step S240, when performing the garbage collection operation during the host write operation, the memory controller 210 dynamically adjusts the write speed of the host write operation according to the number of the plurality of remaining blocks. Specifically, the processor 211 acquires the collection write speed of the garbage collection operation, and adjusts the write speed according to a first remaining ratio between the first total number of the remaining blocks and the total number of the physical blocks. For example, when the first remaining ratio is in different intervals, the processor 211 adopts different speed adjustment multiples, wherein a lower remaining ratio interval corresponds to a lower speed adjustment multiple. If the remaining ratio interval is the lowest remaining ratio interval, the processor 211 further adjusts the write speed according to the effective data ratio of the target collection physical block, to ensure smooth transition of system performance.

[0103] Through the above steps, the memory controller 210 can dynamically adjust the write speed according to the host write behavior, effectively avoiding sudden reduction of the write speed, and improving the performance stability of the storage device 20.

[0104] In another embodiment, when the storage device 20 is in an idle state (e.g., no write instruction is received from the host system 10 for 100 milliseconds), the memory controller 210 performs a preventive garbage collection management. Specifically, the processor 211 first acquires, through the memory interface control circuit 213, a first total effective data amount of a plurality of first written physical blocks in the rewritable non-volatile memory module 220. The processor 211 temporarily stores the data amount information in the buffer memory 214.

[0105] Subsequently, the processor 211 calculates a first effective data ratio between the first total effective data amount and the total storage space of the plurality of first written physical blocks. Specifically, the processor 211 first acquires the total storage space size of the first written physical blocks, and then divides the first total effective data amount by the total storage space to obtain the first effective data ratio. When the first effective data ratio is less than a preset first effective data ratio threshold (e.g., 70% or other predetermined ratio, which is not limited in the present disclosure), it indicates that there is more invalid data in the current storage space, and the processor 211 determines that a pre-garbage collection operation needs to be performed accordingly.

[0106] During the execution of the pre-garbage collection operation, if the data management circuit 212 receives a write instruction from the host system 10, the processor 211 will immediately suspend the garbage collection operation that is currently being executed. Specifically, the processor 211 records the execution progress of the garbage collection operation, and allocates system resources to the host write operation. It is worth noting that since the garbage collection operation is executed preventively during idle time, when the operation is suspended to process the host write instruction, the processor 211 does not impose any restrictions on the write speed of the host write operation, thereby ensuring that the host write performance is not affected.

[0107] When the pre-garbage collection operation is suspended, the processor 211 can perform a series of state saving operations. Specifically, the processor 211 first obtains the current execution progress of the garbage collection operation, including the number of physical blocks that have been processed, the physical block address that is currently being processed, and the processing position within the physical block. Subsequently, the processor 211 records these breakpoint information in the buffer memory 214, which can be used for location positioning when the garbage collection operation is subsequently resumed.

[0108] The processor 211 also sets a resume identifier based on the recorded breakpoint information. Specifically, the resume identifier contains multiple fields: the identifier of the physical block that is currently being processed, the offset address of the operation within the block, the proportion of garbage collection that has been completed, and the priority of the garbage collection operation. These information is organized into a state description structure and stored in a predetermined area of the buffer memory 214.

[0109] When the host write instruction is executed, the processor 211 determines whether to resume the pre-garbage collection operation based on the resume identifier. Specifically, the processor 211 first checks whether the storage device 20 has re-entered the idle state, and then evaluates the amount of garbage collection that has not been completed, in combination with the current system resource usage, to determine whether to immediately resume the garbage collection operation. If the conditions are met, the processor 211 resumes the garbage collection operation from the breakpoint based on the previously saved breakpoint information, ensuring that the storage space is effectively organized.

[0110] This suspension and resumption mechanism enables the memory controller 210 to dynamically switch between the host write operation and the garbage collection operation, ensuring both the host write performance and the progress information of the garbage collection operation.

[0111] Through this preventive garbage collection mechanism, the memory controller 210 can fully utilize the system idle time to organize the storage space, while not affecting the normal write operation of the host system 10, effectively improving the overall performance of the storage device 20.

[0112] Figure 4FIG. 1 is a flowchart of a method for dynamically adjusting a write speed according to an embodiment of the present application.

[0113] Referring to Figure 4 In an embodiment, the memory controller 210 performs a method for dynamically adjusting a write speed. When performing a garbage collection operation during a host write operation, the processor 211 dynamically adjusts the write speed of the host write operation according to the number of remaining blocks in the plurality of physical blocks, in the following steps.

[0114] In step S410, the processor 211 obtains a collection write speed of a garbage collection operation. In brief, the processor 211 monitors the actual write speed of copying valid data from a source physical block to a target physical block during a garbage collection process, through the memory interface control circuit 213.

[0115] In an embodiment, the memory controller 210 obtains a collection write speed of a garbage collection operation in the following manner. In detail, the processor 211 monitors the process of moving data from a source physical block to a target physical block during a garbage collection operation, through the memory interface control circuit 213. The processor 211 records the number of bytes of data moved in each preset time interval (e.g., 1 millisecond), and stores the value in the buffer memory 214. By calculating the average number of write bytes in a plurality of consecutive time intervals, the processor 211 can obtain the actual collection write speed of the current garbage collection operation.

[0116] In step S420, the processor 211 obtains a first remaining ratio between a first total number of remaining blocks in the plurality of physical blocks that have not been written and a total number of the plurality of physical blocks. In detail, the processor 211 first obtains the total number of physical blocks (also referred to as remaining blocks) in the rewritable non-volatile memory module 220 that have not been written, through the memory interface control circuit 213, and then divides the number by the total number of physical blocks to obtain the first remaining ratio.

[0117] In step S430, the processor 211 obtains a current remaining ratio interval corresponding to the first remaining ratio. In detail, the processor 211 presets a plurality of remaining ratio intervals, for example: 50%-100% is a first interval (also referred to as a highest remaining ratio interval), 30%-50% is a second interval (also referred to as a high remaining ratio interval), 10%-30% is a third interval (also referred to as a medium remaining ratio interval), and less than 10% is a fourth interval (also referred to as a low remaining ratio interval). The processor 211 corresponds the first remaining ratio currently calculated to these preset intervals. It should be noted that the specific settings of the above-mentioned intervals can be changed according to actual needs.

[0118] In step S440, the processor 211 determines the corresponding speed adjustment multiplier based on the remaining percentage range. Specifically, a higher remaining percentage range corresponds to a higher speed adjustment multiplier. For example, the first range corresponds to an unlimited speed adjustment multiplier, the second range corresponds to a speed adjustment multiplier of 5 (also called a high speed adjustment multiplier), the third range corresponds to a speed adjustment multiplier of 3 (also called a medium speed adjustment multiplier), and the fourth range corresponds to a speed adjustment multiplier of 1.5 (also called a low speed adjustment multiplier). This design ensures a high write speed when there is sufficient remaining space, and gradually reduces the write speed when there is insufficient remaining space. It should be noted that the values ​​5, 3, and 1.5 corresponding to the high, medium, and low speed adjustment multipliers are exemplary values ​​used to illustrate the relative magnitude relationship, and the present invention is not limited thereto.

[0119] In step S450, the processor 211 adjusts the write speed using the garbage collection write speed and the speed adjustment factor. Specifically, if the current first remaining percentage is in a first range (i.e., the highest remaining percentage range), the processor 211 does not limit the write speed of the host write operation. If the first remaining percentage is in another range, the processor 211 limits the host write speed to a corresponding multiple of the garbage collection write speed.

[0120] Through this multi-level rate limiting mechanism based on the number of remaining blocks, the memory controller 210 can reasonably adjust the host write speed while ensuring stable system operation.

[0121] Figure 6 This is a schematic diagram illustrating the relationship between the speed adjustment ratio and the remaining percentage according to an embodiment of the present invention.

[0122] Reference Figure 6 In one embodiment, graph CT61 illustrates the relationship between the speed adjustment factor of the memory controller 210 and the total number of remaining blocks. The horizontal axis represents the total number of remaining blocks, and this axis is divided into the lowest remaining percentage range (RS61), the medium remaining percentage range (RS62), the high remaining percentage range (RS63), and the highest remaining percentage range (RS64). The vertical axis represents the speed adjustment factor.

[0123] Specifically, when the total number of remaining blocks is in the highest remaining percentage range RS64, the processor 211 does not limit the host write speed. When the total number of remaining blocks is in other ranges, the processor 211 limits the host write speed according to the speed adjustment factor corresponding to the current range. Among them, RS63 corresponds to a high speed adjustment factor, RS62 corresponds to a medium speed adjustment factor, and RS61 corresponds to a low speed adjustment factor.

[0124] When the total number of remaining blocks reaches the critical remaining number, the processor 211 determines that the current is in the lowest remaining percentage interval RS61. In this case, the processor 211 performs an emergency garbage collection strategy: first, one or more target recovery physical blocks (physical blocks used to perform the pre-garbage collection operation) are selected from the plurality of physical blocks. The processor 211 obtains the valid data percentage of each target recovery physical block through the memory interface control circuit 213, and calculates the optimal data moving strategy according to the percentage information.

[0125] For each target recovery physical block, the processor 211 obtains its actual target recovery write speed, and determines the corresponding write speed limit according to the valid data percentage of the physical block. Specifically, when the valid data percentage of the target recovery physical block is low, the processor 211 can use a relatively high write speed limit; when the valid data percentage is high, a lower write speed limit is used to ensure the reliability of data moving. Through this mechanism, the memory controller 210 can still maintain the stable operation of the system in an emergency.

[0126] In an embodiment, when the processor 211 adjusts the write speed according to the valid data percentage of the target recovery physical block, the following steps are specifically performed. The processor 211 first compares the valid data percentage of the target recovery physical block with a preset another recovery valid data percentage threshold (such as 50% or other predetermined proportion, which is not limited in the present disclosure). Specifically, if the valid data percentage of the target recovery physical block is lower than the threshold, the processor 211 sets the emergency speed adjustment multiple to, for example, 1 times, which means that the amount of valid data in the current target recovery physical block is small, and the garbage collection operation can be completed faster. For example, after the pre-garbage collection operation releases one physical block, the host writes data can fill one empty physical block.

[0127] On the contrary, if the valid data percentage exceeds the threshold, the processor 211 sets the emergency speed adjustment multiple to, for example, between 2 and 3 times, to cope with the larger data moving amount. For example, after the pre-garbage collection operation releases one physical block, the host writes data can fill 2 to 3 physical blocks, so as to slow down the host write speed. Subsequently, the processor 211 sets the write speed limit of the host write operation using the product of the target recovery write speed and the determined emergency speed adjustment multiple.

[0128] It is worth mentioning that, Figure 6 The slopes SL1 and SL2 in the above table represent a smooth transition mechanism. In this embodiment, the processor 211 can use linear interpolation to calculate the speed adjustment multiple at the boundary of adjacent intervals, avoiding the sudden change of write speed when switching between intervals.

[0129] In more detail, in one embodiment, to avoid abrupt change of the write speed, the processor 211 implements a smooth transition mechanism. Specifically, when the write speed needs to be adjusted, the processor 211 first obtains the last write speed value from the buffer memory 214. The processor 211 then calculates the speed difference between the current target write speed and the last write speed. When the difference exceeds a preset threshold (e.g., the current speed change exceeds 30% or other predetermined proportion of the last speed), the processor 211 determines that smooth transition is needed.

[0130] In performing the smooth transition, the processor 211 gradually adjusts the write speed from the last value to the target write speed within a preset transition period (e.g., 10 milliseconds or other predetermined time). Specifically, the processor 211 evenly distributes the speed difference into multiple adjustment steps, each having the same time interval, thereby achieving linear transition of the write speed. This smooth transition mechanism can avoid drastic fluctuation of the write speed.

[0131] Figure 5 is a flowchart of dynamically adjusting the write speed in the critical state according to one embodiment of the present application.

[0132] Referring to Figure 5 In one embodiment, when the first total number of the remaining blocks in the multiple physical blocks that have not been written reaches a critical remaining number (e.g., 3), the memory controller 210 performs a special write speed adjustment process. It should be noted that the specific value of the critical remaining number can be determined according to requirements.

[0133] In step S510, the processor 211 selects one or more target recycling physical blocks from the multiple physical blocks to perform garbage collection operations on these physical blocks. Specifically, the processor 211 scans the usage states of all physical blocks through the memory interface control circuit 213, and preferentially selects physical blocks with lower valid data proportion as target recycling physical blocks.

[0134] In step S520, the processor 211 obtains the valid data proportion of each target recycling physical block. The processor 211 reads the valid data distribution information in these physical blocks through the memory interface control circuit 213, and calculates the actual proportion of valid data in each target recycling physical block compared to the storage space of each target recycling physical block.

[0135] In step S530, the processor 211 determines the emergency speed adjustment multiple based on the comparison result of the valid data proportion and another recycling valid data proportion threshold. Specifically, if the valid data proportion of the target recycling physical block is low, a larger speed adjustment multiple is used; if the valid data proportion is high, a smaller speed adjustment multiple is used to avoid excessive reduction of the write speed.

[0136] In step S540, the processor 211 adjusts the write speed of the host write operation using the target reclaim write speed and the emergency speed adjustment ratio. Through this dynamic adjustment mechanism based on the valid data ratio, the memory controller 210 can still maintain reasonable write performance in the critical state.

[0137] Figure 7 FIG. 7B is a schematic diagram of the relationship between the emergency speed adjustment ratio and the valid data ratio according to an embodiment of the present application.

[0138] Referring to Figure 7 FIG. 7B shows the relationship between the emergency speed adjustment ratio and the valid data ratio in the critical state. The horizontal axis represents the valid data ratio of the target reclaim physical block, which is divided into two regions RS71 and RS72 by another reclaim valid data ratio threshold. The vertical axis represents the corresponding emergency speed adjustment ratio.

[0139] When the valid data ratio of the target reclaim physical block is in the RS71 region (i.e., less than the another reclaim valid data ratio threshold), it indicates that the efficiency of the garbage collection operation is relatively high. At this time, the processor 211 adopts a lower emergency speed adjustment ratio (e.g., 1 times), because each garbage collection operation can quickly release new free blocks.

[0140] On the contrary, when the valid data ratio is in the RS72 region (i.e., exceeds the another reclaim valid data ratio threshold), it indicates that the garbage collection operation needs to move a large amount of valid data, and the efficiency is relatively low. At this time, the processor 211 adopts a higher emergency speed adjustment ratio (e.g., 2 to 3 times), giving the garbage collection operation more execution time to avoid drastic fluctuations in the write speed.

[0141] Through this differentiated adjustment mechanism based on the valid data ratio, the memory controller 210 can still maintain stable operation of the system in the critical state.

[0142] Finally, the present embodiment also provides a computer program product, including computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is executed in the processor of the host system, the processor 211 executes the flow steps of the above memory management method and realizes the function of the memory controller 210. The computer program product can be specifically implemented by hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0143] Based on the above, the memory management method and the memory controller provided by the embodiments of the present disclosure can achieve the following technical effects:

[0144] Firstly, by performing the garbage collection operation in advance according to the first valid data ratio when the storage device 20 is idle, and pausing the operation in time when the host write instruction is received, the recovery pressure of the storage device 20 under high load is reduced. Specifically, the processor 211 records the breakpoint information and sets the recovery identifier, so as to ensure that the garbage collection operation can continue to be executed at the appropriate time, effectively balancing the storage performance and resource utilization.

[0145] Secondly, based on the host write behavior analysis mechanism, the processor 211 can identify the write demand and predict the resource consumption trend in advance. The processor 211 can monitor the physical block usage and the valid data ratio in a predetermined period, or combine the cumulative write data amount in the sliding time window, to accurately evaluate the host write demand.

[0146] Thirdly, a multi-level speed limiting strategy is implemented according to the number of remaining physical blocks, so as to avoid sudden changes in the write speed. The processor 211 predefines a plurality of remaining ratio intervals and corresponding speed adjustment multiples, and adopts a multi-stage transition mechanism when the interval is switched, so that the adjustment of the write speed is more stable.

[0147] Fourthly, a differentiated adjustment mechanism based on the valid data ratio is adopted under the critical state. The processor 211 evaluates the valid data ratio of the target recovered physical block, and selects a suitable emergency speed adjustment multiple, so as to avoid the problem of sudden performance drop caused by excessive limitation of the write speed.

[0148] Fifthly, intelligent smooth adjustment of the write speed is realized. The processor 211 calculates the difference between the target write speed and the last write speed, and starts the smooth transition mechanism when needed, so as to ensure that the write speed is gradually adjusted to the target value within the preset transition period, thereby improving the running stability of the storage device.

[0149] Through the above technical solutions, the memory management method provided by the present disclosure significantly improves the performance of the storage device under various load conditions, and is especially suitable for application scenarios that require frequent data writing.

[0150] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory management method suitable for a storage device configured with a rewritable non-volatile memory module, characterized by, The method comprises: obtaining block usage of a plurality of physical blocks of the rewritable non-volatile memory module; when the storage device is in a busy state, determining whether to perform a garbage collection operation according to the block usage of the plurality of physical blocks and a host write demand of the storage device; and when the garbage collection operation is performed during a host write operation, dynamically adjusting a write speed of the host write operation according to a number of remaining blocks in the plurality of physical blocks, comprising: obtaining a recovery write speed of copying valid data from a source physical block to each target recovery physical block in the garbage collection operation; wherein when a first total number of a plurality of remaining blocks in the plurality of physical blocks that have not been written reaches a critical remaining number, the dynamic adjustment further comprises: obtaining a valid data proportion of each target recovery physical block; and adjusting the write speed of the host write operation according to the valid data proportion of the target recovery physical block and the recovery write speed corresponding to the target recovery physical block. Further comprising: when the storage device is in an idle state, obtaining a first total valid data amount of a plurality of first written physical blocks in the plurality of physical blocks, and determining whether to perform a pre-garbage collection operation according to the first total valid data amount; and 2. The memory management method of claim 1, wherein, when a host write instruction is received during the performance of the pre-garbage collection operation, pausing the pre-garbage collection operation. The step of determining whether to perform the pre-garbage collection operation according to the first total valid data amount comprises: obtaining a first valid data proportion between the first total valid data amount and a total storage space of the plurality of first written physical blocks; 3. The memory management method of claim 2, wherein, when the first valid data proportion is less than a first valid data proportion threshold, determining to perform the pre-garbage collection operation. The step of determining whether to perform the garbage collection operation according to the block usage of the plurality of physical blocks and the host write demand of the storage device comprises: obtaining the first total number of the plurality of remaining blocks in the plurality of physical blocks that have not been written; 4. The memory management method of claim 1, wherein, recording a second total number of a plurality of second written physical blocks in the plurality of remaining blocks; when a ratio of the second total number to the first total number exceeds a usage threshold, determining the host write demand; and if it is determined that the host write demand is a high demand, determining to perform the garbage collection operation. The step of determining the host write demand comprises: obtaining a second total valid data amount of the plurality of second written physical blocks; 5. The memory management method of claim 4, wherein, obtaining a second valid data proportion between the second total valid data amount and a total storage space of the plurality of second written physical blocks; and when the second valid data proportion exceeds a second valid data proportion threshold, determining that the host write demand is a high demand. The step of performing the garbage collection operation comprises: ​ 6. The memory management method of claim 5, wherein, ​ selecting one or more target recycling physical blocks from the plurality of physical blocks, to perform the garbage collection operation on the one or more target recycling physical blocks, wherein each target recycling physical block has an effective data ratio less than a recycling effective data ratio threshold.

7. The memory management method of claim 1, wherein, The step of adjusting the write speed of the host write operation according to the first total number of the plurality of remaining blocks in the plurality of physical blocks that have not been written into and the recycling write speed comprises: obtaining a first remaining ratio between the first total number and a total number of the plurality of physical blocks; adjusting the write speed using the recycling write speed according to the first remaining ratio.

8. The memory management method of claim 7, wherein, The step of adjusting the write speed using the recycling write speed according to the first remaining ratio comprises: obtaining a current remaining ratio corresponding to the first remaining ratio; determining a corresponding speed adjustment multiple according to the remaining ratio interval, wherein a lower remaining ratio interval corresponds to a lower speed adjustment multiple; and adjusting the write speed using the recycling write speed of the garbage collection operation and the speed adjustment multiple.

9. The memory management method of claim 8, wherein, The step of dynamically adjusting the write speed of the host write operation according to the number of the plurality of remaining blocks in the plurality of physical blocks further comprises: when the first total number of the plurality of remaining blocks in the plurality of physical blocks that have not been written into reaches the critical remaining number, determining that the remaining ratio interval is a lowest remaining ratio interval.

10. The memory management method of claim 1, wherein, The step of adjusting the write speed of the host write operation according to the effective data ratio of the target recycling physical block and the target recycling write speed corresponding to the target recycling physical block comprises: determining an emergency speed adjustment multiple based on a comparison result of the effective data ratio and another recycling effective data ratio threshold; and adjusting the write speed of the host write operation using the target recycling write speed and the emergency speed adjustment multiple.

11. The memory management method of claim 2, wherein, The step of pausing the pre-garbage collection operation further comprises: obtaining a current execution progress of the pre-garbage collection operation; recording breakpoint information corresponding to the current execution progress; and setting a recovery identifier based on the breakpoint information, wherein when the host write instruction execution is completed, it is determined whether to resume execution of the pre-garbage collection operation according to the recovery identifier.

12. The memory management method of claim 4, wherein, The step of determining the host write demand comprises: setting a sliding time window; in the sliding time window, calculating a cumulative write data amount according to a logical address range of a received host write instruction; and when the cumulative write data amount exceeds a preset data amount threshold, determining that the host write demand is the high demand.

13. The memory management method of claim 8, wherein, The step of adjusting the write speed using the recycling write speed of the garbage collection operation and the speed adjustment multiple comprises: obtaining a last write speed; calculating a speed difference value between a current target write speed and the last write speed; determining whether a smooth transition is needed according to the speed difference value; and if it is determined that the smooth transition is needed, gradually adjusting the write speed to the target write speed within a preset transition period. The step of adjusting the write speed using the recycling write speed of the garbage collection operation and the speed adjustment multiple comprises: obtaining a last write speed; calculating a speed difference value between a current target write speed and the last write speed; determining whether a smooth transition is needed according to the speed difference value; and if it is determined that the smooth transition is needed, gradually adjusting the write speed to the target write speed within a preset transition period.

14. A memory controller for controlling a storage device configured with a re- writable non-volatile memory module, the memory controller comprising: The memory controller comprises: a memory interface control circuit electrically connected to the rewritable non-volatile memory module; a data management circuit electrically connected to the connection interface circuit of the storage device, configured to receive data and instructions from a host system via the connection interface circuit; a buffer memory configured to buffer data; and a processor electrically connected to the memory interface control circuit, the data management circuit and the buffer memory, wherein the processor is configured to: obtain block usage of a plurality of physical blocks of the rewritable non-volatile memory module; when the storage device is in a busy state, determine whether to perform a garbage collection operation according to the block usage of the plurality of physical blocks and a host write demand of the storage device; and when the garbage collection operation is performed during a host write operation, dynamically adjust a write speed of the host write operation according to a number of remaining blocks in the plurality of physical blocks, comprising: obtaining a recovery write speed of copying valid data from a source physical block to each target recovery physical block in the garbage collection operation; wherein when a first total number of a plurality of remaining blocks in the plurality of physical blocks that have not been written reaches a critical remaining number, the dynamic adjustment further comprises: obtaining an effective data proportion of each target recovery physical block; and adjusting the write speed of the host write operation according to the effective data proportion of the target recovery physical block and the recovery write speed corresponding to the target recovery physical block. The processor is further configured to: when the storage device is in an idle state, obtain a first total amount of valid data of a plurality of first written physical blocks in the plurality of physical blocks, and determine whether to perform a pre-garbage collection operation according to the first total amount of valid data; and 15. The memory controller of claim 14, wherein, when a host write instruction is received during the performance of the pre-garbage collection operation, pause the pre-garbage collection operation. The step of determining whether to perform the pre-garbage collection operation according to the first total amount of valid data comprises: obtaining a first effective data proportion between the first total amount of valid data and a total storage space of the plurality of first written physical blocks; when the first effective data proportion is less than a first effective data proportion threshold, determining to perform the pre-garbage collection operation.

16. The memory controller of claim 15, wherein, The step of determining whether to perform the garbage collection operation according to the block usage of the plurality of physical blocks and the host write demand of the storage device comprises: obtaining the first total number of the plurality of remaining blocks in the plurality of physical blocks that have not been written; recording a second total number of a plurality of second written physical blocks in the plurality of remaining blocks; 17. The memory controller of claim 14, wherein, when a ratio of the second total number to the first total number exceeds a usage threshold, determining the host write demand; and ​ ​ ​ If the determined host write demand is a high demand, it is determined to perform the garbage collection operation.

18. The memory controller of claim 17, wherein, The step of determining the host write demand comprises: obtaining a second total valid data amount of the plurality of second written physical blocks; obtaining a second valid data proportion between the second total valid data amount and a total storage space of the plurality of second written physical blocks; and when the second valid data proportion exceeds a second valid data proportion threshold, determining that the host write demand is a high demand.

19. The memory controller of claim 18, wherein, The step of performing the garbage collection operation comprises: selecting one or more target recovery physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target recovery physical blocks, wherein an effective data proportion of each target recovery physical block is less than a recovery valid data proportion threshold.

20. The memory controller of claim 14, wherein, According to the first total number of the plurality of remaining blocks in the plurality of physical blocks that have not been written and the recovery write speed, the step of adjusting the write speed of the current host write operation comprises: obtaining a first remaining proportion between the first total number and a total number of the plurality of physical blocks; adjusting the write speed using the recovery write speed according to the first remaining proportion.

21. The memory controller of claim 20, wherein, According to the first remaining proportion, the step of adjusting the write speed using the recovery write speed comprises: obtaining a current remaining proportion interval corresponding to the first remaining proportion; determining a corresponding speed adjustment multiple according to the remaining proportion interval, wherein a lower remaining proportion interval corresponds to a lower speed adjustment multiple; and adjusting the write speed using the recovery write speed of the garbage collection operation and the speed adjustment multiple.

22. The memory controller of claim 21, wherein, According to the number of the plurality of remaining blocks in the plurality of physical blocks, the step of dynamically adjusting the write speed of the host write operation further comprises: when the first total number of the plurality of remaining blocks in the plurality of physical blocks that have not been written reaches a critical remaining number, determining that the remaining proportion interval is a lowest remaining proportion interval.

23. The memory controller of claim 22, wherein, According to the effective data proportion of the target recovery physical block and the target recovery write speed corresponding to the target recovery physical block, the step of adjusting the write speed of the host write operation comprises: determining an emergency speed adjustment multiple based on a comparison result of the effective data proportion and another recovery valid data proportion threshold; and adjusting the write speed of the host write operation using the target recovery write speed and the emergency speed adjustment multiple.

24. The memory controller of claim 15, wherein, The step of pausing the pre-garbage collection operation further comprises: obtaining a current execution progress of the pre-garbage collection operation; recording breakpoint information corresponding to the current execution progress; and setting a recovery identifier based on the breakpoint information, wherein when the host write instruction execution is completed, it is determined whether to resume execution of the pre-garbage collection operation according to the recovery identifier.

25. The memory controller of claim 17, wherein, The step of determining the host write demand comprises: setting a sliding time window; within the sliding time window, calculating a cumulative write data amount according to a logical address range of a received host write instruction; and When the accumulated write data amount exceeds a preset data amount threshold, it is determined that the host write demand is the high demand.

26. The memory controller of claim 21, wherein, The step of adjusting the write speed using the garbage collection operation's collection write speed and the speed adjustment multiple includes: acquiring a last write speed; calculating a speed difference between a current target write speed and the last write speed; determining whether a smooth transition is needed according to the speed difference; and if it is determined that the smooth transition is needed, gradually adjusting the write speed to the target write speed within a preset transition period.

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