SOC verification method, system, device, medium and program product

Abstract

The present application relates to a SOC verification method, system, device, medium and program product, especially in the field of SOC verification technology. It includes: controlling the SOC to be tested to output a test stimulus through a host agent and sending it to a slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; at this time, the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output-type scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input-type scoreboard; the operation of the SOC to be tested is simulated by a reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input-type scoreboard and the output-type scoreboard respectively to compare whether the simulated input signal is consistent with the test stimulus response, and whether the simulated output signal is consistent with the test stimulus; if they are consistent, it means that the expected behavior of the SOC to be tested is consistent with the actual behavior, and it is determined that the SOC to be tested has passed the verification.

Description

Technical Field

[0001] The present application relates to the field of SOC verification technology, and in particular to a SOC verification method, system, device, medium and program product. Background Art

[0002] System-on-Chip (SOC) is a complex integrated circuit system that integrates multiple functional modules (such as processors, memory, communication interfaces, etc.) on a single chip. SOC verification is the process of ensuring that the functional correctness and performance of the SOC chip meet the design requirements. Since SOC contains many modules with different functions and their interconnections and interactions are complex, verification is extremely challenging. The purpose of verification is to find as many errors in the design as possible before chip manufacturing, reduce the number of repeated chip design tape-outs, thereby reducing costs and shortening product time to market.

[0003] At present, the verification environment required for SOC verification environment template development is mainly established through Universal Verification Methodology (UVM) to shorten the verification iteration time. However, the verification environment built using UVM may have the problem of over-design, which increases unnecessary development costs and maintenance difficulties. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides a SOC verification method, system, device, medium and program product, which can improve the flexibility and scalability of the SOC verification environment template, making it easier for developers to build and maintain the test system.

[0005] In order to achieve the above purpose, the technical solutions provided by the embodiments of the present application are as follows:

[0006] In a first aspect, the present application provides a SOC verification method, which is applied to a SOC verification system. The method includes:

[0007] The host agent controls the SOC to be tested to output a test stimulus, and sends it to the slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input scoreboard; the operation of the SOC to be tested is simulated by the reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input scoreboard and the output scoreboard respectively; the simulated input signal is compared with the test stimulus response by the input scoreboard to see if they are consistent, and the simulated output signal is compared with the test stimulus by the output scoreboard to see if they are consistent; if the simulated input signal is consistent with the test stimulus response and the simulated output signal is consistent with the test stimulus, it is determined that the SOC to be tested has passed the verification.

[0008] As an optional method provided in an embodiment of the present application, before the host agent controls the SOC to be tested to generate test stimulus and sends it to the slave agent, the method also includes: obtaining test cases from the flash memory of the top-level module, and the test cases are generated based on the test configuration files; transmitting the test cases to the high-speed serial peripheral interface QSPI or embedded flash memory of the SOC to be tested to drive the SOC to be tested to configure according to the test cases.

[0009] As an optional method provided in an embodiment of the present application, before controlling the SOC to be tested to output a test stimulus through a host agent and sending it to a slave agent, the method also includes: generating a configuration stimulus according to a test configuration file through a stimulus generation component; transmitting the configuration stimulus to an advanced extensible interface driver through a transaction sequencer of the host agent; transmitting the configuration stimulus to a bus interface of the SOC to be tested through the advanced extensible interface driver to drive the SOC to be tested to configure according to the configuration stimulus.

[0010] As an optional method provided in an embodiment of the present application, the test configuration file is dependently associated with the reference model component, the receiving monitor and the sending monitor.

[0011] In a second aspect, the present application provides a SOC verification system, the system comprising:

[0012] The top-level module is used to start and manage the test case module and establish the connection between the test case module and the SOC to be tested;

[0013] The test case module includes an environment component; the environment component includes: a slave agent, a host agent, a reference model component, an input scoreboard, and an output scoreboard;

[0014] The host agent is used to control the SOC to be tested to output the test stimulus and send it to the slave agent;

[0015] The slave agent is used to respond to the test stimulus and generate a test stimulus response; the slave agent includes a receiving monitor and a sending monitor, the receiving monitor is used to monitor the test stimulus and transmit it to the output type scoreboard; the sending monitor is used to monitor the input to the test stimulus response and transmit it to the input type scoreboard;

[0016] A reference model component is used to simulate the operation of the SOC to be tested, obtain a simulated input signal and a simulated output signal, and transmit them to an input-type scoreboard and an output-type scoreboard respectively;

[0017] Input scoreboard, used to compare the analog input signal with the test stimulus response;

[0018] The output type scoreboard is used to compare whether the analog output signal is consistent with the test stimulus; if the analog input signal is consistent with the test stimulus response and the analog output signal is consistent with the test stimulus, it is determined that the SOC to be tested has passed the verification.

[0019] As an optional method provided in an embodiment of the present application, the test case module further includes a stimulus generation component for generating a configuration stimulus according to the test configuration file;

[0020] The host agent includes a transaction sequencer and an advanced extensible interface driver;

[0021] wherein a transaction sequencer is used to transmit configuration stimulus to an advanced extensible interface driver;

[0022] The advanced scalable interface driver is used to transmit configuration stimulus to the bus interface of the SOC to be tested, so as to drive the SOC to be tested to configure according to the configuration stimulus.

[0023] As an optional method provided in an embodiment of the present application, the top-level module also includes a flash memory for storing test cases, and the test cases are generated based on the test configuration files.

[0024] In a third aspect, the present application provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the SOC verification method as described in the first aspect or any optional embodiment thereof is implemented.

[0025] In a fourth aspect, the present application provides a computer-readable storage medium, comprising: a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the SOC verification method as described in the first aspect or any optional embodiment thereof is implemented.

[0026] In a fifth aspect, the present application provides a computer program product, including: the computer program product includes a computer program, and when the computer program runs on a computer, the computer implements the SOC verification method as described in the first aspect or any optional embodiment thereof.

[0027] Compared with the prior art, the technical solution provided by the embodiments of the present application has the following advantages:

[0028] The disclosed embodiment provides a SOC verification method, system, device, medium and program product, wherein the method first controls the SOC to be tested to output a test stimulus through a host agent and sends it to a slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; at this time, the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input scoreboard; the operation of the SOC to be tested is simulated by a reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input scoreboard and the output scoreboard respectively to compare whether the simulated input signal is consistent with the test stimulus response, and whether the simulated output signal is consistent with the test stimulus; if they are consistent, it means that the expected behavior of the SOC to be tested is consistent with the actual behavior, and it is determined that the SOC to be tested has passed the verification. In this way, by integrating the host agent, the slave agent and its receiving monitor and sending monitor, as well as the reference model component and the input / output scoreboard, a SOC verification environment is built to form a reusable and extensible template, so as to realize comprehensive verification of the SOC to be tested, which is easy to adjust, low cost and high verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 A schematic diagram of the architecture of a SOC verification system provided in an embodiment of the present application;

[0032] Figure 2 A flow chart of a SOC verification method provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the structure of an electronic device described in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the technical terms required to be used in the embodiments or the description of the prior art are briefly introduced below.

[0035] The scope of SOC verification includes functional verification (verifying whether the chip performs various functions according to the design specifications), performance verification (checking whether the chip meets performance indicators such as speed and bandwidth) and reliability verification (ensuring that the chip can work stably under various environmental conditions and working cycles).

[0036] The device under test (DUT) refers to a specific functional module or complete device unit that is specially selected as a test target during the test of electronic circuits, chips, systems, etc. It is the core object of the test system, and testers use various test methods and tools to test and verify its performance, function, reliability and other aspects.

[0037] A dependency relationship describes a situation where a class object depends on another class object to some extent, that is, the implementation of one class depends on the implementation of another class. This relationship is usually unidirectional, indicating that one class object calls the method or attribute of another class object, or uses an instance of a class object as a local variable or method parameter. In the Unified Modeling Language class diagram, the dependency relationship is represented by a dotted arrow, with the arrow pointing from the dependent party to the dependent party. Dependency relationships are usually used to indicate that changes in one class will affect another class.

[0038] Unified Modeling Language Class Diagram (UML) is a visualization tool used to describe classes, class attributes, relationships between classes, and class behaviors in a system. It is the most commonly used diagram in UML.

[0039] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0041] In order to solve some or all of the technical problems existing in the related art, the embodiments of the present application provide a SOC verification method, system, device, medium and program product, wherein the method first controls the SOC to be tested to output a test stimulus through a host agent and sends it to a slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; at this time, the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input scoreboard; the operation of the SOC to be tested is simulated by a reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input scoreboard and the output scoreboard respectively to compare whether the simulated input signal is consistent with the test stimulus response, and whether the simulated output signal is consistent with the test stimulus; if they are consistent, it means that the expected behavior of the SOC to be tested is consistent with the actual behavior, and then it is determined that the SOC to be tested has been verified. In this way, by integrating the host agent, slave agent and its receiving monitor and sending monitor, as well as the reference model components and input / output scoreboard, a SOC verification environment is built to form a reusable and extensible template, which can realize comprehensive verification of the SOC under test, easy to adjust, low cost and high verification efficiency.

[0042] A SOC verification method provided in the embodiment of the present application can be implemented by electronic devices, including but not limited to personal computers, laptops, tablet computers, smart phones, etc. The operating system of the electronic device may include Android, the mobile operating system (iOS) developed by Apple, the operating system (Windows) developed by Microsoft Corporation of the United States, etc., and the embodiment of the present application is not limited to this. The electronic device can be run alone to implement the present application, or it can be connected to the network and implement the present application through interactive operations with other computer devices in the network. Among them, the network in which the electronic device is located includes but is not limited to the Internet, wide area network, metropolitan area network, local area network, virtual private network (Virtual Private Network, VPN) network, etc.

[0043] It should be noted that the protection scope of the SOC verification method described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.

[0044] like Figure 1 As shown, Figure 1 This is a schematic diagram of the architecture of a SOC verification system provided in an embodiment of the present application, and the system is used to implement the SOC verification method provided in an embodiment of the present application. The system includes:

[0045] The top-level module (tb_top) is used to start and manage the test case module (case), establish the connection between the test case module and the SOC to be tested; and regard the SOC as the DUT.

[0046] In some embodiments, the top module also includes a flash memory (flash) for storing test cases. The test case defines the verification scenario and test steps, and can be a C code test case (c case). The C code test case is a code written in C language, which is used to configure each functional module of the SOC and process the terminal service program to implement the various functions of the SOC. The test case is generated by the CPU compilation tool chain according to the test configuration file (test_cfg) to ensure the consistency and repeatability of the verification. The test configuration file defines various configuration information required for the verification environment, including configuration register values ​​and device driver stimulus values. The test configuration file is dependently associated with the test case, the reference model component (refer_model), the receive monitor (rx_monitor), the transmit monitor (tx_monitor) and the receive / transmit driver (tx / rx_driver).

[0047] The test case module includes stimulus generation components (sequences) and environment components (env).

[0048] Among them, the stimulus generation component sequences is used to generate configuration stimulus according to the test configuration file.

[0049] The environment component env includes the reference model component (refer_model), the input scoreboard (scoreboardingress), the output scoreboard (scoreboard egress), the host agent (master agent) and the slave agent (slave agent). The above modules work together to achieve comprehensive verification of the SOC to be tested.

[0050] The master agent is used to control the SOC to be tested to generate test stimulus and send it to the slave agent.

[0051] In some embodiments, the host agent master agent controls the behavior of the SOC to be tested by instantiating a transaction sequencer and an advanced extensible interface driver (axi_driver) and sends a test stimulus. The host agent is proactive. Among them, the transaction sequencer is used to transmit the configuration stimulus generated by the stimulus generation component sequences to the advanced extensible interface driver axi_driver. The advanced extensible interface driver axi_driver is used to send the configuration stimulus to the bus interface (CPU AXIPORT) of the SOC to be tested to drive the SOC to be tested to configure.

[0052] The slave agent is used to respond to the test stimulus and generate a test stimulus response. Specifically, the slave agent is used to simulate the slave connected to the SOC to be tested by instantiating the receiving monitor (rx_monitor), the transmitting monitor (tx_monitor), the interface module (interface), the transaction module (transaction) and the receiving / transmitting driver (tx / rx_driver), and receives the test stimulus from the master agent and generates a test stimulus response. The slave agent is passive.

[0053] In some embodiments, the receiving monitor rx_monitor is used to monitor the test stimulus output by the SOC under test and transmit it to the output type scoreboard; the sending monitor tx_monitor is used to monitor the test stimulus response input to the SOC under test and transmit it to the input type scoreboard.

[0054] The reference model component refer_model is used to simulate the operation of the SOC to be tested to obtain a simulated input signal and a simulated output signal. Specifically, the behavior of the SOC to be tested is simulated to obtain a simulated output, and the simulated output is compared with the actual output of the SOC to be tested to detect potential errors.

[0055] The input scoreboard scoreboard ingress is used to compare whether the simulated input signal of the reference model component is consistent with the test stimulus response of the input SOC to be tested, so as to compare whether the expected behavior and actual behavior of the input SOC to be tested are consistent. If they are inconsistent, an error is recorded.

[0056] The output scoreboard scoreboard egress is used to compare whether the analog output signal of the reference model component is consistent with the test stimulus output of the SOC to be tested, so as to compare whether the expected behavior and actual behavior of the SOC output to be tested are consistent. If they are inconsistent, an error is recorded. If the analog input signal is consistent with the test stimulus response and the analog output signal is consistent with the test stimulus, the SOC to be tested is determined to have passed the verification.

[0057] The above-mentioned SOC verification system builds a verification environment by integrating various verification components, which can realize intelligent SOC verification, help shorten the verification cycle, and thus improve verification efficiency. In addition, the modular design facilitates system expansion and maintenance, thereby adapting to diversified verification needs.

[0058] In some embodiments, the test case module further includes a stimulus generation component for generating a configuration stimulus based on the test configuration file;

[0059] The host agent includes a transaction sequencer and an advanced extensible interface driver;

[0060] wherein a transaction sequencer is used to transmit configuration stimulus to an advanced extensible interface driver;

[0061] The advanced scalable interface driver is used to transmit configuration stimulus to the bus interface of the SOC to be tested, so as to drive the SOC to be tested to configure according to the configuration stimulus.

[0062] Each module in the above SOC verification system can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0063] like Figure 2 As shown, Figure 2 This is a flow chart of a SOC verification method according to an embodiment of the present application. The method can be executed by a SOC verification device or an electronic device, wherein the device can be implemented by software and / or hardware and can generally be integrated in an electronic device. The method mainly includes the following steps S201 to S205:

[0064] S201 . Control the SOC to be tested to generate a test stimulus through a host agent, and send the test stimulus to a slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus.

[0065] In some embodiments, before executing step S201, a configuration stage is also included, which specifically includes: obtaining test cases from the flash memory of the top-level module; transmitting the test cases to the high-speed serial peripheral interface QSPI or embedded flash eflash of the SOC to be tested, so as to drive the SOC to be tested to configure according to the test cases.

[0066] It is understandable that on the SOC side, the CPU obtains the test case (such as c case) from the flash memory of the top module tb_top through QSPI / eflash. It can achieve high-speed and stable transmission of test cases and improve the utilization of hardware resources; this close connection method also makes the verification system more integrated and improves the stability and scalability of the SOC verification environment.

[0067] In some other embodiments, before executing step S201, the configuration stage includes: generating configuration stimuli according to the test configuration file test_cfg through the stimulus generation component sequences; transmitting the configuration stimuli to the advanced extensible interface driver axi_driver through the transaction sequencer sequencer of the host agent master agent; transmitting the configuration stimuli to the bus interface (CPU AXIPORT) of the SOC to be tested through the advanced extensible interface driver to drive the SOC to be tested to configure according to the configuration stimuli.

[0068] The above-mentioned embodiment simulates various input sequences that may appear in actual application scenarios through the stimulus generation component, and comprehensively tests the functional boundaries, exception handling capabilities and performance indicators of the SOC to be tested by generating diversified and targeted stimuli, thereby ensuring that the design of the SOC to be tested meets the expected functional and performance requirements.

[0069] S202: monitor the test stimulus through the receiving monitor of the slave agent and transmit it to the output scoreboard, and monitor the test stimulus response through the sending monitor of the slave agent and transmit it to the input scoreboard.

[0070] S203 , simulating the operation of the SOC to be tested by using the reference model component, obtaining a simulated input signal and a simulated output signal, and transmitting them to an input-type scoreboard and an output-type scoreboard respectively.

[0071] Specifically, the reference model component responds to the test stimulus transmitted by the input-type scoreboard, simulates the operation of the SOC to be tested to obtain a simulated output signal, and transmits it to the output-type scoreboard; responds to the test stimulus transmitted by the output-type scoreboard, simulates the simulated input signal corresponding to the test stimulus, and transmits it to the input-type scoreboard.

[0072] S204: Compare the analog input signal with the test stimulus response through the input-type scoreboard to see if they are consistent, and compare the analog output signal with the test stimulus through the output-type scoreboard to see if they are consistent.

[0073] S205 . If the analog input signal is consistent with the test stimulus response and the analog output signal is consistent with the test stimulus, it is determined that the SOC to be tested passes the verification.

[0074] If the analog input signal is inconsistent with the test stimulus response, and / or the analog output signal is inconsistent with the test stimulus, the scoreboard will record the error as a prompt, which is helpful to ensure the functional integrity and accuracy of the SOC to be tested.

[0075] In summary, the embodiment of the present application provides a SOC verification method, which first controls the SOC to be tested to output a test stimulus through a host agent and sends it to a slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; at this time, the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input scoreboard; the operation of the SOC to be tested is simulated by a reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input scoreboard and the output scoreboard respectively to compare whether the simulated input signal is consistent with the test stimulus response, and whether the simulated output signal is consistent with the test stimulus; if they are consistent, it means that the expected behavior of the SOC to be tested is consistent with the actual behavior, and it is determined that the SOC to be tested has been verified. In this way, by integrating the host agent, the slave agent and its receiving monitor and sending monitor, as well as the reference model component and the input / output scoreboard, a SOC verification environment is built to form a reusable and extensible template, so as to achieve comprehensive verification of the SOC to be tested, which is easy to adjust, low cost and high verification efficiency.

[0076] In one embodiment, the present application provides an electronic device, which may be a terminal, and its internal structure diagram may be as follows: Figure 3 As shown. The electronic device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the electronic device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a SOC verification method is implemented. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the housing of the electronic device, or an external keyboard, touchpad or mouse, etc.

[0077] Those skilled in the art will understand that Figure 3The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0078] In one embodiment, the SOC verification system provided by the present application can be implemented in the form of a computer program. The computer program can be Figure 3 The SOC verification system is run on the electronic device shown. The memory of the electronic device can store various program modules constituting the SOC verification system. The computer program composed of various program modules enables the processor to execute the steps of the SOC verification method of various embodiments of the present application described in this specification.

[0079] For example, Figure 3 The electronic device shown can control the SOC to be tested to output a test stimulus through a host agent in the SOC verification system, and send it to a slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; the electronic device can monitor the test stimulus through a receiving monitor of the slave agent and transmit it to an output-type scoreboard, and the electronic device can monitor the test stimulus response through a sending monitor of the slave agent and transmit it to an input-type scoreboard; the electronic device can simulate the operation of the SOC to be tested through a reference model component, and obtain a simulated input signal and a simulated output signal, which are transmitted to an input-type scoreboard and an output-type scoreboard respectively; the electronic device can compare the simulated input signal with the test stimulus response through the input-type scoreboard, and the electronic device can compare the simulated output signal with the test stimulus through the output-type scoreboard; if the simulated input signal is consistent with the test stimulus response and the simulated output signal is consistent with the test stimulus, it is determined that the SOC to be tested has passed the verification.

[0080] In one embodiment, the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0081] The host agent controls the SOC to be tested to output a test stimulus, and sends it to the slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input scoreboard; the operation of the SOC to be tested is simulated by the reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input scoreboard and the output scoreboard respectively; the simulated input signal is compared with the test stimulus response by the input scoreboard to see if they are consistent, and the simulated output signal is compared with the test stimulus by the output scoreboard to see if they are consistent; if the simulated input signal is consistent with the test stimulus response and the simulated output signal is consistent with the test stimulus, it is determined that the SOC to be tested has passed the verification.

[0082] In one embodiment, the processor also implements the following steps when executing the computer program: before controlling the SOC to be tested to generate test stimulus through the host agent and sending it to the slave agent, the method also includes: obtaining test cases from the flash memory of the top-level module, and the test cases are generated based on the test configuration files; transmitting the test cases to the high-speed serial peripheral interface QSPI or embedded flash memory of the SOC to be tested to drive the SOC to be tested to configure according to the test cases.

[0083] In one embodiment, the processor also implements the following steps when executing the computer program: before controlling the SOC to be tested to output the test stimulus through the host agent and sending it to the slave agent, the method also includes: generating a configuration stimulus according to the test configuration file through the stimulus generation component; transmitting the configuration stimulus to the advanced extensible interface driver through the transaction sequencer of the host agent; transmitting the configuration stimulus to the bus interface of the SOC to be tested through the advanced extensible interface driver to drive the SOC to be tested to configure according to the configuration stimulus.

[0084] In one embodiment, when the processor executes the computer program, the following steps are further implemented: the test configuration file is dependency-associated with the reference model component, the receiving monitor, and the sending monitor.

[0085] When the processor in the electronic device provided by the present application executes a computer program, the host agent first controls the SOC to be tested to output a test stimulus and sends it to the slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; at this time, the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output-type scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input-type scoreboard; the operation of the SOC to be tested is simulated by the reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input-type scoreboard and the output-type scoreboard respectively to compare whether the simulated input signal is consistent with the test stimulus response, and whether the simulated output signal is consistent with the test stimulus; if they are consistent, it means that the expected behavior of the SOC to be tested is consistent with the actual behavior, and it is determined that the SOC to be tested has passed the verification. In this way, by integrating the host agent, the slave agent and its receiving monitor and sending monitor, as well as the reference model component and the input / output-type scoreboard, a SOC verification environment is built to form a reusable and extensible template, so as to achieve comprehensive verification of the SOC to be tested, which is easy to adjust, low cost and high verification efficiency.

[0086] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by the computer program, the following steps are implemented:

[0087] The host agent controls the SOC to be tested to output a test stimulus, and sends it to the slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input scoreboard; the operation of the SOC to be tested is simulated by the reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input scoreboard and the output scoreboard respectively; the simulated input signal is compared with the test stimulus response by the input scoreboard to see if they are consistent, and the simulated output signal is compared with the test stimulus by the output scoreboard to see if they are consistent; if the simulated input signal is consistent with the test stimulus response and the simulated output signal is consistent with the test stimulus, it is determined that the SOC to be tested has passed the verification.

[0088] In one embodiment, the computer program also implements the following steps when executing the computer program: before controlling the SOC to be tested to generate test stimulus through the host agent and sending it to the slave agent, the method also includes: obtaining test cases from the flash memory of the top-level module, and the test cases are generated based on the test configuration files; transmitting the test cases to the high-speed serial peripheral interface QSPI or embedded flash memory of the SOC to be tested to drive the SOC to be tested to configure according to the test cases.

[0089] In one embodiment, the computer program further implements the following steps when executing the computer program: before controlling the SOC to be tested to output a test stimulus through the host agent and sending it to the slave agent, the method also includes: generating a configuration stimulus according to a test configuration file through a stimulus generation component; transmitting the configuration stimulus to an advanced extensible interface driver through a transaction sequencer of the host agent; transmitting the configuration stimulus to a bus interface of the SOC to be tested through the advanced extensible interface driver to drive the SOC to be tested to configure according to the configuration stimulus.

[0090] In one embodiment, when the computer program is executed, the computer program further implements the following steps: the test configuration file is dependency-associated with the reference model component, the receiving monitor, and the sending monitor.

[0091] When the computer program in the computer-readable storage medium provided by the present application executes the computer program, the host agent is first used to control the SOC to be tested to output a test stimulus and send it to the slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; at this time, the test stimulus is monitored by the receiving monitor of the slave agent and transmitted to the output-type scoreboard, and the test stimulus response is monitored by the sending monitor of the slave agent and transmitted to the input-type scoreboard; the operation of the SOC to be tested is simulated by the reference model component to obtain a simulated input signal and a simulated output signal, which are transmitted to the input-type scoreboard and the output-type scoreboard respectively to compare whether the simulated input signal is consistent with the test stimulus response, and whether the simulated output signal is consistent with the test stimulus; if they are consistent, it means that the expected behavior of the SOC to be tested is consistent with the actual behavior, and it is determined that the SOC to be tested has passed the verification. In this way, by integrating the host agent, the slave agent and its receiving monitor and sending monitor, as well as the reference model component and the input / output-type scoreboard, a SOC verification environment is built to form a reusable and extensible template, so as to achieve comprehensive verification of the SOC to be tested, which is easy to adjust, low cost and high verification efficiency.

[0092] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media that include computer-usable program code.

[0093] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0094] In the present application, the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0095] In this application, memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0096] In this application, computer-readable media includes permanent and non-permanent, removable and non-removable storage media. Storage media can be implemented by any method or technology to store information, and the information can be computer-readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. According to the definition in this article, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0097] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0098] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A SOC verification method, characterized in that: Applied to SOC verification system, including: Controlling the SOC to be tested to output a test stimulus through the host agent, and sending the test stimulus to the slave agent, so that the slave agent generates a test stimulus response in response to the test stimulus; The test stimulus is monitored by a receiving monitor of the slave agent and transmitted to an output-type scoreboard, and the test stimulus response is monitored by a sending monitor of the slave agent and transmitted to an input-type scoreboard; Simulating the operation of the SOC to be tested by using a reference model component, obtaining a simulated input signal and a simulated output signal, and transmitting them to the input-type scoreboard and the output-type scoreboard respectively; Comparing the analog input signal with the test stimulus response through an input-type scoreboard to see whether it is consistent, and comparing the analog output signal with the test stimulus through an output-type scoreboard to see whether it is consistent; If the analog input signal is consistent with the test stimulus response and the analog output signal is consistent with the test stimulus, it is determined that the SOC to be tested passes the verification.

2. The method according to claim 1, characterized in that Before the host agent controls the SOC to be tested to generate a test stimulus and sends it to the slave agent, the method further includes: Obtaining a test case from a flash memory of a top-level module, wherein the test case is generated based on a test configuration file; The test case is transmitted to the high-speed serial peripheral interface QSPI or embedded flash memory of the SOC to be tested, so as to drive the SOC to be tested to be configured according to the test case.

3. The method according to claim 1, characterized in that Before the host agent controls the SOC to be tested to output a test stimulus and sends it to the slave agent, the method further includes: Generate configuration stimulus according to the test configuration file through the stimulus generation component; transmitting the configuration stimulus to the advanced extensible interface driver via a transaction sequencer of the host agent; The configuration stimulus is transmitted to the bus interface of the SOC to be tested through the advanced extensible interface driver, so as to drive the SOC to be tested to configure according to the configuration stimulus.

4. The method according to claim 2 or 3, characterized in that: The test configuration file is dependency-associated with the reference model component, the receiving monitor, and the sending monitor.

5. A SOC verification system, characterized in that: include: The top-level module is used to start and manage the test case module and establish a connection between the test case module and the SOC to be tested; The test case module includes an environment component; the environment component includes: a slave agent, a host agent, a reference model component, an input scoreboard and an output scoreboard; The host agent is used to control the SOC to be tested to output a test stimulus and send it to the slave agent; The slave agent is used to generate a test stimulus response in response to the test stimulus; the slave agent includes a receiving monitor and a sending monitor, the receiving monitor is used to monitor the test stimulus and transmit it to the output type scoreboard; the sending monitor is used to monitor the input to the test stimulus response and transmit it to the input type scoreboard; The reference model component is used to simulate the operation of the SOC to be tested, obtain a simulated input signal and a simulated output signal, and transmit them to the input-type scoreboard and the output-type scoreboard respectively; The input-type scoreboard is used to compare whether the analog input signal is consistent with the test stimulus response; The output-type scoreboard is used to compare whether the analog output signal is consistent with the test stimulus; if the analog input signal is consistent with the test stimulus response and the analog output signal is consistent with the test stimulus, it is determined that the SOC to be tested has passed the verification.

6. The verification system according to claim 5, characterized in that: The test case module also includes a stimulus generation component for generating a configuration stimulus according to the test configuration file; The host agent includes a transaction sequencer and an advanced extensible interface driver; Wherein, the transaction sequencer is used to transmit the configuration stimulus to the advanced extensible interface driver; The advanced extensible interface driver is used to transmit the configuration stimulus to the bus interface of the SOC to be tested, so as to drive the SOC to be tested to configure according to the configuration stimulus.

7. The verification system according to claim 5, characterized in that: The top-level module also includes a flash memory for storing test cases, wherein the test cases are generated based on a test configuration file.

8. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the SOC verification method according to any one of claims 1 to 4 when executed by the processor.

9. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the SOC verification method according to any one of claims 1 to 4 is implemented.

10. A computer program product, characterized in that include: The computer program product comprises a computer program, and when the computer program is executed on a computer, the computer is enabled to implement the SOC verification method according to any one of claims 1 to 4.

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