A RISC-V DSP chip ATE test program optimization method, system and storage medium

Abstract

The present invention provides a RISC‑V DSP chip ATE test program optimization method, system and storage medium. First, it is determined whether there is an identical module in a first module sequence and a second module sequence. If so, first module information in the first module sequence and second module information in the second module sequence are extracted; then, according to a first configuration parameter of the first module information and a second configuration parameter of the second module information, a functional verification mode of the chip test is determined; finally, according to the first module sequence or the second module sequence, first waveform information is generated according to the corresponding functional verification mode; by analyzing the modules applied to the functional test, a test waveform is automatically generated, thereby reducing the manual work of testers, improving the test efficiency and reducing the error rate.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and more specifically, to a RISC-V DSP chip ATE test program optimization method, system and storage medium. Background Art

[0002] When the RISC-V DSP chip is tested at the functional level ATE (Automatic Test Equipment), a specific test program is usually required for each function that needs to be tested. The test program is simulated in the RTL simulation environment to generate a test waveform passing through the JTAG / CJTAG pin of the chip. This waveform completes the function of loading the current test program into the RAM of the chip under test and controlling the chip to run this test program.

[0003] The current mainstream test program development method is for the relevant R&D personnel of the main tested modules in each test project to write the test program. When writing the test program, the R&D personnel do not need to consider the ATE test environment, nor do they need to have a deep understanding of ATE testing. They only need to focus on the functional characteristics and configuration methods of the chip itself. When multiple functional modules in the chip need to be tested, the testers are required to summarize the test programs of each module. However, since the testers are not familiar with the functional modules, there are problems such as substandard testing, low debugging efficiency, and high error rate. Therefore, there is an urgent need for a RISC-V DSP chip ATE test technology that automatically optimizes the test program. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a RISC-V DSP chip ATE test program optimization method, system and storage medium, by analyzing the modules required for each function, and determining the function verification mode according to the configuration parameters of the configuration module; then, according to the modules required for the functional test and the corresponding function verification mode, the corresponding test waveform is generated; through automatic analysis and adjustment, the manual work of the tester is reduced, the test efficiency is improved and the error rate is reduced.

[0005] A first aspect of the present invention provides a RISC-V DSP chip ATE test program optimization method, the method comprising:

[0006] Obtain a first module sequence and a second module sequence;

[0007] Determine whether there are identical modules in the first module sequence and the second module sequence;

[0008] If yes, obtain the first module information and the second module information;

[0009] Determine whether a first configuration parameter of the first module information and a second configuration parameter of the second module information are the same;

[0010] If so, set the function verification mode to parallel mode;

[0011] If not, set the function verification mode to serial mode;

[0012] First waveform information is generated according to the first module sequence or the second module sequence and in accordance with a corresponding function verification mode.

[0013] In this solution, the generating of the first waveform information according to the first module sequence or the second module sequence in accordance with the corresponding function verification mode also includes:

[0014] When it is determined that the function verification mode is set to the parallel mode;

[0015] Initialize first module information according to the first configuration parameter;

[0016] Obtaining first output module information and second output module information;

[0017] Determine a first output interface according to the first output module information;

[0018] Acquire a first output parameter, and determine a first output waveform of a first output interface according to the first configuration parameter and the first output parameter;

[0019] Determine a second output interface according to the second output module information;

[0020] A second output parameter is obtained, and a second output waveform of the second output interface is determined according to the first configuration parameter and the second output parameter.

[0021] In this solution, the generating of the first waveform information according to the first module sequence or the second module sequence in accordance with the corresponding function verification mode also includes:

[0022] When it is determined that the function verification mode is set to the serial mode;

[0023] According to a preset test sequence, the third module information and the third output module information are obtained;

[0024] Determine the third output interface according to the third output module information;

[0025] A third output waveform is obtained according to the third configuration information of the third module information and the third output parameter of the third output module.

[0026] This plan also includes:

[0027] Determine whether the third output waveform has been verified;

[0028] If yes, the fourth module information and the fourth output module information are obtained according to the preset output order;

[0029] Determining a fourth output interface according to the fourth output module information;

[0030] A fourth output waveform is obtained according to the fourth configuration information of the fourth module information and the fourth output parameter of the fourth output module.

[0031] This plan also includes:

[0032] When it is determined that the function verification mode is set to the serial mode;

[0033] Get the fifth module information;

[0034] Obtaining a first configuration parameter sequence according to the fifth configuration parameter of the fifth module information;

[0035] According to the first configuration parameter sequence, a second configuration parameter sequence is obtained in a preset arrangement order;

[0036] The waveform verification order is adjusted according to the second configuration parameter sequence.

[0037] This plan also includes:

[0038] Obtaining first comparison information according to the first configuration parameter and the second configuration parameter in an exclusive-OR logic operation manner;

[0039] Determine whether the first comparison information is 0;

[0040] If yes, it means that the first configuration parameter is the same as the second configuration parameter;

[0041] If not, it means that the first configuration parameter and the second configuration parameter are different.

[0042] A second aspect of the present invention provides a RISC-V DSP chip ATE test program optimization system, including a RISC-V DSP chip ATE test program optimization method program, wherein the RISC-V DSP chip ATE test program optimization method program implements the following steps when executed by the processor:

[0043] Obtain a first module sequence and a second module sequence;

[0044] Determine whether there are identical modules in the first module sequence and the second module sequence;

[0045] If yes, obtain the first module information and the second module information;

[0046] Determine whether a first configuration parameter of the first module information and a second configuration parameter of the second module information are the same;

[0047] If so, set the function verification mode to parallel mode;

[0048] If not, set the function verification mode to serial mode;

[0049] First waveform information is generated according to the first module sequence or the second module sequence and in accordance with a corresponding function verification mode.

[0050] In this solution, the generating of the first waveform information according to the first module sequence or the second module sequence in accordance with the corresponding function verification mode also includes:

[0051] When it is determined that the function verification mode is set to the parallel mode;

[0052] Initialize first module information according to the first configuration parameter;

[0053] Obtaining first output module information and second output module information;

[0054] Determine a first output interface according to the first output module information;

[0055] Acquire a first output parameter, and determine a first output waveform of a first output interface according to the first configuration parameter and the first output parameter;

[0056] Determine a second output interface according to the second output module information;

[0057] A second output parameter is obtained, and a second output waveform of the second output interface is determined according to the first configuration parameter and the second output parameter.

[0058] In this solution, the generating of the first waveform information according to the first module sequence or the second module sequence in accordance with the corresponding function verification mode also includes:

[0059] When it is determined that the function verification mode is set to the serial mode;

[0060] According to a preset test sequence, the third module information and the third output module information are obtained;

[0061] Determine the third output interface according to the third output module information;

[0062] A third output waveform is obtained according to the third configuration information of the third module information and the third output parameter of the third output module.

[0063] A third aspect of the present invention provides a computer-readable storage medium, which includes a RISC-V DSP chip ATE test program optimization method program. When the RISC-V DSP chip ATE test program optimization method program is executed by a processor, the steps of the RISC-V DSP chip ATE test program optimization method as described in any one of the above items are implemented.

[0064] The present invention provides a RISC-V DSP chip ATE test program optimization method, system and storage medium. First, it is determined whether there is an identical module in a first module sequence and a second module sequence. If yes, first module information in the first module sequence and second module information in the second module sequence are extracted; then, a function verification mode of a chip test is determined according to a first configuration parameter of the first module information and a second configuration parameter of the second module information; finally, first waveform information is generated according to the first module sequence or the second module sequence and the corresponding function verification mode; and a test waveform is automatically generated by analyzing the modules used in the functional test, thereby reducing the manual work of testers, improving the test efficiency and reducing the error rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope.

[0066] Figure 1 A flow chart of a RISC-V DSP chip ATE test program optimization method of the present invention is shown;

[0067] Figure 2 A flow chart showing the generation of a test waveform in a parallel mode provided by an embodiment of the present invention;

[0068] Figure 3 A flow chart of generating a test waveform in a serial mode provided by an embodiment of the present invention is shown;

[0069] Figure 4 A block diagram of a RISC-V DSP chip ATE test program optimization system of the present invention is shown. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present invention have the same meanings as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present invention are clearly defined in this way.

[0072] The words "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The steps before or after the method of the embodiment of the present invention are not necessarily carried out in order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or a step or several steps can be removed from these processes.

[0073] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0074] Figure 1 A flow chart of a RISC-V DSP chip ATE test program optimization method of the present invention is shown.

[0075] like Figure 1 As shown, the first aspect of the present invention discloses a RISC-V DSP chip ATE test program optimization method, the method comprising:

[0076] S102, obtaining a first module sequence and a second module sequence;

[0077] S104, determining whether there are identical modules in the first module sequence and the second module sequence;

[0078] S106, if yes, obtain the first module information and the second module information;

[0079] S108, determining whether a first configuration parameter of the first module information and a second configuration parameter of the second module information are the same;

[0080] S110, if yes, setting the function verification mode to parallel mode;

[0081] S112, if not, setting the function verification mode to serial mode;

[0082] First waveform information is generated according to the first module sequence or the second module sequence and in accordance with a corresponding function verification mode.

[0083] It should be noted that the first module sequence is a sequence of several modules configured to verify a function; the second module sequence is a sequence of several modules configured to verify another function; the first module information is a configuration module in the first module sequence, which is a module that exists in both the first module sequence and the second module sequence; the second module information is a configuration module in the second module sequence, which is a module that exists in both the first module sequence and the second module sequence; the first configuration parameter is a configuration value of each configuration register of the first module; the second configuration parameter is a configuration value of each configuration register of the second module. In addition, during the chip function level test process, although only one output module is tested, multiple configuration modules are involved, such as a clock module, a power supply module, a system control module, etc. When performing multiple function level test tasks, if the configuration modules of the two test tasks are the same, a parallel test mode can be implemented in which the configuration module is configured once and then multiple output modules are tested; if the configuration modules of the two test tasks are different or the configuration parameters of the configuration modules are different, the test tasks are tested in a serial test mode in a set order.

[0084] In this embodiment, it is assumed that the first module sequence is a combination of modules configured to test function A, and the second module sequence is a combination of modules configured to test function B. First, determine whether there are the same modules in the modules for testing function A and the modules for testing function B, that is, determine whether there are the same configuration modules. If so, extract the same configuration modules, that is, the first module of function A and the second module of function B. Then, determine whether the first configuration parameter of the first module is the same as the second configuration parameter of the second module; if so, it means that function A and function B can be set to parallel test mode; if not, it means that function A and function B are set to serial test mode. Finally, according to the corresponding test mode, after configuring the module combination for testing function A or testing function B, the corresponding test waveform is obtained.

[0085] Figure 2 A flow chart of generating a test waveform in parallel mode provided by an embodiment of the present invention is shown.

[0086] According to an embodiment of the present invention, Figure 2 As shown, the generating of the first waveform information according to the first module sequence or the second module sequence and the corresponding function verification mode also includes:

[0087] S202, when it is determined that the function verification mode is set to the parallel mode;

[0088] S204, initializing first module information according to the first configuration parameters;

[0089] S206, obtaining first output module information and second output module information;

[0090] S208, determining a first output interface according to the first output module information;

[0091] S210, acquiring a first output parameter, and determining a first output waveform of a first output interface according to the first configuration parameter and the first output parameter;

[0092] S212, determining a second output interface according to the second output module information;

[0093] S214, obtaining a second output parameter, and determining a second output waveform of the second output interface according to the first configuration parameter and the second output parameter.

[0094] It should be noted that the first output module information is the module that controls output in the first module sequence; the first output parameter is the configuration parameter of the output register of the first output module; the first output interface is the interface or pin of the first output module for testing the waveform; the second output module information is the module that controls output in the second module sequence; the second output parameter is the configuration parameter of the output register of the second output module; the second output interface is the interface or pin of the second output module for testing the waveform.

[0095] In this embodiment, when the function verification mode is the parallel mode, it means that the configuration modules of function A and function B have the same configuration parameters. Therefore, the test of function A and function B does not need to repeatedly modify the configuration of some modules, and the output waveform is obtained according to the respective output modules. First, initialize the corresponding configuration module according to the configuration parameters of function A or function B. Then, determine the data interface according to the output module of function A, and determine the output waveform according to the configuration parameters and the output parameters, that is, send out the first output waveform through the first output interface of function A. Similarly, determine the data interface according to the output module of function B, and determine the output waveform according to the configuration parameters and the output parameters, that is, send out the second output waveform through the second output interface of function B. Through the parallel test mode, the efficiency of chip function-level testing is improved.

[0096] Figure 3 A flow chart of generating a test waveform in a serial mode provided by an embodiment of the present invention is shown.

[0097] According to an embodiment of the present invention, Figure 3 As shown, the generating of the first waveform information according to the first module sequence or the second module sequence and the corresponding function verification mode also includes:

[0098] S302, when it is determined that the function verification mode is set to the serial mode;

[0099] S304, obtaining third module information and third output module information according to a preset test sequence;

[0100] S306, determining a third output interface according to the third output module information;

[0101] S308: Obtain a third output waveform according to the third configuration information of the third module information and the third output parameter of the third output module.

[0102] It should be noted that the third output module information is the module that controls the output in the module sequence of the function to be tested first; the third output parameter is the configuration parameter of the output register of the third output module; and the third output interface is the interface or pin of the third output module for testing the waveform.

[0103] In this embodiment, when the function verification mode is the serial mode, it means that the configuration modules of function A and function B are different or their configuration parameters are different. Therefore, function A and function B need to be tested in sequence according to the set order. According to the set order, the configuration module and output module of the function to be tested first are determined. First, the configuration module is initialized according to the configuration parameters; then, the output interface is determined according to the output module; finally, the output waveform is determined according to the configuration parameters and the output parameters, and the third output waveform is output through the corresponding third output interface.

[0104] According to an embodiment of the present invention, it also includes:

[0105] Determine whether the third output waveform has been verified;

[0106] If yes, then according to the preset test sequence, the fourth module information and the fourth output module information are obtained;

[0107] Determining a fourth output interface according to the fourth output module information;

[0108] A fourth output waveform is obtained according to the fourth configuration information of the fourth module information and the fourth output parameter of the fourth output module.

[0109] It should be noted that the fourth output module information is the module that controls the output in the module sequence of functions that are tested later in the order; the fourth output parameter is the configuration parameter of the output register of the fourth output module; and the fourth output interface is the interface or pin of the fourth output module for testing the waveform.

[0110] In this embodiment, when the function verification mode is the serial mode, the functions that are in the latter order can be tested only after the waveform verification of the function to be tested first is completed. That is to say, only after the third output waveform is verified, the fourth module information and the fourth output module information are obtained according to the preset test sequence. First, the configuration module is initialized according to the configuration parameters; then, the output interface is determined according to the output module; finally, the output waveform is determined according to the configuration parameters and the output parameters, and the fourth output waveform is output through the corresponding fourth output interface.

[0111] According to an embodiment of the present invention, it also includes:

[0112] When it is determined that the function verification mode is set to the serial mode;

[0113] Get the fifth module information;

[0114] Obtaining a first configuration parameter sequence according to the fifth configuration parameter of the fifth module information;

[0115] According to the first configuration parameter sequence, a second configuration parameter sequence is obtained in a preset arrangement order;

[0116] The waveform verification order is adjusted according to the second configuration parameter sequence.

[0117] It should be noted that the fifth module information is a configuration module of the function to be tested. In this embodiment, first, the configuration parameters of the function to be tested are recorded, and a first configuration parameter sequence is obtained according to the corresponding configuration module. Then, according to the first configuration parameter sequence, the parameters are arranged in ascending or descending order to obtain a second configuration parameter sequence. Finally, according to the second configuration parameter sequence, the verification order of the output waveform is adjusted, that is, the test order of the test function is adjusted.

[0118] According to an embodiment of the present invention, it also includes:

[0119] Obtaining first comparison information according to the first configuration parameter and the second configuration parameter in an exclusive-OR logic operation manner;

[0120] Determine whether the first comparison information is 0;

[0121] If yes, it means that the first configuration parameter is the same as the second configuration parameter;

[0122] If not, it means that the first configuration parameter and the second configuration parameter are different.

[0123] It should be noted that, in this embodiment, whether the configuration parameters of the configuration module are the same is determined by an XOR logic operation. The configuration parameters are usually set as binary numbers. When the XOR logic operation is performed on two binary numbers, when the operation result is 0, it means that the two binary numbers are the same, otherwise, the two binary numbers are not the same. Therefore, the first configuration parameter and the second configuration parameter are calculated by an XOR logic operation to determine whether the two are equal.

[0124] It is worth mentioning that it also includes:

[0125] Obtaining configuration parameters, output parameters and first waveform information of a first module sequence;

[0126] A log file is output according to the configuration parameters, the output parameters and the first waveform information.

[0127] It should be noted that, in this embodiment, the configuration parameters, output parameters and output waveforms of the test functions are recorded in the order of functional testing and saved as log files for verification and review, so as to further improve the accuracy of the test results.

[0128] It is worth mentioning that it also includes:

[0129] Get log files;

[0130] Obtaining second waveform information according to the configuration parameters and output parameter information in the log file;

[0131] Determine whether the first waveform information in the log file is the same as the second waveform information;

[0132] If not, a first warning message is sent.

[0133] It should be noted that, in this embodiment, the correctness of the output waveform is verified through the log file. The second waveform information is determined according to the configuration parameters and output parameters in the log file, and is used to compare with the first waveform information in the log file; when the first waveform information is inconsistent with the second waveform information, it indicates that there is an abnormal sharing of the waveform, and the first warning information is sent to indicate that the function in the log file needs to be retested.

[0134] Figure 4 A block diagram of a RISC-V DSP chip ATE test program optimization system of the present invention is shown.

[0135] like Figure 4 As shown, the second aspect of the present invention discloses a RISC-V DSP chip ATE test program optimization system 4, including a memory 41 and a processor 42, wherein the memory includes a RISC-V DSP chip ATE test program optimization method program, and when the RISC-V DSP chip ATE test program optimization method program is executed by the processor, the following steps are implemented:

[0136] Obtain a first module sequence and a second module sequence;

[0137] Determine whether there are identical modules in the first module sequence and the second module sequence;

[0138] If yes, obtain the first module information and the second module information;

[0139] Determine whether a first configuration parameter of the first module information and a second configuration parameter of the second module information are the same;

[0140] If so, set the function verification mode to parallel mode;

[0141] If not, set the function verification mode to serial mode;

[0142] First waveform information is generated according to the first module sequence or the second module sequence and in accordance with a corresponding function verification mode.

[0143] It should be noted that the first module sequence is a sequence of several modules configured to verify a function; the second module sequence is a sequence of several modules configured to verify another function; the first module information is a configuration module in the first module sequence, which is a module that exists in both the first module sequence and the second module sequence; the second module information is a configuration module in the second module sequence, which is a module that exists in both the first module sequence and the second module sequence; the first configuration parameter is a configuration value of each configuration register of the first module; the second configuration parameter is a configuration value of each configuration register of the second module. In addition, during the chip function level test process, although only one output module is tested, multiple configuration modules are involved, such as a clock module, a power supply module, a system control module, etc. When performing multiple function level test tasks, if the configuration modules of the two test tasks are the same, a parallel test mode can be implemented in which the configuration module is configured once and then multiple output modules are tested; if the configuration modules of the two test tasks are different or the configuration parameters of the configuration modules are different, the test tasks are tested in a serial test mode in a set order.

[0144] In this embodiment, it is assumed that the first module sequence is a combination of modules configured to test function A, and the second module sequence is a combination of modules configured to test function B. First, determine whether there are the same modules in the modules for testing function A and the modules for testing function B, that is, determine whether there are the same configuration modules. If so, extract the same configuration modules, that is, the first module of function A and the second module of function B. Then, determine whether the first configuration parameter of the first module is the same as the second configuration parameter of the second module; if so, it means that function A and function B can be set to parallel test mode; if not, it means that function A and function B are set to serial test mode. Finally, according to the corresponding test mode, after configuring the module combination for testing function A or testing function B, the corresponding test waveform is obtained.

[0145] According to an embodiment of the present invention, generating first waveform information according to the first module sequence or the second module sequence in accordance with the corresponding function verification mode further includes:

[0146] When it is determined that the function verification mode is set to the parallel mode;

[0147] Initialize first module information according to the first configuration parameter;

[0148] Obtaining first output module information and second output module information;

[0149] Determine a first output interface according to the first output module information;

[0150] Acquire a first output parameter, and determine a first output waveform of a first output interface according to the first configuration parameter and the first output parameter;

[0151] Determine a second output interface according to the second output module information;

[0152] A second output parameter is obtained, and a second output waveform of the second output interface is determined according to the first configuration parameter and the second output parameter.

[0153] It should be noted that the first output module information is the module that controls output in the first module sequence; the first output parameter is the configuration parameter of the output register of the first output module; the first output interface is the interface or pin of the first output module for testing the waveform; the second output module information is the module that controls output in the second module sequence; the second output parameter is the configuration parameter of the output register of the second output module; the second output interface is the interface or pin of the second output module for testing the waveform.

[0154] In this embodiment, when the function verification mode is the parallel mode, it means that the configuration modules of function A and function B have the same configuration parameters. Therefore, the test of function A and function B does not need to repeatedly modify the configuration of some modules, and the output waveform is obtained according to the respective output modules. First, initialize the corresponding configuration module according to the configuration parameters of function A or function B. Then, determine the data interface according to the output module of function A, and determine the output waveform according to the configuration parameters and the output parameters, that is, send out the first output waveform through the first output interface of function A. Similarly, determine the data interface according to the output module of function B, and determine the output waveform according to the configuration parameters and the output parameters, that is, send out the second output waveform through the second output interface of function B. Through the parallel test mode, the efficiency of chip function-level testing is improved.

[0155] According to an embodiment of the present invention, generating first waveform information according to the first module sequence or the second module sequence in accordance with the corresponding function verification mode further includes:

[0156] When it is determined that the function verification mode is set to the serial mode;

[0157] According to a preset test sequence, the third module information and the third output module information are obtained;

[0158] Determine the third output interface according to the third output module information;

[0159] A third output waveform is obtained according to the third configuration information of the third module information and the third output parameter of the third output module.

[0160] It should be noted that the third output module information is the module that controls the output in the module sequence of the function to be tested first; the third output parameter is the configuration parameter of the output register of the third output module; and the third output interface is the interface or pin of the third output module for testing the waveform.

[0161] In this embodiment, when the function verification mode is the serial mode, it means that the configuration modules of function A and function B are different or their configuration parameters are different. Therefore, function A and function B need to be tested in sequence according to the set order. According to the set order, the configuration module and output module of the function to be tested first are determined. First, the configuration module is initialized according to the configuration parameters; then, the output interface is determined according to the output module; finally, the output waveform is determined according to the configuration parameters and the output parameters, and the third output waveform is output through the corresponding third output interface.

[0162] According to an embodiment of the present invention, it also includes:

[0163] Determine whether the third output waveform has been verified;

[0164] If yes, then according to the preset test sequence, the fourth module information and the fourth output module information are obtained;

[0165] Determining a fourth output interface according to the fourth output module information;

[0166] A fourth output waveform is obtained according to the fourth configuration information of the fourth module information and the fourth output parameter of the fourth output module.

[0167] It should be noted that the fourth output module information is the module that controls the output in the module sequence of functions that are tested later in the order; the fourth output parameter is the configuration parameter of the output register of the fourth output module; and the fourth output interface is the interface or pin of the fourth output module for testing the waveform.

[0168] In this embodiment, when the function verification mode is the serial mode, the functions that are in the latter order can be tested only after the waveform verification of the function to be tested first is completed. That is to say, only after the third output waveform is verified, the fourth module information and the fourth output module information are obtained according to the preset test sequence. First, the configuration module is initialized according to the configuration parameters; then, the output interface is determined according to the output module; finally, the output waveform is determined according to the configuration parameters and the output parameters, and the fourth output waveform is output through the corresponding fourth output interface.

[0169] According to an embodiment of the present invention, it also includes:

[0170] When it is determined that the function verification mode is set to the serial mode;

[0171] Get the fifth module information;

[0172] Obtaining a first configuration parameter sequence according to the fifth configuration parameter of the fifth module information;

[0173] According to the first configuration parameter sequence, a second configuration parameter sequence is obtained in a preset arrangement order;

[0174] The waveform verification order is adjusted according to the second configuration parameter sequence.

[0175] It should be noted that the fifth module information is a configuration module of the function to be tested. In this embodiment, first, the configuration parameters of the function to be tested are recorded, and a first configuration parameter sequence is obtained according to the corresponding configuration module. Then, according to the first configuration parameter sequence, the parameters are arranged in ascending or descending order to obtain a second configuration parameter sequence. Finally, according to the second configuration parameter sequence, the verification order of the output waveform is adjusted, that is, the test order of the test function is adjusted.

[0176] According to an embodiment of the present invention, it also includes:

[0177] Obtaining first comparison information according to the first configuration parameter and the second configuration parameter in an exclusive-OR logic operation manner;

[0178] Determine whether the first comparison information is 0;

[0179] If yes, it means that the first configuration parameter is the same as the second configuration parameter;

[0180] If not, it means that the first configuration parameter and the second configuration parameter are different.

[0181] It should be noted that, in this embodiment, whether the configuration parameters of the configuration module are the same is determined by an XOR logic operation. The configuration parameters are usually set as binary numbers. When the XOR logic operation is performed on two binary numbers, when the operation result is 0, it means that the two binary numbers are the same, otherwise, the two binary numbers are not the same. Therefore, the first configuration parameter and the second configuration parameter are calculated by an XOR logic operation to determine whether the two are equal.

[0182] It is worth mentioning that it also includes:

[0183] Obtaining configuration parameters, output parameters and first waveform information of a first module sequence;

[0184] A log file is output according to the configuration parameters, the output parameters and the first waveform information.

[0185] It should be noted that, in this embodiment, the configuration parameters, output parameters and output waveforms of the test functions are recorded in the order of functional testing and saved as log files for verification and review, so as to further improve the accuracy of the test results.

[0186] It is worth mentioning that it also includes:

[0187] Get log files;

[0188] Obtaining second waveform information according to the configuration parameters and output parameter information in the log file;

[0189] Determine whether the first waveform information in the log file is the same as the second waveform information;

[0190] If not, a first warning message is sent.

[0191] It should be noted that, in this embodiment, the correctness of the output waveform is verified through the log file. The second waveform information is determined according to the configuration parameters and output parameters in the log file, and is used to compare with the first waveform information in the log file; when the first waveform information is inconsistent with the second waveform information, it indicates that there is an abnormal sharing of the waveform, and the first warning information is sent to indicate that the function in the log file needs to be retested.

[0192] A third aspect of the present invention provides a computer-readable storage medium, which includes a RISC-V DSP chip ATE test program optimization method program. When the RISC-V DSP chip ATE test program optimization method program is executed by a processor, the steps of the RISC-V DSP chip ATE test program optimization method as described in any one of the above items are implemented.

[0193] The present invention provides a RISC-V DSP chip ATE test program optimization method, system and storage medium. First, it is determined whether there is an identical module in a first module sequence and a second module sequence. If yes, first module information in the first module sequence and second module information in the second module sequence are extracted; then, a function verification mode of a chip test is determined according to a first configuration parameter of the first module information and a second configuration parameter of the second module information; finally, first waveform information is generated according to the first module sequence or the second module sequence and the corresponding function verification mode; and a test waveform is automatically generated by analyzing the modules used in the functional test, thereby reducing the manual work of testers, improving the test efficiency and reducing the error rate.

[0194] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0195] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A RISC-V DSP chip ATE test program optimization method, characterized in that: The method comprises: Obtain a first module sequence and a second module sequence; Determine whether there are identical modules in the first module sequence and the second module sequence; If yes, obtain the first module information and the second module information; Determine whether a first configuration parameter of the first module information and a second configuration parameter of the second module information are the same; If so, set the function verification mode to parallel mode; If not, set the function verification mode to serial mode; First waveform information is generated according to the first module sequence or the second module sequence and in accordance with a corresponding function verification mode.

2. A RISC-V DSP chip ATE test program optimization method according to claim 1, characterized in that: The generating first waveform information according to the first module sequence or the second module sequence and in accordance with the corresponding function verification mode also includes: When it is determined that the function verification mode is set to the parallel mode; Initialize first module information according to the first configuration parameter; Obtaining first output module information and second output module information; Determine a first output interface according to the first output module information; Acquire a first output parameter, and determine a first output waveform of a first output interface according to the first configuration parameter and the first output parameter; Determine a second output interface according to the second output module information; A second output parameter is obtained, and a second output waveform of the second output interface is determined according to the first configuration parameter and the second output parameter.

3. A RISC-V DSP chip ATE test program optimization method according to claim 1, characterized in that: The generating first waveform information according to the first module sequence or the second module sequence and in accordance with the corresponding function verification mode also includes: When it is determined that the function verification mode is set to the serial mode; According to a preset test sequence, the third module information and the third output module information are obtained; Determine the third output interface according to the third output module information; A third output waveform is obtained according to the third configuration information of the third module information and the third output parameter of the third output module.

4. A RISC-V DSP chip ATE test program optimization method according to claim 3, characterized in that: Also includes: Determine whether the third output waveform has been verified; If yes, the fourth module information and the fourth output module information are obtained according to the preset output order; Determining a fourth output interface according to the fourth output module information; A fourth output waveform is obtained according to the fourth configuration information of the fourth module information and the fourth output parameter of the fourth output module.

5. A RISC-V DSP chip ATE test program optimization method according to claim 1, characterized in that: Also includes: When it is determined that the function verification mode is set to the serial mode; Get the fifth module information; Obtaining a first configuration parameter sequence according to the fifth configuration parameter of the fifth module information; According to the first configuration parameter sequence, a second configuration parameter sequence is obtained in a preset arrangement order; The waveform verification order is adjusted according to the second configuration parameter sequence.

6. A RISC-V DSP chip ATE test program optimization method according to claim 1, characterized in that: Also includes: Obtaining first comparison information according to the first configuration parameter and the second configuration parameter in an exclusive-OR logic operation manner; Determine whether the first comparison information is 0; If yes, it means that the first configuration parameter is the same as the second configuration parameter; If not, it means that the first configuration parameter and the second configuration parameter are different.

7. A RISC-V DSP chip ATE test program optimization system, characterized in that: The system includes a memory and a processor, wherein the memory includes a RISC-V DSP chip ATE test program optimization method program, and when the RISC-V DSP chip ATE test program optimization method program is executed by the processor, the following steps are implemented: Obtain a first module sequence and a second module sequence; Determine whether there are identical modules in the first module sequence and the second module sequence; If yes, obtain the first module information and the second module information; Determine whether a first configuration parameter of the first module information and a second configuration parameter of the second module information are the same; If so, set the function verification mode to parallel mode; If not, set the function verification mode to serial mode; First waveform information is generated according to the first module sequence or the second module sequence and in accordance with a corresponding function verification mode.

8. A RISC-V DSP chip ATE test program optimization system according to claim 7, characterized in that: The generating first waveform information according to the first module sequence or the second module sequence and in accordance with the corresponding function verification mode also includes: When it is determined that the function verification mode is set to the parallel mode; Initialize first module information according to the first configuration parameter; Obtaining first output module information and second output module information; Determine a first output interface according to the first output module information; Acquire a first output parameter, and determine a first output waveform of a first output interface according to the first configuration parameter and the first output parameter; Determine a second output interface according to the second output module information; A second output parameter is obtained, and a second output waveform of the second output interface is determined according to the first configuration parameter and the second output parameter.

9. A RISC-V DSP chip ATE test program optimization system according to claim 7, characterized in that: The generating first waveform information according to the first module sequence or the second module sequence and in accordance with the corresponding function verification mode also includes: When it is determined that the function verification mode is set to the serial mode; According to a preset test sequence, the third module information and the third output module information are obtained; Determine the third output interface according to the third output module information; A third output waveform is obtained according to the third configuration information of the third module information and the third output parameter of the third output module.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer-readable storage medium includes a RISC-V DSP chip ATE test program optimization method program. When the RISC-V DSP chip ATE test program optimization method program is executed by a processor, the steps of the RISC-V DSP chip ATE test program optimization method as described in any one of claims 1 to 6 are implemented.

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