A Zynq-based on-chip high-speed data transmission system and method
By designing a Zynq-based high-speed on-chip data transmission system, using resources such as AXI bus, ARM processor and AXIDataMoverIP core, the problem that the existing technology cannot meet the high-speed on-chip data transmission requirements of Zynq SoC is solved, and the data transmission effect with high data throughput and low latency is achieved.
Patent Information
- Application Number
- CN202411834974.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-04
AI Technical Summary
The prior art cannot meet the high-speed on-chip data storage requirements based on Zynq SoC, especially in terms of reaching data transmission rates above 4GB/s and not occupying too much ARM processor resources.
Design a high-speed on-chip data transmission system based on Zynq, using resources such as AXI bus, ARM processor, and AXIDataMoverIP core to transmit data through AXIDataMoverIP controller and FIFO to achieve efficient data migration and cache management.
It realizes data transmission with high data throughput and low latency, meeting a variety of application scenarios that require high-speed data transmission on-chip. The data transmission speed of actual scenarios can reach 6GB/s.
Smart Images
Figure CN119759837A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of embedded computer data transmission, and in particular to a Zynq-based on-chip high-speed data transmission system and method. Background Art
[0002] With the rapid development of information technology, data has become one of the most valuable resources in today's society. In many application fields, such as aerospace, industrial automation, automotive electronics, medical equipment, etc., higher requirements are put forward for high-speed data transmission and processing, as well as miniaturization and low power consumption to adapt to more flexible and changeable application scenarios.
[0003] The Zynq series chip is a fully programmable SoC that integrates ARM processors and FPGAs on-chip, and has the advantages of both. It combines powerful software processing capabilities with flexible hardware programmability, making it possible to implement complex functions and high-speed data flows on a single chip.
[0004] The high-speed disk storage requirement for on-chip data based on the Zynq SoC requires a data transfer rate of more than 4GB / s, and cannot occupy too many ARM processor resources. However, the data transmission systems and methods in the prior art cannot meet this requirement. Therefore, it is urgent to design an on-chip high-speed data transmission system and method that can meet the requirement. Summary of the invention
[0005] The present invention provides a Zynq-based on-chip high-speed data transmission system and method, which can achieve high data throughput and low latency data transmission and meet various application scenarios requiring on-chip high-speed data transmission.
[0006] To achieve the above object, the present invention adopts the following technical solutions:
[0007] A Zynq-based on-chip high-speed data transmission system comprises a host computer, a PS end, a PL end, an AXI bus, an AXIDataMoverIP core, and an AXIDataMoverIP controller; the host computer performs data exchange with the PS end through a serial port or a network port, the PS end performs data exchange with the PL end through the AXI bus, the PS end controls the AXIDataMoverIP controller by performing read and write operations on the PL end register, the AXIDataMoverIP controller sends control commands of each channel to the AXIDataMoverIP core through a CMD channel, and the AXIDataMoverIP core realizes data transport in MM2S and S2MM directions by parsing the control commands.
[0008] As a preferred embodiment of the above solution, the host computer exchanges data with the PS end through a UART serial port or a Gigabit Ethernet port.
[0009] As a preferred embodiment of the above solution, the PS end includes an ARM processor, and the ARM processor is connected to a DDR.
[0010] As a preferred embodiment of the above scheme, the PL end includes an FPGA and a storage module, the ARM processor is interconnected with the FPGA at high speed through the LPD and FPD interfaces, and the ARM processor reads and writes registers through the LPD interface and the AXI bus.
[0011] As a preferred embodiment of the above solution, the storage module includes eMMC, Flash, DDR, and SSD storage disk.
[0012] As a preferred embodiment of the above solution, the SSD storage disk adopts a PCIE interface or an m.2 hardware interface.
[0013] A Zynq-based on-chip high-speed data transmission method comprises the following steps:
[0014] S1, PS end realizes the interface communication of serial port and network port, and the host computer exchanges data with ARM processor through serial port or network port;
[0015] S2, ARM processor reads and writes PL-side registers through LPD interface and AXI bus to interact with AXIDataMoverIP controller;
[0016] S3, AXIDataMoverIP controller parses, packages, and performs timing control on the control commands sent down, and sends control commands from DDR to PL and from PL to DDR to AXIDataMoverIP core through MM2S_CMD and S2MM_CMD command channels respectively;
[0017] S4, AXIDataMoverIP core parses the command issued by the CMD channel, and moves data bidirectionally through independent channels, transferring data from DDR to PL and vice versa through M_AXI_MM2S and M_AXI_S2MM channels respectively;
[0018] S5. When data is moved between the PL and PS ends, FIFO is used to cache the data, and the AXIDataMoverIP controller controls the reading and writing of FIFO.
[0019] S6. Data can be read and written to the SSD storage disk through the PCIE interface and the m.2 hardware interface.
[0020] As a preferred embodiment of the above solution, the PL-side AXIDataMoverIP core, DataMoverIP controller, FIFO, and AXI bus clock all use 200Mhz.
[0021] As a preferred embodiment of the above solution, the AXIDataMoverIP core enables MM2S and S2MM channels, the data channel width is 256 bits, and the BTT width is 23 bits.
[0022] As a preferred embodiment of the above solution, the data buffer FIFO depth is 256.
[0023] Due to the above structure, the beneficial effects of the present invention are:
[0024] The present invention uses resources such as AXI bus, ARM processor, Datamover soft core, etc. to design and implement an efficient data transmission solution, which can achieve high data throughput and low latency data transmission, meet a variety of application scenarios that require high-speed data transmission on chip, and the data transmission speed in actual scenario applications can reach 6GB / s. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.
[0026] Figure 1 It is a system schematic diagram of the present invention. DETAILED DESCRIPTION
[0027] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.
[0028] like Figure 1 As shown, this embodiment provides an on-chip high-speed data transmission system based on Zynq, including a host computer, a PS end, a PL end, an AXI bus, an AXIDataMoverIP core, and an AXIDataMoverIP controller; the host computer interacts with the PS end through a serial port or a network port for data exchange, the PS end interacts with the PL end through the AXI bus, the PS end controls the AXIDataMoverIP controller by performing read and write operations on the PL end register, the AXIDataMoverIP controller sends control commands of each channel to the AXIDataMoverIP core through the CMD channel, and the AXIDataMoverIP core implements data transport in MM2S and S2MM directions by parsing the control commands.
[0029] In this embodiment, the host computer exchanges data with the PS end through a UART serial port or a Gigabit Ethernet port.
[0030] In this embodiment, the PS end includes an ARM processor, and the ARM processor is connected to a DDR.
[0031] In this embodiment, the PL end includes an FPGA and a storage module, the ARM processor is interconnected with the FPGA at high speed through LPD and FPD interfaces, and the ARM processor reads and writes registers through the LPD interface and the AXI bus.
[0032] In this embodiment, the storage module includes eMMC, Flash, DDR, and SSD storage disks.
[0033] In this embodiment, the SSD storage disk uses a PCIE interface or an m.2 hardware interface.
[0034] This embodiment also provides a Zynq-based on-chip high-speed data transmission method, comprising the following steps:
[0035] S1, PS end realizes the interface communication of serial port and network port, and the host computer exchanges data with ARM processor through serial port or network port;
[0036] S2, ARM processor reads and writes PL-side registers through LPD interface and AXI bus to interact with AXIDataMoverIP controller;
[0037] S3, AXIDataMoverIP controller parses, packages, and performs timing control on the control commands sent down, and sends control commands from DDR to PL and from PL to DDR to AXIDataMoverIP core through MM2S_CMD and S2MM_CMD command channels respectively;
[0038] S4, AXIDataMoverIP core parses the command issued by the CMD channel, and moves data bidirectionally through independent channels, transferring data from DDR to PL and vice versa through M_AXI_MM2S and M_AXI_S2MM channels respectively;
[0039] S5. When data is moved between the PL and PS ends, FIFO is used to cache the data, and the AXIDataMoverIP controller controls the reading and writing of FIFO.
[0040] S6. Data can be read and written to the SSD storage disk through the PCIE interface and the m.2 hardware interface.
[0041] In this embodiment, the clocks of the PL-side AXI Data Mover IP core, Data Mover IP controller, FIFO, AXI bus, reset module, etc. all use 200 MHz.
[0042] In this embodiment, the AXIDataMoverIP core enables MM2S and S2MM channels, the data channel width is 256 bits, and the BTT width is 23 bits.
[0043] In this embodiment, the data buffer FIFO depth is 256.
[0044] In this embodiment, SoC selects to use the ZYNQ series XCZU7EV-2FFVC1156I of XILINX company as the main control chip.
[0045] In this embodiment, the single data transmission amount of the AXIDataMoverIP core is 4194304 bytes by default, which can be customized.
[0046] The present invention uses resources such as AXI bus, ARM processor, Datamover soft core, etc. to design and implement an efficient data transmission solution, which can achieve high data throughput and low latency data transmission, meet a variety of application scenarios that require high-speed data transmission on chip, and the data transmission speed in actual scenario applications can reach 6GB / s.
[0047] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A Zynq-based on-chip high-speed data transmission system, characterized in that: It includes a host computer, a PS end, a PL end, an AXI bus, an AXIDataMoverIP core, and an AXIDataMoverIP controller; the host computer exchanges data with the PS end through a serial port or a network port, the PS end exchanges data with the PL end through an AXI bus, the PS end controls the AXIDataMoverIP controller by performing read and write operations on the PL end register, the AXIDataMoverIP controller sends control commands of each channel to the AXIDataMoverIP core through a CMD channel, and the AXIDataMoverIP core realizes data transportation in MM2S and S2MM flows by parsing the control commands.
2. The Zynq-based on-chip high-speed data transmission system according to claim 1, characterized in that: The host computer exchanges data with the PS end via the UART serial port or the Gigabit Ethernet port.
3. The Zynq-based on-chip high-speed data transmission system according to claim 1, characterized in that: The PS end includes an ARM processor, and the ARM processor is connected to a DDR.
4. The Zynq-based on-chip high-speed data transmission system according to claim 1, characterized in that: The PL end includes an FPGA and a storage module. The ARM processor is interconnected with the FPGA at high speed through the LPD and FPD interfaces. The ARM processor reads and writes registers through the LPD interface and the AXI bus.
5. The Zynq-based on-chip high-speed data transmission system according to claim 4, characterized in that: The storage module includes eMMC, Flash, and SSD storage disks.
6. The Zynq-based on-chip high-speed data transmission system according to claim 5, characterized in that: The SSD storage disk can use a PCIE interface or an m.2 hardware interface.
7. A Zynq-based intra-chip high-speed data transmission method according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1, PS end realizes the interface communication of serial port and network port, and the host computer exchanges data with ARM processor through serial port or network port; S2, ARM processor reads and writes PL-side registers through LPD interface and AXI bus to interact with AXIDataMoverIP controller; S3, AXIDataMoverIP controller parses, packages, and performs timing control on the control commands sent down, and sends control commands from DDR to PL and from PL to DDR to AXIDataMoverIP core through MM2S_CMD and S2MM_CMD command channels respectively; S4, AXIDataMoverIP core parses the command issued by the CMD channel, and moves data bidirectionally through independent channels, transferring data from DDR to PL and vice versa through M_AXI_MM2S and M_AXI_S2MM channels respectively; S5. When data is moved between the PL and PS ends, FIFO is used to cache the data, and the AXIDataMoverIP controller controls the reading and writing of FIFO. S6. Data can be read and written to the SSD storage disk through the PCIE interface and the m.2 hardware interface.
8. The Zynq-based intra-chip high-speed data transmission method according to claim 7, characterized in that: The PL-side AXIDataMoverIP core, DataMoverIP controller, FIFO, and AXI bus clock all use 200Mhz.
9. The Zynq-based intra-chip high-speed data transmission method according to claim 7, characterized in that: The AXIDataMoverIP core enables MM2S and S2MM channels, with a data channel width of 256 bits and a BTT width of 23 bits.
10. The Zynq-based intra-chip high-speed data transmission method according to claim 7, characterized in that: The data buffer FIFO depth is 256.