A multi-chip data interaction method, system, controller and device

Abstract

The present application discloses a multi-chip data interaction method, system, controller and device, including: the main chip obtains the first frame count of the target data, generates the first target instruction according to the preset communication format from the first frame count, and sends the first target instruction to several secondary chips; if the main chip receives the reply information sent by each secondary chip within a preset time period, the second frame count in the reply information is parsed, and the second frame count is compared with the first frame count to obtain a comparison result, wherein the reply information includes the verification result of each secondary chip on the first target instruction; if the comparison result does not meet the preset conditions, the first target instruction is resent to several secondary chips. The present application can realize effective communication between multiple chips and ensure accurate transmission and reception of data.

Description

Technical Field

[0001] The present application relates to the field of data interaction technology, and in particular to a multi-chip data interaction method, system, controller and device. Background Art

[0002] With the rapid development of computer technology, more and more electronic devices use serial port chips for communication. For example, the power modules in electric vehicles and their charging piles use serial port chips for module control and monitoring.

[0003] Existing serial communication software is usually designed for point-to-point communication. Two devices are directly connected through a serial line, and data flows between them in one or two directions. The communication link is relatively simple and easy to manage. However, in a multi-chip communication scenario, a controller needs to interact with multiple chips, which requires complex software to manage multiple communication links. This not only means handling more data transmission tasks, but more importantly, ensuring that each communication link can receive data correctly and in a timely manner, while avoiding data conflicts and delays. This undoubtedly greatly increases the difficulty of software development and maintenance costs.

[0004] Application Contents

[0005] The present application provides a multi-chip data interaction method, system, controller and device to achieve effective communication between multiple chips and ensure accurate transmission and reception of data.

[0006] In a first aspect, the present application provides a multi-chip data interaction method, comprising:

[0007] The master chip obtains a first frame count of target data, generates a first target instruction according to a preset communication format based on the first frame count, and sends the first target instruction to a plurality of secondary chips;

[0008] If the master chip receives reply information sent by each slave chip within a preset time period, the master chip parses the second frame count in the reply information, and compares the second frame count with the first frame count to obtain a comparison result, wherein the reply information includes the verification result of each slave chip on the first target instruction;

[0009] If the comparison result does not meet the preset condition, the first target instruction is resent to several chips.

[0010] The embodiment of the present application generates the first target instruction according to the preset communication format by using the first frame count, so as to facilitate the subsequent sending of the first target instruction to several secondary chips, thereby facilitating the secondary chips to understand and respond to the requirements of the main chip and reply information; if the main chip receives the reply information sent by each secondary chip within the preset time period, it can be determined whether the main chip has successfully received and processed the instruction within the preset time, thereby facilitating the provision of corresponding processing measures; by parsing the second frame count in the reply information, it is convenient to compare the frame counts later, and it can be determined whether the first target instruction is sent successfully; if the comparison result does not meet the preset conditions, it is necessary to resend the first target instruction to several secondary chips to ensure that all secondary chips can correctly receive the first target instruction, thereby achieving effective communication between multiple chips. Compared with the prior art, the present application can achieve effective communication between multiple chips and ensure accurate transmission and reception of data.

[0011] Furthermore, before sending the first target instruction to a plurality of secondary chips, the method further includes:

[0012] Inputting the first target instruction into a preset checksum calculation algorithm to obtain a first checksum of a preset length;

[0013] The first checksum is added to the first target instruction to update the first target instruction.

[0014] In this way, by verifying the first target instruction, the first target instruction including the checksum can be obtained, which facilitates the subsequent sub-chip to verify the integrity of the data.

[0015] Furthermore, before the master chip receives the reply information sent by each secondary chip within the preset time period, the method further includes:

[0016] The secondary chip parses the received first target instruction to obtain the received instruction and the first checksum;

[0017] Determining a second checksum of the received instruction by the checksum calculation algorithm;

[0018] comparing the first checksum with the second checksum, and if the first checksum is the same as the second checksum, executing the receiving instruction and determining the second frame count;

[0019] The reply information is determined based on the second frame count and the second checksum.

[0020] In this way, by parsing and verifying the first target instruction, the correctness and integrity of the data transmission can be determined, so that the subsequent secondary chip can understand and respond to the requirements of the main chip and reply information.

[0021] Further, after comparing the first checksum with the second checksum, the method further includes:

[0022] If the first checksum is different from the second checksum, an error report is automatically generated based on the check result and sent to the main chip.

[0023] In this way, by sending an error report to the main chip, the result of the main chip data interaction can be ensured.

[0024] Furthermore, it also includes:

[0025] If the master chip does not receive the reply information sent by each slave chip or receives the error report within a preset time period, the first target instruction is resent to the plurality of slave chips.

[0026] In this way, if the main chip does not receive the reply information sent by each secondary chip or receives the error report within the preset time period, the first target instruction can be resent to several secondary chips to ensure the validity of data interaction.

[0027] Furthermore, after resending the first target instruction to a plurality of chips, the method further includes:

[0028] The number of times the main chip sends the first target instruction to each sub-chip is obtained, and it is determined whether the number of times meets a preset number threshold. If the preset number threshold is met, the main chip will re-determine the second target instruction and send it to several sub-chips.

[0029] In this way, by judging whether the number of transmissions meets the preset number threshold, other second target instructions can be sent to the secondary chip when the preset number threshold is met to ensure the validity of data interaction.

[0030] Furthermore, after sending the first target instruction to a plurality of chips, the method further includes:

[0031] Obtain the time interval between the sending time of the first target instruction from the main chip to each secondary chip and the current time, and determine whether the time interval meets the preset time threshold. If it meets the preset time threshold, determine the third frame count, and generate the third target instruction according to the third frame count according to the preset communication format and send it to several secondary chips.

[0032] In this way, it is determined whether the time interval meets the preset time threshold. If the preset time threshold is met, a new third target instruction continues to be sent to the secondary chip to ensure the validity of the data interaction.

[0033] In a second aspect, the present application provides a multi-chip data interaction system, including: an acquisition module, a comparison module and a retransmission module;

[0034] The acquisition module is used for the master chip to acquire the first frame count of the target data, generate the first target instruction according to the preset communication format based on the first frame count, and send the first target instruction to several secondary chips;

[0035] The comparison module is used for parsing the second frame count in the reply information if the master chip receives the reply information sent by each slave chip within a preset time period, and comparing the second frame count with the first frame count to obtain a comparison result, wherein the reply information includes the verification result of each slave chip on the first target instruction;

[0036] The resending module is used to resend the first target instruction to several secondary chips if the comparison result does not meet the preset condition.

[0037] The embodiment of the present application generates the first target instruction according to the preset communication format by using the first frame count, so as to facilitate the subsequent sending of the first target instruction to several secondary chips, thereby facilitating the secondary chips to understand and respond to the requirements of the main chip and reply information; if the main chip receives the reply information sent by each secondary chip within the preset time period, it can be determined whether the main chip has successfully received and processed the instruction within the preset time, thereby facilitating the provision of corresponding processing measures; by parsing the second frame count in the reply information, it is convenient to compare the frame counts later, and it can be determined whether the first target instruction is sent successfully; if the comparison result does not meet the preset conditions, it is necessary to resend the first target instruction to several secondary chips to ensure that all secondary chips can correctly receive the first target instruction, thereby achieving effective communication between multiple chips. Compared with the prior art, the present application can achieve effective communication between multiple chips and ensure accurate transmission and reception of data.

[0038] In a third aspect, the present application provides a controller including a main chip and a sub-chip, wherein the main chip is used to implement the steps of the multi-chip data interaction method as described in the present application.

[0039] In a fourth aspect, the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the multi-chip data interaction method described in the present application are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a flowchart of an embodiment of a multi-chip data interaction method provided by the present application;

[0041] Figure 2 Schematic diagram of the communication format provided by this application;

[0042] Figure 3 It is a flowchart of another embodiment of a multi-chip data interaction method provided by the present application;

[0043] Figure 4 It is a structural diagram of an embodiment of a multi-chip data interaction system provided by the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] It should be understood that the step numbers used in this article are only for the convenience of description and are not intended to limit the order in which the steps are executed.

[0046] It should be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise.

[0047] The terms “include” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0048] The term "and / or" means and includes any and all possible combinations of one or more of the associated listed items.

[0049] With the rapid development of computer technology, many electronic devices use serial chip communication, such as electric vehicles and charging pile power modules. Existing serial communication software is usually designed for point-to-point communication, where data flows unidirectionally or bidirectionally between them, and the communication link is relatively simple and easy to manage. However, in multi-chip communication, the controller needs to interact with multiple chips, which requires complex software to manage multiple communication links. This not only means handling more data transmission tasks, but more importantly, ensuring that each communication link can receive data correctly and in a timely manner, while avoiding data conflicts and delays. This undoubtedly greatly increases the difficulty of software development and maintenance costs.

[0050] Next, the nouns involved in this application are analyzed:

[0051] Artificial intelligence (AI) is a new technical science that studies and develops theories, methods, technologies and application systems for simulating, extending and expanding human intelligence. AI is a branch of computer science that attempts to understand the essence of intelligence and produce a new type of intelligent machine that can respond in a similar way to human intelligence. Research in this field includes robotics, speech recognition, image recognition, natural language processing and expert systems. AI can simulate the information process of human consciousness and thinking. AI is also a theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.

[0052] Based on this, an embodiment of the present application provides a multi-chip data interaction method and system, which can realize effective communication between multiple chips and ensure accurate transmission and reception of data.

[0053] A multi-chip data interaction method and system provided in an embodiment of the present application are specifically illustrated through the following embodiments. First, a multi-chip data interaction method in an embodiment of the present application is described.

[0054] A multi-chip data interaction method provided in an embodiment of the present application relates to the field of data interaction technology. A multi-chip data interaction method provided in an embodiment of the present application can be applied to a terminal, can also be applied to a server side, and can also be software running in a terminal or a server side. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, etc.; the server side can be configured as an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application that implements a multi-chip data interaction method, etc., but is not limited to the above forms.

[0055] The present application can also be used in numerous general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0056] Embodiment 1

[0057] Please refer to Figure 1 , Figure 1 It is a flowchart of an embodiment of a multi-chip data interaction method provided by the present application, including steps S101 to S103;

[0058] Step S101, the master chip obtains a first frame count of target data, generates a first target instruction according to a preset communication format based on the first frame count, and sends the first target instruction to a plurality of secondary chips;

[0059] In some embodiments, the main chip obtains the first frame count of the target data, specifically, initializes the main chip and the sub-chip, and configures the communication interface (such as SPI, I2C, UART, etc.) between the main chip and the sub-chip, and then writes code to read the sensor or access the memory address to obtain the first frame count of the first frame data of the target data.

[0060] In some embodiments, the first frame count is used to generate the first target instruction according to a preset communication format. Specifically, first, the communication format of the first target instruction is clarified, and then the first frame count is added to the data block, and the frame start, frame count, frame length, data block and reserved data combination are filled in according to the preset communication format to generate the first target instruction.

[0061] It should be noted that the communication format includes frame start, frame count, frame length, data block, reservation, CheckSum check, etc. Figure 2The communication format diagram provided for this application, in which each part has requirements for length and content: ① Frame start: 2 bytes, fixed to specific content; ② Frame count: 1 byte, starting from 1, increasing by 1 each time, and returning to 1 when reaching 255; ③ Frame length: 1 byte, indicating the number of data blocks (i.e. the number of data blocks); ④ Data block: 9 bytes for each data block, the specific content is determined according to the data block ID; ⑤ CheckSum check: 4 bytes, which is the sum check result of all previous bytes. Finally, it is also necessary to specify the data content that needs to be filled in the corresponding bytes of the data block corresponding to the id.

[0062] In some embodiments, before sending the first target instruction to several chips, the method further includes: inputting the first target instruction into a preset checksum calculation algorithm to obtain a first checksum of a preset length; and adding the first checksum to the first target instruction to update the first target instruction. Specifically, the first target instruction is input into a preset checksum calculation algorithm, and the checksum calculation algorithm calculates a 4-byte checksum based on the input data. After the checksum is calculated, the checksum is added after the first target instruction to update the first target instruction.

[0063] In this way, by verifying the first target instruction, the first target instruction including the checksum can be obtained, which facilitates the subsequent sub-chip to verify the integrity of the data.

[0064] In some embodiments, the first target instruction is sent to several sub-chips. Specifically, according to system requirements, the instruction is broadcast to all sub-chips or sent only to specific sub-chips, and the first target instruction is sent using a corresponding communication protocol function.

[0065] It should be noted that when the main chip needs to send instructions to several sub-chips, a new serial port needs to be added to the main chip for communication, and the data content in the data blocks between different chips needs to be specified so that the main chip can send instructions to multiple sub-chips.

[0066] Step S102, if the master chip receives reply information sent by each slave chip within a preset time period, the master chip parses the second frame count in the reply information, and compares the second frame count with the first frame count to obtain a comparison result, wherein the reply information includes the verification result of each slave chip on the first target instruction;

[0067] In some embodiments, before the main chip receives the reply information sent by each secondary chip within a preset time period, it also includes: the secondary chip parses the received first target instruction to obtain the received instruction and the first checksum; determines the second checksum of the received instruction through the checksum calculation algorithm; compares the first checksum with the second checksum, and if the first checksum is the same as the second checksum, executes the received instruction and determines the second frame count; and determines the reply information based on the second frame count and the second checksum. Specifically, after receiving the first target instruction, the secondary chip splits the last 4 bytes and the previous bytes of the first target instruction to obtain a receiving instruction and a first checksum, and then inputs the receiving instruction into the same checksum calculation algorithm as the main chip to calculate a second checksum of 4 bytes, and then compares the second checksum calculated by the algorithm with the first checksum obtained by the previous split instruction. If the comparison results are the same, it means that the check is passed, then the secondary chip will execute the first target instruction of the main chip, and increment the value of the first frame count by one to obtain the second frame count, fill the data according to the communication format to generate a pre-reply instruction, and calculate the third checksum of the pre-reply instruction, and combine the pre-send instruction and the third checksum to generate a reply message and send it to the main chip to notify the main chip to start executing the first target instruction.

[0068] In this way, by parsing and verifying the first target instruction, the correctness and integrity of the data transmission can be determined, so that the subsequent secondary chip can understand and respond to the requirements of the main chip and reply information.

[0069] In some embodiments, after comparing the first checksum with the second checksum, the process further includes: if the first checksum is different from the second checksum, automatically generating an error report based on the check result and sending it to the master chip. Specifically, if the comparison result of the first checksum is different from the second checksum, it means that the check fails, and the secondary chip sends a value without increasing the frame count to the master chip, that is, an error report, to remind the master chip that the check fails.

[0070] In this way, by sending an error report to the main chip, the result of the main chip data interaction can be ensured.

[0071] In some embodiments, it further includes: if the main chip does not receive the reply information sent by each sub-chip or receives the error report within a preset time period, the first target instruction is re-sent to several sub-chips. Specifically, after the main chip sends the first target instruction to the sub-chip, it will wait for a preset time period. If it does not receive the reply information sent by the sub-chip or receives the error report sent by the sub-chip within the preset time period, the main chip will send the previous first target instruction to the sub-chip again according to the intra-frame retransmission mechanism, and then continue to wait for a period of time until it receives the reply information from the sub-chip or the number of transmissions meets the preset number of times, and then stop sending the first target instruction.

[0072] In this way, if the main chip does not receive the reply information sent by each secondary chip or receives the error report within the preset time period, the first target instruction can be resent to several secondary chips to ensure the validity of data interaction.

[0073] In some embodiments, if the main chip receives reply information sent by each chip within a preset time period, the second frame count in the reply information is parsed, and the second frame count is compared with the first frame count to obtain a comparison result. Specifically, when the main chip receives reply information within a preset time period, the reply information is parsed to obtain the second frame count, and the second frame count is compared with the first frame count to obtain a comparison result.

[0074] Step S103: if the comparison result does not meet the preset condition, the first target instruction is resent to several chips.

[0075] In some embodiments, if the comparison result does not meet the preset conditions, the first target instruction is resent to several secondary chips. Specifically, if the second frame count increases by 1 compared with the recorded first frame count, it means that the secondary chip has successfully received the instruction. If the second frame count is the same as the recorded first frame count, it means that the first target instruction has failed to be sent, that is, the preset conditions are not met. In this case, the main chip will resend the first target instruction to several secondary chips.

[0076] In some embodiments, after the first target instruction is resent to several sub-chips, it also includes: obtaining the number of times the main chip sends the first target instruction to each sub-chip, and judging whether the number of times meets the preset number threshold. If the preset number threshold is met, the main chip will re-determine the second target instruction and send it to several sub-chips. Specifically, the number of times the main chip sends the first target instruction to each sub-chip is recorded by a counter, and a preset number threshold is set to judge whether the first target instruction needs to be resent. After the main chip sends the first target instruction to the sub-chip each time, the sending number counter of the corresponding sub-chip is updated. After each sending or periodic checking, it is judged whether the number of times each sub-chip sends reaches the preset number threshold. If the number of times a certain sub-chip sends reaches or exceeds the preset threshold, the main chip needs to re-determine the second target instruction, that is, give up sending the first target instruction and send a new second target instruction, and send the new second target instruction to all sub-chips (or only to specific sub-chips according to specific needs).

[0077] In this way, by judging whether the number of transmissions meets the preset number threshold, other second target instructions can be sent to the secondary chip when the preset number threshold is met to ensure the validity of data interaction.

[0078] In some embodiments, after sending the first target instruction to several secondary chips, it also includes: obtaining the time interval between the sending time of the first target instruction from the main chip to each secondary chip and the current time, and judging whether the time interval meets the preset time threshold; if the preset time threshold is met, determining the third frame count, and generating the third target instruction according to the third frame count in a preset communication format and sending it to several secondary chips. Specifically, the main chip stores the timestamp of sending the first target instruction to each sub-chip, and sets a preset time threshold to determine whether the time interval meets the requirements. When the main chip sends the first target instruction to a sub-chip, the current timestamp is recorded as the sending time, and the current time is obtained at the same time, and the time interval between the time when each sub-chip sends the first target instruction and the current time is calculated. For the time interval of each sub-chip, it is determined whether it reaches or exceeds the preset time threshold. If the time interval of a sub-chip meets the preset threshold, there is no need to wait for the reply information of the sub-chip. If other instructions need to be sent, the first frame count is incremented by 1 to determine the third frame count, and the third frame count is encapsulated into a third target instruction according to the preset communication format, and the third target instruction is sent to the specified sub-chip (it may be all sub-chips, or it may be a sub-chip that meets specific conditions).

[0079] In this way, it is determined whether the time interval meets the preset time threshold. If the preset time threshold is met, a new third target instruction continues to be sent to the secondary chip to ensure the validity of the data interaction.

[0080] The embodiment of the present application generates the first target instruction according to the preset communication format by using the first frame count, so as to facilitate the subsequent sending of the first target instruction to several secondary chips, thereby facilitating the secondary chips to understand and respond to the requirements of the main chip and reply information; if the main chip receives the reply information sent by each secondary chip within the preset time period, it can be determined whether the main chip has successfully received and processed the instruction within the preset time, thereby facilitating the provision of corresponding processing measures; by parsing the second frame count in the reply information, it is convenient to compare the frame counts later, and it can be determined whether the first target instruction is sent successfully; if the comparison result does not meet the preset conditions, it is necessary to resend the first target instruction to several secondary chips to ensure that all secondary chips can correctly receive the first target instruction, thereby achieving effective communication between multiple chips. Compared with the prior art, the present application can achieve effective communication between multiple chips and ensure accurate transmission and reception of data.

[0081] Embodiment 2

[0082] This application provides Figure 3 To facilitate understanding, Figure 3 It is a flowchart of another embodiment of a multi-chip data interaction method provided by the present application;

[0083] When the main chip needs to send the first target instruction, the first frame count will be encapsulated into the first target instruction according to the preset communication format, and then the first checksum of the first target instruction will be calculated. The first checksum and other information will be combined to update the first target instruction, and the first target instruction will be sent to several sub-chips.

[0084] After receiving the first target instruction, the secondary chip will parse the first frame count of the first target instruction to obtain the received instruction and the first frame count, and then calculate the second checksum of the received instruction, and then check the second checksum with the first checksum. If the check is successful, a reply message is generated to notify the main chip to execute the first target instruction at the same time. If the check fails, an error report is generated to notify the main chip to resend the first target instruction.

[0085] When the main chip sends a first target instruction to several secondary chips, communication reply timing will be performed. If the reply instruction of the secondary chip is still not received after exceeding the preset time threshold, the first target chip needs to be resent to several secondary chips.

[0086] After the master chip receives the error report from the slave chip, it needs to resend the first target chip to several slave chips.

[0087] After receiving the reply information from the slave chip, the master chip will parse the reply information to determine whether the first target instruction is sent successfully. If the sending fails, the first target chip needs to be resent to several slave chips.

[0088] It should be noted that the data interaction process between the primary chip and the secondary chip has been described in detail in the first embodiment, and will not be described again here.

[0089] Embodiment 3

[0090] Please refer to Figure 4 , Figure 4 It is a structural diagram of an embodiment of a multi-chip data interaction system provided by the present application, comprising: an acquisition module 100, a comparison module 200 and a retransmission module 300;

[0091] The acquisition module 100 is used for the master chip to acquire the first frame count of the target data, generate the first target instruction according to the preset communication format based on the first frame count, and send the first target instruction to several secondary chips;

[0092] The comparison module 200 is used for parsing the second frame count in the reply information if the master chip receives the reply information sent by each slave chip within a preset time period, and comparing the second frame count with the first frame count to obtain a comparison result, wherein the reply information includes the verification result of each slave chip on the first target instruction;

[0093] The resending module 300 is used to resend the first target instruction to several secondary chips if the comparison result does not meet the preset condition.

[0094] The embodiment of the present application generates the first target instruction according to the preset communication format by using the first frame count, so as to facilitate the subsequent sending of the first target instruction to several secondary chips, thereby facilitating the secondary chips to understand and respond to the requirements of the main chip and reply information; if the main chip receives the reply information sent by each secondary chip within the preset time period, it can be determined whether the main chip has successfully received and processed the instruction within the preset time, thereby facilitating the provision of corresponding processing measures; by parsing the second frame count in the reply information, it is convenient to compare the frame counts later, and it can be determined whether the first target instruction is sent successfully; if the comparison result does not meet the preset conditions, it is necessary to resend the first target instruction to several secondary chips to ensure that all secondary chips can correctly receive the first target instruction, thereby achieving effective communication between multiple chips. Compared with the prior art, the present application can achieve effective communication between multiple chips and ensure accurate transmission and reception of data.

[0095] Since the information interaction, execution process, etc. between the modules within the above-mentioned multi-chip data interaction system are based on the same concept as the embodiment of a multi-chip data interaction method in the first aspect of the present invention, the technical effects achieved are basically the same. For specific contents, please refer to the description in the first embodiment of the method of the present invention, and will not be repeated here.

[0096] In a third aspect, the present application provides a controller including a main chip and a sub-chip, wherein the main chip is used to implement the steps of the multi-chip data interaction method as described in the first embodiment of the present application.

[0097] In a fourth aspect, the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the multi-chip data interaction method as described in Embodiment 1 of the present application are implemented.

[0098] The device embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separated, i.e., may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the method of this embodiment.

[0099] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-monitorable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0100] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application.

[0101] It is particularly pointed out that for those skilled in the art, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A multi-chip data interaction method, characterized in that: include: The master chip obtains a first frame count of target data, generates a first target instruction according to a preset communication format based on the first frame count, and sends the first target instruction to a plurality of secondary chips; If the master chip receives reply information sent by each slave chip within a preset time period, the master chip parses the second frame count in the reply information, and compares the second frame count with the first frame count to obtain a comparison result, wherein the reply information includes the verification result of each slave chip on the first target instruction; If the comparison result does not meet the preset condition, the first target instruction is resent to several chips.

2. The multi-chip data interaction method according to claim 1, characterized in that: Before sending the first target instruction to a plurality of secondary chips, the method further includes: Inputting the first target instruction into a preset checksum calculation algorithm to obtain a first checksum of a preset length; The first checksum is added to the first target instruction to update the first target instruction.

3. The multi-chip data interaction method according to claim 2, characterized in that: Before the master chip receives the reply information sent by each secondary chip within the preset time period, the method further includes: The secondary chip parses the received first target instruction to obtain the received instruction and the first checksum; Determining a second checksum of the received instruction by the checksum calculation algorithm; comparing the first checksum with the second checksum, and if the first checksum is the same as the second checksum, executing the receiving instruction and determining the second frame count; The reply information is determined based on the second frame count and the second checksum.

4. The multi-chip data interaction method according to claim 3, characterized in that: After comparing the first checksum with the second checksum, the method further includes: If the first checksum is different from the second checksum, an error report is automatically generated based on the check result and sent to the main chip.

5. The multi-chip data interaction method according to claim 4, characterized in that: Also includes: If the master chip does not receive the reply information sent by each slave chip or receives the error report within a preset time period, the first target instruction is resent to the plurality of slave chips.

6. The multi-chip data interaction method according to any one of claims 1 to 5, characterized in that: After resending the first target instruction to a plurality of chips, the method further includes: The number of times the main chip sends the first target instruction to each sub-chip is obtained, and it is determined whether the number of times meets a preset number threshold. If the preset number threshold is met, the main chip will re-determine the second target instruction and send it to several sub-chips.

7. The multi-chip data interaction method according to claim 1, characterized in that: After sending the first target instruction to a plurality of chips, the method further includes: Obtain the time interval between the sending time of the first target instruction from the main chip to each secondary chip and the current time, and determine whether the time interval meets the preset time threshold. If it meets the preset time threshold, determine the third frame count, and generate the third target instruction according to the third frame count in a preset communication format and send it to several secondary chips.

8. A multi-chip data interaction system, characterized in that: include: Acquisition module, comparison module and resend module; The acquisition module is used for the master chip to acquire the first frame count of the target data, generate the first target instruction according to the preset communication format based on the first frame count, and send the first target instruction to several secondary chips; The comparison module is used for parsing the second frame count in the reply information if the master chip receives the reply information sent by each slave chip within a preset time period, and comparing the second frame count with the first frame count to obtain a comparison result, wherein the reply information includes the verification result of each slave chip on the first target instruction; The resending module is used to resend the first target instruction to several secondary chips if the comparison result does not meet the preset condition.

9. A controller, characterized in that: It comprises a main chip and a sub-chip, wherein the main chip is used to implement the steps of the multi-chip data interaction method as described in any one of claims 1 to 7.

10. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the multi-chip data interaction method as described in any one of claims 1 to 7 are implemented.

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